177adf3f0SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 26e98016cSGiridhar Malavali /* 36e98016cSGiridhar Malavali * QLogic Fibre Channel HBA Driver 4bd21eaf9SArmen Baloyan * Copyright (c) 2003-2014 QLogic Corporation 56e98016cSGiridhar Malavali */ 66e98016cSGiridhar Malavali #ifndef __QLA_BSG_H 76e98016cSGiridhar Malavali #define __QLA_BSG_H 86e98016cSGiridhar Malavali 96e98016cSGiridhar Malavali /* BSG Vendor specific commands */ 106e98016cSGiridhar Malavali #define QL_VND_LOOPBACK 0x01 116e98016cSGiridhar Malavali #define QL_VND_A84_RESET 0x02 126e98016cSGiridhar Malavali #define QL_VND_A84_UPDATE_FW 0x03 136e98016cSGiridhar Malavali #define QL_VND_A84_MGMT_CMD 0x04 146e98016cSGiridhar Malavali #define QL_VND_IIDMA 0x05 156e98016cSGiridhar Malavali #define QL_VND_FCP_PRIO_CFG_CMD 0x06 16f19af163SHarish Zunjarrao #define QL_VND_READ_FLASH 0x07 17f19af163SHarish Zunjarrao #define QL_VND_UPDATE_FLASH 0x08 18697a4bc6SJoe Carnuccio #define QL_VND_SET_FRU_VERSION 0x0B 19697a4bc6SJoe Carnuccio #define QL_VND_READ_FRU_STATUS 0x0C 20697a4bc6SJoe Carnuccio #define QL_VND_WRITE_FRU_STATUS 0x0D 21a9b6f722SSaurav Kashyap #define QL_VND_DIAG_IO_CMD 0x0A 229ebb5d9cSJoe Carnuccio #define QL_VND_WRITE_I2C 0x10 239ebb5d9cSJoe Carnuccio #define QL_VND_READ_I2C 0x11 248ae6d9c7SGiridhar Malavali #define QL_VND_FX00_MGMT_CMD 0x12 25db64e930SJoe Carnuccio #define QL_VND_SERDES_OP 0x13 26e8887c51SJoe Carnuccio #define QL_VND_SERDES_OP_EX 0x14 274243c115SSawan Chandak #define QL_VND_GET_FLASH_UPDATE_CAPS 0x15 284243c115SSawan Chandak #define QL_VND_SET_FLASH_UPDATE_CAPS 0x16 29969a6199SSawan Chandak #define QL_VND_GET_BBCR_DATA 0x17 30243de676SHarish Zunjarrao #define QL_VND_GET_PRIV_STATS 0x18 31ec891462SJoe Carnuccio #define QL_VND_DPORT_DIAGNOSTICS 0x19 328437dda0SSawan Chandak #define QL_VND_GET_PRIV_STATS_EX 0x1A 335fa8774cSJoe Carnuccio #define QL_VND_SS_GET_FLASH_IMAGE_STATUS 0x1E 347ebb336eSQuinn Tran #define QL_VND_EDIF_MGMT 0X1F 35dbf1f53cSSaurav Kashyap #define QL_VND_MANAGE_HOST_STATS 0x23 36dbf1f53cSSaurav Kashyap #define QL_VND_GET_HOST_STATS 0x24 37dbf1f53cSSaurav Kashyap #define QL_VND_GET_TGT_STATS 0x25 38dbf1f53cSSaurav Kashyap #define QL_VND_MANAGE_HOST_PORT 0x26 399e1c3206SBikash Hazarika #define QL_VND_MBX_PASSTHRU 0x2B 40476da8faSBikash Hazarika #define QL_VND_DPORT_DIAGNOSTICS_V2 0x2C 41697a4bc6SJoe Carnuccio 42697a4bc6SJoe Carnuccio /* BSG Vendor specific subcode returns */ 43697a4bc6SJoe Carnuccio #define EXT_STATUS_OK 0 44697a4bc6SJoe Carnuccio #define EXT_STATUS_ERR 1 45a9b6f722SSaurav Kashyap #define EXT_STATUS_BUSY 2 46697a4bc6SJoe Carnuccio #define EXT_STATUS_INVALID_PARAM 6 47a9b6f722SSaurav Kashyap #define EXT_STATUS_DATA_OVERRUN 7 48a9b6f722SSaurav Kashyap #define EXT_STATUS_DATA_UNDERRUN 8 49697a4bc6SJoe Carnuccio #define EXT_STATUS_MAILBOX 11 50dbf1f53cSSaurav Kashyap #define EXT_STATUS_BUFFER_TOO_SMALL 16 51697a4bc6SJoe Carnuccio #define EXT_STATUS_NO_MEMORY 17 52a9b6f722SSaurav Kashyap #define EXT_STATUS_DEVICE_OFFLINE 22 53a9b6f722SSaurav Kashyap 54a9b6f722SSaurav Kashyap /* 55a9b6f722SSaurav Kashyap * To support bidirectional iocb 56a9b6f722SSaurav Kashyap * BSG Vendor specific returns 57a9b6f722SSaurav Kashyap */ 58a9b6f722SSaurav Kashyap #define EXT_STATUS_NOT_SUPPORTED 27 59a9b6f722SSaurav Kashyap #define EXT_STATUS_INVALID_CFG 28 60a9b6f722SSaurav Kashyap #define EXT_STATUS_DMA_ERR 29 61a9b6f722SSaurav Kashyap #define EXT_STATUS_TIMEOUT 30 62a9b6f722SSaurav Kashyap #define EXT_STATUS_THREAD_FAILED 31 63a9b6f722SSaurav Kashyap #define EXT_STATUS_DATA_CMP_FAILED 32 64476da8faSBikash Hazarika #define EXT_STATUS_DPORT_DIAG_ERR 40 65476da8faSBikash Hazarika #define EXT_STATUS_DPORT_DIAG_IN_PROCESS 41 66476da8faSBikash Hazarika #define EXT_STATUS_DPORT_DIAG_NOT_RUNNING 42 676e98016cSGiridhar Malavali 686e98016cSGiridhar Malavali /* BSG definations for interpreting CommandSent field */ 696e98016cSGiridhar Malavali #define INT_DEF_LB_LOOPBACK_CMD 0 706e98016cSGiridhar Malavali #define INT_DEF_LB_ECHO_CMD 1 716e98016cSGiridhar Malavali 7223f2ebd1SSarang Radke /* Loopback related definations */ 738fcd6b8bSChad Dupuis #define INTERNAL_LOOPBACK 0xF1 7423f2ebd1SSarang Radke #define EXTERNAL_LOOPBACK 0xF2 7523f2ebd1SSarang Radke #define ENABLE_INTERNAL_LOOPBACK 0x02 768fcd6b8bSChad Dupuis #define ENABLE_EXTERNAL_LOOPBACK 0x04 7723f2ebd1SSarang Radke #define INTERNAL_LOOPBACK_MASK 0x000E 7823f2ebd1SSarang Radke #define MAX_ELS_FRAME_PAYLOAD 252 7923f2ebd1SSarang Radke #define ELS_OPCODE_BYTE 0x10 8023f2ebd1SSarang Radke 816e98016cSGiridhar Malavali /* BSG Vendor specific definations */ 826e98016cSGiridhar Malavali #define A84_ISSUE_WRITE_TYPE_CMD 0 836e98016cSGiridhar Malavali #define A84_ISSUE_READ_TYPE_CMD 1 846e98016cSGiridhar Malavali #define A84_CLEANUP_CMD 2 856e98016cSGiridhar Malavali #define A84_ISSUE_RESET_OP_FW 3 866e98016cSGiridhar Malavali #define A84_ISSUE_RESET_DIAG_FW 4 876e98016cSGiridhar Malavali #define A84_ISSUE_UPDATE_OPFW_CMD 5 886e98016cSGiridhar Malavali #define A84_ISSUE_UPDATE_DIAGFW_CMD 6 896e98016cSGiridhar Malavali 906e98016cSGiridhar Malavali struct qla84_mgmt_param { 916e98016cSGiridhar Malavali union { 926e98016cSGiridhar Malavali struct { 936e98016cSGiridhar Malavali uint32_t start_addr; 946e98016cSGiridhar Malavali } mem; /* for QLA84_MGMT_READ/WRITE_MEM */ 956e98016cSGiridhar Malavali struct { 966e98016cSGiridhar Malavali uint32_t id; 976e98016cSGiridhar Malavali #define QLA84_MGMT_CONFIG_ID_UIF 1 986e98016cSGiridhar Malavali #define QLA84_MGMT_CONFIG_ID_FCOE_COS 2 996e98016cSGiridhar Malavali #define QLA84_MGMT_CONFIG_ID_PAUSE 3 1006e98016cSGiridhar Malavali #define QLA84_MGMT_CONFIG_ID_TIMEOUTS 4 1016e98016cSGiridhar Malavali 1026e98016cSGiridhar Malavali uint32_t param0; 1036e98016cSGiridhar Malavali uint32_t param1; 1046e98016cSGiridhar Malavali } config; /* for QLA84_MGMT_CHNG_CONFIG */ 1056e98016cSGiridhar Malavali 1066e98016cSGiridhar Malavali struct { 1076e98016cSGiridhar Malavali uint32_t type; 1086e98016cSGiridhar Malavali #define QLA84_MGMT_INFO_CONFIG_LOG_DATA 1 /* Get Config Log Data */ 1096e98016cSGiridhar Malavali #define QLA84_MGMT_INFO_LOG_DATA 2 /* Get Log Data */ 1106e98016cSGiridhar Malavali #define QLA84_MGMT_INFO_PORT_STAT 3 /* Get Port Statistics */ 1116e98016cSGiridhar Malavali #define QLA84_MGMT_INFO_LIF_STAT 4 /* Get LIF Statistics */ 1126e98016cSGiridhar Malavali #define QLA84_MGMT_INFO_ASIC_STAT 5 /* Get ASIC Statistics */ 1136e98016cSGiridhar Malavali #define QLA84_MGMT_INFO_CONFIG_PARAMS 6 /* Get Config Parameters */ 1146e98016cSGiridhar Malavali #define QLA84_MGMT_INFO_PANIC_LOG 7 /* Get Panic Log */ 1156e98016cSGiridhar Malavali 1166e98016cSGiridhar Malavali uint32_t context; 1176e98016cSGiridhar Malavali /* 1186e98016cSGiridhar Malavali * context definitions for QLA84_MGMT_INFO_CONFIG_LOG_DATA 1196e98016cSGiridhar Malavali */ 1206e98016cSGiridhar Malavali #define IC_LOG_DATA_LOG_ID_DEBUG_LOG 0 1216e98016cSGiridhar Malavali #define IC_LOG_DATA_LOG_ID_LEARN_LOG 1 1226e98016cSGiridhar Malavali #define IC_LOG_DATA_LOG_ID_FC_ACL_INGRESS_LOG 2 1236e98016cSGiridhar Malavali #define IC_LOG_DATA_LOG_ID_FC_ACL_EGRESS_LOG 3 1246e98016cSGiridhar Malavali #define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_INGRESS_LOG 4 1256e98016cSGiridhar Malavali #define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_EGRESS_LOG 5 1266e98016cSGiridhar Malavali #define IC_LOG_DATA_LOG_ID_MESSAGE_TRANSMIT_LOG 6 1276e98016cSGiridhar Malavali #define IC_LOG_DATA_LOG_ID_MESSAGE_RECEIVE_LOG 7 1286e98016cSGiridhar Malavali #define IC_LOG_DATA_LOG_ID_LINK_EVENT_LOG 8 1296e98016cSGiridhar Malavali #define IC_LOG_DATA_LOG_ID_DCX_LOG 9 1306e98016cSGiridhar Malavali 1316e98016cSGiridhar Malavali /* 1326e98016cSGiridhar Malavali * context definitions for QLA84_MGMT_INFO_PORT_STAT 1336e98016cSGiridhar Malavali */ 1346e98016cSGiridhar Malavali #define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT0 0 1356e98016cSGiridhar Malavali #define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT1 1 1366e98016cSGiridhar Malavali #define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT0 2 1376e98016cSGiridhar Malavali #define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT1 3 1386e98016cSGiridhar Malavali #define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT0 4 1396e98016cSGiridhar Malavali #define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT1 5 1406e98016cSGiridhar Malavali 1416e98016cSGiridhar Malavali 1426e98016cSGiridhar Malavali /* 1436e98016cSGiridhar Malavali * context definitions for QLA84_MGMT_INFO_LIF_STAT 1446e98016cSGiridhar Malavali */ 1456e98016cSGiridhar Malavali #define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT0 0 1466e98016cSGiridhar Malavali #define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT1 1 1476e98016cSGiridhar Malavali #define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT0 2 1486e98016cSGiridhar Malavali #define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT1 3 1496e98016cSGiridhar Malavali #define IC_LIF_STATISTICS_LIF_NUMBER_CPU 6 1506e98016cSGiridhar Malavali 1516e98016cSGiridhar Malavali } info; /* for QLA84_MGMT_GET_INFO */ 1526e98016cSGiridhar Malavali } u; 1536e98016cSGiridhar Malavali }; 1546e98016cSGiridhar Malavali 1556e98016cSGiridhar Malavali struct qla84_msg_mgmt { 1566e98016cSGiridhar Malavali uint16_t cmd; 1576e98016cSGiridhar Malavali #define QLA84_MGMT_READ_MEM 0x00 1586e98016cSGiridhar Malavali #define QLA84_MGMT_WRITE_MEM 0x01 1596e98016cSGiridhar Malavali #define QLA84_MGMT_CHNG_CONFIG 0x02 1606e98016cSGiridhar Malavali #define QLA84_MGMT_GET_INFO 0x03 1616e98016cSGiridhar Malavali uint16_t rsrvd; 1626e98016cSGiridhar Malavali struct qla84_mgmt_param mgmtp;/* parameters for cmd */ 1636e98016cSGiridhar Malavali uint32_t len; /* bytes in payload following this struct */ 1645224f790SGustavo A. R. Silva uint8_t payload[]; /* payload for cmd */ 1656e98016cSGiridhar Malavali }; 1666e98016cSGiridhar Malavali 1676e98016cSGiridhar Malavali struct qla_bsg_a84_mgmt { 1686e98016cSGiridhar Malavali struct qla84_msg_mgmt mgmt; 1696e98016cSGiridhar Malavali } __attribute__ ((packed)); 1706e98016cSGiridhar Malavali 1716e98016cSGiridhar Malavali struct qla_scsi_addr { 1726e98016cSGiridhar Malavali uint16_t bus; 1736e98016cSGiridhar Malavali uint16_t target; 1746e98016cSGiridhar Malavali } __attribute__ ((packed)); 1756e98016cSGiridhar Malavali 1766e98016cSGiridhar Malavali struct qla_ext_dest_addr { 1776e98016cSGiridhar Malavali union { 1786e98016cSGiridhar Malavali uint8_t wwnn[8]; 1796e98016cSGiridhar Malavali uint8_t wwpn[8]; 1806e98016cSGiridhar Malavali uint8_t id[4]; 1816e98016cSGiridhar Malavali struct qla_scsi_addr scsi_addr; 1826e98016cSGiridhar Malavali } dest_addr; 1836e98016cSGiridhar Malavali uint16_t dest_type; 1846e98016cSGiridhar Malavali #define EXT_DEF_TYPE_WWPN 2 1856e98016cSGiridhar Malavali uint16_t lun; 1866e98016cSGiridhar Malavali uint16_t padding[2]; 1876e98016cSGiridhar Malavali } __attribute__ ((packed)); 1886e98016cSGiridhar Malavali 1896e98016cSGiridhar Malavali struct qla_port_param { 1906e98016cSGiridhar Malavali struct qla_ext_dest_addr fc_scsi_addr; 1916e98016cSGiridhar Malavali uint16_t mode; 1926e98016cSGiridhar Malavali uint16_t speed; 1936e98016cSGiridhar Malavali } __attribute__ ((packed)); 194697a4bc6SJoe Carnuccio 1959e1c3206SBikash Hazarika struct qla_mbx_passthru { 1969e1c3206SBikash Hazarika uint16_t reserved1[2]; 1979e1c3206SBikash Hazarika uint16_t mbx_in[32]; 1989e1c3206SBikash Hazarika uint16_t mbx_out[32]; 1999e1c3206SBikash Hazarika uint32_t reserved2[16]; 2009e1c3206SBikash Hazarika } __packed; 201697a4bc6SJoe Carnuccio 202697a4bc6SJoe Carnuccio /* FRU VPD */ 203697a4bc6SJoe Carnuccio 204697a4bc6SJoe Carnuccio #define MAX_FRU_SIZE 36 205697a4bc6SJoe Carnuccio 206697a4bc6SJoe Carnuccio struct qla_field_address { 207697a4bc6SJoe Carnuccio uint16_t offset; 208697a4bc6SJoe Carnuccio uint16_t device; 209697a4bc6SJoe Carnuccio uint16_t option; 210697a4bc6SJoe Carnuccio } __packed; 211697a4bc6SJoe Carnuccio 212697a4bc6SJoe Carnuccio struct qla_field_info { 213697a4bc6SJoe Carnuccio uint8_t version[MAX_FRU_SIZE]; 214697a4bc6SJoe Carnuccio } __packed; 215697a4bc6SJoe Carnuccio 216697a4bc6SJoe Carnuccio struct qla_image_version { 217697a4bc6SJoe Carnuccio struct qla_field_address field_address; 218697a4bc6SJoe Carnuccio struct qla_field_info field_info; 219697a4bc6SJoe Carnuccio } __packed; 220697a4bc6SJoe Carnuccio 221697a4bc6SJoe Carnuccio struct qla_image_version_list { 222697a4bc6SJoe Carnuccio uint32_t count; 2235224f790SGustavo A. R. Silva struct qla_image_version version[]; 224697a4bc6SJoe Carnuccio } __packed; 225697a4bc6SJoe Carnuccio 226697a4bc6SJoe Carnuccio struct qla_status_reg { 227697a4bc6SJoe Carnuccio struct qla_field_address field_address; 228697a4bc6SJoe Carnuccio uint8_t status_reg; 229697a4bc6SJoe Carnuccio uint8_t reserved[7]; 230697a4bc6SJoe Carnuccio } __packed; 231697a4bc6SJoe Carnuccio 2329ebb5d9cSJoe Carnuccio struct qla_i2c_access { 2339ebb5d9cSJoe Carnuccio uint16_t device; 2349ebb5d9cSJoe Carnuccio uint16_t offset; 2359ebb5d9cSJoe Carnuccio uint16_t option; 2369ebb5d9cSJoe Carnuccio uint16_t length; 2379ebb5d9cSJoe Carnuccio uint8_t buffer[0x40]; 2389ebb5d9cSJoe Carnuccio } __packed; 2399ebb5d9cSJoe Carnuccio 240db64e930SJoe Carnuccio /* 26xx serdes register interface */ 241db64e930SJoe Carnuccio 242db64e930SJoe Carnuccio /* serdes reg commands */ 243db64e930SJoe Carnuccio #define INT_SC_SERDES_READ_REG 1 244db64e930SJoe Carnuccio #define INT_SC_SERDES_WRITE_REG 2 245db64e930SJoe Carnuccio 246db64e930SJoe Carnuccio struct qla_serdes_reg { 247db64e930SJoe Carnuccio uint16_t cmd; 248db64e930SJoe Carnuccio uint16_t addr; 249db64e930SJoe Carnuccio uint16_t val; 250db64e930SJoe Carnuccio } __packed; 251db64e930SJoe Carnuccio 252e8887c51SJoe Carnuccio struct qla_serdes_reg_ex { 253e8887c51SJoe Carnuccio uint16_t cmd; 254e8887c51SJoe Carnuccio uint32_t addr; 255e8887c51SJoe Carnuccio uint32_t val; 256e8887c51SJoe Carnuccio } __packed; 257e8887c51SJoe Carnuccio 2584243c115SSawan Chandak struct qla_flash_update_caps { 2594243c115SSawan Chandak uint64_t capabilities; 2604243c115SSawan Chandak uint32_t outage_duration; 2614243c115SSawan Chandak uint8_t reserved[20]; 2624243c115SSawan Chandak } __packed; 263969a6199SSawan Chandak 264969a6199SSawan Chandak /* BB_CR Status */ 265969a6199SSawan Chandak #define QLA_BBCR_STATUS_DISABLED 0 266969a6199SSawan Chandak #define QLA_BBCR_STATUS_ENABLED 1 267c73191b8SHarish Zunjarrao #define QLA_BBCR_STATUS_UNKNOWN 2 268969a6199SSawan Chandak 269969a6199SSawan Chandak /* BB_CR State */ 270969a6199SSawan Chandak #define QLA_BBCR_STATE_OFFLINE 0 271969a6199SSawan Chandak #define QLA_BBCR_STATE_ONLINE 1 272969a6199SSawan Chandak 273969a6199SSawan Chandak /* BB_CR Offline Reason Code */ 274969a6199SSawan Chandak #define QLA_BBCR_REASON_PORT_SPEED 1 275969a6199SSawan Chandak #define QLA_BBCR_REASON_PEER_PORT 2 276969a6199SSawan Chandak #define QLA_BBCR_REASON_SWITCH 3 277969a6199SSawan Chandak #define QLA_BBCR_REASON_LOGIN_REJECT 4 278969a6199SSawan Chandak 279969a6199SSawan Chandak struct qla_bbcr_data { 280969a6199SSawan Chandak uint8_t status; /* 1 - enabled, 0 - Disabled */ 281969a6199SSawan Chandak uint8_t state; /* 1 - online, 0 - offline */ 282969a6199SSawan Chandak uint8_t configured_bbscn; /* 0-15 */ 283969a6199SSawan Chandak uint8_t negotiated_bbscn; /* 0-15 */ 284969a6199SSawan Chandak uint8_t offline_reason_code; 285c73191b8SHarish Zunjarrao uint16_t mbx1; /* Port state */ 286c73191b8SHarish Zunjarrao uint8_t reserved[9]; 287969a6199SSawan Chandak } __packed; 288ec891462SJoe Carnuccio 289ec891462SJoe Carnuccio struct qla_dport_diag { 290ec891462SJoe Carnuccio uint16_t options; 291ec891462SJoe Carnuccio uint32_t buf[16]; 292ec891462SJoe Carnuccio uint8_t unused[62]; 293ec891462SJoe Carnuccio } __packed; 294ec891462SJoe Carnuccio 295476da8faSBikash Hazarika #define QLA_GET_DPORT_RESULT_V2 0 /* Get Result */ 296476da8faSBikash Hazarika #define QLA_RESTART_DPORT_TEST_V2 1 /* Restart test */ 297476da8faSBikash Hazarika #define QLA_START_DPORT_TEST_V2 2 /* Start test */ 298476da8faSBikash Hazarika struct qla_dport_diag_v2 { 299476da8faSBikash Hazarika uint16_t options; 300476da8faSBikash Hazarika uint16_t mbx1; 301476da8faSBikash Hazarika uint16_t mbx2; 302476da8faSBikash Hazarika uint8_t unused[58]; 303476da8faSBikash Hazarika uint8_t buf[1024]; /* Test Result */ 304476da8faSBikash Hazarika } __packed; 305476da8faSBikash Hazarika 306ec891462SJoe Carnuccio /* D_Port options */ 307ec891462SJoe Carnuccio #define QLA_DPORT_RESULT 0x0 308ec891462SJoe Carnuccio #define QLA_DPORT_START 0x2 309ec891462SJoe Carnuccio 3105fa8774cSJoe Carnuccio /* active images in flash */ 3115fa8774cSJoe Carnuccio struct qla_active_regions { 3125fa8774cSJoe Carnuccio uint8_t global_image; 3135fa8774cSJoe Carnuccio uint8_t board_config; 3145fa8774cSJoe Carnuccio uint8_t vpd_nvram; 3155fa8774cSJoe Carnuccio uint8_t npiv_config_0_1; 3165fa8774cSJoe Carnuccio uint8_t npiv_config_2_3; 317*d9ba85efSAnil Gurumurthy uint8_t nvme_params; 318*d9ba85efSAnil Gurumurthy uint8_t reserved[31]; 3195fa8774cSJoe Carnuccio } __packed; 3205fa8774cSJoe Carnuccio 3217ebb336eSQuinn Tran #include "qla_edif_bsg.h" 3227ebb336eSQuinn Tran 3236e98016cSGiridhar Malavali #endif 324