1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2004-2006 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 #define FDMI_DID 0xfffffaU 22 #define NameServer_DID 0xfffffcU 23 #define SCR_DID 0xfffffdU 24 #define Fabric_DID 0xfffffeU 25 #define Bcast_DID 0xffffffU 26 #define Mask_DID 0xffffffU 27 #define CT_DID_MASK 0xffff00U 28 #define Fabric_DID_MASK 0xfff000U 29 #define WELL_KNOWN_DID_MASK 0xfffff0U 30 31 #define PT2PT_LocalID 1 32 #define PT2PT_RemoteID 2 33 34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 36 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */ 37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 38 39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 40 0 */ 41 42 #define FCELSSIZE 1024 /* maximum ELS transfer size */ 43 44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 45 #define LPFC_IP_RING 1 /* ring 1 for IP commands */ 46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 47 #define LPFC_FCP_NEXT_RING 3 48 49 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 50 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 51 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 IP command ring entries */ 52 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 IP response ring entries */ 53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 55 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 56 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 57 #define SLI2_IOCB_CMD_R3_ENTRIES 0 58 #define SLI2_IOCB_RSP_R3_ENTRIES 0 59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 61 62 /* Common Transport structures and definitions */ 63 64 union CtRevisionId { 65 /* Structure is in Big Endian format */ 66 struct { 67 uint32_t Revision:8; 68 uint32_t InId:24; 69 } bits; 70 uint32_t word; 71 }; 72 73 union CtCommandResponse { 74 /* Structure is in Big Endian format */ 75 struct { 76 uint32_t CmdRsp:16; 77 uint32_t Size:16; 78 } bits; 79 uint32_t word; 80 }; 81 82 struct lpfc_sli_ct_request { 83 /* Structure is in Big Endian format */ 84 union CtRevisionId RevisionId; 85 uint8_t FsType; 86 uint8_t FsSubType; 87 uint8_t Options; 88 uint8_t Rsrvd1; 89 union CtCommandResponse CommandResponse; 90 uint8_t Rsrvd2; 91 uint8_t ReasonCode; 92 uint8_t Explanation; 93 uint8_t VendorUnique; 94 95 union { 96 uint32_t PortID; 97 struct gid { 98 uint8_t PortType; /* for GID_PT requests */ 99 uint8_t DomainScope; 100 uint8_t AreaScope; 101 uint8_t Fc4Type; /* for GID_FT requests */ 102 } gid; 103 struct rft { 104 uint32_t PortId; /* For RFT_ID requests */ 105 106 #ifdef __BIG_ENDIAN_BITFIELD 107 uint32_t rsvd0:16; 108 uint32_t rsvd1:7; 109 uint32_t fcpReg:1; /* Type 8 */ 110 uint32_t rsvd2:2; 111 uint32_t ipReg:1; /* Type 5 */ 112 uint32_t rsvd3:5; 113 #else /* __LITTLE_ENDIAN_BITFIELD */ 114 uint32_t rsvd0:16; 115 uint32_t fcpReg:1; /* Type 8 */ 116 uint32_t rsvd1:7; 117 uint32_t rsvd3:5; 118 uint32_t ipReg:1; /* Type 5 */ 119 uint32_t rsvd2:2; 120 #endif 121 122 uint32_t rsvd[7]; 123 } rft; 124 struct rnn { 125 uint32_t PortId; /* For RNN_ID requests */ 126 uint8_t wwnn[8]; 127 } rnn; 128 struct rsnn { /* For RSNN_ID requests */ 129 uint8_t wwnn[8]; 130 uint8_t len; 131 uint8_t symbname[255]; 132 } rsnn; 133 } un; 134 }; 135 136 #define SLI_CT_REVISION 1 137 #define GID_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 260) 138 #define RFT_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 228) 139 #define RNN_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 252) 140 #define RSNN_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request)) 141 142 /* 143 * FsType Definitions 144 */ 145 146 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 147 #define SLI_CT_TIME_SERVICE 0xFB 148 #define SLI_CT_DIRECTORY_SERVICE 0xFC 149 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 150 151 /* 152 * Directory Service Subtypes 153 */ 154 155 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 156 157 /* 158 * Response Codes 159 */ 160 161 #define SLI_CT_RESPONSE_FS_RJT 0x8001 162 #define SLI_CT_RESPONSE_FS_ACC 0x8002 163 164 /* 165 * Reason Codes 166 */ 167 168 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 169 #define SLI_CT_INVALID_COMMAND 0x01 170 #define SLI_CT_INVALID_VERSION 0x02 171 #define SLI_CT_LOGICAL_ERROR 0x03 172 #define SLI_CT_INVALID_IU_SIZE 0x04 173 #define SLI_CT_LOGICAL_BUSY 0x05 174 #define SLI_CT_PROTOCOL_ERROR 0x07 175 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 176 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 177 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 178 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 179 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 180 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 181 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 182 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 183 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 184 #define SLI_CT_VENDOR_UNIQUE 0xff 185 186 /* 187 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 188 */ 189 190 #define SLI_CT_NO_PORT_ID 0x01 191 #define SLI_CT_NO_PORT_NAME 0x02 192 #define SLI_CT_NO_NODE_NAME 0x03 193 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 194 #define SLI_CT_NO_IP_ADDRESS 0x05 195 #define SLI_CT_NO_IPA 0x06 196 #define SLI_CT_NO_FC4_TYPES 0x07 197 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 198 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 199 #define SLI_CT_NO_PORT_TYPE 0x0A 200 #define SLI_CT_ACCESS_DENIED 0x10 201 #define SLI_CT_INVALID_PORT_ID 0x11 202 #define SLI_CT_DATABASE_EMPTY 0x12 203 204 /* 205 * Name Server Command Codes 206 */ 207 208 #define SLI_CTNS_GA_NXT 0x0100 209 #define SLI_CTNS_GPN_ID 0x0112 210 #define SLI_CTNS_GNN_ID 0x0113 211 #define SLI_CTNS_GCS_ID 0x0114 212 #define SLI_CTNS_GFT_ID 0x0117 213 #define SLI_CTNS_GSPN_ID 0x0118 214 #define SLI_CTNS_GPT_ID 0x011A 215 #define SLI_CTNS_GID_PN 0x0121 216 #define SLI_CTNS_GID_NN 0x0131 217 #define SLI_CTNS_GIP_NN 0x0135 218 #define SLI_CTNS_GIPA_NN 0x0136 219 #define SLI_CTNS_GSNN_NN 0x0139 220 #define SLI_CTNS_GNN_IP 0x0153 221 #define SLI_CTNS_GIPA_IP 0x0156 222 #define SLI_CTNS_GID_FT 0x0171 223 #define SLI_CTNS_GID_PT 0x01A1 224 #define SLI_CTNS_RPN_ID 0x0212 225 #define SLI_CTNS_RNN_ID 0x0213 226 #define SLI_CTNS_RCS_ID 0x0214 227 #define SLI_CTNS_RFT_ID 0x0217 228 #define SLI_CTNS_RSPN_ID 0x0218 229 #define SLI_CTNS_RPT_ID 0x021A 230 #define SLI_CTNS_RIP_NN 0x0235 231 #define SLI_CTNS_RIPA_NN 0x0236 232 #define SLI_CTNS_RSNN_NN 0x0239 233 #define SLI_CTNS_DA_ID 0x0300 234 235 /* 236 * Port Types 237 */ 238 239 #define SLI_CTPT_N_PORT 0x01 240 #define SLI_CTPT_NL_PORT 0x02 241 #define SLI_CTPT_FNL_PORT 0x03 242 #define SLI_CTPT_IP 0x04 243 #define SLI_CTPT_FCP 0x08 244 #define SLI_CTPT_NX_PORT 0x7F 245 #define SLI_CTPT_F_PORT 0x81 246 #define SLI_CTPT_FL_PORT 0x82 247 #define SLI_CTPT_E_PORT 0x84 248 249 #define SLI_CT_LAST_ENTRY 0x80000000 250 251 /* Fibre Channel Service Parameter definitions */ 252 253 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 254 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 255 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 256 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 257 258 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 259 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 260 #define FC_PH3 0x20 /* FC-PH-3 version */ 261 262 #define FF_FRAME_SIZE 2048 263 264 struct lpfc_name { 265 union { 266 struct { 267 #ifdef __BIG_ENDIAN_BITFIELD 268 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 269 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 270 8:11 of IEEE ext */ 271 #else /* __LITTLE_ENDIAN_BITFIELD */ 272 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 273 8:11 of IEEE ext */ 274 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 275 #endif 276 277 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 278 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 279 #define NAME_FC_TYPE 0x3 /* FC native name type */ 280 #define NAME_IP_TYPE 0x4 /* IP address */ 281 #define NAME_CCITT_TYPE 0xC 282 #define NAME_CCITT_GR_TYPE 0xE 283 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE 284 extended Lsb */ 285 uint8_t IEEE[6]; /* FC IEEE address */ 286 } s; 287 uint8_t wwn[8]; 288 } u; 289 }; 290 291 struct csp { 292 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 293 uint8_t fcphLow; 294 uint8_t bbCreditMsb; 295 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 296 297 #ifdef __BIG_ENDIAN_BITFIELD 298 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */ 299 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 300 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */ 301 uint16_t fPort:1; /* FC Word 1, bit 28 */ 302 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 303 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 304 uint16_t multicast:1; /* FC Word 1, bit 25 */ 305 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 306 307 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 308 uint16_t simplex:1; /* FC Word 1, bit 22 */ 309 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 310 uint16_t dhd:1; /* FC Word 1, bit 18 */ 311 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 312 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 313 #else /* __LITTLE_ENDIAN_BITFIELD */ 314 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 315 uint16_t multicast:1; /* FC Word 1, bit 25 */ 316 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 317 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 318 uint16_t fPort:1; /* FC Word 1, bit 28 */ 319 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */ 320 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 321 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */ 322 323 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 324 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 325 uint16_t dhd:1; /* FC Word 1, bit 18 */ 326 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 327 uint16_t simplex:1; /* FC Word 1, bit 22 */ 328 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 329 #endif 330 331 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 332 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 333 union { 334 struct { 335 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 336 337 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 338 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 339 340 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 341 } nPort; 342 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 343 } w2; 344 345 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 346 }; 347 348 struct class_parms { 349 #ifdef __BIG_ENDIAN_BITFIELD 350 uint8_t classValid:1; /* FC Word 0, bit 31 */ 351 uint8_t intermix:1; /* FC Word 0, bit 30 */ 352 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 353 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 354 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 355 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 356 #else /* __LITTLE_ENDIAN_BITFIELD */ 357 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 358 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 359 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 360 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 361 uint8_t intermix:1; /* FC Word 0, bit 30 */ 362 uint8_t classValid:1; /* FC Word 0, bit 31 */ 363 364 #endif 365 366 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 367 368 #ifdef __BIG_ENDIAN_BITFIELD 369 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 370 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 371 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 372 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 373 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 374 #else /* __LITTLE_ENDIAN_BITFIELD */ 375 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 376 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 377 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 378 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 379 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 380 #endif 381 382 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 383 384 #ifdef __BIG_ENDIAN_BITFIELD 385 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 386 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 387 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 388 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 389 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 390 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 391 #else /* __LITTLE_ENDIAN_BITFIELD */ 392 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 393 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 394 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 395 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 396 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 397 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 398 #endif 399 400 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 401 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 402 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 403 404 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 405 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 406 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 407 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 408 409 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 410 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 411 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 412 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 413 }; 414 415 struct serv_parm { /* Structure is in Big Endian format */ 416 struct csp cmn; 417 struct lpfc_name portName; 418 struct lpfc_name nodeName; 419 struct class_parms cls1; 420 struct class_parms cls2; 421 struct class_parms cls3; 422 struct class_parms cls4; 423 uint8_t vendorVersion[16]; 424 }; 425 426 /* 427 * Extended Link Service LS_COMMAND codes (Payload Word 0) 428 */ 429 #ifdef __BIG_ENDIAN_BITFIELD 430 #define ELS_CMD_MASK 0xffff0000 431 #define ELS_RSP_MASK 0xff000000 432 #define ELS_CMD_LS_RJT 0x01000000 433 #define ELS_CMD_ACC 0x02000000 434 #define ELS_CMD_PLOGI 0x03000000 435 #define ELS_CMD_FLOGI 0x04000000 436 #define ELS_CMD_LOGO 0x05000000 437 #define ELS_CMD_ABTX 0x06000000 438 #define ELS_CMD_RCS 0x07000000 439 #define ELS_CMD_RES 0x08000000 440 #define ELS_CMD_RSS 0x09000000 441 #define ELS_CMD_RSI 0x0A000000 442 #define ELS_CMD_ESTS 0x0B000000 443 #define ELS_CMD_ESTC 0x0C000000 444 #define ELS_CMD_ADVC 0x0D000000 445 #define ELS_CMD_RTV 0x0E000000 446 #define ELS_CMD_RLS 0x0F000000 447 #define ELS_CMD_ECHO 0x10000000 448 #define ELS_CMD_TEST 0x11000000 449 #define ELS_CMD_RRQ 0x12000000 450 #define ELS_CMD_PRLI 0x20100014 451 #define ELS_CMD_PRLO 0x21100014 452 #define ELS_CMD_PDISC 0x50000000 453 #define ELS_CMD_FDISC 0x51000000 454 #define ELS_CMD_ADISC 0x52000000 455 #define ELS_CMD_FARP 0x54000000 456 #define ELS_CMD_FARPR 0x55000000 457 #define ELS_CMD_RPS 0x56000000 458 #define ELS_CMD_RPL 0x57000000 459 #define ELS_CMD_FAN 0x60000000 460 #define ELS_CMD_RSCN 0x61040000 461 #define ELS_CMD_SCR 0x62000000 462 #define ELS_CMD_RNID 0x78000000 463 #define ELS_CMD_LIRR 0x7A000000 464 #else /* __LITTLE_ENDIAN_BITFIELD */ 465 #define ELS_CMD_MASK 0xffff 466 #define ELS_RSP_MASK 0xff 467 #define ELS_CMD_LS_RJT 0x01 468 #define ELS_CMD_ACC 0x02 469 #define ELS_CMD_PLOGI 0x03 470 #define ELS_CMD_FLOGI 0x04 471 #define ELS_CMD_LOGO 0x05 472 #define ELS_CMD_ABTX 0x06 473 #define ELS_CMD_RCS 0x07 474 #define ELS_CMD_RES 0x08 475 #define ELS_CMD_RSS 0x09 476 #define ELS_CMD_RSI 0x0A 477 #define ELS_CMD_ESTS 0x0B 478 #define ELS_CMD_ESTC 0x0C 479 #define ELS_CMD_ADVC 0x0D 480 #define ELS_CMD_RTV 0x0E 481 #define ELS_CMD_RLS 0x0F 482 #define ELS_CMD_ECHO 0x10 483 #define ELS_CMD_TEST 0x11 484 #define ELS_CMD_RRQ 0x12 485 #define ELS_CMD_PRLI 0x14001020 486 #define ELS_CMD_PRLO 0x14001021 487 #define ELS_CMD_PDISC 0x50 488 #define ELS_CMD_FDISC 0x51 489 #define ELS_CMD_ADISC 0x52 490 #define ELS_CMD_FARP 0x54 491 #define ELS_CMD_FARPR 0x55 492 #define ELS_CMD_RPS 0x56 493 #define ELS_CMD_RPL 0x57 494 #define ELS_CMD_FAN 0x60 495 #define ELS_CMD_RSCN 0x0461 496 #define ELS_CMD_SCR 0x62 497 #define ELS_CMD_RNID 0x78 498 #define ELS_CMD_LIRR 0x7A 499 #endif 500 501 /* 502 * LS_RJT Payload Definition 503 */ 504 505 struct ls_rjt { /* Structure is in Big Endian format */ 506 union { 507 uint32_t lsRjtError; 508 struct { 509 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 510 511 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 512 /* LS_RJT reason codes */ 513 #define LSRJT_INVALID_CMD 0x01 514 #define LSRJT_LOGICAL_ERR 0x03 515 #define LSRJT_LOGICAL_BSY 0x05 516 #define LSRJT_PROTOCOL_ERR 0x07 517 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 518 #define LSRJT_CMD_UNSUPPORTED 0x0B 519 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 520 521 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 522 /* LS_RJT reason explanation */ 523 #define LSEXP_NOTHING_MORE 0x00 524 #define LSEXP_SPARM_OPTIONS 0x01 525 #define LSEXP_SPARM_ICTL 0x03 526 #define LSEXP_SPARM_RCTL 0x05 527 #define LSEXP_SPARM_RCV_SIZE 0x07 528 #define LSEXP_SPARM_CONCUR_SEQ 0x09 529 #define LSEXP_SPARM_CREDIT 0x0B 530 #define LSEXP_INVALID_PNAME 0x0D 531 #define LSEXP_INVALID_NNAME 0x0E 532 #define LSEXP_INVALID_CSP 0x0F 533 #define LSEXP_INVALID_ASSOC_HDR 0x11 534 #define LSEXP_ASSOC_HDR_REQ 0x13 535 #define LSEXP_INVALID_O_SID 0x15 536 #define LSEXP_INVALID_OX_RX 0x17 537 #define LSEXP_CMD_IN_PROGRESS 0x19 538 #define LSEXP_INVALID_NPORT_ID 0x1F 539 #define LSEXP_INVALID_SEQ_ID 0x21 540 #define LSEXP_INVALID_XCHG 0x23 541 #define LSEXP_INACTIVE_XCHG 0x25 542 #define LSEXP_RQ_REQUIRED 0x27 543 #define LSEXP_OUT_OF_RESOURCE 0x29 544 #define LSEXP_CANT_GIVE_DATA 0x2A 545 #define LSEXP_REQ_UNSUPPORTED 0x2C 546 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 547 } b; 548 } un; 549 }; 550 551 /* 552 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 553 */ 554 555 typedef struct _LOGO { /* Structure is in Big Endian format */ 556 union { 557 uint32_t nPortId32; /* Access nPortId as a word */ 558 struct { 559 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 560 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 561 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 562 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 563 } b; 564 } un; 565 struct lpfc_name portName; /* N_port name field */ 566 } LOGO; 567 568 /* 569 * FCP Login (PRLI Request / ACC) Payload Definition 570 */ 571 572 #define PRLX_PAGE_LEN 0x10 573 #define TPRLO_PAGE_LEN 0x14 574 575 typedef struct _PRLI { /* Structure is in Big Endian format */ 576 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 577 578 #define PRLI_FCP_TYPE 0x08 579 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 580 581 #ifdef __BIG_ENDIAN_BITFIELD 582 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 583 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 584 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 585 586 /* ACC = imagePairEstablished */ 587 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 588 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 589 #else /* __LITTLE_ENDIAN_BITFIELD */ 590 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 591 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 592 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 593 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 594 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 595 /* ACC = imagePairEstablished */ 596 #endif 597 598 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 599 #define PRLI_NO_RESOURCES 0x2 600 #define PRLI_INIT_INCOMPLETE 0x3 601 #define PRLI_NO_SUCH_PA 0x4 602 #define PRLI_PREDEF_CONFIG 0x5 603 #define PRLI_PARTIAL_SUCCESS 0x6 604 #define PRLI_INVALID_PAGE_CNT 0x7 605 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 606 607 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 608 609 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 610 611 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 612 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 613 614 #ifdef __BIG_ENDIAN_BITFIELD 615 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 616 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 617 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 618 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 619 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 620 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 621 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 622 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 623 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 624 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 625 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 626 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 627 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 628 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 629 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 630 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 631 #else /* __LITTLE_ENDIAN_BITFIELD */ 632 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 633 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 634 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 635 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 636 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 637 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 638 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 639 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 640 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 641 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 642 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 643 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 644 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 645 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 646 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 647 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 648 #endif 649 } PRLI; 650 651 /* 652 * FCP Logout (PRLO Request / ACC) Payload Definition 653 */ 654 655 typedef struct _PRLO { /* Structure is in Big Endian format */ 656 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 657 658 #define PRLO_FCP_TYPE 0x08 659 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 660 661 #ifdef __BIG_ENDIAN_BITFIELD 662 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 663 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 664 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 665 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 666 #else /* __LITTLE_ENDIAN_BITFIELD */ 667 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 668 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 669 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 670 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 671 #endif 672 673 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 674 #define PRLO_NO_SUCH_IMAGE 0x4 675 #define PRLO_INVALID_PAGE_CNT 0x7 676 677 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 678 679 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 680 681 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 682 683 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 684 } PRLO; 685 686 typedef struct _ADISC { /* Structure is in Big Endian format */ 687 uint32_t hardAL_PA; 688 struct lpfc_name portName; 689 struct lpfc_name nodeName; 690 uint32_t DID; 691 } ADISC; 692 693 typedef struct _FARP { /* Structure is in Big Endian format */ 694 uint32_t Mflags:8; 695 uint32_t Odid:24; 696 #define FARP_NO_ACTION 0 /* FARP information enclosed, no 697 action */ 698 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 699 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 700 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 701 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 702 supported */ 703 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 704 supported */ 705 uint32_t Rflags:8; 706 uint32_t Rdid:24; 707 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 708 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 709 struct lpfc_name OportName; 710 struct lpfc_name OnodeName; 711 struct lpfc_name RportName; 712 struct lpfc_name RnodeName; 713 uint8_t Oipaddr[16]; 714 uint8_t Ripaddr[16]; 715 } FARP; 716 717 typedef struct _FAN { /* Structure is in Big Endian format */ 718 uint32_t Fdid; 719 struct lpfc_name FportName; 720 struct lpfc_name FnodeName; 721 } FAN; 722 723 typedef struct _SCR { /* Structure is in Big Endian format */ 724 uint8_t resvd1; 725 uint8_t resvd2; 726 uint8_t resvd3; 727 uint8_t Function; 728 #define SCR_FUNC_FABRIC 0x01 729 #define SCR_FUNC_NPORT 0x02 730 #define SCR_FUNC_FULL 0x03 731 #define SCR_CLEAR 0xff 732 } SCR; 733 734 typedef struct _RNID_TOP_DISC { 735 struct lpfc_name portName; 736 uint8_t resvd[8]; 737 uint32_t unitType; 738 #define RNID_HBA 0x7 739 #define RNID_HOST 0xa 740 #define RNID_DRIVER 0xd 741 uint32_t physPort; 742 uint32_t attachedNodes; 743 uint16_t ipVersion; 744 #define RNID_IPV4 0x1 745 #define RNID_IPV6 0x2 746 uint16_t UDPport; 747 uint8_t ipAddr[16]; 748 uint16_t resvd1; 749 uint16_t flags; 750 #define RNID_TD_SUPPORT 0x1 751 #define RNID_LP_VALID 0x2 752 } RNID_TOP_DISC; 753 754 typedef struct _RNID { /* Structure is in Big Endian format */ 755 uint8_t Format; 756 #define RNID_TOPOLOGY_DISC 0xdf 757 uint8_t CommonLen; 758 uint8_t resvd1; 759 uint8_t SpecificLen; 760 struct lpfc_name portName; 761 struct lpfc_name nodeName; 762 union { 763 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 764 } un; 765 } RNID; 766 767 typedef struct _RPS { /* Structure is in Big Endian format */ 768 union { 769 uint32_t portNum; 770 struct lpfc_name portName; 771 } un; 772 } RPS; 773 774 typedef struct _RPS_RSP { /* Structure is in Big Endian format */ 775 uint16_t rsvd1; 776 uint16_t portStatus; 777 uint32_t linkFailureCnt; 778 uint32_t lossSyncCnt; 779 uint32_t lossSignalCnt; 780 uint32_t primSeqErrCnt; 781 uint32_t invalidXmitWord; 782 uint32_t crcCnt; 783 } RPS_RSP; 784 785 typedef struct _RPL { /* Structure is in Big Endian format */ 786 uint32_t maxsize; 787 uint32_t index; 788 } RPL; 789 790 typedef struct _PORT_NUM_BLK { 791 uint32_t portNum; 792 uint32_t portID; 793 struct lpfc_name portName; 794 } PORT_NUM_BLK; 795 796 typedef struct _RPL_RSP { /* Structure is in Big Endian format */ 797 uint32_t listLen; 798 uint32_t index; 799 PORT_NUM_BLK port_num_blk; 800 } RPL_RSP; 801 802 /* This is used for RSCN command */ 803 typedef struct _D_ID { /* Structure is in Big Endian format */ 804 union { 805 uint32_t word; 806 struct { 807 #ifdef __BIG_ENDIAN_BITFIELD 808 uint8_t resv; 809 uint8_t domain; 810 uint8_t area; 811 uint8_t id; 812 #else /* __LITTLE_ENDIAN_BITFIELD */ 813 uint8_t id; 814 uint8_t area; 815 uint8_t domain; 816 uint8_t resv; 817 #endif 818 } b; 819 } un; 820 } D_ID; 821 822 /* 823 * Structure to define all ELS Payload types 824 */ 825 826 typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 827 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 828 uint8_t elsByte1; 829 uint8_t elsByte2; 830 uint8_t elsByte3; 831 union { 832 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 833 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 834 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 835 PRLI prli; /* Payload for PRLI/ACC */ 836 PRLO prlo; /* Payload for PRLO/ACC */ 837 ADISC adisc; /* Payload for ADISC/ACC */ 838 FARP farp; /* Payload for FARP/ACC */ 839 FAN fan; /* Payload for FAN */ 840 SCR scr; /* Payload for SCR/ACC */ 841 RNID rnid; /* Payload for RNID */ 842 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 843 } un; 844 } ELS_PKT; 845 846 /* 847 * FDMI 848 * HBA MAnagement Operations Command Codes 849 */ 850 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 851 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 852 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 853 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 854 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 855 #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */ 856 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 857 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 858 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 859 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 860 861 /* 862 * Management Service Subtypes 863 */ 864 #define SLI_CT_FDMI_Subtypes 0x10 865 866 /* 867 * HBA Management Service Reject Code 868 */ 869 #define REJECT_CODE 0x9 /* Unable to perform command request */ 870 871 /* 872 * HBA Management Service Reject Reason Code 873 * Please refer to the Reason Codes above 874 */ 875 876 /* 877 * HBA Attribute Types 878 */ 879 #define NODE_NAME 0x1 880 #define MANUFACTURER 0x2 881 #define SERIAL_NUMBER 0x3 882 #define MODEL 0x4 883 #define MODEL_DESCRIPTION 0x5 884 #define HARDWARE_VERSION 0x6 885 #define DRIVER_VERSION 0x7 886 #define OPTION_ROM_VERSION 0x8 887 #define FIRMWARE_VERSION 0x9 888 #define OS_NAME_VERSION 0xa 889 #define MAX_CT_PAYLOAD_LEN 0xb 890 891 /* 892 * Port Attrubute Types 893 */ 894 #define SUPPORTED_FC4_TYPES 0x1 895 #define SUPPORTED_SPEED 0x2 896 #define PORT_SPEED 0x3 897 #define MAX_FRAME_SIZE 0x4 898 #define OS_DEVICE_NAME 0x5 899 #define HOST_NAME 0x6 900 901 union AttributesDef { 902 /* Structure is in Big Endian format */ 903 struct { 904 uint32_t AttrType:16; 905 uint32_t AttrLen:16; 906 } bits; 907 uint32_t word; 908 }; 909 910 911 /* 912 * HBA Attribute Entry (8 - 260 bytes) 913 */ 914 typedef struct { 915 union AttributesDef ad; 916 union { 917 uint32_t VendorSpecific; 918 uint8_t Manufacturer[64]; 919 uint8_t SerialNumber[64]; 920 uint8_t Model[256]; 921 uint8_t ModelDescription[256]; 922 uint8_t HardwareVersion[256]; 923 uint8_t DriverVersion[256]; 924 uint8_t OptionROMVersion[256]; 925 uint8_t FirmwareVersion[256]; 926 struct lpfc_name NodeName; 927 uint8_t SupportFC4Types[32]; 928 uint32_t SupportSpeed; 929 uint32_t PortSpeed; 930 uint32_t MaxFrameSize; 931 uint8_t OsDeviceName[256]; 932 uint8_t OsNameVersion[256]; 933 uint32_t MaxCTPayloadLen; 934 uint8_t HostName[256]; 935 } un; 936 } ATTRIBUTE_ENTRY; 937 938 /* 939 * HBA Attribute Block 940 */ 941 typedef struct { 942 uint32_t EntryCnt; /* Number of HBA attribute entries */ 943 ATTRIBUTE_ENTRY Entry; /* Variable-length array */ 944 } ATTRIBUTE_BLOCK; 945 946 /* 947 * Port Entry 948 */ 949 typedef struct { 950 struct lpfc_name PortName; 951 } PORT_ENTRY; 952 953 /* 954 * HBA Identifier 955 */ 956 typedef struct { 957 struct lpfc_name PortName; 958 } HBA_IDENTIFIER; 959 960 /* 961 * Registered Port List Format 962 */ 963 typedef struct { 964 uint32_t EntryCnt; 965 PORT_ENTRY pe; /* Variable-length array */ 966 } REG_PORT_LIST; 967 968 /* 969 * Register HBA(RHBA) 970 */ 971 typedef struct { 972 HBA_IDENTIFIER hi; 973 REG_PORT_LIST rpl; /* variable-length array */ 974 /* ATTRIBUTE_BLOCK ab; */ 975 } REG_HBA; 976 977 /* 978 * Register HBA Attributes (RHAT) 979 */ 980 typedef struct { 981 struct lpfc_name HBA_PortName; 982 ATTRIBUTE_BLOCK ab; 983 } REG_HBA_ATTRIBUTE; 984 985 /* 986 * Register Port Attributes (RPA) 987 */ 988 typedef struct { 989 struct lpfc_name PortName; 990 ATTRIBUTE_BLOCK ab; 991 } REG_PORT_ATTRIBUTE; 992 993 /* 994 * Get Registered HBA List (GRHL) Accept Payload Format 995 */ 996 typedef struct { 997 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */ 998 struct lpfc_name HBA_PortName; /* Variable-length array */ 999 } GRHL_ACC_PAYLOAD; 1000 1001 /* 1002 * Get Registered Port List (GRPL) Accept Payload Format 1003 */ 1004 typedef struct { 1005 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */ 1006 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */ 1007 } GRPL_ACC_PAYLOAD; 1008 1009 /* 1010 * Get Port Attributes (GPAT) Accept Payload Format 1011 */ 1012 1013 typedef struct { 1014 ATTRIBUTE_BLOCK pab; 1015 } GPAT_ACC_PAYLOAD; 1016 1017 1018 /* 1019 * Begin HBA configuration parameters. 1020 * The PCI configuration register BAR assignments are: 1021 * BAR0, offset 0x10 - SLIM base memory address 1022 * BAR1, offset 0x14 - SLIM base memory high address 1023 * BAR2, offset 0x18 - REGISTER base memory address 1024 * BAR3, offset 0x1c - REGISTER base memory high address 1025 * BAR4, offset 0x20 - BIU I/O registers 1026 * BAR5, offset 0x24 - REGISTER base io high address 1027 */ 1028 1029 /* Number of rings currently used and available. */ 1030 #define MAX_CONFIGURED_RINGS 3 1031 #define MAX_RINGS 4 1032 1033 /* IOCB / Mailbox is owned by FireFly */ 1034 #define OWN_CHIP 1 1035 1036 /* IOCB / Mailbox is owned by Host */ 1037 #define OWN_HOST 0 1038 1039 /* Number of 4-byte words in an IOCB. */ 1040 #define IOCB_WORD_SZ 8 1041 1042 /* defines for type field in fc header */ 1043 #define FC_ELS_DATA 0x1 1044 #define FC_LLC_SNAP 0x5 1045 #define FC_FCP_DATA 0x8 1046 #define FC_COMMON_TRANSPORT_ULP 0x20 1047 1048 /* defines for rctl field in fc header */ 1049 #define FC_DEV_DATA 0x0 1050 #define FC_UNSOL_CTL 0x2 1051 #define FC_SOL_CTL 0x3 1052 #define FC_UNSOL_DATA 0x4 1053 #define FC_FCP_CMND 0x6 1054 #define FC_ELS_REQ 0x22 1055 #define FC_ELS_RSP 0x23 1056 1057 /* network headers for Dfctl field */ 1058 #define FC_NET_HDR 0x20 1059 1060 /* Start FireFly Register definitions */ 1061 #define PCI_VENDOR_ID_EMULEX 0x10df 1062 #define PCI_DEVICE_ID_FIREFLY 0x1ae5 1063 #define PCI_DEVICE_ID_RFLY 0xf095 1064 #define PCI_DEVICE_ID_PFLY 0xf098 1065 #define PCI_DEVICE_ID_LP101 0xf0a1 1066 #define PCI_DEVICE_ID_TFLY 0xf0a5 1067 #define PCI_DEVICE_ID_BSMB 0xf0d1 1068 #define PCI_DEVICE_ID_BMID 0xf0d5 1069 #define PCI_DEVICE_ID_ZSMB 0xf0e1 1070 #define PCI_DEVICE_ID_ZMID 0xf0e5 1071 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5 1072 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 1073 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 1074 #define PCI_DEVICE_ID_SUPERFLY 0xf700 1075 #define PCI_DEVICE_ID_DRAGONFLY 0xf800 1076 #define PCI_DEVICE_ID_CENTAUR 0xf900 1077 #define PCI_DEVICE_ID_PEGASUS 0xf980 1078 #define PCI_DEVICE_ID_THOR 0xfa00 1079 #define PCI_DEVICE_ID_VIPER 0xfb00 1080 #define PCI_DEVICE_ID_LP10000S 0xfc00 1081 #define PCI_DEVICE_ID_LP11000S 0xfc10 1082 #define PCI_DEVICE_ID_LPE11000S 0xfc20 1083 #define PCI_DEVICE_ID_HELIOS 0xfd00 1084 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 1085 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 1086 #define PCI_DEVICE_ID_ZEPHYR 0xfe00 1087 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 1088 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 1089 1090 #define PCI_SUBSYSTEM_ID_LP11000S 0xfc11 1091 #define PCI_SUBSYSTEM_ID_LP11002S 0xfc12 1092 #define PCI_SUBSYSTEM_ID_LPE11000S 0xfc21 1093 #define PCI_SUBSYSTEM_ID_LPE11002S 0xfc22 1094 #define PCI_SUBSYSTEM_ID_LPE11010S 0xfc2A 1095 1096 #define JEDEC_ID_ADDRESS 0x0080001c 1097 #define FIREFLY_JEDEC_ID 0x1ACC 1098 #define SUPERFLY_JEDEC_ID 0x0020 1099 #define DRAGONFLY_JEDEC_ID 0x0021 1100 #define DRAGONFLY_V2_JEDEC_ID 0x0025 1101 #define CENTAUR_2G_JEDEC_ID 0x0026 1102 #define CENTAUR_1G_JEDEC_ID 0x0028 1103 #define PEGASUS_ORION_JEDEC_ID 0x0036 1104 #define PEGASUS_JEDEC_ID 0x0038 1105 #define THOR_JEDEC_ID 0x0012 1106 #define HELIOS_JEDEC_ID 0x0364 1107 #define ZEPHYR_JEDEC_ID 0x0577 1108 #define VIPER_JEDEC_ID 0x4838 1109 1110 #define JEDEC_ID_MASK 0x0FFFF000 1111 #define JEDEC_ID_SHIFT 12 1112 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1113 1114 typedef struct { /* FireFly BIU registers */ 1115 uint32_t hostAtt; /* See definitions for Host Attention 1116 register */ 1117 uint32_t chipAtt; /* See definitions for Chip Attention 1118 register */ 1119 uint32_t hostStatus; /* See definitions for Host Status register */ 1120 uint32_t hostControl; /* See definitions for Host Control register */ 1121 uint32_t buiConfig; /* See definitions for BIU configuration 1122 register */ 1123 } FF_REGS; 1124 1125 /* IO Register size in bytes */ 1126 #define FF_REG_AREA_SIZE 256 1127 1128 /* Host Attention Register */ 1129 1130 #define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1131 1132 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1133 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1134 #define HA_R0ATT 0x00000008 /* Bit 3 */ 1135 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1136 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1137 #define HA_R1ATT 0x00000080 /* Bit 7 */ 1138 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1139 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1140 #define HA_R2ATT 0x00000800 /* Bit 11 */ 1141 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1142 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1143 #define HA_R3ATT 0x00008000 /* Bit 15 */ 1144 #define HA_LATT 0x20000000 /* Bit 29 */ 1145 #define HA_MBATT 0x40000000 /* Bit 30 */ 1146 #define HA_ERATT 0x80000000 /* Bit 31 */ 1147 1148 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1149 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1150 #define HA_RXATT 0x00000008 /* Bit 3 */ 1151 #define HA_RXMASK 0x0000000f 1152 1153 /* Chip Attention Register */ 1154 1155 #define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1156 1157 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1158 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1159 #define CA_R0ATT 0x00000008 /* Bit 3 */ 1160 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1161 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1162 #define CA_R1ATT 0x00000080 /* Bit 7 */ 1163 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1164 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1165 #define CA_R2ATT 0x00000800 /* Bit 11 */ 1166 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1167 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1168 #define CA_R3ATT 0x00008000 /* Bit 15 */ 1169 #define CA_MBATT 0x40000000 /* Bit 30 */ 1170 1171 /* Host Status Register */ 1172 1173 #define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1174 1175 #define HS_MBRDY 0x00400000 /* Bit 22 */ 1176 #define HS_FFRDY 0x00800000 /* Bit 23 */ 1177 #define HS_FFER8 0x01000000 /* Bit 24 */ 1178 #define HS_FFER7 0x02000000 /* Bit 25 */ 1179 #define HS_FFER6 0x04000000 /* Bit 26 */ 1180 #define HS_FFER5 0x08000000 /* Bit 27 */ 1181 #define HS_FFER4 0x10000000 /* Bit 28 */ 1182 #define HS_FFER3 0x20000000 /* Bit 29 */ 1183 #define HS_FFER2 0x40000000 /* Bit 30 */ 1184 #define HS_FFER1 0x80000000 /* Bit 31 */ 1185 #define HS_FFERM 0xFF000000 /* Mask for error bits 31:24 */ 1186 1187 /* Host Control Register */ 1188 1189 #define HC_REG_OFFSET 12 /* Word offset from register base address */ 1190 1191 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1192 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1193 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1194 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1195 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1196 #define HC_INITHBI 0x02000000 /* Bit 25 */ 1197 #define HC_INITMB 0x04000000 /* Bit 26 */ 1198 #define HC_INITFF 0x08000000 /* Bit 27 */ 1199 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1200 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1201 1202 /* Mailbox Commands */ 1203 #define MBX_SHUTDOWN 0x00 /* terminate testing */ 1204 #define MBX_LOAD_SM 0x01 1205 #define MBX_READ_NV 0x02 1206 #define MBX_WRITE_NV 0x03 1207 #define MBX_RUN_BIU_DIAG 0x04 1208 #define MBX_INIT_LINK 0x05 1209 #define MBX_DOWN_LINK 0x06 1210 #define MBX_CONFIG_LINK 0x07 1211 #define MBX_CONFIG_RING 0x09 1212 #define MBX_RESET_RING 0x0A 1213 #define MBX_READ_CONFIG 0x0B 1214 #define MBX_READ_RCONFIG 0x0C 1215 #define MBX_READ_SPARM 0x0D 1216 #define MBX_READ_STATUS 0x0E 1217 #define MBX_READ_RPI 0x0F 1218 #define MBX_READ_XRI 0x10 1219 #define MBX_READ_REV 0x11 1220 #define MBX_READ_LNK_STAT 0x12 1221 #define MBX_REG_LOGIN 0x13 1222 #define MBX_UNREG_LOGIN 0x14 1223 #define MBX_READ_LA 0x15 1224 #define MBX_CLEAR_LA 0x16 1225 #define MBX_DUMP_MEMORY 0x17 1226 #define MBX_DUMP_CONTEXT 0x18 1227 #define MBX_RUN_DIAGS 0x19 1228 #define MBX_RESTART 0x1A 1229 #define MBX_UPDATE_CFG 0x1B 1230 #define MBX_DOWN_LOAD 0x1C 1231 #define MBX_DEL_LD_ENTRY 0x1D 1232 #define MBX_RUN_PROGRAM 0x1E 1233 #define MBX_SET_MASK 0x20 1234 #define MBX_SET_SLIM 0x21 1235 #define MBX_UNREG_D_ID 0x23 1236 #define MBX_KILL_BOARD 0x24 1237 #define MBX_CONFIG_FARP 0x25 1238 #define MBX_BEACON 0x2A 1239 1240 #define MBX_LOAD_AREA 0x81 1241 #define MBX_RUN_BIU_DIAG64 0x84 1242 #define MBX_CONFIG_PORT 0x88 1243 #define MBX_READ_SPARM64 0x8D 1244 #define MBX_READ_RPI64 0x8F 1245 #define MBX_REG_LOGIN64 0x93 1246 #define MBX_READ_LA64 0x95 1247 1248 #define MBX_FLASH_WR_ULA 0x98 1249 #define MBX_SET_DEBUG 0x99 1250 #define MBX_LOAD_EXP_ROM 0x9C 1251 1252 #define MBX_MAX_CMDS 0x9D 1253 #define MBX_SLI2_CMD_MASK 0x80 1254 1255 /* IOCB Commands */ 1256 1257 #define CMD_RCV_SEQUENCE_CX 0x01 1258 #define CMD_XMIT_SEQUENCE_CR 0x02 1259 #define CMD_XMIT_SEQUENCE_CX 0x03 1260 #define CMD_XMIT_BCAST_CN 0x04 1261 #define CMD_XMIT_BCAST_CX 0x05 1262 #define CMD_QUE_RING_BUF_CN 0x06 1263 #define CMD_QUE_XRI_BUF_CX 0x07 1264 #define CMD_IOCB_CONTINUE_CN 0x08 1265 #define CMD_RET_XRI_BUF_CX 0x09 1266 #define CMD_ELS_REQUEST_CR 0x0A 1267 #define CMD_ELS_REQUEST_CX 0x0B 1268 #define CMD_RCV_ELS_REQ_CX 0x0D 1269 #define CMD_ABORT_XRI_CN 0x0E 1270 #define CMD_ABORT_XRI_CX 0x0F 1271 #define CMD_CLOSE_XRI_CN 0x10 1272 #define CMD_CLOSE_XRI_CX 0x11 1273 #define CMD_CREATE_XRI_CR 0x12 1274 #define CMD_CREATE_XRI_CX 0x13 1275 #define CMD_GET_RPI_CN 0x14 1276 #define CMD_XMIT_ELS_RSP_CX 0x15 1277 #define CMD_GET_RPI_CR 0x16 1278 #define CMD_XRI_ABORTED_CX 0x17 1279 #define CMD_FCP_IWRITE_CR 0x18 1280 #define CMD_FCP_IWRITE_CX 0x19 1281 #define CMD_FCP_IREAD_CR 0x1A 1282 #define CMD_FCP_IREAD_CX 0x1B 1283 #define CMD_FCP_ICMND_CR 0x1C 1284 #define CMD_FCP_ICMND_CX 0x1D 1285 1286 #define CMD_ADAPTER_MSG 0x20 1287 #define CMD_ADAPTER_DUMP 0x22 1288 1289 /* SLI_2 IOCB Command Set */ 1290 1291 #define CMD_RCV_SEQUENCE64_CX 0x81 1292 #define CMD_XMIT_SEQUENCE64_CR 0x82 1293 #define CMD_XMIT_SEQUENCE64_CX 0x83 1294 #define CMD_XMIT_BCAST64_CN 0x84 1295 #define CMD_XMIT_BCAST64_CX 0x85 1296 #define CMD_QUE_RING_BUF64_CN 0x86 1297 #define CMD_QUE_XRI_BUF64_CX 0x87 1298 #define CMD_IOCB_CONTINUE64_CN 0x88 1299 #define CMD_RET_XRI_BUF64_CX 0x89 1300 #define CMD_ELS_REQUEST64_CR 0x8A 1301 #define CMD_ELS_REQUEST64_CX 0x8B 1302 #define CMD_ABORT_MXRI64_CN 0x8C 1303 #define CMD_RCV_ELS_REQ64_CX 0x8D 1304 #define CMD_XMIT_ELS_RSP64_CX 0x95 1305 #define CMD_FCP_IWRITE64_CR 0x98 1306 #define CMD_FCP_IWRITE64_CX 0x99 1307 #define CMD_FCP_IREAD64_CR 0x9A 1308 #define CMD_FCP_IREAD64_CX 0x9B 1309 #define CMD_FCP_ICMND64_CR 0x9C 1310 #define CMD_FCP_ICMND64_CX 0x9D 1311 1312 #define CMD_GEN_REQUEST64_CR 0xC2 1313 #define CMD_GEN_REQUEST64_CX 0xC3 1314 1315 #define CMD_MAX_IOCB_CMD 0xE6 1316 #define CMD_IOCB_MASK 0xff 1317 1318 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 1319 iocb */ 1320 #define LPFC_MAX_ADPTMSG 32 /* max msg data */ 1321 /* 1322 * Define Status 1323 */ 1324 #define MBX_SUCCESS 0 1325 #define MBXERR_NUM_RINGS 1 1326 #define MBXERR_NUM_IOCBS 2 1327 #define MBXERR_IOCBS_EXCEEDED 3 1328 #define MBXERR_BAD_RING_NUMBER 4 1329 #define MBXERR_MASK_ENTRIES_RANGE 5 1330 #define MBXERR_MASKS_EXCEEDED 6 1331 #define MBXERR_BAD_PROFILE 7 1332 #define MBXERR_BAD_DEF_CLASS 8 1333 #define MBXERR_BAD_MAX_RESPONDER 9 1334 #define MBXERR_BAD_MAX_ORIGINATOR 10 1335 #define MBXERR_RPI_REGISTERED 11 1336 #define MBXERR_RPI_FULL 12 1337 #define MBXERR_NO_RESOURCES 13 1338 #define MBXERR_BAD_RCV_LENGTH 14 1339 #define MBXERR_DMA_ERROR 15 1340 #define MBXERR_ERROR 16 1341 #define MBX_NOT_FINISHED 255 1342 1343 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 1344 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 1345 1346 /* 1347 * Begin Structure Definitions for Mailbox Commands 1348 */ 1349 1350 typedef struct { 1351 #ifdef __BIG_ENDIAN_BITFIELD 1352 uint8_t tval; 1353 uint8_t tmask; 1354 uint8_t rval; 1355 uint8_t rmask; 1356 #else /* __LITTLE_ENDIAN_BITFIELD */ 1357 uint8_t rmask; 1358 uint8_t rval; 1359 uint8_t tmask; 1360 uint8_t tval; 1361 #endif 1362 } RR_REG; 1363 1364 struct ulp_bde { 1365 uint32_t bdeAddress; 1366 #ifdef __BIG_ENDIAN_BITFIELD 1367 uint32_t bdeReserved:4; 1368 uint32_t bdeAddrHigh:4; 1369 uint32_t bdeSize:24; 1370 #else /* __LITTLE_ENDIAN_BITFIELD */ 1371 uint32_t bdeSize:24; 1372 uint32_t bdeAddrHigh:4; 1373 uint32_t bdeReserved:4; 1374 #endif 1375 }; 1376 1377 struct ulp_bde64 { /* SLI-2 */ 1378 union ULP_BDE_TUS { 1379 uint32_t w; 1380 struct { 1381 #ifdef __BIG_ENDIAN_BITFIELD 1382 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 1383 VALUE !! */ 1384 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 1385 #else /* __LITTLE_ENDIAN_BITFIELD */ 1386 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 1387 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 1388 VALUE !! */ 1389 #endif 1390 1391 #define BUFF_USE_RSVD 0x01 /* bdeFlags */ 1392 #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */ 1393 #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */ 1394 #define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, 0=xmit 1395 buffer */ 1396 #define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr 0=64 bit 1397 addr */ 1398 #define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */ 1399 #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */ 1400 #define BUFF_TYPE_INVALID 0x80 /* "" "" */ 1401 } f; 1402 } tus; 1403 uint32_t addrLow; 1404 uint32_t addrHigh; 1405 }; 1406 #define BDE64_SIZE_WORD 0 1407 #define BPL64_SIZE_WORD 0x40 1408 1409 typedef struct ULP_BDL { /* SLI-2 */ 1410 #ifdef __BIG_ENDIAN_BITFIELD 1411 uint32_t bdeFlags:8; /* BDL Flags */ 1412 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1413 #else /* __LITTLE_ENDIAN_BITFIELD */ 1414 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1415 uint32_t bdeFlags:8; /* BDL Flags */ 1416 #endif 1417 1418 uint32_t addrLow; /* Address 0:31 */ 1419 uint32_t addrHigh; /* Address 32:63 */ 1420 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1421 } ULP_BDL; 1422 1423 /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 1424 1425 typedef struct { 1426 #ifdef __BIG_ENDIAN_BITFIELD 1427 uint32_t rsvd2:25; 1428 uint32_t acknowledgment:1; 1429 uint32_t version:1; 1430 uint32_t erase_or_prog:1; 1431 uint32_t update_flash:1; 1432 uint32_t update_ram:1; 1433 uint32_t method:1; 1434 uint32_t load_cmplt:1; 1435 #else /* __LITTLE_ENDIAN_BITFIELD */ 1436 uint32_t load_cmplt:1; 1437 uint32_t method:1; 1438 uint32_t update_ram:1; 1439 uint32_t update_flash:1; 1440 uint32_t erase_or_prog:1; 1441 uint32_t version:1; 1442 uint32_t acknowledgment:1; 1443 uint32_t rsvd2:25; 1444 #endif 1445 1446 uint32_t dl_to_adr_low; 1447 uint32_t dl_to_adr_high; 1448 uint32_t dl_len; 1449 union { 1450 uint32_t dl_from_mbx_offset; 1451 struct ulp_bde dl_from_bde; 1452 struct ulp_bde64 dl_from_bde64; 1453 } un; 1454 1455 } LOAD_SM_VAR; 1456 1457 /* Structure for MB Command READ_NVPARM (02) */ 1458 1459 typedef struct { 1460 uint32_t rsvd1[3]; /* Read as all one's */ 1461 uint32_t rsvd2; /* Read as all zero's */ 1462 uint32_t portname[2]; /* N_PORT name */ 1463 uint32_t nodename[2]; /* NODE name */ 1464 1465 #ifdef __BIG_ENDIAN_BITFIELD 1466 uint32_t pref_DID:24; 1467 uint32_t hardAL_PA:8; 1468 #else /* __LITTLE_ENDIAN_BITFIELD */ 1469 uint32_t hardAL_PA:8; 1470 uint32_t pref_DID:24; 1471 #endif 1472 1473 uint32_t rsvd3[21]; /* Read as all one's */ 1474 } READ_NV_VAR; 1475 1476 /* Structure for MB Command WRITE_NVPARMS (03) */ 1477 1478 typedef struct { 1479 uint32_t rsvd1[3]; /* Must be all one's */ 1480 uint32_t rsvd2; /* Must be all zero's */ 1481 uint32_t portname[2]; /* N_PORT name */ 1482 uint32_t nodename[2]; /* NODE name */ 1483 1484 #ifdef __BIG_ENDIAN_BITFIELD 1485 uint32_t pref_DID:24; 1486 uint32_t hardAL_PA:8; 1487 #else /* __LITTLE_ENDIAN_BITFIELD */ 1488 uint32_t hardAL_PA:8; 1489 uint32_t pref_DID:24; 1490 #endif 1491 1492 uint32_t rsvd3[21]; /* Must be all one's */ 1493 } WRITE_NV_VAR; 1494 1495 /* Structure for MB Command RUN_BIU_DIAG (04) */ 1496 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 1497 1498 typedef struct { 1499 uint32_t rsvd1; 1500 union { 1501 struct { 1502 struct ulp_bde xmit_bde; 1503 struct ulp_bde rcv_bde; 1504 } s1; 1505 struct { 1506 struct ulp_bde64 xmit_bde64; 1507 struct ulp_bde64 rcv_bde64; 1508 } s2; 1509 } un; 1510 } BIU_DIAG_VAR; 1511 1512 /* Structure for MB Command INIT_LINK (05) */ 1513 1514 typedef struct { 1515 #ifdef __BIG_ENDIAN_BITFIELD 1516 uint32_t rsvd1:24; 1517 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1518 #else /* __LITTLE_ENDIAN_BITFIELD */ 1519 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1520 uint32_t rsvd1:24; 1521 #endif 1522 1523 #ifdef __BIG_ENDIAN_BITFIELD 1524 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1525 uint8_t rsvd2; 1526 uint16_t link_flags; 1527 #else /* __LITTLE_ENDIAN_BITFIELD */ 1528 uint16_t link_flags; 1529 uint8_t rsvd2; 1530 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1531 #endif 1532 1533 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 1534 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 1535 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 1536 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 1537 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 1538 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 1539 1540 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 1541 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 1542 1543 uint32_t link_speed; 1544 #define LINK_SPEED_AUTO 0 /* Auto selection */ 1545 #define LINK_SPEED_1G 1 /* 1 Gigabaud */ 1546 #define LINK_SPEED_2G 2 /* 2 Gigabaud */ 1547 #define LINK_SPEED_4G 4 /* 4 Gigabaud */ 1548 #define LINK_SPEED_8G 8 /* 4 Gigabaud */ 1549 #define LINK_SPEED_10G 16 /* 10 Gigabaud */ 1550 1551 } INIT_LINK_VAR; 1552 1553 /* Structure for MB Command DOWN_LINK (06) */ 1554 1555 typedef struct { 1556 uint32_t rsvd1; 1557 } DOWN_LINK_VAR; 1558 1559 /* Structure for MB Command CONFIG_LINK (07) */ 1560 1561 typedef struct { 1562 #ifdef __BIG_ENDIAN_BITFIELD 1563 uint32_t cr:1; 1564 uint32_t ci:1; 1565 uint32_t cr_delay:6; 1566 uint32_t cr_count:8; 1567 uint32_t rsvd1:8; 1568 uint32_t MaxBBC:8; 1569 #else /* __LITTLE_ENDIAN_BITFIELD */ 1570 uint32_t MaxBBC:8; 1571 uint32_t rsvd1:8; 1572 uint32_t cr_count:8; 1573 uint32_t cr_delay:6; 1574 uint32_t ci:1; 1575 uint32_t cr:1; 1576 #endif 1577 1578 uint32_t myId; 1579 uint32_t rsvd2; 1580 uint32_t edtov; 1581 uint32_t arbtov; 1582 uint32_t ratov; 1583 uint32_t rttov; 1584 uint32_t altov; 1585 uint32_t crtov; 1586 uint32_t citov; 1587 #ifdef __BIG_ENDIAN_BITFIELD 1588 uint32_t rrq_enable:1; 1589 uint32_t rrq_immed:1; 1590 uint32_t rsvd4:29; 1591 uint32_t ack0_enable:1; 1592 #else /* __LITTLE_ENDIAN_BITFIELD */ 1593 uint32_t ack0_enable:1; 1594 uint32_t rsvd4:29; 1595 uint32_t rrq_immed:1; 1596 uint32_t rrq_enable:1; 1597 #endif 1598 } CONFIG_LINK; 1599 1600 /* Structure for MB Command PART_SLIM (08) 1601 * will be removed since SLI1 is no longer supported! 1602 */ 1603 typedef struct { 1604 #ifdef __BIG_ENDIAN_BITFIELD 1605 uint16_t offCiocb; 1606 uint16_t numCiocb; 1607 uint16_t offRiocb; 1608 uint16_t numRiocb; 1609 #else /* __LITTLE_ENDIAN_BITFIELD */ 1610 uint16_t numCiocb; 1611 uint16_t offCiocb; 1612 uint16_t numRiocb; 1613 uint16_t offRiocb; 1614 #endif 1615 } RING_DEF; 1616 1617 typedef struct { 1618 #ifdef __BIG_ENDIAN_BITFIELD 1619 uint32_t unused1:24; 1620 uint32_t numRing:8; 1621 #else /* __LITTLE_ENDIAN_BITFIELD */ 1622 uint32_t numRing:8; 1623 uint32_t unused1:24; 1624 #endif 1625 1626 RING_DEF ringdef[4]; 1627 uint32_t hbainit; 1628 } PART_SLIM_VAR; 1629 1630 /* Structure for MB Command CONFIG_RING (09) */ 1631 1632 typedef struct { 1633 #ifdef __BIG_ENDIAN_BITFIELD 1634 uint32_t unused2:6; 1635 uint32_t recvSeq:1; 1636 uint32_t recvNotify:1; 1637 uint32_t numMask:8; 1638 uint32_t profile:8; 1639 uint32_t unused1:4; 1640 uint32_t ring:4; 1641 #else /* __LITTLE_ENDIAN_BITFIELD */ 1642 uint32_t ring:4; 1643 uint32_t unused1:4; 1644 uint32_t profile:8; 1645 uint32_t numMask:8; 1646 uint32_t recvNotify:1; 1647 uint32_t recvSeq:1; 1648 uint32_t unused2:6; 1649 #endif 1650 1651 #ifdef __BIG_ENDIAN_BITFIELD 1652 uint16_t maxRespXchg; 1653 uint16_t maxOrigXchg; 1654 #else /* __LITTLE_ENDIAN_BITFIELD */ 1655 uint16_t maxOrigXchg; 1656 uint16_t maxRespXchg; 1657 #endif 1658 1659 RR_REG rrRegs[6]; 1660 } CONFIG_RING_VAR; 1661 1662 /* Structure for MB Command RESET_RING (10) */ 1663 1664 typedef struct { 1665 uint32_t ring_no; 1666 } RESET_RING_VAR; 1667 1668 /* Structure for MB Command READ_CONFIG (11) */ 1669 1670 typedef struct { 1671 #ifdef __BIG_ENDIAN_BITFIELD 1672 uint32_t cr:1; 1673 uint32_t ci:1; 1674 uint32_t cr_delay:6; 1675 uint32_t cr_count:8; 1676 uint32_t InitBBC:8; 1677 uint32_t MaxBBC:8; 1678 #else /* __LITTLE_ENDIAN_BITFIELD */ 1679 uint32_t MaxBBC:8; 1680 uint32_t InitBBC:8; 1681 uint32_t cr_count:8; 1682 uint32_t cr_delay:6; 1683 uint32_t ci:1; 1684 uint32_t cr:1; 1685 #endif 1686 1687 #ifdef __BIG_ENDIAN_BITFIELD 1688 uint32_t topology:8; 1689 uint32_t myDid:24; 1690 #else /* __LITTLE_ENDIAN_BITFIELD */ 1691 uint32_t myDid:24; 1692 uint32_t topology:8; 1693 #endif 1694 1695 /* Defines for topology (defined previously) */ 1696 #ifdef __BIG_ENDIAN_BITFIELD 1697 uint32_t AR:1; 1698 uint32_t IR:1; 1699 uint32_t rsvd1:29; 1700 uint32_t ack0:1; 1701 #else /* __LITTLE_ENDIAN_BITFIELD */ 1702 uint32_t ack0:1; 1703 uint32_t rsvd1:29; 1704 uint32_t IR:1; 1705 uint32_t AR:1; 1706 #endif 1707 1708 uint32_t edtov; 1709 uint32_t arbtov; 1710 uint32_t ratov; 1711 uint32_t rttov; 1712 uint32_t altov; 1713 uint32_t lmt; 1714 #define LMT_RESERVED 0x000 /* Not used */ 1715 #define LMT_1Gb 0x004 1716 #define LMT_2Gb 0x008 1717 #define LMT_4Gb 0x040 1718 #define LMT_8Gb 0x080 1719 #define LMT_10Gb 0x100 1720 1721 1722 uint32_t rsvd2; 1723 uint32_t rsvd3; 1724 uint32_t max_xri; 1725 uint32_t max_iocb; 1726 uint32_t max_rpi; 1727 uint32_t avail_xri; 1728 uint32_t avail_iocb; 1729 uint32_t avail_rpi; 1730 uint32_t default_rpi; 1731 } READ_CONFIG_VAR; 1732 1733 /* Structure for MB Command READ_RCONFIG (12) */ 1734 1735 typedef struct { 1736 #ifdef __BIG_ENDIAN_BITFIELD 1737 uint32_t rsvd2:7; 1738 uint32_t recvNotify:1; 1739 uint32_t numMask:8; 1740 uint32_t profile:8; 1741 uint32_t rsvd1:4; 1742 uint32_t ring:4; 1743 #else /* __LITTLE_ENDIAN_BITFIELD */ 1744 uint32_t ring:4; 1745 uint32_t rsvd1:4; 1746 uint32_t profile:8; 1747 uint32_t numMask:8; 1748 uint32_t recvNotify:1; 1749 uint32_t rsvd2:7; 1750 #endif 1751 1752 #ifdef __BIG_ENDIAN_BITFIELD 1753 uint16_t maxResp; 1754 uint16_t maxOrig; 1755 #else /* __LITTLE_ENDIAN_BITFIELD */ 1756 uint16_t maxOrig; 1757 uint16_t maxResp; 1758 #endif 1759 1760 RR_REG rrRegs[6]; 1761 1762 #ifdef __BIG_ENDIAN_BITFIELD 1763 uint16_t cmdRingOffset; 1764 uint16_t cmdEntryCnt; 1765 uint16_t rspRingOffset; 1766 uint16_t rspEntryCnt; 1767 uint16_t nextCmdOffset; 1768 uint16_t rsvd3; 1769 uint16_t nextRspOffset; 1770 uint16_t rsvd4; 1771 #else /* __LITTLE_ENDIAN_BITFIELD */ 1772 uint16_t cmdEntryCnt; 1773 uint16_t cmdRingOffset; 1774 uint16_t rspEntryCnt; 1775 uint16_t rspRingOffset; 1776 uint16_t rsvd3; 1777 uint16_t nextCmdOffset; 1778 uint16_t rsvd4; 1779 uint16_t nextRspOffset; 1780 #endif 1781 } READ_RCONF_VAR; 1782 1783 /* Structure for MB Command READ_SPARM (13) */ 1784 /* Structure for MB Command READ_SPARM64 (0x8D) */ 1785 1786 typedef struct { 1787 uint32_t rsvd1; 1788 uint32_t rsvd2; 1789 union { 1790 struct ulp_bde sp; /* This BDE points to struct serv_parm 1791 structure */ 1792 struct ulp_bde64 sp64; 1793 } un; 1794 } READ_SPARM_VAR; 1795 1796 /* Structure for MB Command READ_STATUS (14) */ 1797 1798 typedef struct { 1799 #ifdef __BIG_ENDIAN_BITFIELD 1800 uint32_t rsvd1:31; 1801 uint32_t clrCounters:1; 1802 uint16_t activeXriCnt; 1803 uint16_t activeRpiCnt; 1804 #else /* __LITTLE_ENDIAN_BITFIELD */ 1805 uint32_t clrCounters:1; 1806 uint32_t rsvd1:31; 1807 uint16_t activeRpiCnt; 1808 uint16_t activeXriCnt; 1809 #endif 1810 1811 uint32_t xmitByteCnt; 1812 uint32_t rcvByteCnt; 1813 uint32_t xmitFrameCnt; 1814 uint32_t rcvFrameCnt; 1815 uint32_t xmitSeqCnt; 1816 uint32_t rcvSeqCnt; 1817 uint32_t totalOrigExchanges; 1818 uint32_t totalRespExchanges; 1819 uint32_t rcvPbsyCnt; 1820 uint32_t rcvFbsyCnt; 1821 } READ_STATUS_VAR; 1822 1823 /* Structure for MB Command READ_RPI (15) */ 1824 /* Structure for MB Command READ_RPI64 (0x8F) */ 1825 1826 typedef struct { 1827 #ifdef __BIG_ENDIAN_BITFIELD 1828 uint16_t nextRpi; 1829 uint16_t reqRpi; 1830 uint32_t rsvd2:8; 1831 uint32_t DID:24; 1832 #else /* __LITTLE_ENDIAN_BITFIELD */ 1833 uint16_t reqRpi; 1834 uint16_t nextRpi; 1835 uint32_t DID:24; 1836 uint32_t rsvd2:8; 1837 #endif 1838 1839 union { 1840 struct ulp_bde sp; 1841 struct ulp_bde64 sp64; 1842 } un; 1843 1844 } READ_RPI_VAR; 1845 1846 /* Structure for MB Command READ_XRI (16) */ 1847 1848 typedef struct { 1849 #ifdef __BIG_ENDIAN_BITFIELD 1850 uint16_t nextXri; 1851 uint16_t reqXri; 1852 uint16_t rsvd1; 1853 uint16_t rpi; 1854 uint32_t rsvd2:8; 1855 uint32_t DID:24; 1856 uint32_t rsvd3:8; 1857 uint32_t SID:24; 1858 uint32_t rsvd4; 1859 uint8_t seqId; 1860 uint8_t rsvd5; 1861 uint16_t seqCount; 1862 uint16_t oxId; 1863 uint16_t rxId; 1864 uint32_t rsvd6:30; 1865 uint32_t si:1; 1866 uint32_t exchOrig:1; 1867 #else /* __LITTLE_ENDIAN_BITFIELD */ 1868 uint16_t reqXri; 1869 uint16_t nextXri; 1870 uint16_t rpi; 1871 uint16_t rsvd1; 1872 uint32_t DID:24; 1873 uint32_t rsvd2:8; 1874 uint32_t SID:24; 1875 uint32_t rsvd3:8; 1876 uint32_t rsvd4; 1877 uint16_t seqCount; 1878 uint8_t rsvd5; 1879 uint8_t seqId; 1880 uint16_t rxId; 1881 uint16_t oxId; 1882 uint32_t exchOrig:1; 1883 uint32_t si:1; 1884 uint32_t rsvd6:30; 1885 #endif 1886 } READ_XRI_VAR; 1887 1888 /* Structure for MB Command READ_REV (17) */ 1889 1890 typedef struct { 1891 #ifdef __BIG_ENDIAN_BITFIELD 1892 uint32_t cv:1; 1893 uint32_t rr:1; 1894 uint32_t rsvd1:29; 1895 uint32_t rv:1; 1896 #else /* __LITTLE_ENDIAN_BITFIELD */ 1897 uint32_t rv:1; 1898 uint32_t rsvd1:29; 1899 uint32_t rr:1; 1900 uint32_t cv:1; 1901 #endif 1902 1903 uint32_t biuRev; 1904 uint32_t smRev; 1905 union { 1906 uint32_t smFwRev; 1907 struct { 1908 #ifdef __BIG_ENDIAN_BITFIELD 1909 uint8_t ProgType; 1910 uint8_t ProgId; 1911 uint16_t ProgVer:4; 1912 uint16_t ProgRev:4; 1913 uint16_t ProgFixLvl:2; 1914 uint16_t ProgDistType:2; 1915 uint16_t DistCnt:4; 1916 #else /* __LITTLE_ENDIAN_BITFIELD */ 1917 uint16_t DistCnt:4; 1918 uint16_t ProgDistType:2; 1919 uint16_t ProgFixLvl:2; 1920 uint16_t ProgRev:4; 1921 uint16_t ProgVer:4; 1922 uint8_t ProgId; 1923 uint8_t ProgType; 1924 #endif 1925 1926 } b; 1927 } un; 1928 uint32_t endecRev; 1929 #ifdef __BIG_ENDIAN_BITFIELD 1930 uint8_t feaLevelHigh; 1931 uint8_t feaLevelLow; 1932 uint8_t fcphHigh; 1933 uint8_t fcphLow; 1934 #else /* __LITTLE_ENDIAN_BITFIELD */ 1935 uint8_t fcphLow; 1936 uint8_t fcphHigh; 1937 uint8_t feaLevelLow; 1938 uint8_t feaLevelHigh; 1939 #endif 1940 1941 uint32_t postKernRev; 1942 uint32_t opFwRev; 1943 uint8_t opFwName[16]; 1944 uint32_t sli1FwRev; 1945 uint8_t sli1FwName[16]; 1946 uint32_t sli2FwRev; 1947 uint8_t sli2FwName[16]; 1948 uint32_t rsvd2; 1949 uint32_t RandomData[7]; 1950 } READ_REV_VAR; 1951 1952 /* Structure for MB Command READ_LINK_STAT (18) */ 1953 1954 typedef struct { 1955 uint32_t rsvd1; 1956 uint32_t linkFailureCnt; 1957 uint32_t lossSyncCnt; 1958 1959 uint32_t lossSignalCnt; 1960 uint32_t primSeqErrCnt; 1961 uint32_t invalidXmitWord; 1962 uint32_t crcCnt; 1963 uint32_t primSeqTimeout; 1964 uint32_t elasticOverrun; 1965 uint32_t arbTimeout; 1966 } READ_LNK_VAR; 1967 1968 /* Structure for MB Command REG_LOGIN (19) */ 1969 /* Structure for MB Command REG_LOGIN64 (0x93) */ 1970 1971 typedef struct { 1972 #ifdef __BIG_ENDIAN_BITFIELD 1973 uint16_t rsvd1; 1974 uint16_t rpi; 1975 uint32_t rsvd2:8; 1976 uint32_t did:24; 1977 #else /* __LITTLE_ENDIAN_BITFIELD */ 1978 uint16_t rpi; 1979 uint16_t rsvd1; 1980 uint32_t did:24; 1981 uint32_t rsvd2:8; 1982 #endif 1983 1984 union { 1985 struct ulp_bde sp; 1986 struct ulp_bde64 sp64; 1987 } un; 1988 1989 } REG_LOGIN_VAR; 1990 1991 /* Word 30 contents for REG_LOGIN */ 1992 typedef union { 1993 struct { 1994 #ifdef __BIG_ENDIAN_BITFIELD 1995 uint16_t rsvd1:12; 1996 uint16_t wd30_class:4; 1997 uint16_t xri; 1998 #else /* __LITTLE_ENDIAN_BITFIELD */ 1999 uint16_t xri; 2000 uint16_t wd30_class:4; 2001 uint16_t rsvd1:12; 2002 #endif 2003 } f; 2004 uint32_t word; 2005 } REG_WD30; 2006 2007 /* Structure for MB Command UNREG_LOGIN (20) */ 2008 2009 typedef struct { 2010 #ifdef __BIG_ENDIAN_BITFIELD 2011 uint16_t rsvd1; 2012 uint16_t rpi; 2013 #else /* __LITTLE_ENDIAN_BITFIELD */ 2014 uint16_t rpi; 2015 uint16_t rsvd1; 2016 #endif 2017 } UNREG_LOGIN_VAR; 2018 2019 /* Structure for MB Command UNREG_D_ID (0x23) */ 2020 2021 typedef struct { 2022 uint32_t did; 2023 } UNREG_D_ID_VAR; 2024 2025 /* Structure for MB Command READ_LA (21) */ 2026 /* Structure for MB Command READ_LA64 (0x95) */ 2027 2028 typedef struct { 2029 uint32_t eventTag; /* Event tag */ 2030 #ifdef __BIG_ENDIAN_BITFIELD 2031 uint32_t rsvd1:22; 2032 uint32_t pb:1; 2033 uint32_t il:1; 2034 uint32_t attType:8; 2035 #else /* __LITTLE_ENDIAN_BITFIELD */ 2036 uint32_t attType:8; 2037 uint32_t il:1; 2038 uint32_t pb:1; 2039 uint32_t rsvd1:22; 2040 #endif 2041 2042 #define AT_RESERVED 0x00 /* Reserved - attType */ 2043 #define AT_LINK_UP 0x01 /* Link is up */ 2044 #define AT_LINK_DOWN 0x02 /* Link is down */ 2045 2046 #ifdef __BIG_ENDIAN_BITFIELD 2047 uint8_t granted_AL_PA; 2048 uint8_t lipAlPs; 2049 uint8_t lipType; 2050 uint8_t topology; 2051 #else /* __LITTLE_ENDIAN_BITFIELD */ 2052 uint8_t topology; 2053 uint8_t lipType; 2054 uint8_t lipAlPs; 2055 uint8_t granted_AL_PA; 2056 #endif 2057 2058 #define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 2059 #define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 2060 2061 union { 2062 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer 2063 to */ 2064 /* store the LILP AL_PA position map into */ 2065 struct ulp_bde64 lilpBde64; 2066 } un; 2067 2068 #ifdef __BIG_ENDIAN_BITFIELD 2069 uint32_t Dlu:1; 2070 uint32_t Dtf:1; 2071 uint32_t Drsvd2:14; 2072 uint32_t DlnkSpeed:8; 2073 uint32_t DnlPort:4; 2074 uint32_t Dtx:2; 2075 uint32_t Drx:2; 2076 #else /* __LITTLE_ENDIAN_BITFIELD */ 2077 uint32_t Drx:2; 2078 uint32_t Dtx:2; 2079 uint32_t DnlPort:4; 2080 uint32_t DlnkSpeed:8; 2081 uint32_t Drsvd2:14; 2082 uint32_t Dtf:1; 2083 uint32_t Dlu:1; 2084 #endif 2085 2086 #ifdef __BIG_ENDIAN_BITFIELD 2087 uint32_t Ulu:1; 2088 uint32_t Utf:1; 2089 uint32_t Ursvd2:14; 2090 uint32_t UlnkSpeed:8; 2091 uint32_t UnlPort:4; 2092 uint32_t Utx:2; 2093 uint32_t Urx:2; 2094 #else /* __LITTLE_ENDIAN_BITFIELD */ 2095 uint32_t Urx:2; 2096 uint32_t Utx:2; 2097 uint32_t UnlPort:4; 2098 uint32_t UlnkSpeed:8; 2099 uint32_t Ursvd2:14; 2100 uint32_t Utf:1; 2101 uint32_t Ulu:1; 2102 #endif 2103 2104 #define LA_UNKNW_LINK 0x0 /* lnkSpeed */ 2105 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */ 2106 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */ 2107 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */ 2108 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */ 2109 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */ 2110 2111 } READ_LA_VAR; 2112 2113 /* Structure for MB Command CLEAR_LA (22) */ 2114 2115 typedef struct { 2116 uint32_t eventTag; /* Event tag */ 2117 uint32_t rsvd1; 2118 } CLEAR_LA_VAR; 2119 2120 /* Structure for MB Command DUMP */ 2121 2122 typedef struct { 2123 #ifdef __BIG_ENDIAN_BITFIELD 2124 uint32_t rsvd:25; 2125 uint32_t ra:1; 2126 uint32_t co:1; 2127 uint32_t cv:1; 2128 uint32_t type:4; 2129 uint32_t entry_index:16; 2130 uint32_t region_id:16; 2131 #else /* __LITTLE_ENDIAN_BITFIELD */ 2132 uint32_t type:4; 2133 uint32_t cv:1; 2134 uint32_t co:1; 2135 uint32_t ra:1; 2136 uint32_t rsvd:25; 2137 uint32_t region_id:16; 2138 uint32_t entry_index:16; 2139 #endif 2140 2141 uint32_t rsvd1; 2142 uint32_t word_cnt; 2143 uint32_t resp_offset; 2144 } DUMP_VAR; 2145 2146 #define DMP_MEM_REG 0x1 2147 #define DMP_NV_PARAMS 0x2 2148 2149 #define DMP_REGION_VPD 0xe 2150 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 2151 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 2152 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 2153 2154 /* Structure for MB Command CONFIG_PORT (0x88) */ 2155 2156 typedef struct { 2157 uint32_t pcbLen; 2158 uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 2159 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 2160 uint32_t hbainit[5]; 2161 } CONFIG_PORT_VAR; 2162 2163 /* SLI-2 Port Control Block */ 2164 2165 /* SLIM POINTER */ 2166 #define SLIMOFF 0x30 /* WORD */ 2167 2168 typedef struct _SLI2_RDSC { 2169 uint32_t cmdEntries; 2170 uint32_t cmdAddrLow; 2171 uint32_t cmdAddrHigh; 2172 2173 uint32_t rspEntries; 2174 uint32_t rspAddrLow; 2175 uint32_t rspAddrHigh; 2176 } SLI2_RDSC; 2177 2178 typedef struct _PCB { 2179 #ifdef __BIG_ENDIAN_BITFIELD 2180 uint32_t type:8; 2181 #define TYPE_NATIVE_SLI2 0x01; 2182 uint32_t feature:8; 2183 #define FEATURE_INITIAL_SLI2 0x01; 2184 uint32_t rsvd:12; 2185 uint32_t maxRing:4; 2186 #else /* __LITTLE_ENDIAN_BITFIELD */ 2187 uint32_t maxRing:4; 2188 uint32_t rsvd:12; 2189 uint32_t feature:8; 2190 #define FEATURE_INITIAL_SLI2 0x01; 2191 uint32_t type:8; 2192 #define TYPE_NATIVE_SLI2 0x01; 2193 #endif 2194 2195 uint32_t mailBoxSize; 2196 uint32_t mbAddrLow; 2197 uint32_t mbAddrHigh; 2198 2199 uint32_t hgpAddrLow; 2200 uint32_t hgpAddrHigh; 2201 2202 uint32_t pgpAddrLow; 2203 uint32_t pgpAddrHigh; 2204 SLI2_RDSC rdsc[MAX_RINGS]; 2205 } PCB_t; 2206 2207 /* NEW_FEATURE */ 2208 typedef struct { 2209 #ifdef __BIG_ENDIAN_BITFIELD 2210 uint32_t rsvd0:27; 2211 uint32_t discardFarp:1; 2212 uint32_t IPEnable:1; 2213 uint32_t nodeName:1; 2214 uint32_t portName:1; 2215 uint32_t filterEnable:1; 2216 #else /* __LITTLE_ENDIAN_BITFIELD */ 2217 uint32_t filterEnable:1; 2218 uint32_t portName:1; 2219 uint32_t nodeName:1; 2220 uint32_t IPEnable:1; 2221 uint32_t discardFarp:1; 2222 uint32_t rsvd:27; 2223 #endif 2224 2225 uint8_t portname[8]; /* Used to be struct lpfc_name */ 2226 uint8_t nodename[8]; 2227 uint32_t rsvd1; 2228 uint32_t rsvd2; 2229 uint32_t rsvd3; 2230 uint32_t IPAddress; 2231 } CONFIG_FARP_VAR; 2232 2233 /* Union of all Mailbox Command types */ 2234 #define MAILBOX_CMD_WSIZE 32 2235 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 2236 2237 typedef union { 2238 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; 2239 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 2240 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 2241 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 2242 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 2243 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 2244 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 2245 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 2246 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 2247 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 2248 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 2249 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 2250 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 2251 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 2252 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 2253 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 2254 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 2255 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 2256 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 2257 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 2258 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 2259 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */ 2260 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 2261 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 2262 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 2263 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) NEW_FEATURE */ 2264 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 2265 } MAILVARIANTS; 2266 2267 /* 2268 * SLI-2 specific structures 2269 */ 2270 2271 struct lpfc_hgp { 2272 __le32 cmdPutInx; 2273 __le32 rspGetInx; 2274 }; 2275 2276 struct lpfc_pgp { 2277 __le32 cmdGetInx; 2278 __le32 rspPutInx; 2279 }; 2280 2281 typedef struct _SLI2_DESC { 2282 struct lpfc_hgp host[MAX_RINGS]; 2283 uint32_t unused1[16]; 2284 struct lpfc_pgp port[MAX_RINGS]; 2285 } SLI2_DESC; 2286 2287 typedef union { 2288 SLI2_DESC s2; 2289 } SLI_VAR; 2290 2291 typedef struct { 2292 #ifdef __BIG_ENDIAN_BITFIELD 2293 uint16_t mbxStatus; 2294 uint8_t mbxCommand; 2295 uint8_t mbxReserved:6; 2296 uint8_t mbxHc:1; 2297 uint8_t mbxOwner:1; /* Low order bit first word */ 2298 #else /* __LITTLE_ENDIAN_BITFIELD */ 2299 uint8_t mbxOwner:1; /* Low order bit first word */ 2300 uint8_t mbxHc:1; 2301 uint8_t mbxReserved:6; 2302 uint8_t mbxCommand; 2303 uint16_t mbxStatus; 2304 #endif 2305 2306 MAILVARIANTS un; 2307 SLI_VAR us; 2308 } MAILBOX_t; 2309 2310 /* 2311 * Begin Structure Definitions for IOCB Commands 2312 */ 2313 2314 typedef struct { 2315 #ifdef __BIG_ENDIAN_BITFIELD 2316 uint8_t statAction; 2317 uint8_t statRsn; 2318 uint8_t statBaExp; 2319 uint8_t statLocalError; 2320 #else /* __LITTLE_ENDIAN_BITFIELD */ 2321 uint8_t statLocalError; 2322 uint8_t statBaExp; 2323 uint8_t statRsn; 2324 uint8_t statAction; 2325 #endif 2326 /* statRsn P/F_RJT reason codes */ 2327 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 2328 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 2329 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 2330 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 2331 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 2332 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 2333 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 2334 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 2335 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 2336 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 2337 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 2338 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 2339 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 2340 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 2341 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 2342 #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 2343 #define RJT_XCHG_ERR 0x11 /* Exchange error */ 2344 #define RJT_PROT_ERR 0x12 /* Protocol error */ 2345 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 2346 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 2347 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 2348 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 2349 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 2350 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 2351 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 2352 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 2353 2354 #define IOERR_SUCCESS 0x00 /* statLocalError */ 2355 #define IOERR_MISSING_CONTINUE 0x01 2356 #define IOERR_SEQUENCE_TIMEOUT 0x02 2357 #define IOERR_INTERNAL_ERROR 0x03 2358 #define IOERR_INVALID_RPI 0x04 2359 #define IOERR_NO_XRI 0x05 2360 #define IOERR_ILLEGAL_COMMAND 0x06 2361 #define IOERR_XCHG_DROPPED 0x07 2362 #define IOERR_ILLEGAL_FIELD 0x08 2363 #define IOERR_BAD_CONTINUE 0x09 2364 #define IOERR_TOO_MANY_BUFFERS 0x0A 2365 #define IOERR_RCV_BUFFER_WAITING 0x0B 2366 #define IOERR_NO_CONNECTION 0x0C 2367 #define IOERR_TX_DMA_FAILED 0x0D 2368 #define IOERR_RX_DMA_FAILED 0x0E 2369 #define IOERR_ILLEGAL_FRAME 0x0F 2370 #define IOERR_EXTRA_DATA 0x10 2371 #define IOERR_NO_RESOURCES 0x11 2372 #define IOERR_RESERVED 0x12 2373 #define IOERR_ILLEGAL_LENGTH 0x13 2374 #define IOERR_UNSUPPORTED_FEATURE 0x14 2375 #define IOERR_ABORT_IN_PROGRESS 0x15 2376 #define IOERR_ABORT_REQUESTED 0x16 2377 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 2378 #define IOERR_LOOP_OPEN_FAILURE 0x18 2379 #define IOERR_RING_RESET 0x19 2380 #define IOERR_LINK_DOWN 0x1A 2381 #define IOERR_CORRUPTED_DATA 0x1B 2382 #define IOERR_CORRUPTED_RPI 0x1C 2383 #define IOERR_OUT_OF_ORDER_DATA 0x1D 2384 #define IOERR_OUT_OF_ORDER_ACK 0x1E 2385 #define IOERR_DUP_FRAME 0x1F 2386 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 2387 #define IOERR_BAD_HOST_ADDRESS 0x21 2388 #define IOERR_RCV_HDRBUF_WAITING 0x22 2389 #define IOERR_MISSING_HDR_BUFFER 0x23 2390 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 2391 #define IOERR_ABORTMULT_REQUESTED 0x25 2392 #define IOERR_BUFFER_SHORTAGE 0x28 2393 #define IOERR_DEFAULT 0x29 2394 #define IOERR_CNT 0x2A 2395 2396 #define IOERR_DRVR_MASK 0x100 2397 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 2398 #define IOERR_SLI_BRESET 0x102 2399 #define IOERR_SLI_ABORTED 0x103 2400 } PARM_ERR; 2401 2402 typedef union { 2403 struct { 2404 #ifdef __BIG_ENDIAN_BITFIELD 2405 uint8_t Rctl; /* R_CTL field */ 2406 uint8_t Type; /* TYPE field */ 2407 uint8_t Dfctl; /* DF_CTL field */ 2408 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 2409 #else /* __LITTLE_ENDIAN_BITFIELD */ 2410 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 2411 uint8_t Dfctl; /* DF_CTL field */ 2412 uint8_t Type; /* TYPE field */ 2413 uint8_t Rctl; /* R_CTL field */ 2414 #endif 2415 2416 #define BC 0x02 /* Broadcast Received - Fctl */ 2417 #define SI 0x04 /* Sequence Initiative */ 2418 #define LA 0x08 /* Ignore Link Attention state */ 2419 #define LS 0x80 /* Last Sequence */ 2420 } hcsw; 2421 uint32_t reserved; 2422 } WORD5; 2423 2424 /* IOCB Command template for a generic response */ 2425 typedef struct { 2426 uint32_t reserved[4]; 2427 PARM_ERR perr; 2428 } GENERIC_RSP; 2429 2430 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 2431 typedef struct { 2432 struct ulp_bde xrsqbde[2]; 2433 uint32_t xrsqRo; /* Starting Relative Offset */ 2434 WORD5 w5; /* Header control/status word */ 2435 } XR_SEQ_FIELDS; 2436 2437 /* IOCB Command template for ELS_REQUEST */ 2438 typedef struct { 2439 struct ulp_bde elsReq; 2440 struct ulp_bde elsRsp; 2441 2442 #ifdef __BIG_ENDIAN_BITFIELD 2443 uint32_t word4Rsvd:7; 2444 uint32_t fl:1; 2445 uint32_t myID:24; 2446 uint32_t word5Rsvd:8; 2447 uint32_t remoteID:24; 2448 #else /* __LITTLE_ENDIAN_BITFIELD */ 2449 uint32_t myID:24; 2450 uint32_t fl:1; 2451 uint32_t word4Rsvd:7; 2452 uint32_t remoteID:24; 2453 uint32_t word5Rsvd:8; 2454 #endif 2455 } ELS_REQUEST; 2456 2457 /* IOCB Command template for RCV_ELS_REQ */ 2458 typedef struct { 2459 struct ulp_bde elsReq[2]; 2460 uint32_t parmRo; 2461 2462 #ifdef __BIG_ENDIAN_BITFIELD 2463 uint32_t word5Rsvd:8; 2464 uint32_t remoteID:24; 2465 #else /* __LITTLE_ENDIAN_BITFIELD */ 2466 uint32_t remoteID:24; 2467 uint32_t word5Rsvd:8; 2468 #endif 2469 } RCV_ELS_REQ; 2470 2471 /* IOCB Command template for ABORT / CLOSE_XRI */ 2472 typedef struct { 2473 uint32_t rsvd[3]; 2474 uint32_t abortType; 2475 #define ABORT_TYPE_ABTX 0x00000000 2476 #define ABORT_TYPE_ABTS 0x00000001 2477 uint32_t parm; 2478 #ifdef __BIG_ENDIAN_BITFIELD 2479 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 2480 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 2481 #else /* __LITTLE_ENDIAN_BITFIELD */ 2482 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 2483 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 2484 #endif 2485 } AC_XRI; 2486 2487 /* IOCB Command template for ABORT_MXRI64 */ 2488 typedef struct { 2489 uint32_t rsvd[3]; 2490 uint32_t abortType; 2491 uint32_t parm; 2492 uint32_t iotag32; 2493 } A_MXRI64; 2494 2495 /* IOCB Command template for GET_RPI */ 2496 typedef struct { 2497 uint32_t rsvd[4]; 2498 uint32_t parmRo; 2499 #ifdef __BIG_ENDIAN_BITFIELD 2500 uint32_t word5Rsvd:8; 2501 uint32_t remoteID:24; 2502 #else /* __LITTLE_ENDIAN_BITFIELD */ 2503 uint32_t remoteID:24; 2504 uint32_t word5Rsvd:8; 2505 #endif 2506 } GET_RPI; 2507 2508 /* IOCB Command template for all FCP Initiator commands */ 2509 typedef struct { 2510 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 2511 struct ulp_bde fcpi_rsp; /* Rcv buffer */ 2512 uint32_t fcpi_parm; 2513 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 2514 } FCPI_FIELDS; 2515 2516 /* IOCB Command template for all FCP Target commands */ 2517 typedef struct { 2518 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 2519 uint32_t fcpt_Offset; 2520 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 2521 } FCPT_FIELDS; 2522 2523 /* SLI-2 IOCB structure definitions */ 2524 2525 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 2526 typedef struct { 2527 ULP_BDL bdl; 2528 uint32_t xrsqRo; /* Starting Relative Offset */ 2529 WORD5 w5; /* Header control/status word */ 2530 } XMT_SEQ_FIELDS64; 2531 2532 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 2533 typedef struct { 2534 struct ulp_bde64 rcvBde; 2535 uint32_t rsvd1; 2536 uint32_t xrsqRo; /* Starting Relative Offset */ 2537 WORD5 w5; /* Header control/status word */ 2538 } RCV_SEQ_FIELDS64; 2539 2540 /* IOCB Command template for ELS_REQUEST64 */ 2541 typedef struct { 2542 ULP_BDL bdl; 2543 #ifdef __BIG_ENDIAN_BITFIELD 2544 uint32_t word4Rsvd:7; 2545 uint32_t fl:1; 2546 uint32_t myID:24; 2547 uint32_t word5Rsvd:8; 2548 uint32_t remoteID:24; 2549 #else /* __LITTLE_ENDIAN_BITFIELD */ 2550 uint32_t myID:24; 2551 uint32_t fl:1; 2552 uint32_t word4Rsvd:7; 2553 uint32_t remoteID:24; 2554 uint32_t word5Rsvd:8; 2555 #endif 2556 } ELS_REQUEST64; 2557 2558 /* IOCB Command template for GEN_REQUEST64 */ 2559 typedef struct { 2560 ULP_BDL bdl; 2561 uint32_t xrsqRo; /* Starting Relative Offset */ 2562 WORD5 w5; /* Header control/status word */ 2563 } GEN_REQUEST64; 2564 2565 /* IOCB Command template for RCV_ELS_REQ64 */ 2566 typedef struct { 2567 struct ulp_bde64 elsReq; 2568 uint32_t rcvd1; 2569 uint32_t parmRo; 2570 2571 #ifdef __BIG_ENDIAN_BITFIELD 2572 uint32_t word5Rsvd:8; 2573 uint32_t remoteID:24; 2574 #else /* __LITTLE_ENDIAN_BITFIELD */ 2575 uint32_t remoteID:24; 2576 uint32_t word5Rsvd:8; 2577 #endif 2578 } RCV_ELS_REQ64; 2579 2580 /* IOCB Command template for all 64 bit FCP Initiator commands */ 2581 typedef struct { 2582 ULP_BDL bdl; 2583 uint32_t fcpi_parm; 2584 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 2585 } FCPI_FIELDS64; 2586 2587 /* IOCB Command template for all 64 bit FCP Target commands */ 2588 typedef struct { 2589 ULP_BDL bdl; 2590 uint32_t fcpt_Offset; 2591 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 2592 } FCPT_FIELDS64; 2593 2594 typedef struct _IOCB { /* IOCB structure */ 2595 union { 2596 GENERIC_RSP grsp; /* Generic response */ 2597 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 2598 struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 2599 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 2600 AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 2601 A_MXRI64 amxri; /* abort multiple xri command overlay */ 2602 GET_RPI getrpi; /* GET_RPI template */ 2603 FCPI_FIELDS fcpi; /* FCP Initiator template */ 2604 FCPT_FIELDS fcpt; /* FCP target template */ 2605 2606 /* SLI-2 structures */ 2607 2608 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 2609 bde_64s */ 2610 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 2611 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 2612 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 2613 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 2614 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 2615 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 2616 2617 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 2618 } un; 2619 union { 2620 struct { 2621 #ifdef __BIG_ENDIAN_BITFIELD 2622 uint16_t ulpContext; /* High order bits word 6 */ 2623 uint16_t ulpIoTag; /* Low order bits word 6 */ 2624 #else /* __LITTLE_ENDIAN_BITFIELD */ 2625 uint16_t ulpIoTag; /* Low order bits word 6 */ 2626 uint16_t ulpContext; /* High order bits word 6 */ 2627 #endif 2628 } t1; 2629 struct { 2630 #ifdef __BIG_ENDIAN_BITFIELD 2631 uint16_t ulpContext; /* High order bits word 6 */ 2632 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 2633 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 2634 #else /* __LITTLE_ENDIAN_BITFIELD */ 2635 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 2636 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 2637 uint16_t ulpContext; /* High order bits word 6 */ 2638 #endif 2639 } t2; 2640 } un1; 2641 #define ulpContext un1.t1.ulpContext 2642 #define ulpIoTag un1.t1.ulpIoTag 2643 #define ulpIoTag0 un1.t2.ulpIoTag0 2644 2645 #ifdef __BIG_ENDIAN_BITFIELD 2646 uint32_t ulpTimeout:8; 2647 uint32_t ulpXS:1; 2648 uint32_t ulpFCP2Rcvy:1; 2649 uint32_t ulpPU:2; 2650 uint32_t ulpIr:1; 2651 uint32_t ulpClass:3; 2652 uint32_t ulpCommand:8; 2653 uint32_t ulpStatus:4; 2654 uint32_t ulpBdeCount:2; 2655 uint32_t ulpLe:1; 2656 uint32_t ulpOwner:1; /* Low order bit word 7 */ 2657 #else /* __LITTLE_ENDIAN_BITFIELD */ 2658 uint32_t ulpOwner:1; /* Low order bit word 7 */ 2659 uint32_t ulpLe:1; 2660 uint32_t ulpBdeCount:2; 2661 uint32_t ulpStatus:4; 2662 uint32_t ulpCommand:8; 2663 uint32_t ulpClass:3; 2664 uint32_t ulpIr:1; 2665 uint32_t ulpPU:2; 2666 uint32_t ulpFCP2Rcvy:1; 2667 uint32_t ulpXS:1; 2668 uint32_t ulpTimeout:8; 2669 #endif 2670 2671 #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 2672 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 2673 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 2674 #define CLASS1 0 /* Class 1 */ 2675 #define CLASS2 1 /* Class 2 */ 2676 #define CLASS3 2 /* Class 3 */ 2677 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 2678 2679 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 2680 #define IOSTAT_FCP_RSP_ERROR 0x1 2681 #define IOSTAT_REMOTE_STOP 0x2 2682 #define IOSTAT_LOCAL_REJECT 0x3 2683 #define IOSTAT_NPORT_RJT 0x4 2684 #define IOSTAT_FABRIC_RJT 0x5 2685 #define IOSTAT_NPORT_BSY 0x6 2686 #define IOSTAT_FABRIC_BSY 0x7 2687 #define IOSTAT_INTERMED_RSP 0x8 2688 #define IOSTAT_LS_RJT 0x9 2689 #define IOSTAT_BA_RJT 0xA 2690 #define IOSTAT_RSVD1 0xB 2691 #define IOSTAT_RSVD2 0xC 2692 #define IOSTAT_RSVD3 0xD 2693 #define IOSTAT_RSVD4 0xE 2694 #define IOSTAT_RSVD5 0xF 2695 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 2696 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 2697 #define IOSTAT_CNT 0x11 2698 2699 } IOCB_t; 2700 2701 2702 #define SLI1_SLIM_SIZE (4 * 1024) 2703 2704 /* Up to 498 IOCBs will fit into 16k 2705 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 2706 */ 2707 #define SLI2_SLIM_SIZE (16 * 1024) 2708 2709 /* Maximum IOCBs that will fit in SLI2 slim */ 2710 #define MAX_SLI2_IOCB 498 2711 2712 struct lpfc_sli2_slim { 2713 MAILBOX_t mbx; 2714 PCB_t pcb; 2715 IOCB_t IOCBs[MAX_SLI2_IOCB]; 2716 }; 2717 2718 /******************************************************************* 2719 This macro check PCI device to allow special handling for LC HBAs. 2720 2721 Parameters: 2722 device : struct pci_dev 's device field 2723 2724 return 1 => TRUE 2725 0 => FALSE 2726 *******************************************************************/ 2727 static inline int 2728 lpfc_is_LC_HBA(unsigned short device) 2729 { 2730 if ((device == PCI_DEVICE_ID_TFLY) || 2731 (device == PCI_DEVICE_ID_PFLY) || 2732 (device == PCI_DEVICE_ID_LP101) || 2733 (device == PCI_DEVICE_ID_BMID) || 2734 (device == PCI_DEVICE_ID_BSMB) || 2735 (device == PCI_DEVICE_ID_ZMID) || 2736 (device == PCI_DEVICE_ID_ZSMB) || 2737 (device == PCI_DEVICE_ID_RFLY)) 2738 return 1; 2739 else 2740 return 0; 2741 } 2742