1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2004-2010 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 #define FDMI_DID 0xfffffaU 22 #define NameServer_DID 0xfffffcU 23 #define SCR_DID 0xfffffdU 24 #define Fabric_DID 0xfffffeU 25 #define Bcast_DID 0xffffffU 26 #define Mask_DID 0xffffffU 27 #define CT_DID_MASK 0xffff00U 28 #define Fabric_DID_MASK 0xfff000U 29 #define WELL_KNOWN_DID_MASK 0xfffff0U 30 31 #define PT2PT_LocalID 1 32 #define PT2PT_RemoteID 2 33 34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 36 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */ 37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 38 39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 40 0 */ 41 42 #define FCELSSIZE 1024 /* maximum ELS transfer size */ 43 44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 45 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */ 46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 47 #define LPFC_FCP_NEXT_RING 3 48 49 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 50 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 51 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */ 52 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */ 53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 55 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 56 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 57 #define SLI2_IOCB_CMD_R3_ENTRIES 0 58 #define SLI2_IOCB_RSP_R3_ENTRIES 0 59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 61 62 #define SLI2_IOCB_CMD_SIZE 32 63 #define SLI2_IOCB_RSP_SIZE 32 64 #define SLI3_IOCB_CMD_SIZE 128 65 #define SLI3_IOCB_RSP_SIZE 64 66 67 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff 68 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff 69 70 /* vendor ID used in SCSI netlink calls */ 71 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX) 72 73 /* Common Transport structures and definitions */ 74 75 union CtRevisionId { 76 /* Structure is in Big Endian format */ 77 struct { 78 uint32_t Revision:8; 79 uint32_t InId:24; 80 } bits; 81 uint32_t word; 82 }; 83 84 union CtCommandResponse { 85 /* Structure is in Big Endian format */ 86 struct { 87 uint32_t CmdRsp:16; 88 uint32_t Size:16; 89 } bits; 90 uint32_t word; 91 }; 92 93 #define FC4_FEATURE_INIT 0x2 94 #define FC4_FEATURE_TARGET 0x1 95 96 struct lpfc_sli_ct_request { 97 /* Structure is in Big Endian format */ 98 union CtRevisionId RevisionId; 99 uint8_t FsType; 100 uint8_t FsSubType; 101 uint8_t Options; 102 uint8_t Rsrvd1; 103 union CtCommandResponse CommandResponse; 104 uint8_t Rsrvd2; 105 uint8_t ReasonCode; 106 uint8_t Explanation; 107 uint8_t VendorUnique; 108 109 union { 110 uint32_t PortID; 111 struct gid { 112 uint8_t PortType; /* for GID_PT requests */ 113 uint8_t DomainScope; 114 uint8_t AreaScope; 115 uint8_t Fc4Type; /* for GID_FT requests */ 116 } gid; 117 struct rft { 118 uint32_t PortId; /* For RFT_ID requests */ 119 120 #ifdef __BIG_ENDIAN_BITFIELD 121 uint32_t rsvd0:16; 122 uint32_t rsvd1:7; 123 uint32_t fcpReg:1; /* Type 8 */ 124 uint32_t rsvd2:2; 125 uint32_t ipReg:1; /* Type 5 */ 126 uint32_t rsvd3:5; 127 #else /* __LITTLE_ENDIAN_BITFIELD */ 128 uint32_t rsvd0:16; 129 uint32_t fcpReg:1; /* Type 8 */ 130 uint32_t rsvd1:7; 131 uint32_t rsvd3:5; 132 uint32_t ipReg:1; /* Type 5 */ 133 uint32_t rsvd2:2; 134 #endif 135 136 uint32_t rsvd[7]; 137 } rft; 138 struct rnn { 139 uint32_t PortId; /* For RNN_ID requests */ 140 uint8_t wwnn[8]; 141 } rnn; 142 struct rsnn { /* For RSNN_ID requests */ 143 uint8_t wwnn[8]; 144 uint8_t len; 145 uint8_t symbname[255]; 146 } rsnn; 147 struct da_id { /* For DA_ID requests */ 148 uint32_t port_id; 149 } da_id; 150 struct rspn { /* For RSPN_ID requests */ 151 uint32_t PortId; 152 uint8_t len; 153 uint8_t symbname[255]; 154 } rspn; 155 struct gff { 156 uint32_t PortId; 157 } gff; 158 struct gff_acc { 159 uint8_t fbits[128]; 160 } gff_acc; 161 #define FCP_TYPE_FEATURE_OFFSET 7 162 struct rff { 163 uint32_t PortId; 164 uint8_t reserved[2]; 165 uint8_t fbits; 166 uint8_t type_code; /* type=8 for FCP */ 167 } rff; 168 } un; 169 }; 170 171 #define SLI_CT_REVISION 1 172 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 173 sizeof(struct gid)) 174 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 175 sizeof(struct gff)) 176 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 177 sizeof(struct rft)) 178 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 179 sizeof(struct rff)) 180 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 181 sizeof(struct rnn)) 182 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 183 sizeof(struct rsnn)) 184 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 185 sizeof(struct da_id)) 186 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 187 sizeof(struct rspn)) 188 189 /* 190 * FsType Definitions 191 */ 192 193 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 194 #define SLI_CT_TIME_SERVICE 0xFB 195 #define SLI_CT_DIRECTORY_SERVICE 0xFC 196 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 197 198 /* 199 * Directory Service Subtypes 200 */ 201 202 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 203 204 /* 205 * Response Codes 206 */ 207 208 #define SLI_CT_RESPONSE_FS_RJT 0x8001 209 #define SLI_CT_RESPONSE_FS_ACC 0x8002 210 211 /* 212 * Reason Codes 213 */ 214 215 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 216 #define SLI_CT_INVALID_COMMAND 0x01 217 #define SLI_CT_INVALID_VERSION 0x02 218 #define SLI_CT_LOGICAL_ERROR 0x03 219 #define SLI_CT_INVALID_IU_SIZE 0x04 220 #define SLI_CT_LOGICAL_BUSY 0x05 221 #define SLI_CT_PROTOCOL_ERROR 0x07 222 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 223 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 224 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 225 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 226 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 227 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 228 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 229 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 230 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 231 #define SLI_CT_VENDOR_UNIQUE 0xff 232 233 /* 234 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 235 */ 236 237 #define SLI_CT_NO_PORT_ID 0x01 238 #define SLI_CT_NO_PORT_NAME 0x02 239 #define SLI_CT_NO_NODE_NAME 0x03 240 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 241 #define SLI_CT_NO_IP_ADDRESS 0x05 242 #define SLI_CT_NO_IPA 0x06 243 #define SLI_CT_NO_FC4_TYPES 0x07 244 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 245 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 246 #define SLI_CT_NO_PORT_TYPE 0x0A 247 #define SLI_CT_ACCESS_DENIED 0x10 248 #define SLI_CT_INVALID_PORT_ID 0x11 249 #define SLI_CT_DATABASE_EMPTY 0x12 250 251 /* 252 * Name Server Command Codes 253 */ 254 255 #define SLI_CTNS_GA_NXT 0x0100 256 #define SLI_CTNS_GPN_ID 0x0112 257 #define SLI_CTNS_GNN_ID 0x0113 258 #define SLI_CTNS_GCS_ID 0x0114 259 #define SLI_CTNS_GFT_ID 0x0117 260 #define SLI_CTNS_GSPN_ID 0x0118 261 #define SLI_CTNS_GPT_ID 0x011A 262 #define SLI_CTNS_GFF_ID 0x011F 263 #define SLI_CTNS_GID_PN 0x0121 264 #define SLI_CTNS_GID_NN 0x0131 265 #define SLI_CTNS_GIP_NN 0x0135 266 #define SLI_CTNS_GIPA_NN 0x0136 267 #define SLI_CTNS_GSNN_NN 0x0139 268 #define SLI_CTNS_GNN_IP 0x0153 269 #define SLI_CTNS_GIPA_IP 0x0156 270 #define SLI_CTNS_GID_FT 0x0171 271 #define SLI_CTNS_GID_PT 0x01A1 272 #define SLI_CTNS_RPN_ID 0x0212 273 #define SLI_CTNS_RNN_ID 0x0213 274 #define SLI_CTNS_RCS_ID 0x0214 275 #define SLI_CTNS_RFT_ID 0x0217 276 #define SLI_CTNS_RSPN_ID 0x0218 277 #define SLI_CTNS_RPT_ID 0x021A 278 #define SLI_CTNS_RFF_ID 0x021F 279 #define SLI_CTNS_RIP_NN 0x0235 280 #define SLI_CTNS_RIPA_NN 0x0236 281 #define SLI_CTNS_RSNN_NN 0x0239 282 #define SLI_CTNS_DA_ID 0x0300 283 284 /* 285 * Port Types 286 */ 287 288 #define SLI_CTPT_N_PORT 0x01 289 #define SLI_CTPT_NL_PORT 0x02 290 #define SLI_CTPT_FNL_PORT 0x03 291 #define SLI_CTPT_IP 0x04 292 #define SLI_CTPT_FCP 0x08 293 #define SLI_CTPT_NX_PORT 0x7F 294 #define SLI_CTPT_F_PORT 0x81 295 #define SLI_CTPT_FL_PORT 0x82 296 #define SLI_CTPT_E_PORT 0x84 297 298 #define SLI_CT_LAST_ENTRY 0x80000000 299 300 /* Fibre Channel Service Parameter definitions */ 301 302 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 303 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 304 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 305 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 306 307 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 308 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 309 #define FC_PH3 0x20 /* FC-PH-3 version */ 310 311 #define FF_FRAME_SIZE 2048 312 313 struct lpfc_name { 314 union { 315 struct { 316 #ifdef __BIG_ENDIAN_BITFIELD 317 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 318 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 319 8:11 of IEEE ext */ 320 #else /* __LITTLE_ENDIAN_BITFIELD */ 321 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 322 8:11 of IEEE ext */ 323 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 324 #endif 325 326 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 327 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 328 #define NAME_FC_TYPE 0x3 /* FC native name type */ 329 #define NAME_IP_TYPE 0x4 /* IP address */ 330 #define NAME_CCITT_TYPE 0xC 331 #define NAME_CCITT_GR_TYPE 0xE 332 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE 333 extended Lsb */ 334 uint8_t IEEE[6]; /* FC IEEE address */ 335 } s; 336 uint8_t wwn[8]; 337 } u; 338 }; 339 340 struct csp { 341 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 342 uint8_t fcphLow; 343 uint8_t bbCreditMsb; 344 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 345 346 /* 347 * Word 1 Bit 31 in common service parameter is overloaded. 348 * Word 1 Bit 31 in FLOGI request is multiple NPort request 349 * Word 1 Bit 31 in FLOGI response is clean address bit 350 */ 351 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */ 352 /* 353 * Word 1 Bit 30 in common service parameter is overloaded. 354 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics 355 * Word 1 Bit 30 in PLOGI request is random offset 356 */ 357 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */ 358 #ifdef __BIG_ENDIAN_BITFIELD 359 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 360 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 361 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 362 uint16_t fPort:1; /* FC Word 1, bit 28 */ 363 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 364 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 365 uint16_t multicast:1; /* FC Word 1, bit 25 */ 366 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 367 368 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 369 uint16_t simplex:1; /* FC Word 1, bit 22 */ 370 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 371 uint16_t dhd:1; /* FC Word 1, bit 18 */ 372 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 373 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 374 #else /* __LITTLE_ENDIAN_BITFIELD */ 375 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 376 uint16_t multicast:1; /* FC Word 1, bit 25 */ 377 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 378 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 379 uint16_t fPort:1; /* FC Word 1, bit 28 */ 380 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 381 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 382 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 383 384 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 385 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 386 uint16_t dhd:1; /* FC Word 1, bit 18 */ 387 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 388 uint16_t simplex:1; /* FC Word 1, bit 22 */ 389 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 390 #endif 391 392 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 393 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 394 union { 395 struct { 396 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 397 398 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 399 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 400 401 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 402 } nPort; 403 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 404 } w2; 405 406 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 407 }; 408 409 struct class_parms { 410 #ifdef __BIG_ENDIAN_BITFIELD 411 uint8_t classValid:1; /* FC Word 0, bit 31 */ 412 uint8_t intermix:1; /* FC Word 0, bit 30 */ 413 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 414 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 415 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 416 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 417 #else /* __LITTLE_ENDIAN_BITFIELD */ 418 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 419 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 420 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 421 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 422 uint8_t intermix:1; /* FC Word 0, bit 30 */ 423 uint8_t classValid:1; /* FC Word 0, bit 31 */ 424 425 #endif 426 427 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 428 429 #ifdef __BIG_ENDIAN_BITFIELD 430 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 431 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 432 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 433 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 434 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 435 #else /* __LITTLE_ENDIAN_BITFIELD */ 436 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 437 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 438 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 439 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 440 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 441 #endif 442 443 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 444 445 #ifdef __BIG_ENDIAN_BITFIELD 446 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 447 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 448 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 449 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 450 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 451 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 452 #else /* __LITTLE_ENDIAN_BITFIELD */ 453 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 454 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 455 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 456 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 457 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 458 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 459 #endif 460 461 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 462 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 463 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 464 465 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 466 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 467 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 468 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 469 470 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 471 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 472 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 473 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 474 }; 475 476 struct serv_parm { /* Structure is in Big Endian format */ 477 struct csp cmn; 478 struct lpfc_name portName; 479 struct lpfc_name nodeName; 480 struct class_parms cls1; 481 struct class_parms cls2; 482 struct class_parms cls3; 483 struct class_parms cls4; 484 uint8_t vendorVersion[16]; 485 }; 486 487 /* 488 * Virtual Fabric Tagging Header 489 */ 490 struct fc_vft_header { 491 uint32_t word0; 492 #define fc_vft_hdr_r_ctl_SHIFT 24 493 #define fc_vft_hdr_r_ctl_MASK 0xFF 494 #define fc_vft_hdr_r_ctl_WORD word0 495 #define fc_vft_hdr_ver_SHIFT 22 496 #define fc_vft_hdr_ver_MASK 0x3 497 #define fc_vft_hdr_ver_WORD word0 498 #define fc_vft_hdr_type_SHIFT 18 499 #define fc_vft_hdr_type_MASK 0xF 500 #define fc_vft_hdr_type_WORD word0 501 #define fc_vft_hdr_e_SHIFT 16 502 #define fc_vft_hdr_e_MASK 0x1 503 #define fc_vft_hdr_e_WORD word0 504 #define fc_vft_hdr_priority_SHIFT 13 505 #define fc_vft_hdr_priority_MASK 0x7 506 #define fc_vft_hdr_priority_WORD word0 507 #define fc_vft_hdr_vf_id_SHIFT 1 508 #define fc_vft_hdr_vf_id_MASK 0xFFF 509 #define fc_vft_hdr_vf_id_WORD word0 510 uint32_t word1; 511 #define fc_vft_hdr_hopct_SHIFT 24 512 #define fc_vft_hdr_hopct_MASK 0xFF 513 #define fc_vft_hdr_hopct_WORD word1 514 }; 515 516 /* 517 * Extended Link Service LS_COMMAND codes (Payload Word 0) 518 */ 519 #ifdef __BIG_ENDIAN_BITFIELD 520 #define ELS_CMD_MASK 0xffff0000 521 #define ELS_RSP_MASK 0xff000000 522 #define ELS_CMD_LS_RJT 0x01000000 523 #define ELS_CMD_ACC 0x02000000 524 #define ELS_CMD_PLOGI 0x03000000 525 #define ELS_CMD_FLOGI 0x04000000 526 #define ELS_CMD_LOGO 0x05000000 527 #define ELS_CMD_ABTX 0x06000000 528 #define ELS_CMD_RCS 0x07000000 529 #define ELS_CMD_RES 0x08000000 530 #define ELS_CMD_RSS 0x09000000 531 #define ELS_CMD_RSI 0x0A000000 532 #define ELS_CMD_ESTS 0x0B000000 533 #define ELS_CMD_ESTC 0x0C000000 534 #define ELS_CMD_ADVC 0x0D000000 535 #define ELS_CMD_RTV 0x0E000000 536 #define ELS_CMD_RLS 0x0F000000 537 #define ELS_CMD_ECHO 0x10000000 538 #define ELS_CMD_TEST 0x11000000 539 #define ELS_CMD_RRQ 0x12000000 540 #define ELS_CMD_PRLI 0x20100014 541 #define ELS_CMD_PRLO 0x21100014 542 #define ELS_CMD_PRLO_ACC 0x02100014 543 #define ELS_CMD_PDISC 0x50000000 544 #define ELS_CMD_FDISC 0x51000000 545 #define ELS_CMD_ADISC 0x52000000 546 #define ELS_CMD_FARP 0x54000000 547 #define ELS_CMD_FARPR 0x55000000 548 #define ELS_CMD_RPS 0x56000000 549 #define ELS_CMD_RPL 0x57000000 550 #define ELS_CMD_FAN 0x60000000 551 #define ELS_CMD_RSCN 0x61040000 552 #define ELS_CMD_SCR 0x62000000 553 #define ELS_CMD_RNID 0x78000000 554 #define ELS_CMD_LIRR 0x7A000000 555 #else /* __LITTLE_ENDIAN_BITFIELD */ 556 #define ELS_CMD_MASK 0xffff 557 #define ELS_RSP_MASK 0xff 558 #define ELS_CMD_LS_RJT 0x01 559 #define ELS_CMD_ACC 0x02 560 #define ELS_CMD_PLOGI 0x03 561 #define ELS_CMD_FLOGI 0x04 562 #define ELS_CMD_LOGO 0x05 563 #define ELS_CMD_ABTX 0x06 564 #define ELS_CMD_RCS 0x07 565 #define ELS_CMD_RES 0x08 566 #define ELS_CMD_RSS 0x09 567 #define ELS_CMD_RSI 0x0A 568 #define ELS_CMD_ESTS 0x0B 569 #define ELS_CMD_ESTC 0x0C 570 #define ELS_CMD_ADVC 0x0D 571 #define ELS_CMD_RTV 0x0E 572 #define ELS_CMD_RLS 0x0F 573 #define ELS_CMD_ECHO 0x10 574 #define ELS_CMD_TEST 0x11 575 #define ELS_CMD_RRQ 0x12 576 #define ELS_CMD_PRLI 0x14001020 577 #define ELS_CMD_PRLO 0x14001021 578 #define ELS_CMD_PRLO_ACC 0x14001002 579 #define ELS_CMD_PDISC 0x50 580 #define ELS_CMD_FDISC 0x51 581 #define ELS_CMD_ADISC 0x52 582 #define ELS_CMD_FARP 0x54 583 #define ELS_CMD_FARPR 0x55 584 #define ELS_CMD_RPS 0x56 585 #define ELS_CMD_RPL 0x57 586 #define ELS_CMD_FAN 0x60 587 #define ELS_CMD_RSCN 0x0461 588 #define ELS_CMD_SCR 0x62 589 #define ELS_CMD_RNID 0x78 590 #define ELS_CMD_LIRR 0x7A 591 #endif 592 593 /* 594 * LS_RJT Payload Definition 595 */ 596 597 struct ls_rjt { /* Structure is in Big Endian format */ 598 union { 599 uint32_t lsRjtError; 600 struct { 601 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 602 603 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 604 /* LS_RJT reason codes */ 605 #define LSRJT_INVALID_CMD 0x01 606 #define LSRJT_LOGICAL_ERR 0x03 607 #define LSRJT_LOGICAL_BSY 0x05 608 #define LSRJT_PROTOCOL_ERR 0x07 609 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 610 #define LSRJT_CMD_UNSUPPORTED 0x0B 611 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 612 613 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 614 /* LS_RJT reason explanation */ 615 #define LSEXP_NOTHING_MORE 0x00 616 #define LSEXP_SPARM_OPTIONS 0x01 617 #define LSEXP_SPARM_ICTL 0x03 618 #define LSEXP_SPARM_RCTL 0x05 619 #define LSEXP_SPARM_RCV_SIZE 0x07 620 #define LSEXP_SPARM_CONCUR_SEQ 0x09 621 #define LSEXP_SPARM_CREDIT 0x0B 622 #define LSEXP_INVALID_PNAME 0x0D 623 #define LSEXP_INVALID_NNAME 0x0E 624 #define LSEXP_INVALID_CSP 0x0F 625 #define LSEXP_INVALID_ASSOC_HDR 0x11 626 #define LSEXP_ASSOC_HDR_REQ 0x13 627 #define LSEXP_INVALID_O_SID 0x15 628 #define LSEXP_INVALID_OX_RX 0x17 629 #define LSEXP_CMD_IN_PROGRESS 0x19 630 #define LSEXP_PORT_LOGIN_REQ 0x1E 631 #define LSEXP_INVALID_NPORT_ID 0x1F 632 #define LSEXP_INVALID_SEQ_ID 0x21 633 #define LSEXP_INVALID_XCHG 0x23 634 #define LSEXP_INACTIVE_XCHG 0x25 635 #define LSEXP_RQ_REQUIRED 0x27 636 #define LSEXP_OUT_OF_RESOURCE 0x29 637 #define LSEXP_CANT_GIVE_DATA 0x2A 638 #define LSEXP_REQ_UNSUPPORTED 0x2C 639 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 640 } b; 641 } un; 642 }; 643 644 /* 645 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 646 */ 647 648 typedef struct _LOGO { /* Structure is in Big Endian format */ 649 union { 650 uint32_t nPortId32; /* Access nPortId as a word */ 651 struct { 652 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 653 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 654 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 655 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 656 } b; 657 } un; 658 struct lpfc_name portName; /* N_port name field */ 659 } LOGO; 660 661 /* 662 * FCP Login (PRLI Request / ACC) Payload Definition 663 */ 664 665 #define PRLX_PAGE_LEN 0x10 666 #define TPRLO_PAGE_LEN 0x14 667 668 typedef struct _PRLI { /* Structure is in Big Endian format */ 669 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 670 671 #define PRLI_FCP_TYPE 0x08 672 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 673 674 #ifdef __BIG_ENDIAN_BITFIELD 675 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 676 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 677 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 678 679 /* ACC = imagePairEstablished */ 680 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 681 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 682 #else /* __LITTLE_ENDIAN_BITFIELD */ 683 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 684 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 685 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 686 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 687 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 688 /* ACC = imagePairEstablished */ 689 #endif 690 691 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 692 #define PRLI_NO_RESOURCES 0x2 693 #define PRLI_INIT_INCOMPLETE 0x3 694 #define PRLI_NO_SUCH_PA 0x4 695 #define PRLI_PREDEF_CONFIG 0x5 696 #define PRLI_PARTIAL_SUCCESS 0x6 697 #define PRLI_INVALID_PAGE_CNT 0x7 698 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 699 700 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 701 702 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 703 704 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 705 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 706 707 #ifdef __BIG_ENDIAN_BITFIELD 708 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 709 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 710 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 711 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 712 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 713 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 714 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 715 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 716 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 717 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 718 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 719 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 720 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 721 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 722 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 723 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 724 #else /* __LITTLE_ENDIAN_BITFIELD */ 725 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 726 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 727 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 728 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 729 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 730 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 731 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 732 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 733 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 734 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 735 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 736 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 737 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 738 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 739 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 740 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 741 #endif 742 } PRLI; 743 744 /* 745 * FCP Logout (PRLO Request / ACC) Payload Definition 746 */ 747 748 typedef struct _PRLO { /* Structure is in Big Endian format */ 749 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 750 751 #define PRLO_FCP_TYPE 0x08 752 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 753 754 #ifdef __BIG_ENDIAN_BITFIELD 755 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 756 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 757 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 758 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 759 #else /* __LITTLE_ENDIAN_BITFIELD */ 760 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 761 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 762 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 763 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 764 #endif 765 766 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 767 #define PRLO_NO_SUCH_IMAGE 0x4 768 #define PRLO_INVALID_PAGE_CNT 0x7 769 770 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 771 772 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 773 774 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 775 776 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 777 } PRLO; 778 779 typedef struct _ADISC { /* Structure is in Big Endian format */ 780 uint32_t hardAL_PA; 781 struct lpfc_name portName; 782 struct lpfc_name nodeName; 783 uint32_t DID; 784 } ADISC; 785 786 typedef struct _FARP { /* Structure is in Big Endian format */ 787 uint32_t Mflags:8; 788 uint32_t Odid:24; 789 #define FARP_NO_ACTION 0 /* FARP information enclosed, no 790 action */ 791 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 792 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 793 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 794 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 795 supported */ 796 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 797 supported */ 798 uint32_t Rflags:8; 799 uint32_t Rdid:24; 800 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 801 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 802 struct lpfc_name OportName; 803 struct lpfc_name OnodeName; 804 struct lpfc_name RportName; 805 struct lpfc_name RnodeName; 806 uint8_t Oipaddr[16]; 807 uint8_t Ripaddr[16]; 808 } FARP; 809 810 typedef struct _FAN { /* Structure is in Big Endian format */ 811 uint32_t Fdid; 812 struct lpfc_name FportName; 813 struct lpfc_name FnodeName; 814 } FAN; 815 816 typedef struct _SCR { /* Structure is in Big Endian format */ 817 uint8_t resvd1; 818 uint8_t resvd2; 819 uint8_t resvd3; 820 uint8_t Function; 821 #define SCR_FUNC_FABRIC 0x01 822 #define SCR_FUNC_NPORT 0x02 823 #define SCR_FUNC_FULL 0x03 824 #define SCR_CLEAR 0xff 825 } SCR; 826 827 typedef struct _RNID_TOP_DISC { 828 struct lpfc_name portName; 829 uint8_t resvd[8]; 830 uint32_t unitType; 831 #define RNID_HBA 0x7 832 #define RNID_HOST 0xa 833 #define RNID_DRIVER 0xd 834 uint32_t physPort; 835 uint32_t attachedNodes; 836 uint16_t ipVersion; 837 #define RNID_IPV4 0x1 838 #define RNID_IPV6 0x2 839 uint16_t UDPport; 840 uint8_t ipAddr[16]; 841 uint16_t resvd1; 842 uint16_t flags; 843 #define RNID_TD_SUPPORT 0x1 844 #define RNID_LP_VALID 0x2 845 } RNID_TOP_DISC; 846 847 typedef struct _RNID { /* Structure is in Big Endian format */ 848 uint8_t Format; 849 #define RNID_TOPOLOGY_DISC 0xdf 850 uint8_t CommonLen; 851 uint8_t resvd1; 852 uint8_t SpecificLen; 853 struct lpfc_name portName; 854 struct lpfc_name nodeName; 855 union { 856 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 857 } un; 858 } RNID; 859 860 typedef struct _RPS { /* Structure is in Big Endian format */ 861 union { 862 uint32_t portNum; 863 struct lpfc_name portName; 864 } un; 865 } RPS; 866 867 typedef struct _RPS_RSP { /* Structure is in Big Endian format */ 868 uint16_t rsvd1; 869 uint16_t portStatus; 870 uint32_t linkFailureCnt; 871 uint32_t lossSyncCnt; 872 uint32_t lossSignalCnt; 873 uint32_t primSeqErrCnt; 874 uint32_t invalidXmitWord; 875 uint32_t crcCnt; 876 } RPS_RSP; 877 878 struct RLS { /* Structure is in Big Endian format */ 879 uint32_t rls; 880 #define rls_rsvd_SHIFT 24 881 #define rls_rsvd_MASK 0x000000ff 882 #define rls_rsvd_WORD rls 883 #define rls_did_SHIFT 0 884 #define rls_did_MASK 0x00ffffff 885 #define rls_did_WORD rls 886 }; 887 888 struct RLS_RSP { /* Structure is in Big Endian format */ 889 uint32_t linkFailureCnt; 890 uint32_t lossSyncCnt; 891 uint32_t lossSignalCnt; 892 uint32_t primSeqErrCnt; 893 uint32_t invalidXmitWord; 894 uint32_t crcCnt; 895 }; 896 897 struct RRQ { /* Structure is in Big Endian format */ 898 uint32_t rrq; 899 #define rrq_rsvd_SHIFT 24 900 #define rrq_rsvd_MASK 0x000000ff 901 #define rrq_rsvd_WORD rrq 902 #define rrq_did_SHIFT 0 903 #define rrq_did_MASK 0x00ffffff 904 #define rrq_did_WORD rrq 905 uint32_t rrq_exchg; 906 #define rrq_oxid_SHIFT 16 907 #define rrq_oxid_MASK 0xffff 908 #define rrq_oxid_WORD rrq_exchg 909 #define rrq_rxid_SHIFT 0 910 #define rrq_rxid_MASK 0xffff 911 #define rrq_rxid_WORD rrq_exchg 912 }; 913 914 #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */ 915 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/ 916 917 struct RTV_RSP { /* Structure is in Big Endian format */ 918 uint32_t ratov; 919 uint32_t edtov; 920 uint32_t qtov; 921 #define qtov_rsvd0_SHIFT 28 922 #define qtov_rsvd0_MASK 0x0000000f 923 #define qtov_rsvd0_WORD qtov /* reserved */ 924 #define qtov_edtovres_SHIFT 27 925 #define qtov_edtovres_MASK 0x00000001 926 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */ 927 #define qtov__rsvd1_SHIFT 19 928 #define qtov_rsvd1_MASK 0x0000003f 929 #define qtov_rsvd1_WORD qtov /* reserved */ 930 #define qtov_rttov_SHIFT 18 931 #define qtov_rttov_MASK 0x00000001 932 #define qtov_rttov_WORD qtov /* R_T_TOV value */ 933 #define qtov_rsvd2_SHIFT 0 934 #define qtov_rsvd2_MASK 0x0003ffff 935 #define qtov_rsvd2_WORD qtov /* reserved */ 936 }; 937 938 939 typedef struct _RPL { /* Structure is in Big Endian format */ 940 uint32_t maxsize; 941 uint32_t index; 942 } RPL; 943 944 typedef struct _PORT_NUM_BLK { 945 uint32_t portNum; 946 uint32_t portID; 947 struct lpfc_name portName; 948 } PORT_NUM_BLK; 949 950 typedef struct _RPL_RSP { /* Structure is in Big Endian format */ 951 uint32_t listLen; 952 uint32_t index; 953 PORT_NUM_BLK port_num_blk; 954 } RPL_RSP; 955 956 /* This is used for RSCN command */ 957 typedef struct _D_ID { /* Structure is in Big Endian format */ 958 union { 959 uint32_t word; 960 struct { 961 #ifdef __BIG_ENDIAN_BITFIELD 962 uint8_t resv; 963 uint8_t domain; 964 uint8_t area; 965 uint8_t id; 966 #else /* __LITTLE_ENDIAN_BITFIELD */ 967 uint8_t id; 968 uint8_t area; 969 uint8_t domain; 970 uint8_t resv; 971 #endif 972 } b; 973 } un; 974 } D_ID; 975 976 #define RSCN_ADDRESS_FORMAT_PORT 0x0 977 #define RSCN_ADDRESS_FORMAT_AREA 0x1 978 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2 979 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3 980 #define RSCN_ADDRESS_FORMAT_MASK 0x3 981 982 /* 983 * Structure to define all ELS Payload types 984 */ 985 986 typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 987 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 988 uint8_t elsByte1; 989 uint8_t elsByte2; 990 uint8_t elsByte3; 991 union { 992 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 993 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 994 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 995 PRLI prli; /* Payload for PRLI/ACC */ 996 PRLO prlo; /* Payload for PRLO/ACC */ 997 ADISC adisc; /* Payload for ADISC/ACC */ 998 FARP farp; /* Payload for FARP/ACC */ 999 FAN fan; /* Payload for FAN */ 1000 SCR scr; /* Payload for SCR/ACC */ 1001 RNID rnid; /* Payload for RNID */ 1002 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 1003 } un; 1004 } ELS_PKT; 1005 1006 /* 1007 * FDMI 1008 * HBA MAnagement Operations Command Codes 1009 */ 1010 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 1011 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 1012 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 1013 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 1014 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 1015 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */ 1016 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 1017 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 1018 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 1019 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 1020 1021 /* 1022 * Management Service Subtypes 1023 */ 1024 #define SLI_CT_FDMI_Subtypes 0x10 1025 1026 /* 1027 * HBA Management Service Reject Code 1028 */ 1029 #define REJECT_CODE 0x9 /* Unable to perform command request */ 1030 1031 /* 1032 * HBA Management Service Reject Reason Code 1033 * Please refer to the Reason Codes above 1034 */ 1035 1036 /* 1037 * HBA Attribute Types 1038 */ 1039 #define NODE_NAME 0x1 1040 #define MANUFACTURER 0x2 1041 #define SERIAL_NUMBER 0x3 1042 #define MODEL 0x4 1043 #define MODEL_DESCRIPTION 0x5 1044 #define HARDWARE_VERSION 0x6 1045 #define DRIVER_VERSION 0x7 1046 #define OPTION_ROM_VERSION 0x8 1047 #define FIRMWARE_VERSION 0x9 1048 #define OS_NAME_VERSION 0xa 1049 #define MAX_CT_PAYLOAD_LEN 0xb 1050 1051 /* 1052 * Port Attrubute Types 1053 */ 1054 #define SUPPORTED_FC4_TYPES 0x1 1055 #define SUPPORTED_SPEED 0x2 1056 #define PORT_SPEED 0x3 1057 #define MAX_FRAME_SIZE 0x4 1058 #define OS_DEVICE_NAME 0x5 1059 #define HOST_NAME 0x6 1060 1061 union AttributesDef { 1062 /* Structure is in Big Endian format */ 1063 struct { 1064 uint32_t AttrType:16; 1065 uint32_t AttrLen:16; 1066 } bits; 1067 uint32_t word; 1068 }; 1069 1070 1071 /* 1072 * HBA Attribute Entry (8 - 260 bytes) 1073 */ 1074 typedef struct { 1075 union AttributesDef ad; 1076 union { 1077 uint32_t VendorSpecific; 1078 uint8_t Manufacturer[64]; 1079 uint8_t SerialNumber[64]; 1080 uint8_t Model[256]; 1081 uint8_t ModelDescription[256]; 1082 uint8_t HardwareVersion[256]; 1083 uint8_t DriverVersion[256]; 1084 uint8_t OptionROMVersion[256]; 1085 uint8_t FirmwareVersion[256]; 1086 struct lpfc_name NodeName; 1087 uint8_t SupportFC4Types[32]; 1088 uint32_t SupportSpeed; 1089 uint32_t PortSpeed; 1090 uint32_t MaxFrameSize; 1091 uint8_t OsDeviceName[256]; 1092 uint8_t OsNameVersion[256]; 1093 uint32_t MaxCTPayloadLen; 1094 uint8_t HostName[256]; 1095 } un; 1096 } ATTRIBUTE_ENTRY; 1097 1098 /* 1099 * HBA Attribute Block 1100 */ 1101 typedef struct { 1102 uint32_t EntryCnt; /* Number of HBA attribute entries */ 1103 ATTRIBUTE_ENTRY Entry; /* Variable-length array */ 1104 } ATTRIBUTE_BLOCK; 1105 1106 /* 1107 * Port Entry 1108 */ 1109 typedef struct { 1110 struct lpfc_name PortName; 1111 } PORT_ENTRY; 1112 1113 /* 1114 * HBA Identifier 1115 */ 1116 typedef struct { 1117 struct lpfc_name PortName; 1118 } HBA_IDENTIFIER; 1119 1120 /* 1121 * Registered Port List Format 1122 */ 1123 typedef struct { 1124 uint32_t EntryCnt; 1125 PORT_ENTRY pe; /* Variable-length array */ 1126 } REG_PORT_LIST; 1127 1128 /* 1129 * Register HBA(RHBA) 1130 */ 1131 typedef struct { 1132 HBA_IDENTIFIER hi; 1133 REG_PORT_LIST rpl; /* variable-length array */ 1134 /* ATTRIBUTE_BLOCK ab; */ 1135 } REG_HBA; 1136 1137 /* 1138 * Register HBA Attributes (RHAT) 1139 */ 1140 typedef struct { 1141 struct lpfc_name HBA_PortName; 1142 ATTRIBUTE_BLOCK ab; 1143 } REG_HBA_ATTRIBUTE; 1144 1145 /* 1146 * Register Port Attributes (RPA) 1147 */ 1148 typedef struct { 1149 struct lpfc_name PortName; 1150 ATTRIBUTE_BLOCK ab; 1151 } REG_PORT_ATTRIBUTE; 1152 1153 /* 1154 * Get Registered HBA List (GRHL) Accept Payload Format 1155 */ 1156 typedef struct { 1157 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */ 1158 struct lpfc_name HBA_PortName; /* Variable-length array */ 1159 } GRHL_ACC_PAYLOAD; 1160 1161 /* 1162 * Get Registered Port List (GRPL) Accept Payload Format 1163 */ 1164 typedef struct { 1165 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */ 1166 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */ 1167 } GRPL_ACC_PAYLOAD; 1168 1169 /* 1170 * Get Port Attributes (GPAT) Accept Payload Format 1171 */ 1172 1173 typedef struct { 1174 ATTRIBUTE_BLOCK pab; 1175 } GPAT_ACC_PAYLOAD; 1176 1177 1178 /* 1179 * Begin HBA configuration parameters. 1180 * The PCI configuration register BAR assignments are: 1181 * BAR0, offset 0x10 - SLIM base memory address 1182 * BAR1, offset 0x14 - SLIM base memory high address 1183 * BAR2, offset 0x18 - REGISTER base memory address 1184 * BAR3, offset 0x1c - REGISTER base memory high address 1185 * BAR4, offset 0x20 - BIU I/O registers 1186 * BAR5, offset 0x24 - REGISTER base io high address 1187 */ 1188 1189 /* Number of rings currently used and available. */ 1190 #define MAX_CONFIGURED_RINGS 3 1191 #define MAX_RINGS 4 1192 1193 /* IOCB / Mailbox is owned by FireFly */ 1194 #define OWN_CHIP 1 1195 1196 /* IOCB / Mailbox is owned by Host */ 1197 #define OWN_HOST 0 1198 1199 /* Number of 4-byte words in an IOCB. */ 1200 #define IOCB_WORD_SZ 8 1201 1202 /* network headers for Dfctl field */ 1203 #define FC_NET_HDR 0x20 1204 1205 /* Start FireFly Register definitions */ 1206 #define PCI_VENDOR_ID_EMULEX 0x10df 1207 #define PCI_DEVICE_ID_FIREFLY 0x1ae5 1208 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100 1209 #define PCI_DEVICE_ID_BALIUS 0xe131 1210 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180 1211 #define PCI_DEVICE_ID_LANCER_FC 0xe200 1212 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208 1213 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260 1214 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268 1215 #define PCI_DEVICE_ID_SAT_SMB 0xf011 1216 #define PCI_DEVICE_ID_SAT_MID 0xf015 1217 #define PCI_DEVICE_ID_RFLY 0xf095 1218 #define PCI_DEVICE_ID_PFLY 0xf098 1219 #define PCI_DEVICE_ID_LP101 0xf0a1 1220 #define PCI_DEVICE_ID_TFLY 0xf0a5 1221 #define PCI_DEVICE_ID_BSMB 0xf0d1 1222 #define PCI_DEVICE_ID_BMID 0xf0d5 1223 #define PCI_DEVICE_ID_ZSMB 0xf0e1 1224 #define PCI_DEVICE_ID_ZMID 0xf0e5 1225 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5 1226 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 1227 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 1228 #define PCI_DEVICE_ID_SAT 0xf100 1229 #define PCI_DEVICE_ID_SAT_SCSP 0xf111 1230 #define PCI_DEVICE_ID_SAT_DCSP 0xf112 1231 #define PCI_DEVICE_ID_FALCON 0xf180 1232 #define PCI_DEVICE_ID_SUPERFLY 0xf700 1233 #define PCI_DEVICE_ID_DRAGONFLY 0xf800 1234 #define PCI_DEVICE_ID_CENTAUR 0xf900 1235 #define PCI_DEVICE_ID_PEGASUS 0xf980 1236 #define PCI_DEVICE_ID_THOR 0xfa00 1237 #define PCI_DEVICE_ID_VIPER 0xfb00 1238 #define PCI_DEVICE_ID_LP10000S 0xfc00 1239 #define PCI_DEVICE_ID_LP11000S 0xfc10 1240 #define PCI_DEVICE_ID_LPE11000S 0xfc20 1241 #define PCI_DEVICE_ID_SAT_S 0xfc40 1242 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50 1243 #define PCI_DEVICE_ID_HELIOS 0xfd00 1244 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 1245 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 1246 #define PCI_DEVICE_ID_ZEPHYR 0xfe00 1247 #define PCI_DEVICE_ID_HORNET 0xfe05 1248 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 1249 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 1250 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2 1251 #define PCI_DEVICE_ID_TIGERSHARK 0x0704 1252 #define PCI_DEVICE_ID_TOMCAT 0x0714 1253 1254 #define JEDEC_ID_ADDRESS 0x0080001c 1255 #define FIREFLY_JEDEC_ID 0x1ACC 1256 #define SUPERFLY_JEDEC_ID 0x0020 1257 #define DRAGONFLY_JEDEC_ID 0x0021 1258 #define DRAGONFLY_V2_JEDEC_ID 0x0025 1259 #define CENTAUR_2G_JEDEC_ID 0x0026 1260 #define CENTAUR_1G_JEDEC_ID 0x0028 1261 #define PEGASUS_ORION_JEDEC_ID 0x0036 1262 #define PEGASUS_JEDEC_ID 0x0038 1263 #define THOR_JEDEC_ID 0x0012 1264 #define HELIOS_JEDEC_ID 0x0364 1265 #define ZEPHYR_JEDEC_ID 0x0577 1266 #define VIPER_JEDEC_ID 0x4838 1267 #define SATURN_JEDEC_ID 0x1004 1268 #define HORNET_JDEC_ID 0x2057706D 1269 1270 #define JEDEC_ID_MASK 0x0FFFF000 1271 #define JEDEC_ID_SHIFT 12 1272 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1273 1274 typedef struct { /* FireFly BIU registers */ 1275 uint32_t hostAtt; /* See definitions for Host Attention 1276 register */ 1277 uint32_t chipAtt; /* See definitions for Chip Attention 1278 register */ 1279 uint32_t hostStatus; /* See definitions for Host Status register */ 1280 uint32_t hostControl; /* See definitions for Host Control register */ 1281 uint32_t buiConfig; /* See definitions for BIU configuration 1282 register */ 1283 } FF_REGS; 1284 1285 /* IO Register size in bytes */ 1286 #define FF_REG_AREA_SIZE 256 1287 1288 /* Host Attention Register */ 1289 1290 #define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1291 1292 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1293 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1294 #define HA_R0ATT 0x00000008 /* Bit 3 */ 1295 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1296 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1297 #define HA_R1ATT 0x00000080 /* Bit 7 */ 1298 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1299 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1300 #define HA_R2ATT 0x00000800 /* Bit 11 */ 1301 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1302 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1303 #define HA_R3ATT 0x00008000 /* Bit 15 */ 1304 #define HA_LATT 0x20000000 /* Bit 29 */ 1305 #define HA_MBATT 0x40000000 /* Bit 30 */ 1306 #define HA_ERATT 0x80000000 /* Bit 31 */ 1307 1308 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1309 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1310 #define HA_RXATT 0x00000008 /* Bit 3 */ 1311 #define HA_RXMASK 0x0000000f 1312 1313 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT) 1314 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT) 1315 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT) 1316 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT) 1317 1318 #define HA_R0_POS 3 1319 #define HA_R1_POS 7 1320 #define HA_R2_POS 11 1321 #define HA_R3_POS 15 1322 #define HA_LE_POS 29 1323 #define HA_MB_POS 30 1324 #define HA_ER_POS 31 1325 /* Chip Attention Register */ 1326 1327 #define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1328 1329 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1330 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1331 #define CA_R0ATT 0x00000008 /* Bit 3 */ 1332 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1333 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1334 #define CA_R1ATT 0x00000080 /* Bit 7 */ 1335 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1336 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1337 #define CA_R2ATT 0x00000800 /* Bit 11 */ 1338 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1339 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1340 #define CA_R3ATT 0x00008000 /* Bit 15 */ 1341 #define CA_MBATT 0x40000000 /* Bit 30 */ 1342 1343 /* Host Status Register */ 1344 1345 #define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1346 1347 #define HS_MBRDY 0x00400000 /* Bit 22 */ 1348 #define HS_FFRDY 0x00800000 /* Bit 23 */ 1349 #define HS_FFER8 0x01000000 /* Bit 24 */ 1350 #define HS_FFER7 0x02000000 /* Bit 25 */ 1351 #define HS_FFER6 0x04000000 /* Bit 26 */ 1352 #define HS_FFER5 0x08000000 /* Bit 27 */ 1353 #define HS_FFER4 0x10000000 /* Bit 28 */ 1354 #define HS_FFER3 0x20000000 /* Bit 29 */ 1355 #define HS_FFER2 0x40000000 /* Bit 30 */ 1356 #define HS_FFER1 0x80000000 /* Bit 31 */ 1357 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */ 1358 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ 1359 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */ 1360 /* Host Control Register */ 1361 1362 #define HC_REG_OFFSET 12 /* Byte offset from register base address */ 1363 1364 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1365 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1366 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1367 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1368 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1369 #define HC_INITHBI 0x02000000 /* Bit 25 */ 1370 #define HC_INITMB 0x04000000 /* Bit 26 */ 1371 #define HC_INITFF 0x08000000 /* Bit 27 */ 1372 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1373 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1374 1375 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */ 1376 #define MSIX_DFLT_ID 0 1377 #define MSIX_RNG0_ID 0 1378 #define MSIX_RNG1_ID 1 1379 #define MSIX_RNG2_ID 2 1380 #define MSIX_RNG3_ID 3 1381 1382 #define MSIX_LINK_ID 4 1383 #define MSIX_MBOX_ID 5 1384 1385 #define MSIX_SPARE0_ID 6 1386 #define MSIX_SPARE1_ID 7 1387 1388 /* Mailbox Commands */ 1389 #define MBX_SHUTDOWN 0x00 /* terminate testing */ 1390 #define MBX_LOAD_SM 0x01 1391 #define MBX_READ_NV 0x02 1392 #define MBX_WRITE_NV 0x03 1393 #define MBX_RUN_BIU_DIAG 0x04 1394 #define MBX_INIT_LINK 0x05 1395 #define MBX_DOWN_LINK 0x06 1396 #define MBX_CONFIG_LINK 0x07 1397 #define MBX_CONFIG_RING 0x09 1398 #define MBX_RESET_RING 0x0A 1399 #define MBX_READ_CONFIG 0x0B 1400 #define MBX_READ_RCONFIG 0x0C 1401 #define MBX_READ_SPARM 0x0D 1402 #define MBX_READ_STATUS 0x0E 1403 #define MBX_READ_RPI 0x0F 1404 #define MBX_READ_XRI 0x10 1405 #define MBX_READ_REV 0x11 1406 #define MBX_READ_LNK_STAT 0x12 1407 #define MBX_REG_LOGIN 0x13 1408 #define MBX_UNREG_LOGIN 0x14 1409 #define MBX_CLEAR_LA 0x16 1410 #define MBX_DUMP_MEMORY 0x17 1411 #define MBX_DUMP_CONTEXT 0x18 1412 #define MBX_RUN_DIAGS 0x19 1413 #define MBX_RESTART 0x1A 1414 #define MBX_UPDATE_CFG 0x1B 1415 #define MBX_DOWN_LOAD 0x1C 1416 #define MBX_DEL_LD_ENTRY 0x1D 1417 #define MBX_RUN_PROGRAM 0x1E 1418 #define MBX_SET_MASK 0x20 1419 #define MBX_SET_VARIABLE 0x21 1420 #define MBX_UNREG_D_ID 0x23 1421 #define MBX_KILL_BOARD 0x24 1422 #define MBX_CONFIG_FARP 0x25 1423 #define MBX_BEACON 0x2A 1424 #define MBX_CONFIG_MSI 0x30 1425 #define MBX_HEARTBEAT 0x31 1426 #define MBX_WRITE_VPARMS 0x32 1427 #define MBX_ASYNCEVT_ENABLE 0x33 1428 #define MBX_READ_EVENT_LOG_STATUS 0x37 1429 #define MBX_READ_EVENT_LOG 0x38 1430 #define MBX_WRITE_EVENT_LOG 0x39 1431 1432 #define MBX_PORT_CAPABILITIES 0x3B 1433 #define MBX_PORT_IOV_CONTROL 0x3C 1434 1435 #define MBX_CONFIG_HBQ 0x7C 1436 #define MBX_LOAD_AREA 0x81 1437 #define MBX_RUN_BIU_DIAG64 0x84 1438 #define MBX_CONFIG_PORT 0x88 1439 #define MBX_READ_SPARM64 0x8D 1440 #define MBX_READ_RPI64 0x8F 1441 #define MBX_REG_LOGIN64 0x93 1442 #define MBX_READ_TOPOLOGY 0x95 1443 #define MBX_REG_VPI 0x96 1444 #define MBX_UNREG_VPI 0x97 1445 1446 #define MBX_WRITE_WWN 0x98 1447 #define MBX_SET_DEBUG 0x99 1448 #define MBX_LOAD_EXP_ROM 0x9C 1449 #define MBX_SLI4_CONFIG 0x9B 1450 #define MBX_SLI4_REQ_FTRS 0x9D 1451 #define MBX_MAX_CMDS 0x9E 1452 #define MBX_RESUME_RPI 0x9E 1453 #define MBX_SLI2_CMD_MASK 0x80 1454 #define MBX_REG_VFI 0x9F 1455 #define MBX_REG_FCFI 0xA0 1456 #define MBX_UNREG_VFI 0xA1 1457 #define MBX_UNREG_FCFI 0xA2 1458 #define MBX_INIT_VFI 0xA3 1459 #define MBX_INIT_VPI 0xA4 1460 1461 #define MBX_AUTH_PORT 0xF8 1462 #define MBX_SECURITY_MGMT 0xF9 1463 1464 /* IOCB Commands */ 1465 1466 #define CMD_RCV_SEQUENCE_CX 0x01 1467 #define CMD_XMIT_SEQUENCE_CR 0x02 1468 #define CMD_XMIT_SEQUENCE_CX 0x03 1469 #define CMD_XMIT_BCAST_CN 0x04 1470 #define CMD_XMIT_BCAST_CX 0x05 1471 #define CMD_QUE_RING_BUF_CN 0x06 1472 #define CMD_QUE_XRI_BUF_CX 0x07 1473 #define CMD_IOCB_CONTINUE_CN 0x08 1474 #define CMD_RET_XRI_BUF_CX 0x09 1475 #define CMD_ELS_REQUEST_CR 0x0A 1476 #define CMD_ELS_REQUEST_CX 0x0B 1477 #define CMD_RCV_ELS_REQ_CX 0x0D 1478 #define CMD_ABORT_XRI_CN 0x0E 1479 #define CMD_ABORT_XRI_CX 0x0F 1480 #define CMD_CLOSE_XRI_CN 0x10 1481 #define CMD_CLOSE_XRI_CX 0x11 1482 #define CMD_CREATE_XRI_CR 0x12 1483 #define CMD_CREATE_XRI_CX 0x13 1484 #define CMD_GET_RPI_CN 0x14 1485 #define CMD_XMIT_ELS_RSP_CX 0x15 1486 #define CMD_GET_RPI_CR 0x16 1487 #define CMD_XRI_ABORTED_CX 0x17 1488 #define CMD_FCP_IWRITE_CR 0x18 1489 #define CMD_FCP_IWRITE_CX 0x19 1490 #define CMD_FCP_IREAD_CR 0x1A 1491 #define CMD_FCP_IREAD_CX 0x1B 1492 #define CMD_FCP_ICMND_CR 0x1C 1493 #define CMD_FCP_ICMND_CX 0x1D 1494 #define CMD_FCP_TSEND_CX 0x1F 1495 #define CMD_FCP_TRECEIVE_CX 0x21 1496 #define CMD_FCP_TRSP_CX 0x23 1497 #define CMD_FCP_AUTO_TRSP_CX 0x29 1498 1499 #define CMD_ADAPTER_MSG 0x20 1500 #define CMD_ADAPTER_DUMP 0x22 1501 1502 /* SLI_2 IOCB Command Set */ 1503 1504 #define CMD_ASYNC_STATUS 0x7C 1505 #define CMD_RCV_SEQUENCE64_CX 0x81 1506 #define CMD_XMIT_SEQUENCE64_CR 0x82 1507 #define CMD_XMIT_SEQUENCE64_CX 0x83 1508 #define CMD_XMIT_BCAST64_CN 0x84 1509 #define CMD_XMIT_BCAST64_CX 0x85 1510 #define CMD_QUE_RING_BUF64_CN 0x86 1511 #define CMD_QUE_XRI_BUF64_CX 0x87 1512 #define CMD_IOCB_CONTINUE64_CN 0x88 1513 #define CMD_RET_XRI_BUF64_CX 0x89 1514 #define CMD_ELS_REQUEST64_CR 0x8A 1515 #define CMD_ELS_REQUEST64_CX 0x8B 1516 #define CMD_ABORT_MXRI64_CN 0x8C 1517 #define CMD_RCV_ELS_REQ64_CX 0x8D 1518 #define CMD_XMIT_ELS_RSP64_CX 0x95 1519 #define CMD_XMIT_BLS_RSP64_CX 0x97 1520 #define CMD_FCP_IWRITE64_CR 0x98 1521 #define CMD_FCP_IWRITE64_CX 0x99 1522 #define CMD_FCP_IREAD64_CR 0x9A 1523 #define CMD_FCP_IREAD64_CX 0x9B 1524 #define CMD_FCP_ICMND64_CR 0x9C 1525 #define CMD_FCP_ICMND64_CX 0x9D 1526 #define CMD_FCP_TSEND64_CX 0x9F 1527 #define CMD_FCP_TRECEIVE64_CX 0xA1 1528 #define CMD_FCP_TRSP64_CX 0xA3 1529 1530 #define CMD_QUE_XRI64_CX 0xB3 1531 #define CMD_IOCB_RCV_SEQ64_CX 0xB5 1532 #define CMD_IOCB_RCV_ELS64_CX 0xB7 1533 #define CMD_IOCB_RET_XRI64_CX 0xB9 1534 #define CMD_IOCB_RCV_CONT64_CX 0xBB 1535 1536 #define CMD_GEN_REQUEST64_CR 0xC2 1537 #define CMD_GEN_REQUEST64_CX 0xC3 1538 1539 /* Unhandled SLI-3 Commands */ 1540 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0 1541 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1 1542 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1 1543 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD 1544 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6 1545 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA 1546 #define CMD_IOCB_RET_HBQE64_CN 0xCA 1547 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC 1548 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD 1549 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF 1550 #define CMD_IOCB_LOGENTRY_CN 0x94 1551 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96 1552 1553 /* Data Security SLI Commands */ 1554 #define DSSCMD_IWRITE64_CR 0xF8 1555 #define DSSCMD_IWRITE64_CX 0xF9 1556 #define DSSCMD_IREAD64_CR 0xFA 1557 #define DSSCMD_IREAD64_CX 0xFB 1558 1559 #define CMD_MAX_IOCB_CMD 0xFB 1560 #define CMD_IOCB_MASK 0xff 1561 1562 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 1563 iocb */ 1564 #define LPFC_MAX_ADPTMSG 32 /* max msg data */ 1565 /* 1566 * Define Status 1567 */ 1568 #define MBX_SUCCESS 0 1569 #define MBXERR_NUM_RINGS 1 1570 #define MBXERR_NUM_IOCBS 2 1571 #define MBXERR_IOCBS_EXCEEDED 3 1572 #define MBXERR_BAD_RING_NUMBER 4 1573 #define MBXERR_MASK_ENTRIES_RANGE 5 1574 #define MBXERR_MASKS_EXCEEDED 6 1575 #define MBXERR_BAD_PROFILE 7 1576 #define MBXERR_BAD_DEF_CLASS 8 1577 #define MBXERR_BAD_MAX_RESPONDER 9 1578 #define MBXERR_BAD_MAX_ORIGINATOR 10 1579 #define MBXERR_RPI_REGISTERED 11 1580 #define MBXERR_RPI_FULL 12 1581 #define MBXERR_NO_RESOURCES 13 1582 #define MBXERR_BAD_RCV_LENGTH 14 1583 #define MBXERR_DMA_ERROR 15 1584 #define MBXERR_ERROR 16 1585 #define MBXERR_LINK_DOWN 0x33 1586 #define MBXERR_SEC_NO_PERMISSION 0xF02 1587 #define MBX_NOT_FINISHED 255 1588 1589 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 1590 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 1591 1592 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ 1593 1594 /* 1595 * Begin Structure Definitions for Mailbox Commands 1596 */ 1597 1598 typedef struct { 1599 #ifdef __BIG_ENDIAN_BITFIELD 1600 uint8_t tval; 1601 uint8_t tmask; 1602 uint8_t rval; 1603 uint8_t rmask; 1604 #else /* __LITTLE_ENDIAN_BITFIELD */ 1605 uint8_t rmask; 1606 uint8_t rval; 1607 uint8_t tmask; 1608 uint8_t tval; 1609 #endif 1610 } RR_REG; 1611 1612 struct ulp_bde { 1613 uint32_t bdeAddress; 1614 #ifdef __BIG_ENDIAN_BITFIELD 1615 uint32_t bdeReserved:4; 1616 uint32_t bdeAddrHigh:4; 1617 uint32_t bdeSize:24; 1618 #else /* __LITTLE_ENDIAN_BITFIELD */ 1619 uint32_t bdeSize:24; 1620 uint32_t bdeAddrHigh:4; 1621 uint32_t bdeReserved:4; 1622 #endif 1623 }; 1624 1625 typedef struct ULP_BDL { /* SLI-2 */ 1626 #ifdef __BIG_ENDIAN_BITFIELD 1627 uint32_t bdeFlags:8; /* BDL Flags */ 1628 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1629 #else /* __LITTLE_ENDIAN_BITFIELD */ 1630 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1631 uint32_t bdeFlags:8; /* BDL Flags */ 1632 #endif 1633 1634 uint32_t addrLow; /* Address 0:31 */ 1635 uint32_t addrHigh; /* Address 32:63 */ 1636 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1637 } ULP_BDL; 1638 1639 /* 1640 * BlockGuard Definitions 1641 */ 1642 1643 enum lpfc_protgrp_type { 1644 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */ 1645 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */ 1646 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */ 1647 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */ 1648 }; 1649 1650 /* PDE Descriptors */ 1651 #define LPFC_PDE5_DESCRIPTOR 0x85 1652 #define LPFC_PDE6_DESCRIPTOR 0x86 1653 #define LPFC_PDE7_DESCRIPTOR 0x87 1654 1655 /* BlockGuard Opcodes */ 1656 #define BG_OP_IN_NODIF_OUT_CRC 0x0 1657 #define BG_OP_IN_CRC_OUT_NODIF 0x1 1658 #define BG_OP_IN_NODIF_OUT_CSUM 0x2 1659 #define BG_OP_IN_CSUM_OUT_NODIF 0x3 1660 #define BG_OP_IN_CRC_OUT_CRC 0x4 1661 #define BG_OP_IN_CSUM_OUT_CSUM 0x5 1662 #define BG_OP_IN_CRC_OUT_CSUM 0x6 1663 #define BG_OP_IN_CSUM_OUT_CRC 0x7 1664 1665 struct lpfc_pde5 { 1666 uint32_t word0; 1667 #define pde5_type_SHIFT 24 1668 #define pde5_type_MASK 0x000000ff 1669 #define pde5_type_WORD word0 1670 #define pde5_rsvd0_SHIFT 0 1671 #define pde5_rsvd0_MASK 0x00ffffff 1672 #define pde5_rsvd0_WORD word0 1673 uint32_t reftag; /* Reference Tag Value */ 1674 uint32_t reftagtr; /* Reference Tag Translation Value */ 1675 }; 1676 1677 struct lpfc_pde6 { 1678 uint32_t word0; 1679 #define pde6_type_SHIFT 24 1680 #define pde6_type_MASK 0x000000ff 1681 #define pde6_type_WORD word0 1682 #define pde6_rsvd0_SHIFT 0 1683 #define pde6_rsvd0_MASK 0x00ffffff 1684 #define pde6_rsvd0_WORD word0 1685 uint32_t word1; 1686 #define pde6_rsvd1_SHIFT 26 1687 #define pde6_rsvd1_MASK 0x0000003f 1688 #define pde6_rsvd1_WORD word1 1689 #define pde6_na_SHIFT 25 1690 #define pde6_na_MASK 0x00000001 1691 #define pde6_na_WORD word1 1692 #define pde6_rsvd2_SHIFT 16 1693 #define pde6_rsvd2_MASK 0x000001FF 1694 #define pde6_rsvd2_WORD word1 1695 #define pde6_apptagtr_SHIFT 0 1696 #define pde6_apptagtr_MASK 0x0000ffff 1697 #define pde6_apptagtr_WORD word1 1698 uint32_t word2; 1699 #define pde6_optx_SHIFT 28 1700 #define pde6_optx_MASK 0x0000000f 1701 #define pde6_optx_WORD word2 1702 #define pde6_oprx_SHIFT 24 1703 #define pde6_oprx_MASK 0x0000000f 1704 #define pde6_oprx_WORD word2 1705 #define pde6_nr_SHIFT 23 1706 #define pde6_nr_MASK 0x00000001 1707 #define pde6_nr_WORD word2 1708 #define pde6_ce_SHIFT 22 1709 #define pde6_ce_MASK 0x00000001 1710 #define pde6_ce_WORD word2 1711 #define pde6_re_SHIFT 21 1712 #define pde6_re_MASK 0x00000001 1713 #define pde6_re_WORD word2 1714 #define pde6_ae_SHIFT 20 1715 #define pde6_ae_MASK 0x00000001 1716 #define pde6_ae_WORD word2 1717 #define pde6_ai_SHIFT 19 1718 #define pde6_ai_MASK 0x00000001 1719 #define pde6_ai_WORD word2 1720 #define pde6_bs_SHIFT 16 1721 #define pde6_bs_MASK 0x00000007 1722 #define pde6_bs_WORD word2 1723 #define pde6_apptagval_SHIFT 0 1724 #define pde6_apptagval_MASK 0x0000ffff 1725 #define pde6_apptagval_WORD word2 1726 }; 1727 1728 struct lpfc_pde7 { 1729 uint32_t word0; 1730 #define pde7_type_SHIFT 24 1731 #define pde7_type_MASK 0x000000ff 1732 #define pde7_type_WORD word0 1733 #define pde7_rsvd0_SHIFT 0 1734 #define pde7_rsvd0_MASK 0x00ffffff 1735 #define pde7_rsvd0_WORD word0 1736 uint32_t addrHigh; 1737 uint32_t addrLow; 1738 }; 1739 1740 /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 1741 1742 typedef struct { 1743 #ifdef __BIG_ENDIAN_BITFIELD 1744 uint32_t rsvd2:25; 1745 uint32_t acknowledgment:1; 1746 uint32_t version:1; 1747 uint32_t erase_or_prog:1; 1748 uint32_t update_flash:1; 1749 uint32_t update_ram:1; 1750 uint32_t method:1; 1751 uint32_t load_cmplt:1; 1752 #else /* __LITTLE_ENDIAN_BITFIELD */ 1753 uint32_t load_cmplt:1; 1754 uint32_t method:1; 1755 uint32_t update_ram:1; 1756 uint32_t update_flash:1; 1757 uint32_t erase_or_prog:1; 1758 uint32_t version:1; 1759 uint32_t acknowledgment:1; 1760 uint32_t rsvd2:25; 1761 #endif 1762 1763 uint32_t dl_to_adr_low; 1764 uint32_t dl_to_adr_high; 1765 uint32_t dl_len; 1766 union { 1767 uint32_t dl_from_mbx_offset; 1768 struct ulp_bde dl_from_bde; 1769 struct ulp_bde64 dl_from_bde64; 1770 } un; 1771 1772 } LOAD_SM_VAR; 1773 1774 /* Structure for MB Command READ_NVPARM (02) */ 1775 1776 typedef struct { 1777 uint32_t rsvd1[3]; /* Read as all one's */ 1778 uint32_t rsvd2; /* Read as all zero's */ 1779 uint32_t portname[2]; /* N_PORT name */ 1780 uint32_t nodename[2]; /* NODE name */ 1781 1782 #ifdef __BIG_ENDIAN_BITFIELD 1783 uint32_t pref_DID:24; 1784 uint32_t hardAL_PA:8; 1785 #else /* __LITTLE_ENDIAN_BITFIELD */ 1786 uint32_t hardAL_PA:8; 1787 uint32_t pref_DID:24; 1788 #endif 1789 1790 uint32_t rsvd3[21]; /* Read as all one's */ 1791 } READ_NV_VAR; 1792 1793 /* Structure for MB Command WRITE_NVPARMS (03) */ 1794 1795 typedef struct { 1796 uint32_t rsvd1[3]; /* Must be all one's */ 1797 uint32_t rsvd2; /* Must be all zero's */ 1798 uint32_t portname[2]; /* N_PORT name */ 1799 uint32_t nodename[2]; /* NODE name */ 1800 1801 #ifdef __BIG_ENDIAN_BITFIELD 1802 uint32_t pref_DID:24; 1803 uint32_t hardAL_PA:8; 1804 #else /* __LITTLE_ENDIAN_BITFIELD */ 1805 uint32_t hardAL_PA:8; 1806 uint32_t pref_DID:24; 1807 #endif 1808 1809 uint32_t rsvd3[21]; /* Must be all one's */ 1810 } WRITE_NV_VAR; 1811 1812 /* Structure for MB Command RUN_BIU_DIAG (04) */ 1813 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 1814 1815 typedef struct { 1816 uint32_t rsvd1; 1817 union { 1818 struct { 1819 struct ulp_bde xmit_bde; 1820 struct ulp_bde rcv_bde; 1821 } s1; 1822 struct { 1823 struct ulp_bde64 xmit_bde64; 1824 struct ulp_bde64 rcv_bde64; 1825 } s2; 1826 } un; 1827 } BIU_DIAG_VAR; 1828 1829 /* Structure for MB command READ_EVENT_LOG (0x38) */ 1830 struct READ_EVENT_LOG_VAR { 1831 uint32_t word1; 1832 #define lpfc_event_log_SHIFT 29 1833 #define lpfc_event_log_MASK 0x00000001 1834 #define lpfc_event_log_WORD word1 1835 #define USE_MAILBOX_RESPONSE 1 1836 uint32_t offset; 1837 struct ulp_bde64 rcv_bde64; 1838 }; 1839 1840 /* Structure for MB Command INIT_LINK (05) */ 1841 1842 typedef struct { 1843 #ifdef __BIG_ENDIAN_BITFIELD 1844 uint32_t rsvd1:24; 1845 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1846 #else /* __LITTLE_ENDIAN_BITFIELD */ 1847 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1848 uint32_t rsvd1:24; 1849 #endif 1850 1851 #ifdef __BIG_ENDIAN_BITFIELD 1852 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1853 uint8_t rsvd2; 1854 uint16_t link_flags; 1855 #else /* __LITTLE_ENDIAN_BITFIELD */ 1856 uint16_t link_flags; 1857 uint8_t rsvd2; 1858 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1859 #endif 1860 1861 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 1862 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 1863 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 1864 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 1865 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 1866 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ 1867 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 1868 1869 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 1870 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 1871 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */ 1872 1873 uint32_t link_speed; 1874 #define LINK_SPEED_AUTO 0x0 /* Auto selection */ 1875 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */ 1876 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */ 1877 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */ 1878 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */ 1879 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */ 1880 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */ 1881 1882 } INIT_LINK_VAR; 1883 1884 /* Structure for MB Command DOWN_LINK (06) */ 1885 1886 typedef struct { 1887 uint32_t rsvd1; 1888 } DOWN_LINK_VAR; 1889 1890 /* Structure for MB Command CONFIG_LINK (07) */ 1891 1892 typedef struct { 1893 #ifdef __BIG_ENDIAN_BITFIELD 1894 uint32_t cr:1; 1895 uint32_t ci:1; 1896 uint32_t cr_delay:6; 1897 uint32_t cr_count:8; 1898 uint32_t rsvd1:8; 1899 uint32_t MaxBBC:8; 1900 #else /* __LITTLE_ENDIAN_BITFIELD */ 1901 uint32_t MaxBBC:8; 1902 uint32_t rsvd1:8; 1903 uint32_t cr_count:8; 1904 uint32_t cr_delay:6; 1905 uint32_t ci:1; 1906 uint32_t cr:1; 1907 #endif 1908 1909 uint32_t myId; 1910 uint32_t rsvd2; 1911 uint32_t edtov; 1912 uint32_t arbtov; 1913 uint32_t ratov; 1914 uint32_t rttov; 1915 uint32_t altov; 1916 uint32_t crtov; 1917 uint32_t citov; 1918 #ifdef __BIG_ENDIAN_BITFIELD 1919 uint32_t rrq_enable:1; 1920 uint32_t rrq_immed:1; 1921 uint32_t rsvd4:29; 1922 uint32_t ack0_enable:1; 1923 #else /* __LITTLE_ENDIAN_BITFIELD */ 1924 uint32_t ack0_enable:1; 1925 uint32_t rsvd4:29; 1926 uint32_t rrq_immed:1; 1927 uint32_t rrq_enable:1; 1928 #endif 1929 } CONFIG_LINK; 1930 1931 /* Structure for MB Command PART_SLIM (08) 1932 * will be removed since SLI1 is no longer supported! 1933 */ 1934 typedef struct { 1935 #ifdef __BIG_ENDIAN_BITFIELD 1936 uint16_t offCiocb; 1937 uint16_t numCiocb; 1938 uint16_t offRiocb; 1939 uint16_t numRiocb; 1940 #else /* __LITTLE_ENDIAN_BITFIELD */ 1941 uint16_t numCiocb; 1942 uint16_t offCiocb; 1943 uint16_t numRiocb; 1944 uint16_t offRiocb; 1945 #endif 1946 } RING_DEF; 1947 1948 typedef struct { 1949 #ifdef __BIG_ENDIAN_BITFIELD 1950 uint32_t unused1:24; 1951 uint32_t numRing:8; 1952 #else /* __LITTLE_ENDIAN_BITFIELD */ 1953 uint32_t numRing:8; 1954 uint32_t unused1:24; 1955 #endif 1956 1957 RING_DEF ringdef[4]; 1958 uint32_t hbainit; 1959 } PART_SLIM_VAR; 1960 1961 /* Structure for MB Command CONFIG_RING (09) */ 1962 1963 typedef struct { 1964 #ifdef __BIG_ENDIAN_BITFIELD 1965 uint32_t unused2:6; 1966 uint32_t recvSeq:1; 1967 uint32_t recvNotify:1; 1968 uint32_t numMask:8; 1969 uint32_t profile:8; 1970 uint32_t unused1:4; 1971 uint32_t ring:4; 1972 #else /* __LITTLE_ENDIAN_BITFIELD */ 1973 uint32_t ring:4; 1974 uint32_t unused1:4; 1975 uint32_t profile:8; 1976 uint32_t numMask:8; 1977 uint32_t recvNotify:1; 1978 uint32_t recvSeq:1; 1979 uint32_t unused2:6; 1980 #endif 1981 1982 #ifdef __BIG_ENDIAN_BITFIELD 1983 uint16_t maxRespXchg; 1984 uint16_t maxOrigXchg; 1985 #else /* __LITTLE_ENDIAN_BITFIELD */ 1986 uint16_t maxOrigXchg; 1987 uint16_t maxRespXchg; 1988 #endif 1989 1990 RR_REG rrRegs[6]; 1991 } CONFIG_RING_VAR; 1992 1993 /* Structure for MB Command RESET_RING (10) */ 1994 1995 typedef struct { 1996 uint32_t ring_no; 1997 } RESET_RING_VAR; 1998 1999 /* Structure for MB Command READ_CONFIG (11) */ 2000 2001 typedef struct { 2002 #ifdef __BIG_ENDIAN_BITFIELD 2003 uint32_t cr:1; 2004 uint32_t ci:1; 2005 uint32_t cr_delay:6; 2006 uint32_t cr_count:8; 2007 uint32_t InitBBC:8; 2008 uint32_t MaxBBC:8; 2009 #else /* __LITTLE_ENDIAN_BITFIELD */ 2010 uint32_t MaxBBC:8; 2011 uint32_t InitBBC:8; 2012 uint32_t cr_count:8; 2013 uint32_t cr_delay:6; 2014 uint32_t ci:1; 2015 uint32_t cr:1; 2016 #endif 2017 2018 #ifdef __BIG_ENDIAN_BITFIELD 2019 uint32_t topology:8; 2020 uint32_t myDid:24; 2021 #else /* __LITTLE_ENDIAN_BITFIELD */ 2022 uint32_t myDid:24; 2023 uint32_t topology:8; 2024 #endif 2025 2026 /* Defines for topology (defined previously) */ 2027 #ifdef __BIG_ENDIAN_BITFIELD 2028 uint32_t AR:1; 2029 uint32_t IR:1; 2030 uint32_t rsvd1:29; 2031 uint32_t ack0:1; 2032 #else /* __LITTLE_ENDIAN_BITFIELD */ 2033 uint32_t ack0:1; 2034 uint32_t rsvd1:29; 2035 uint32_t IR:1; 2036 uint32_t AR:1; 2037 #endif 2038 2039 uint32_t edtov; 2040 uint32_t arbtov; 2041 uint32_t ratov; 2042 uint32_t rttov; 2043 uint32_t altov; 2044 uint32_t lmt; 2045 #define LMT_RESERVED 0x000 /* Not used */ 2046 #define LMT_1Gb 0x004 2047 #define LMT_2Gb 0x008 2048 #define LMT_4Gb 0x040 2049 #define LMT_8Gb 0x080 2050 #define LMT_10Gb 0x100 2051 #define LMT_16Gb 0x200 2052 uint32_t rsvd2; 2053 uint32_t rsvd3; 2054 uint32_t max_xri; 2055 uint32_t max_iocb; 2056 uint32_t max_rpi; 2057 uint32_t avail_xri; 2058 uint32_t avail_iocb; 2059 uint32_t avail_rpi; 2060 uint32_t max_vpi; 2061 uint32_t rsvd4; 2062 uint32_t rsvd5; 2063 uint32_t avail_vpi; 2064 } READ_CONFIG_VAR; 2065 2066 /* Structure for MB Command READ_RCONFIG (12) */ 2067 2068 typedef struct { 2069 #ifdef __BIG_ENDIAN_BITFIELD 2070 uint32_t rsvd2:7; 2071 uint32_t recvNotify:1; 2072 uint32_t numMask:8; 2073 uint32_t profile:8; 2074 uint32_t rsvd1:4; 2075 uint32_t ring:4; 2076 #else /* __LITTLE_ENDIAN_BITFIELD */ 2077 uint32_t ring:4; 2078 uint32_t rsvd1:4; 2079 uint32_t profile:8; 2080 uint32_t numMask:8; 2081 uint32_t recvNotify:1; 2082 uint32_t rsvd2:7; 2083 #endif 2084 2085 #ifdef __BIG_ENDIAN_BITFIELD 2086 uint16_t maxResp; 2087 uint16_t maxOrig; 2088 #else /* __LITTLE_ENDIAN_BITFIELD */ 2089 uint16_t maxOrig; 2090 uint16_t maxResp; 2091 #endif 2092 2093 RR_REG rrRegs[6]; 2094 2095 #ifdef __BIG_ENDIAN_BITFIELD 2096 uint16_t cmdRingOffset; 2097 uint16_t cmdEntryCnt; 2098 uint16_t rspRingOffset; 2099 uint16_t rspEntryCnt; 2100 uint16_t nextCmdOffset; 2101 uint16_t rsvd3; 2102 uint16_t nextRspOffset; 2103 uint16_t rsvd4; 2104 #else /* __LITTLE_ENDIAN_BITFIELD */ 2105 uint16_t cmdEntryCnt; 2106 uint16_t cmdRingOffset; 2107 uint16_t rspEntryCnt; 2108 uint16_t rspRingOffset; 2109 uint16_t rsvd3; 2110 uint16_t nextCmdOffset; 2111 uint16_t rsvd4; 2112 uint16_t nextRspOffset; 2113 #endif 2114 } READ_RCONF_VAR; 2115 2116 /* Structure for MB Command READ_SPARM (13) */ 2117 /* Structure for MB Command READ_SPARM64 (0x8D) */ 2118 2119 typedef struct { 2120 uint32_t rsvd1; 2121 uint32_t rsvd2; 2122 union { 2123 struct ulp_bde sp; /* This BDE points to struct serv_parm 2124 structure */ 2125 struct ulp_bde64 sp64; 2126 } un; 2127 #ifdef __BIG_ENDIAN_BITFIELD 2128 uint16_t rsvd3; 2129 uint16_t vpi; 2130 #else /* __LITTLE_ENDIAN_BITFIELD */ 2131 uint16_t vpi; 2132 uint16_t rsvd3; 2133 #endif 2134 } READ_SPARM_VAR; 2135 2136 /* Structure for MB Command READ_STATUS (14) */ 2137 2138 typedef struct { 2139 #ifdef __BIG_ENDIAN_BITFIELD 2140 uint32_t rsvd1:31; 2141 uint32_t clrCounters:1; 2142 uint16_t activeXriCnt; 2143 uint16_t activeRpiCnt; 2144 #else /* __LITTLE_ENDIAN_BITFIELD */ 2145 uint32_t clrCounters:1; 2146 uint32_t rsvd1:31; 2147 uint16_t activeRpiCnt; 2148 uint16_t activeXriCnt; 2149 #endif 2150 2151 uint32_t xmitByteCnt; 2152 uint32_t rcvByteCnt; 2153 uint32_t xmitFrameCnt; 2154 uint32_t rcvFrameCnt; 2155 uint32_t xmitSeqCnt; 2156 uint32_t rcvSeqCnt; 2157 uint32_t totalOrigExchanges; 2158 uint32_t totalRespExchanges; 2159 uint32_t rcvPbsyCnt; 2160 uint32_t rcvFbsyCnt; 2161 } READ_STATUS_VAR; 2162 2163 /* Structure for MB Command READ_RPI (15) */ 2164 /* Structure for MB Command READ_RPI64 (0x8F) */ 2165 2166 typedef struct { 2167 #ifdef __BIG_ENDIAN_BITFIELD 2168 uint16_t nextRpi; 2169 uint16_t reqRpi; 2170 uint32_t rsvd2:8; 2171 uint32_t DID:24; 2172 #else /* __LITTLE_ENDIAN_BITFIELD */ 2173 uint16_t reqRpi; 2174 uint16_t nextRpi; 2175 uint32_t DID:24; 2176 uint32_t rsvd2:8; 2177 #endif 2178 2179 union { 2180 struct ulp_bde sp; 2181 struct ulp_bde64 sp64; 2182 } un; 2183 2184 } READ_RPI_VAR; 2185 2186 /* Structure for MB Command READ_XRI (16) */ 2187 2188 typedef struct { 2189 #ifdef __BIG_ENDIAN_BITFIELD 2190 uint16_t nextXri; 2191 uint16_t reqXri; 2192 uint16_t rsvd1; 2193 uint16_t rpi; 2194 uint32_t rsvd2:8; 2195 uint32_t DID:24; 2196 uint32_t rsvd3:8; 2197 uint32_t SID:24; 2198 uint32_t rsvd4; 2199 uint8_t seqId; 2200 uint8_t rsvd5; 2201 uint16_t seqCount; 2202 uint16_t oxId; 2203 uint16_t rxId; 2204 uint32_t rsvd6:30; 2205 uint32_t si:1; 2206 uint32_t exchOrig:1; 2207 #else /* __LITTLE_ENDIAN_BITFIELD */ 2208 uint16_t reqXri; 2209 uint16_t nextXri; 2210 uint16_t rpi; 2211 uint16_t rsvd1; 2212 uint32_t DID:24; 2213 uint32_t rsvd2:8; 2214 uint32_t SID:24; 2215 uint32_t rsvd3:8; 2216 uint32_t rsvd4; 2217 uint16_t seqCount; 2218 uint8_t rsvd5; 2219 uint8_t seqId; 2220 uint16_t rxId; 2221 uint16_t oxId; 2222 uint32_t exchOrig:1; 2223 uint32_t si:1; 2224 uint32_t rsvd6:30; 2225 #endif 2226 } READ_XRI_VAR; 2227 2228 /* Structure for MB Command READ_REV (17) */ 2229 2230 typedef struct { 2231 #ifdef __BIG_ENDIAN_BITFIELD 2232 uint32_t cv:1; 2233 uint32_t rr:1; 2234 uint32_t rsvd2:2; 2235 uint32_t v3req:1; 2236 uint32_t v3rsp:1; 2237 uint32_t rsvd1:25; 2238 uint32_t rv:1; 2239 #else /* __LITTLE_ENDIAN_BITFIELD */ 2240 uint32_t rv:1; 2241 uint32_t rsvd1:25; 2242 uint32_t v3rsp:1; 2243 uint32_t v3req:1; 2244 uint32_t rsvd2:2; 2245 uint32_t rr:1; 2246 uint32_t cv:1; 2247 #endif 2248 2249 uint32_t biuRev; 2250 uint32_t smRev; 2251 union { 2252 uint32_t smFwRev; 2253 struct { 2254 #ifdef __BIG_ENDIAN_BITFIELD 2255 uint8_t ProgType; 2256 uint8_t ProgId; 2257 uint16_t ProgVer:4; 2258 uint16_t ProgRev:4; 2259 uint16_t ProgFixLvl:2; 2260 uint16_t ProgDistType:2; 2261 uint16_t DistCnt:4; 2262 #else /* __LITTLE_ENDIAN_BITFIELD */ 2263 uint16_t DistCnt:4; 2264 uint16_t ProgDistType:2; 2265 uint16_t ProgFixLvl:2; 2266 uint16_t ProgRev:4; 2267 uint16_t ProgVer:4; 2268 uint8_t ProgId; 2269 uint8_t ProgType; 2270 #endif 2271 2272 } b; 2273 } un; 2274 uint32_t endecRev; 2275 #ifdef __BIG_ENDIAN_BITFIELD 2276 uint8_t feaLevelHigh; 2277 uint8_t feaLevelLow; 2278 uint8_t fcphHigh; 2279 uint8_t fcphLow; 2280 #else /* __LITTLE_ENDIAN_BITFIELD */ 2281 uint8_t fcphLow; 2282 uint8_t fcphHigh; 2283 uint8_t feaLevelLow; 2284 uint8_t feaLevelHigh; 2285 #endif 2286 2287 uint32_t postKernRev; 2288 uint32_t opFwRev; 2289 uint8_t opFwName[16]; 2290 uint32_t sli1FwRev; 2291 uint8_t sli1FwName[16]; 2292 uint32_t sli2FwRev; 2293 uint8_t sli2FwName[16]; 2294 uint32_t sli3Feat; 2295 uint32_t RandomData[6]; 2296 } READ_REV_VAR; 2297 2298 /* Structure for MB Command READ_LINK_STAT (18) */ 2299 2300 typedef struct { 2301 uint32_t rsvd1; 2302 uint32_t linkFailureCnt; 2303 uint32_t lossSyncCnt; 2304 2305 uint32_t lossSignalCnt; 2306 uint32_t primSeqErrCnt; 2307 uint32_t invalidXmitWord; 2308 uint32_t crcCnt; 2309 uint32_t primSeqTimeout; 2310 uint32_t elasticOverrun; 2311 uint32_t arbTimeout; 2312 } READ_LNK_VAR; 2313 2314 /* Structure for MB Command REG_LOGIN (19) */ 2315 /* Structure for MB Command REG_LOGIN64 (0x93) */ 2316 2317 typedef struct { 2318 #ifdef __BIG_ENDIAN_BITFIELD 2319 uint16_t rsvd1; 2320 uint16_t rpi; 2321 uint32_t rsvd2:8; 2322 uint32_t did:24; 2323 #else /* __LITTLE_ENDIAN_BITFIELD */ 2324 uint16_t rpi; 2325 uint16_t rsvd1; 2326 uint32_t did:24; 2327 uint32_t rsvd2:8; 2328 #endif 2329 2330 union { 2331 struct ulp_bde sp; 2332 struct ulp_bde64 sp64; 2333 } un; 2334 2335 #ifdef __BIG_ENDIAN_BITFIELD 2336 uint16_t rsvd6; 2337 uint16_t vpi; 2338 #else /* __LITTLE_ENDIAN_BITFIELD */ 2339 uint16_t vpi; 2340 uint16_t rsvd6; 2341 #endif 2342 2343 } REG_LOGIN_VAR; 2344 2345 /* Word 30 contents for REG_LOGIN */ 2346 typedef union { 2347 struct { 2348 #ifdef __BIG_ENDIAN_BITFIELD 2349 uint16_t rsvd1:12; 2350 uint16_t wd30_class:4; 2351 uint16_t xri; 2352 #else /* __LITTLE_ENDIAN_BITFIELD */ 2353 uint16_t xri; 2354 uint16_t wd30_class:4; 2355 uint16_t rsvd1:12; 2356 #endif 2357 } f; 2358 uint32_t word; 2359 } REG_WD30; 2360 2361 /* Structure for MB Command UNREG_LOGIN (20) */ 2362 2363 typedef struct { 2364 #ifdef __BIG_ENDIAN_BITFIELD 2365 uint16_t rsvd1; 2366 uint16_t rpi; 2367 uint32_t rsvd2; 2368 uint32_t rsvd3; 2369 uint32_t rsvd4; 2370 uint32_t rsvd5; 2371 uint16_t rsvd6; 2372 uint16_t vpi; 2373 #else /* __LITTLE_ENDIAN_BITFIELD */ 2374 uint16_t rpi; 2375 uint16_t rsvd1; 2376 uint32_t rsvd2; 2377 uint32_t rsvd3; 2378 uint32_t rsvd4; 2379 uint32_t rsvd5; 2380 uint16_t vpi; 2381 uint16_t rsvd6; 2382 #endif 2383 } UNREG_LOGIN_VAR; 2384 2385 /* Structure for MB Command REG_VPI (0x96) */ 2386 typedef struct { 2387 #ifdef __BIG_ENDIAN_BITFIELD 2388 uint32_t rsvd1; 2389 uint32_t rsvd2:7; 2390 uint32_t upd:1; 2391 uint32_t sid:24; 2392 uint32_t wwn[2]; 2393 uint32_t rsvd5; 2394 uint16_t vfi; 2395 uint16_t vpi; 2396 #else /* __LITTLE_ENDIAN */ 2397 uint32_t rsvd1; 2398 uint32_t sid:24; 2399 uint32_t upd:1; 2400 uint32_t rsvd2:7; 2401 uint32_t wwn[2]; 2402 uint32_t rsvd5; 2403 uint16_t vpi; 2404 uint16_t vfi; 2405 #endif 2406 } REG_VPI_VAR; 2407 2408 /* Structure for MB Command UNREG_VPI (0x97) */ 2409 typedef struct { 2410 uint32_t rsvd1; 2411 #ifdef __BIG_ENDIAN_BITFIELD 2412 uint16_t rsvd2; 2413 uint16_t sli4_vpi; 2414 #else /* __LITTLE_ENDIAN */ 2415 uint16_t sli4_vpi; 2416 uint16_t rsvd2; 2417 #endif 2418 uint32_t rsvd3; 2419 uint32_t rsvd4; 2420 uint32_t rsvd5; 2421 #ifdef __BIG_ENDIAN_BITFIELD 2422 uint16_t rsvd6; 2423 uint16_t vpi; 2424 #else /* __LITTLE_ENDIAN */ 2425 uint16_t vpi; 2426 uint16_t rsvd6; 2427 #endif 2428 } UNREG_VPI_VAR; 2429 2430 /* Structure for MB Command UNREG_D_ID (0x23) */ 2431 2432 typedef struct { 2433 uint32_t did; 2434 uint32_t rsvd2; 2435 uint32_t rsvd3; 2436 uint32_t rsvd4; 2437 uint32_t rsvd5; 2438 #ifdef __BIG_ENDIAN_BITFIELD 2439 uint16_t rsvd6; 2440 uint16_t vpi; 2441 #else 2442 uint16_t vpi; 2443 uint16_t rsvd6; 2444 #endif 2445 } UNREG_D_ID_VAR; 2446 2447 /* Structure for MB Command READ_TOPOLOGY (0x95) */ 2448 struct lpfc_mbx_read_top { 2449 uint32_t eventTag; /* Event tag */ 2450 uint32_t word2; 2451 #define lpfc_mbx_read_top_fa_SHIFT 12 2452 #define lpfc_mbx_read_top_fa_MASK 0x00000001 2453 #define lpfc_mbx_read_top_fa_WORD word2 2454 #define lpfc_mbx_read_top_mm_SHIFT 11 2455 #define lpfc_mbx_read_top_mm_MASK 0x00000001 2456 #define lpfc_mbx_read_top_mm_WORD word2 2457 #define lpfc_mbx_read_top_pb_SHIFT 9 2458 #define lpfc_mbx_read_top_pb_MASK 0X00000001 2459 #define lpfc_mbx_read_top_pb_WORD word2 2460 #define lpfc_mbx_read_top_il_SHIFT 8 2461 #define lpfc_mbx_read_top_il_MASK 0x00000001 2462 #define lpfc_mbx_read_top_il_WORD word2 2463 #define lpfc_mbx_read_top_att_type_SHIFT 0 2464 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF 2465 #define lpfc_mbx_read_top_att_type_WORD word2 2466 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */ 2467 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */ 2468 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */ 2469 uint32_t word3; 2470 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24 2471 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF 2472 #define lpfc_mbx_read_top_alpa_granted_WORD word3 2473 #define lpfc_mbx_read_top_lip_alps_SHIFT 16 2474 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF 2475 #define lpfc_mbx_read_top_lip_alps_WORD word3 2476 #define lpfc_mbx_read_top_lip_type_SHIFT 8 2477 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF 2478 #define lpfc_mbx_read_top_lip_type_WORD word3 2479 #define lpfc_mbx_read_top_topology_SHIFT 0 2480 #define lpfc_mbx_read_top_topology_MASK 0x000000FF 2481 #define lpfc_mbx_read_top_topology_WORD word3 2482 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 2483 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 2484 #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */ 2485 /* store the LILP AL_PA position map into */ 2486 struct ulp_bde64 lilpBde64; 2487 #define LPFC_ALPA_MAP_SIZE 128 2488 uint32_t word7; 2489 #define lpfc_mbx_read_top_ld_lu_SHIFT 31 2490 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001 2491 #define lpfc_mbx_read_top_ld_lu_WORD word7 2492 #define lpfc_mbx_read_top_ld_tf_SHIFT 30 2493 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001 2494 #define lpfc_mbx_read_top_ld_tf_WORD word7 2495 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8 2496 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF 2497 #define lpfc_mbx_read_top_ld_link_spd_WORD word7 2498 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4 2499 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F 2500 #define lpfc_mbx_read_top_ld_nl_port_WORD word7 2501 #define lpfc_mbx_read_top_ld_tx_SHIFT 2 2502 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003 2503 #define lpfc_mbx_read_top_ld_tx_WORD word7 2504 #define lpfc_mbx_read_top_ld_rx_SHIFT 0 2505 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003 2506 #define lpfc_mbx_read_top_ld_rx_WORD word7 2507 uint32_t word8; 2508 #define lpfc_mbx_read_top_lu_SHIFT 31 2509 #define lpfc_mbx_read_top_lu_MASK 0x00000001 2510 #define lpfc_mbx_read_top_lu_WORD word8 2511 #define lpfc_mbx_read_top_tf_SHIFT 30 2512 #define lpfc_mbx_read_top_tf_MASK 0x00000001 2513 #define lpfc_mbx_read_top_tf_WORD word8 2514 #define lpfc_mbx_read_top_link_spd_SHIFT 8 2515 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF 2516 #define lpfc_mbx_read_top_link_spd_WORD word8 2517 #define lpfc_mbx_read_top_nl_port_SHIFT 4 2518 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F 2519 #define lpfc_mbx_read_top_nl_port_WORD word8 2520 #define lpfc_mbx_read_top_tx_SHIFT 2 2521 #define lpfc_mbx_read_top_tx_MASK 0x00000003 2522 #define lpfc_mbx_read_top_tx_WORD word8 2523 #define lpfc_mbx_read_top_rx_SHIFT 0 2524 #define lpfc_mbx_read_top_rx_MASK 0x00000003 2525 #define lpfc_mbx_read_top_rx_WORD word8 2526 #define LPFC_LINK_SPEED_UNKNOWN 0x0 2527 #define LPFC_LINK_SPEED_1GHZ 0x04 2528 #define LPFC_LINK_SPEED_2GHZ 0x08 2529 #define LPFC_LINK_SPEED_4GHZ 0x10 2530 #define LPFC_LINK_SPEED_8GHZ 0x20 2531 #define LPFC_LINK_SPEED_10GHZ 0x40 2532 #define LPFC_LINK_SPEED_16GHZ 0x80 2533 }; 2534 2535 /* Structure for MB Command CLEAR_LA (22) */ 2536 2537 typedef struct { 2538 uint32_t eventTag; /* Event tag */ 2539 uint32_t rsvd1; 2540 } CLEAR_LA_VAR; 2541 2542 /* Structure for MB Command DUMP */ 2543 2544 typedef struct { 2545 #ifdef __BIG_ENDIAN_BITFIELD 2546 uint32_t rsvd:25; 2547 uint32_t ra:1; 2548 uint32_t co:1; 2549 uint32_t cv:1; 2550 uint32_t type:4; 2551 uint32_t entry_index:16; 2552 uint32_t region_id:16; 2553 #else /* __LITTLE_ENDIAN_BITFIELD */ 2554 uint32_t type:4; 2555 uint32_t cv:1; 2556 uint32_t co:1; 2557 uint32_t ra:1; 2558 uint32_t rsvd:25; 2559 uint32_t region_id:16; 2560 uint32_t entry_index:16; 2561 #endif 2562 2563 uint32_t sli4_length; 2564 uint32_t word_cnt; 2565 uint32_t resp_offset; 2566 } DUMP_VAR; 2567 2568 #define DMP_MEM_REG 0x1 2569 #define DMP_NV_PARAMS 0x2 2570 2571 #define DMP_REGION_VPD 0xe 2572 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 2573 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 2574 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 2575 2576 #define DMP_REGION_VPORT 0x16 /* VPort info region */ 2577 #define DMP_VPORT_REGION_SIZE 0x200 2578 #define DMP_MBOX_OFFSET_WORD 0x5 2579 2580 #define DMP_REGION_23 0x17 /* fcoe param and port state region */ 2581 #define DMP_RGN23_SIZE 0x400 2582 2583 #define WAKE_UP_PARMS_REGION_ID 4 2584 #define WAKE_UP_PARMS_WORD_SIZE 15 2585 2586 struct vport_rec { 2587 uint8_t wwpn[8]; 2588 uint8_t wwnn[8]; 2589 }; 2590 2591 #define VPORT_INFO_SIG 0x32324752 2592 #define VPORT_INFO_REV_MASK 0xff 2593 #define VPORT_INFO_REV 0x1 2594 #define MAX_STATIC_VPORT_COUNT 16 2595 struct static_vport_info { 2596 uint32_t signature; 2597 uint32_t rev; 2598 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT]; 2599 uint32_t resvd[66]; 2600 }; 2601 2602 /* Option rom version structure */ 2603 struct prog_id { 2604 #ifdef __BIG_ENDIAN_BITFIELD 2605 uint8_t type; 2606 uint8_t id; 2607 uint32_t ver:4; /* Major Version */ 2608 uint32_t rev:4; /* Revision */ 2609 uint32_t lev:2; /* Level */ 2610 uint32_t dist:2; /* Dist Type */ 2611 uint32_t num:4; /* number after dist type */ 2612 #else /* __LITTLE_ENDIAN_BITFIELD */ 2613 uint32_t num:4; /* number after dist type */ 2614 uint32_t dist:2; /* Dist Type */ 2615 uint32_t lev:2; /* Level */ 2616 uint32_t rev:4; /* Revision */ 2617 uint32_t ver:4; /* Major Version */ 2618 uint8_t id; 2619 uint8_t type; 2620 #endif 2621 }; 2622 2623 /* Structure for MB Command UPDATE_CFG (0x1B) */ 2624 2625 struct update_cfg_var { 2626 #ifdef __BIG_ENDIAN_BITFIELD 2627 uint32_t rsvd2:16; 2628 uint32_t type:8; 2629 uint32_t rsvd:1; 2630 uint32_t ra:1; 2631 uint32_t co:1; 2632 uint32_t cv:1; 2633 uint32_t req:4; 2634 uint32_t entry_length:16; 2635 uint32_t region_id:16; 2636 #else /* __LITTLE_ENDIAN_BITFIELD */ 2637 uint32_t req:4; 2638 uint32_t cv:1; 2639 uint32_t co:1; 2640 uint32_t ra:1; 2641 uint32_t rsvd:1; 2642 uint32_t type:8; 2643 uint32_t rsvd2:16; 2644 uint32_t region_id:16; 2645 uint32_t entry_length:16; 2646 #endif 2647 2648 uint32_t resp_info; 2649 uint32_t byte_cnt; 2650 uint32_t data_offset; 2651 }; 2652 2653 struct hbq_mask { 2654 #ifdef __BIG_ENDIAN_BITFIELD 2655 uint8_t tmatch; 2656 uint8_t tmask; 2657 uint8_t rctlmatch; 2658 uint8_t rctlmask; 2659 #else /* __LITTLE_ENDIAN */ 2660 uint8_t rctlmask; 2661 uint8_t rctlmatch; 2662 uint8_t tmask; 2663 uint8_t tmatch; 2664 #endif 2665 }; 2666 2667 2668 /* Structure for MB Command CONFIG_HBQ (7c) */ 2669 2670 struct config_hbq_var { 2671 #ifdef __BIG_ENDIAN_BITFIELD 2672 uint32_t rsvd1 :7; 2673 uint32_t recvNotify :1; /* Receive Notification */ 2674 uint32_t numMask :8; /* # Mask Entries */ 2675 uint32_t profile :8; /* Selection Profile */ 2676 uint32_t rsvd2 :8; 2677 #else /* __LITTLE_ENDIAN */ 2678 uint32_t rsvd2 :8; 2679 uint32_t profile :8; /* Selection Profile */ 2680 uint32_t numMask :8; /* # Mask Entries */ 2681 uint32_t recvNotify :1; /* Receive Notification */ 2682 uint32_t rsvd1 :7; 2683 #endif 2684 2685 #ifdef __BIG_ENDIAN_BITFIELD 2686 uint32_t hbqId :16; 2687 uint32_t rsvd3 :12; 2688 uint32_t ringMask :4; 2689 #else /* __LITTLE_ENDIAN */ 2690 uint32_t ringMask :4; 2691 uint32_t rsvd3 :12; 2692 uint32_t hbqId :16; 2693 #endif 2694 2695 #ifdef __BIG_ENDIAN_BITFIELD 2696 uint32_t entry_count :16; 2697 uint32_t rsvd4 :8; 2698 uint32_t headerLen :8; 2699 #else /* __LITTLE_ENDIAN */ 2700 uint32_t headerLen :8; 2701 uint32_t rsvd4 :8; 2702 uint32_t entry_count :16; 2703 #endif 2704 2705 uint32_t hbqaddrLow; 2706 uint32_t hbqaddrHigh; 2707 2708 #ifdef __BIG_ENDIAN_BITFIELD 2709 uint32_t rsvd5 :31; 2710 uint32_t logEntry :1; 2711 #else /* __LITTLE_ENDIAN */ 2712 uint32_t logEntry :1; 2713 uint32_t rsvd5 :31; 2714 #endif 2715 2716 uint32_t rsvd6; /* w7 */ 2717 uint32_t rsvd7; /* w8 */ 2718 uint32_t rsvd8; /* w9 */ 2719 2720 struct hbq_mask hbqMasks[6]; 2721 2722 2723 union { 2724 uint32_t allprofiles[12]; 2725 2726 struct { 2727 #ifdef __BIG_ENDIAN_BITFIELD 2728 uint32_t seqlenoff :16; 2729 uint32_t maxlen :16; 2730 #else /* __LITTLE_ENDIAN */ 2731 uint32_t maxlen :16; 2732 uint32_t seqlenoff :16; 2733 #endif 2734 #ifdef __BIG_ENDIAN_BITFIELD 2735 uint32_t rsvd1 :28; 2736 uint32_t seqlenbcnt :4; 2737 #else /* __LITTLE_ENDIAN */ 2738 uint32_t seqlenbcnt :4; 2739 uint32_t rsvd1 :28; 2740 #endif 2741 uint32_t rsvd[10]; 2742 } profile2; 2743 2744 struct { 2745 #ifdef __BIG_ENDIAN_BITFIELD 2746 uint32_t seqlenoff :16; 2747 uint32_t maxlen :16; 2748 #else /* __LITTLE_ENDIAN */ 2749 uint32_t maxlen :16; 2750 uint32_t seqlenoff :16; 2751 #endif 2752 #ifdef __BIG_ENDIAN_BITFIELD 2753 uint32_t cmdcodeoff :28; 2754 uint32_t rsvd1 :12; 2755 uint32_t seqlenbcnt :4; 2756 #else /* __LITTLE_ENDIAN */ 2757 uint32_t seqlenbcnt :4; 2758 uint32_t rsvd1 :12; 2759 uint32_t cmdcodeoff :28; 2760 #endif 2761 uint32_t cmdmatch[8]; 2762 2763 uint32_t rsvd[2]; 2764 } profile3; 2765 2766 struct { 2767 #ifdef __BIG_ENDIAN_BITFIELD 2768 uint32_t seqlenoff :16; 2769 uint32_t maxlen :16; 2770 #else /* __LITTLE_ENDIAN */ 2771 uint32_t maxlen :16; 2772 uint32_t seqlenoff :16; 2773 #endif 2774 #ifdef __BIG_ENDIAN_BITFIELD 2775 uint32_t cmdcodeoff :28; 2776 uint32_t rsvd1 :12; 2777 uint32_t seqlenbcnt :4; 2778 #else /* __LITTLE_ENDIAN */ 2779 uint32_t seqlenbcnt :4; 2780 uint32_t rsvd1 :12; 2781 uint32_t cmdcodeoff :28; 2782 #endif 2783 uint32_t cmdmatch[8]; 2784 2785 uint32_t rsvd[2]; 2786 } profile5; 2787 2788 } profiles; 2789 2790 }; 2791 2792 2793 2794 /* Structure for MB Command CONFIG_PORT (0x88) */ 2795 typedef struct { 2796 #ifdef __BIG_ENDIAN_BITFIELD 2797 uint32_t cBE : 1; 2798 uint32_t cET : 1; 2799 uint32_t cHpcb : 1; 2800 uint32_t cMA : 1; 2801 uint32_t sli_mode : 4; 2802 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 2803 * config block */ 2804 #else /* __LITTLE_ENDIAN */ 2805 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 2806 * config block */ 2807 uint32_t sli_mode : 4; 2808 uint32_t cMA : 1; 2809 uint32_t cHpcb : 1; 2810 uint32_t cET : 1; 2811 uint32_t cBE : 1; 2812 #endif 2813 2814 uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 2815 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 2816 uint32_t hbainit[5]; 2817 #ifdef __BIG_ENDIAN_BITFIELD 2818 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 2819 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 2820 #else /* __LITTLE_ENDIAN */ 2821 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 2822 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 2823 #endif 2824 2825 #ifdef __BIG_ENDIAN_BITFIELD 2826 uint32_t rsvd1 : 19; /* Reserved */ 2827 uint32_t cdss : 1; /* Configure Data Security SLI */ 2828 uint32_t casabt : 1; /* Configure async abts status notice */ 2829 uint32_t rsvd2 : 2; /* Reserved */ 2830 uint32_t cbg : 1; /* Configure BlockGuard */ 2831 uint32_t cmv : 1; /* Configure Max VPIs */ 2832 uint32_t ccrp : 1; /* Config Command Ring Polling */ 2833 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 2834 uint32_t chbs : 1; /* Cofigure Host Backing store */ 2835 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 2836 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 2837 uint32_t cmx : 1; /* Configure Max XRIs */ 2838 uint32_t cmr : 1; /* Configure Max RPIs */ 2839 #else /* __LITTLE_ENDIAN */ 2840 uint32_t cmr : 1; /* Configure Max RPIs */ 2841 uint32_t cmx : 1; /* Configure Max XRIs */ 2842 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 2843 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 2844 uint32_t chbs : 1; /* Cofigure Host Backing store */ 2845 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 2846 uint32_t ccrp : 1; /* Config Command Ring Polling */ 2847 uint32_t cmv : 1; /* Configure Max VPIs */ 2848 uint32_t cbg : 1; /* Configure BlockGuard */ 2849 uint32_t rsvd2 : 2; /* Reserved */ 2850 uint32_t casabt : 1; /* Configure async abts status notice */ 2851 uint32_t cdss : 1; /* Configure Data Security SLI */ 2852 uint32_t rsvd1 : 19; /* Reserved */ 2853 #endif 2854 #ifdef __BIG_ENDIAN_BITFIELD 2855 uint32_t rsvd3 : 19; /* Reserved */ 2856 uint32_t gdss : 1; /* Configure Data Security SLI */ 2857 uint32_t gasabt : 1; /* Grant async abts status notice */ 2858 uint32_t rsvd4 : 2; /* Reserved */ 2859 uint32_t gbg : 1; /* Grant BlockGuard */ 2860 uint32_t gmv : 1; /* Grant Max VPIs */ 2861 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 2862 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 2863 uint32_t ghbs : 1; /* Grant Host Backing Store */ 2864 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 2865 uint32_t gerbm : 1; /* Grant ERBM Request */ 2866 uint32_t gmx : 1; /* Grant Max XRIs */ 2867 uint32_t gmr : 1; /* Grant Max RPIs */ 2868 #else /* __LITTLE_ENDIAN */ 2869 uint32_t gmr : 1; /* Grant Max RPIs */ 2870 uint32_t gmx : 1; /* Grant Max XRIs */ 2871 uint32_t gerbm : 1; /* Grant ERBM Request */ 2872 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 2873 uint32_t ghbs : 1; /* Grant Host Backing Store */ 2874 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 2875 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 2876 uint32_t gmv : 1; /* Grant Max VPIs */ 2877 uint32_t gbg : 1; /* Grant BlockGuard */ 2878 uint32_t rsvd4 : 2; /* Reserved */ 2879 uint32_t gasabt : 1; /* Grant async abts status notice */ 2880 uint32_t gdss : 1; /* Configure Data Security SLI */ 2881 uint32_t rsvd3 : 19; /* Reserved */ 2882 #endif 2883 2884 #ifdef __BIG_ENDIAN_BITFIELD 2885 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 2886 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 2887 #else /* __LITTLE_ENDIAN */ 2888 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 2889 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 2890 #endif 2891 2892 #ifdef __BIG_ENDIAN_BITFIELD 2893 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 2894 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 2895 #else /* __LITTLE_ENDIAN */ 2896 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 2897 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 2898 #endif 2899 2900 uint32_t rsvd6; /* Reserved */ 2901 2902 #ifdef __BIG_ENDIAN_BITFIELD 2903 uint32_t fips_rev : 3; /* FIPS Spec Revision */ 2904 uint32_t fips_level : 4; /* FIPS Level */ 2905 uint32_t sec_err : 9; /* security crypto error */ 2906 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 2907 #else /* __LITTLE_ENDIAN */ 2908 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 2909 uint32_t sec_err : 9; /* security crypto error */ 2910 uint32_t fips_level : 4; /* FIPS Level */ 2911 uint32_t fips_rev : 3; /* FIPS Spec Revision */ 2912 #endif 2913 2914 } CONFIG_PORT_VAR; 2915 2916 /* Structure for MB Command CONFIG_MSI (0x30) */ 2917 struct config_msi_var { 2918 #ifdef __BIG_ENDIAN_BITFIELD 2919 uint32_t dfltMsgNum:8; /* Default message number */ 2920 uint32_t rsvd1:11; /* Reserved */ 2921 uint32_t NID:5; /* Number of secondary attention IDs */ 2922 uint32_t rsvd2:5; /* Reserved */ 2923 uint32_t dfltPresent:1; /* Default message number present */ 2924 uint32_t addFlag:1; /* Add association flag */ 2925 uint32_t reportFlag:1; /* Report association flag */ 2926 #else /* __LITTLE_ENDIAN_BITFIELD */ 2927 uint32_t reportFlag:1; /* Report association flag */ 2928 uint32_t addFlag:1; /* Add association flag */ 2929 uint32_t dfltPresent:1; /* Default message number present */ 2930 uint32_t rsvd2:5; /* Reserved */ 2931 uint32_t NID:5; /* Number of secondary attention IDs */ 2932 uint32_t rsvd1:11; /* Reserved */ 2933 uint32_t dfltMsgNum:8; /* Default message number */ 2934 #endif 2935 uint32_t attentionConditions[2]; 2936 uint8_t attentionId[16]; 2937 uint8_t messageNumberByHA[64]; 2938 uint8_t messageNumberByID[16]; 2939 uint32_t autoClearHA[2]; 2940 #ifdef __BIG_ENDIAN_BITFIELD 2941 uint32_t rsvd3:16; 2942 uint32_t autoClearID:16; 2943 #else /* __LITTLE_ENDIAN_BITFIELD */ 2944 uint32_t autoClearID:16; 2945 uint32_t rsvd3:16; 2946 #endif 2947 uint32_t rsvd4; 2948 }; 2949 2950 /* SLI-2 Port Control Block */ 2951 2952 /* SLIM POINTER */ 2953 #define SLIMOFF 0x30 /* WORD */ 2954 2955 typedef struct _SLI2_RDSC { 2956 uint32_t cmdEntries; 2957 uint32_t cmdAddrLow; 2958 uint32_t cmdAddrHigh; 2959 2960 uint32_t rspEntries; 2961 uint32_t rspAddrLow; 2962 uint32_t rspAddrHigh; 2963 } SLI2_RDSC; 2964 2965 typedef struct _PCB { 2966 #ifdef __BIG_ENDIAN_BITFIELD 2967 uint32_t type:8; 2968 #define TYPE_NATIVE_SLI2 0x01 2969 uint32_t feature:8; 2970 #define FEATURE_INITIAL_SLI2 0x01 2971 uint32_t rsvd:12; 2972 uint32_t maxRing:4; 2973 #else /* __LITTLE_ENDIAN_BITFIELD */ 2974 uint32_t maxRing:4; 2975 uint32_t rsvd:12; 2976 uint32_t feature:8; 2977 #define FEATURE_INITIAL_SLI2 0x01 2978 uint32_t type:8; 2979 #define TYPE_NATIVE_SLI2 0x01 2980 #endif 2981 2982 uint32_t mailBoxSize; 2983 uint32_t mbAddrLow; 2984 uint32_t mbAddrHigh; 2985 2986 uint32_t hgpAddrLow; 2987 uint32_t hgpAddrHigh; 2988 2989 uint32_t pgpAddrLow; 2990 uint32_t pgpAddrHigh; 2991 SLI2_RDSC rdsc[MAX_RINGS]; 2992 } PCB_t; 2993 2994 /* NEW_FEATURE */ 2995 typedef struct { 2996 #ifdef __BIG_ENDIAN_BITFIELD 2997 uint32_t rsvd0:27; 2998 uint32_t discardFarp:1; 2999 uint32_t IPEnable:1; 3000 uint32_t nodeName:1; 3001 uint32_t portName:1; 3002 uint32_t filterEnable:1; 3003 #else /* __LITTLE_ENDIAN_BITFIELD */ 3004 uint32_t filterEnable:1; 3005 uint32_t portName:1; 3006 uint32_t nodeName:1; 3007 uint32_t IPEnable:1; 3008 uint32_t discardFarp:1; 3009 uint32_t rsvd:27; 3010 #endif 3011 3012 uint8_t portname[8]; /* Used to be struct lpfc_name */ 3013 uint8_t nodename[8]; 3014 uint32_t rsvd1; 3015 uint32_t rsvd2; 3016 uint32_t rsvd3; 3017 uint32_t IPAddress; 3018 } CONFIG_FARP_VAR; 3019 3020 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */ 3021 3022 typedef struct { 3023 #ifdef __BIG_ENDIAN_BITFIELD 3024 uint32_t rsvd:30; 3025 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3026 #else /* __LITTLE_ENDIAN */ 3027 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3028 uint32_t rsvd:30; 3029 #endif 3030 } ASYNCEVT_ENABLE_VAR; 3031 3032 /* Union of all Mailbox Command types */ 3033 #define MAILBOX_CMD_WSIZE 32 3034 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 3035 /* ext_wsize times 4 bytes should not be greater than max xmit size */ 3036 #define MAILBOX_EXT_WSIZE 512 3037 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t)) 3038 #define MAILBOX_HBA_EXT_OFFSET 0x100 3039 /* max mbox xmit size is a page size for sysfs IO operations */ 3040 #define MAILBOX_SYSFS_MAX 4096 3041 3042 typedef union { 3043 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/ 3044 * feature/max ring number 3045 */ 3046 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 3047 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 3048 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 3049 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 3050 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 3051 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 3052 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 3053 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 3054 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 3055 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 3056 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 3057 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 3058 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 3059 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 3060 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 3061 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 3062 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 3063 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 3064 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 3065 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 3066 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 3067 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 3068 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 3069 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) 3070 * NEW_FEATURE 3071 */ 3072 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */ 3073 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/ 3074 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 3075 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */ 3076 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 3077 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 3078 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */ 3079 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38 3080 * (READ_EVENT_LOG) 3081 */ 3082 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */ 3083 } MAILVARIANTS; 3084 3085 /* 3086 * SLI-2 specific structures 3087 */ 3088 3089 struct lpfc_hgp { 3090 __le32 cmdPutInx; 3091 __le32 rspGetInx; 3092 }; 3093 3094 struct lpfc_pgp { 3095 __le32 cmdGetInx; 3096 __le32 rspPutInx; 3097 }; 3098 3099 struct sli2_desc { 3100 uint32_t unused1[16]; 3101 struct lpfc_hgp host[MAX_RINGS]; 3102 struct lpfc_pgp port[MAX_RINGS]; 3103 }; 3104 3105 struct sli3_desc { 3106 struct lpfc_hgp host[MAX_RINGS]; 3107 uint32_t reserved[8]; 3108 uint32_t hbq_put[16]; 3109 }; 3110 3111 struct sli3_pgp { 3112 struct lpfc_pgp port[MAX_RINGS]; 3113 uint32_t hbq_get[16]; 3114 }; 3115 3116 union sli_var { 3117 struct sli2_desc s2; 3118 struct sli3_desc s3; 3119 struct sli3_pgp s3_pgp; 3120 }; 3121 3122 typedef struct { 3123 #ifdef __BIG_ENDIAN_BITFIELD 3124 uint16_t mbxStatus; 3125 uint8_t mbxCommand; 3126 uint8_t mbxReserved:6; 3127 uint8_t mbxHc:1; 3128 uint8_t mbxOwner:1; /* Low order bit first word */ 3129 #else /* __LITTLE_ENDIAN_BITFIELD */ 3130 uint8_t mbxOwner:1; /* Low order bit first word */ 3131 uint8_t mbxHc:1; 3132 uint8_t mbxReserved:6; 3133 uint8_t mbxCommand; 3134 uint16_t mbxStatus; 3135 #endif 3136 3137 MAILVARIANTS un; 3138 union sli_var us; 3139 } MAILBOX_t; 3140 3141 /* 3142 * Begin Structure Definitions for IOCB Commands 3143 */ 3144 3145 typedef struct { 3146 #ifdef __BIG_ENDIAN_BITFIELD 3147 uint8_t statAction; 3148 uint8_t statRsn; 3149 uint8_t statBaExp; 3150 uint8_t statLocalError; 3151 #else /* __LITTLE_ENDIAN_BITFIELD */ 3152 uint8_t statLocalError; 3153 uint8_t statBaExp; 3154 uint8_t statRsn; 3155 uint8_t statAction; 3156 #endif 3157 /* statRsn P/F_RJT reason codes */ 3158 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 3159 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 3160 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 3161 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 3162 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 3163 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 3164 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 3165 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 3166 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 3167 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 3168 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 3169 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 3170 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 3171 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 3172 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 3173 #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 3174 #define RJT_XCHG_ERR 0x11 /* Exchange error */ 3175 #define RJT_PROT_ERR 0x12 /* Protocol error */ 3176 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 3177 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 3178 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 3179 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 3180 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 3181 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 3182 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 3183 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 3184 3185 #define IOERR_SUCCESS 0x00 /* statLocalError */ 3186 #define IOERR_MISSING_CONTINUE 0x01 3187 #define IOERR_SEQUENCE_TIMEOUT 0x02 3188 #define IOERR_INTERNAL_ERROR 0x03 3189 #define IOERR_INVALID_RPI 0x04 3190 #define IOERR_NO_XRI 0x05 3191 #define IOERR_ILLEGAL_COMMAND 0x06 3192 #define IOERR_XCHG_DROPPED 0x07 3193 #define IOERR_ILLEGAL_FIELD 0x08 3194 #define IOERR_BAD_CONTINUE 0x09 3195 #define IOERR_TOO_MANY_BUFFERS 0x0A 3196 #define IOERR_RCV_BUFFER_WAITING 0x0B 3197 #define IOERR_NO_CONNECTION 0x0C 3198 #define IOERR_TX_DMA_FAILED 0x0D 3199 #define IOERR_RX_DMA_FAILED 0x0E 3200 #define IOERR_ILLEGAL_FRAME 0x0F 3201 #define IOERR_EXTRA_DATA 0x10 3202 #define IOERR_NO_RESOURCES 0x11 3203 #define IOERR_RESERVED 0x12 3204 #define IOERR_ILLEGAL_LENGTH 0x13 3205 #define IOERR_UNSUPPORTED_FEATURE 0x14 3206 #define IOERR_ABORT_IN_PROGRESS 0x15 3207 #define IOERR_ABORT_REQUESTED 0x16 3208 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 3209 #define IOERR_LOOP_OPEN_FAILURE 0x18 3210 #define IOERR_RING_RESET 0x19 3211 #define IOERR_LINK_DOWN 0x1A 3212 #define IOERR_CORRUPTED_DATA 0x1B 3213 #define IOERR_CORRUPTED_RPI 0x1C 3214 #define IOERR_OUT_OF_ORDER_DATA 0x1D 3215 #define IOERR_OUT_OF_ORDER_ACK 0x1E 3216 #define IOERR_DUP_FRAME 0x1F 3217 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 3218 #define IOERR_BAD_HOST_ADDRESS 0x21 3219 #define IOERR_RCV_HDRBUF_WAITING 0x22 3220 #define IOERR_MISSING_HDR_BUFFER 0x23 3221 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 3222 #define IOERR_ABORTMULT_REQUESTED 0x25 3223 #define IOERR_BUFFER_SHORTAGE 0x28 3224 #define IOERR_DEFAULT 0x29 3225 #define IOERR_CNT 0x2A 3226 #define IOERR_SLER_FAILURE 0x46 3227 #define IOERR_SLER_CMD_RCV_FAILURE 0x47 3228 #define IOERR_SLER_REC_RJT_ERR 0x48 3229 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49 3230 #define IOERR_SLER_SRR_RJT_ERR 0x4A 3231 #define IOERR_SLER_RRQ_RJT_ERR 0x4C 3232 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D 3233 #define IOERR_SLER_ABTS_ERR 0x4E 3234 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0 3235 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1 3236 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2 3237 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3 3238 #define IOERR_DRVR_MASK 0x100 3239 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 3240 #define IOERR_SLI_BRESET 0x102 3241 #define IOERR_SLI_ABORTED 0x103 3242 } PARM_ERR; 3243 3244 typedef union { 3245 struct { 3246 #ifdef __BIG_ENDIAN_BITFIELD 3247 uint8_t Rctl; /* R_CTL field */ 3248 uint8_t Type; /* TYPE field */ 3249 uint8_t Dfctl; /* DF_CTL field */ 3250 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3251 #else /* __LITTLE_ENDIAN_BITFIELD */ 3252 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3253 uint8_t Dfctl; /* DF_CTL field */ 3254 uint8_t Type; /* TYPE field */ 3255 uint8_t Rctl; /* R_CTL field */ 3256 #endif 3257 3258 #define BC 0x02 /* Broadcast Received - Fctl */ 3259 #define SI 0x04 /* Sequence Initiative */ 3260 #define LA 0x08 /* Ignore Link Attention state */ 3261 #define LS 0x80 /* Last Sequence */ 3262 } hcsw; 3263 uint32_t reserved; 3264 } WORD5; 3265 3266 /* IOCB Command template for a generic response */ 3267 typedef struct { 3268 uint32_t reserved[4]; 3269 PARM_ERR perr; 3270 } GENERIC_RSP; 3271 3272 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 3273 typedef struct { 3274 struct ulp_bde xrsqbde[2]; 3275 uint32_t xrsqRo; /* Starting Relative Offset */ 3276 WORD5 w5; /* Header control/status word */ 3277 } XR_SEQ_FIELDS; 3278 3279 /* IOCB Command template for ELS_REQUEST */ 3280 typedef struct { 3281 struct ulp_bde elsReq; 3282 struct ulp_bde elsRsp; 3283 3284 #ifdef __BIG_ENDIAN_BITFIELD 3285 uint32_t word4Rsvd:7; 3286 uint32_t fl:1; 3287 uint32_t myID:24; 3288 uint32_t word5Rsvd:8; 3289 uint32_t remoteID:24; 3290 #else /* __LITTLE_ENDIAN_BITFIELD */ 3291 uint32_t myID:24; 3292 uint32_t fl:1; 3293 uint32_t word4Rsvd:7; 3294 uint32_t remoteID:24; 3295 uint32_t word5Rsvd:8; 3296 #endif 3297 } ELS_REQUEST; 3298 3299 /* IOCB Command template for RCV_ELS_REQ */ 3300 typedef struct { 3301 struct ulp_bde elsReq[2]; 3302 uint32_t parmRo; 3303 3304 #ifdef __BIG_ENDIAN_BITFIELD 3305 uint32_t word5Rsvd:8; 3306 uint32_t remoteID:24; 3307 #else /* __LITTLE_ENDIAN_BITFIELD */ 3308 uint32_t remoteID:24; 3309 uint32_t word5Rsvd:8; 3310 #endif 3311 } RCV_ELS_REQ; 3312 3313 /* IOCB Command template for ABORT / CLOSE_XRI */ 3314 typedef struct { 3315 uint32_t rsvd[3]; 3316 uint32_t abortType; 3317 #define ABORT_TYPE_ABTX 0x00000000 3318 #define ABORT_TYPE_ABTS 0x00000001 3319 uint32_t parm; 3320 #ifdef __BIG_ENDIAN_BITFIELD 3321 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3322 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3323 #else /* __LITTLE_ENDIAN_BITFIELD */ 3324 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3325 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3326 #endif 3327 } AC_XRI; 3328 3329 /* IOCB Command template for ABORT_MXRI64 */ 3330 typedef struct { 3331 uint32_t rsvd[3]; 3332 uint32_t abortType; 3333 uint32_t parm; 3334 uint32_t iotag32; 3335 } A_MXRI64; 3336 3337 /* IOCB Command template for GET_RPI */ 3338 typedef struct { 3339 uint32_t rsvd[4]; 3340 uint32_t parmRo; 3341 #ifdef __BIG_ENDIAN_BITFIELD 3342 uint32_t word5Rsvd:8; 3343 uint32_t remoteID:24; 3344 #else /* __LITTLE_ENDIAN_BITFIELD */ 3345 uint32_t remoteID:24; 3346 uint32_t word5Rsvd:8; 3347 #endif 3348 } GET_RPI; 3349 3350 /* IOCB Command template for all FCP Initiator commands */ 3351 typedef struct { 3352 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 3353 struct ulp_bde fcpi_rsp; /* Rcv buffer */ 3354 uint32_t fcpi_parm; 3355 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3356 } FCPI_FIELDS; 3357 3358 /* IOCB Command template for all FCP Target commands */ 3359 typedef struct { 3360 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 3361 uint32_t fcpt_Offset; 3362 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3363 } FCPT_FIELDS; 3364 3365 /* SLI-2 IOCB structure definitions */ 3366 3367 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 3368 typedef struct { 3369 ULP_BDL bdl; 3370 uint32_t xrsqRo; /* Starting Relative Offset */ 3371 WORD5 w5; /* Header control/status word */ 3372 } XMT_SEQ_FIELDS64; 3373 3374 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 3375 typedef struct { 3376 struct ulp_bde64 rcvBde; 3377 uint32_t rsvd1; 3378 uint32_t xrsqRo; /* Starting Relative Offset */ 3379 WORD5 w5; /* Header control/status word */ 3380 } RCV_SEQ_FIELDS64; 3381 3382 /* IOCB Command template for ELS_REQUEST64 */ 3383 typedef struct { 3384 ULP_BDL bdl; 3385 #ifdef __BIG_ENDIAN_BITFIELD 3386 uint32_t word4Rsvd:7; 3387 uint32_t fl:1; 3388 uint32_t myID:24; 3389 uint32_t word5Rsvd:8; 3390 uint32_t remoteID:24; 3391 #else /* __LITTLE_ENDIAN_BITFIELD */ 3392 uint32_t myID:24; 3393 uint32_t fl:1; 3394 uint32_t word4Rsvd:7; 3395 uint32_t remoteID:24; 3396 uint32_t word5Rsvd:8; 3397 #endif 3398 } ELS_REQUEST64; 3399 3400 /* IOCB Command template for GEN_REQUEST64 */ 3401 typedef struct { 3402 ULP_BDL bdl; 3403 uint32_t xrsqRo; /* Starting Relative Offset */ 3404 WORD5 w5; /* Header control/status word */ 3405 } GEN_REQUEST64; 3406 3407 /* IOCB Command template for RCV_ELS_REQ64 */ 3408 typedef struct { 3409 struct ulp_bde64 elsReq; 3410 uint32_t rcvd1; 3411 uint32_t parmRo; 3412 3413 #ifdef __BIG_ENDIAN_BITFIELD 3414 uint32_t word5Rsvd:8; 3415 uint32_t remoteID:24; 3416 #else /* __LITTLE_ENDIAN_BITFIELD */ 3417 uint32_t remoteID:24; 3418 uint32_t word5Rsvd:8; 3419 #endif 3420 } RCV_ELS_REQ64; 3421 3422 /* IOCB Command template for RCV_SEQ64 */ 3423 struct rcv_seq64 { 3424 struct ulp_bde64 elsReq; 3425 uint32_t hbq_1; 3426 uint32_t parmRo; 3427 #ifdef __BIG_ENDIAN_BITFIELD 3428 uint32_t rctl:8; 3429 uint32_t type:8; 3430 uint32_t dfctl:8; 3431 uint32_t ls:1; 3432 uint32_t fs:1; 3433 uint32_t rsvd2:3; 3434 uint32_t si:1; 3435 uint32_t bc:1; 3436 uint32_t rsvd3:1; 3437 #else /* __LITTLE_ENDIAN_BITFIELD */ 3438 uint32_t rsvd3:1; 3439 uint32_t bc:1; 3440 uint32_t si:1; 3441 uint32_t rsvd2:3; 3442 uint32_t fs:1; 3443 uint32_t ls:1; 3444 uint32_t dfctl:8; 3445 uint32_t type:8; 3446 uint32_t rctl:8; 3447 #endif 3448 }; 3449 3450 /* IOCB Command template for all 64 bit FCP Initiator commands */ 3451 typedef struct { 3452 ULP_BDL bdl; 3453 uint32_t fcpi_parm; 3454 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3455 } FCPI_FIELDS64; 3456 3457 /* IOCB Command template for all 64 bit FCP Target commands */ 3458 typedef struct { 3459 ULP_BDL bdl; 3460 uint32_t fcpt_Offset; 3461 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3462 } FCPT_FIELDS64; 3463 3464 /* IOCB Command template for Async Status iocb commands */ 3465 typedef struct { 3466 uint32_t rsvd[4]; 3467 uint32_t param; 3468 #ifdef __BIG_ENDIAN_BITFIELD 3469 uint16_t evt_code; /* High order bits word 5 */ 3470 uint16_t sub_ctxt_tag; /* Low order bits word 5 */ 3471 #else /* __LITTLE_ENDIAN_BITFIELD */ 3472 uint16_t sub_ctxt_tag; /* High order bits word 5 */ 3473 uint16_t evt_code; /* Low order bits word 5 */ 3474 #endif 3475 } ASYNCSTAT_FIELDS; 3476 #define ASYNC_TEMP_WARN 0x100 3477 #define ASYNC_TEMP_SAFE 0x101 3478 #define ASYNC_STATUS_CN 0x102 3479 3480 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7) 3481 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */ 3482 3483 struct rcv_sli3 { 3484 #ifdef __BIG_ENDIAN_BITFIELD 3485 uint16_t ox_id; 3486 uint16_t seq_cnt; 3487 3488 uint16_t vpi; 3489 uint16_t word9Rsvd; 3490 #else /* __LITTLE_ENDIAN */ 3491 uint16_t seq_cnt; 3492 uint16_t ox_id; 3493 3494 uint16_t word9Rsvd; 3495 uint16_t vpi; 3496 #endif 3497 uint32_t word10Rsvd; 3498 uint32_t acc_len; /* accumulated length */ 3499 struct ulp_bde64 bde2; 3500 }; 3501 3502 /* Structure used for a single HBQ entry */ 3503 struct lpfc_hbq_entry { 3504 struct ulp_bde64 bde; 3505 uint32_t buffer_tag; 3506 }; 3507 3508 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */ 3509 typedef struct { 3510 struct lpfc_hbq_entry buff; 3511 uint32_t rsvd; 3512 uint32_t rsvd1; 3513 } QUE_XRI64_CX_FIELDS; 3514 3515 struct que_xri64cx_ext_fields { 3516 uint32_t iotag64_low; 3517 uint32_t iotag64_high; 3518 uint32_t ebde_count; 3519 uint32_t rsvd; 3520 struct lpfc_hbq_entry buff[5]; 3521 }; 3522 3523 struct sli3_bg_fields { 3524 uint32_t filler[6]; /* word 8-13 in IOCB */ 3525 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */ 3526 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */ 3527 #define BGS_BIDIR_BG_PROF_MASK 0xff000000 3528 #define BGS_BIDIR_BG_PROF_SHIFT 24 3529 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000 3530 #define BGS_BIDIR_ERR_COND_SHIFT 16 3531 #define BGS_BG_PROFILE_MASK 0x0000ff00 3532 #define BGS_BG_PROFILE_SHIFT 8 3533 #define BGS_INVALID_PROF_MASK 0x00000020 3534 #define BGS_INVALID_PROF_SHIFT 5 3535 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010 3536 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4 3537 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008 3538 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3 3539 #define BGS_REFTAG_ERR_MASK 0x00000004 3540 #define BGS_REFTAG_ERR_SHIFT 2 3541 #define BGS_APPTAG_ERR_MASK 0x00000002 3542 #define BGS_APPTAG_ERR_SHIFT 1 3543 #define BGS_GUARD_ERR_MASK 0x00000001 3544 #define BGS_GUARD_ERR_SHIFT 0 3545 uint32_t bgstat; /* word 15 - BlockGuard Status */ 3546 }; 3547 3548 static inline uint32_t 3549 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat) 3550 { 3551 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >> 3552 BGS_BIDIR_BG_PROF_SHIFT; 3553 } 3554 3555 static inline uint32_t 3556 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat) 3557 { 3558 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >> 3559 BGS_BIDIR_ERR_COND_SHIFT; 3560 } 3561 3562 static inline uint32_t 3563 lpfc_bgs_get_bg_prof(uint32_t bgstat) 3564 { 3565 return (bgstat & BGS_BG_PROFILE_MASK) >> 3566 BGS_BG_PROFILE_SHIFT; 3567 } 3568 3569 static inline uint32_t 3570 lpfc_bgs_get_invalid_prof(uint32_t bgstat) 3571 { 3572 return (bgstat & BGS_INVALID_PROF_MASK) >> 3573 BGS_INVALID_PROF_SHIFT; 3574 } 3575 3576 static inline uint32_t 3577 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat) 3578 { 3579 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >> 3580 BGS_UNINIT_DIF_BLOCK_SHIFT; 3581 } 3582 3583 static inline uint32_t 3584 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat) 3585 { 3586 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >> 3587 BGS_HI_WATER_MARK_PRESENT_SHIFT; 3588 } 3589 3590 static inline uint32_t 3591 lpfc_bgs_get_reftag_err(uint32_t bgstat) 3592 { 3593 return (bgstat & BGS_REFTAG_ERR_MASK) >> 3594 BGS_REFTAG_ERR_SHIFT; 3595 } 3596 3597 static inline uint32_t 3598 lpfc_bgs_get_apptag_err(uint32_t bgstat) 3599 { 3600 return (bgstat & BGS_APPTAG_ERR_MASK) >> 3601 BGS_APPTAG_ERR_SHIFT; 3602 } 3603 3604 static inline uint32_t 3605 lpfc_bgs_get_guard_err(uint32_t bgstat) 3606 { 3607 return (bgstat & BGS_GUARD_ERR_MASK) >> 3608 BGS_GUARD_ERR_SHIFT; 3609 } 3610 3611 #define LPFC_EXT_DATA_BDE_COUNT 3 3612 struct fcp_irw_ext { 3613 uint32_t io_tag64_low; 3614 uint32_t io_tag64_high; 3615 #ifdef __BIG_ENDIAN_BITFIELD 3616 uint8_t reserved1; 3617 uint8_t reserved2; 3618 uint8_t reserved3; 3619 uint8_t ebde_count; 3620 #else /* __LITTLE_ENDIAN */ 3621 uint8_t ebde_count; 3622 uint8_t reserved3; 3623 uint8_t reserved2; 3624 uint8_t reserved1; 3625 #endif 3626 uint32_t reserved4; 3627 struct ulp_bde64 rbde; /* response bde */ 3628 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */ 3629 uint8_t icd[32]; /* immediate command data (32 bytes) */ 3630 }; 3631 3632 typedef struct _IOCB { /* IOCB structure */ 3633 union { 3634 GENERIC_RSP grsp; /* Generic response */ 3635 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 3636 struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 3637 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 3638 AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 3639 A_MXRI64 amxri; /* abort multiple xri command overlay */ 3640 GET_RPI getrpi; /* GET_RPI template */ 3641 FCPI_FIELDS fcpi; /* FCP Initiator template */ 3642 FCPT_FIELDS fcpt; /* FCP target template */ 3643 3644 /* SLI-2 structures */ 3645 3646 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 3647 * bde_64s */ 3648 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 3649 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 3650 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 3651 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 3652 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 3653 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 3654 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */ 3655 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */ 3656 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */ 3657 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */ 3658 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 3659 } un; 3660 union { 3661 struct { 3662 #ifdef __BIG_ENDIAN_BITFIELD 3663 uint16_t ulpContext; /* High order bits word 6 */ 3664 uint16_t ulpIoTag; /* Low order bits word 6 */ 3665 #else /* __LITTLE_ENDIAN_BITFIELD */ 3666 uint16_t ulpIoTag; /* Low order bits word 6 */ 3667 uint16_t ulpContext; /* High order bits word 6 */ 3668 #endif 3669 } t1; 3670 struct { 3671 #ifdef __BIG_ENDIAN_BITFIELD 3672 uint16_t ulpContext; /* High order bits word 6 */ 3673 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 3674 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 3675 #else /* __LITTLE_ENDIAN_BITFIELD */ 3676 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 3677 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 3678 uint16_t ulpContext; /* High order bits word 6 */ 3679 #endif 3680 } t2; 3681 } un1; 3682 #define ulpContext un1.t1.ulpContext 3683 #define ulpIoTag un1.t1.ulpIoTag 3684 #define ulpIoTag0 un1.t2.ulpIoTag0 3685 3686 #ifdef __BIG_ENDIAN_BITFIELD 3687 uint32_t ulpTimeout:8; 3688 uint32_t ulpXS:1; 3689 uint32_t ulpFCP2Rcvy:1; 3690 uint32_t ulpPU:2; 3691 uint32_t ulpIr:1; 3692 uint32_t ulpClass:3; 3693 uint32_t ulpCommand:8; 3694 uint32_t ulpStatus:4; 3695 uint32_t ulpBdeCount:2; 3696 uint32_t ulpLe:1; 3697 uint32_t ulpOwner:1; /* Low order bit word 7 */ 3698 #else /* __LITTLE_ENDIAN_BITFIELD */ 3699 uint32_t ulpOwner:1; /* Low order bit word 7 */ 3700 uint32_t ulpLe:1; 3701 uint32_t ulpBdeCount:2; 3702 uint32_t ulpStatus:4; 3703 uint32_t ulpCommand:8; 3704 uint32_t ulpClass:3; 3705 uint32_t ulpIr:1; 3706 uint32_t ulpPU:2; 3707 uint32_t ulpFCP2Rcvy:1; 3708 uint32_t ulpXS:1; 3709 uint32_t ulpTimeout:8; 3710 #endif 3711 3712 union { 3713 struct rcv_sli3 rcvsli3; /* words 8 - 15 */ 3714 3715 /* words 8-31 used for que_xri_cx iocb */ 3716 struct que_xri64cx_ext_fields que_xri64cx_ext_words; 3717 struct fcp_irw_ext fcp_ext; 3718 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ 3719 3720 /* words 8-15 for BlockGuard */ 3721 struct sli3_bg_fields sli3_bg; 3722 } unsli3; 3723 3724 #define ulpCt_h ulpXS 3725 #define ulpCt_l ulpFCP2Rcvy 3726 3727 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */ 3728 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ 3729 #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 3730 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 3731 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 3732 #define PARM_NPIV_DID 3 3733 #define CLASS1 0 /* Class 1 */ 3734 #define CLASS2 1 /* Class 2 */ 3735 #define CLASS3 2 /* Class 3 */ 3736 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 3737 3738 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 3739 #define IOSTAT_FCP_RSP_ERROR 0x1 3740 #define IOSTAT_REMOTE_STOP 0x2 3741 #define IOSTAT_LOCAL_REJECT 0x3 3742 #define IOSTAT_NPORT_RJT 0x4 3743 #define IOSTAT_FABRIC_RJT 0x5 3744 #define IOSTAT_NPORT_BSY 0x6 3745 #define IOSTAT_FABRIC_BSY 0x7 3746 #define IOSTAT_INTERMED_RSP 0x8 3747 #define IOSTAT_LS_RJT 0x9 3748 #define IOSTAT_BA_RJT 0xA 3749 #define IOSTAT_RSVD1 0xB 3750 #define IOSTAT_RSVD2 0xC 3751 #define IOSTAT_RSVD3 0xD 3752 #define IOSTAT_RSVD4 0xE 3753 #define IOSTAT_NEED_BUFFER 0xF 3754 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 3755 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 3756 #define IOSTAT_CNT 0x11 3757 3758 } IOCB_t; 3759 3760 3761 #define SLI1_SLIM_SIZE (4 * 1024) 3762 3763 /* Up to 498 IOCBs will fit into 16k 3764 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 3765 */ 3766 #define SLI2_SLIM_SIZE (64 * 1024) 3767 3768 /* Maximum IOCBs that will fit in SLI2 slim */ 3769 #define MAX_SLI2_IOCB 498 3770 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \ 3771 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \ 3772 sizeof(uint32_t) * MAILBOX_EXT_WSIZE)) 3773 3774 /* HBQ entries are 4 words each = 4k */ 3775 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \ 3776 lpfc_sli_hbq_count()) 3777 3778 struct lpfc_sli2_slim { 3779 MAILBOX_t mbx; 3780 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE]; 3781 PCB_t pcb; 3782 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE]; 3783 }; 3784 3785 /* 3786 * This function checks PCI device to allow special handling for LC HBAs. 3787 * 3788 * Parameters: 3789 * device : struct pci_dev 's device field 3790 * 3791 * return 1 => TRUE 3792 * 0 => FALSE 3793 */ 3794 static inline int 3795 lpfc_is_LC_HBA(unsigned short device) 3796 { 3797 if ((device == PCI_DEVICE_ID_TFLY) || 3798 (device == PCI_DEVICE_ID_PFLY) || 3799 (device == PCI_DEVICE_ID_LP101) || 3800 (device == PCI_DEVICE_ID_BMID) || 3801 (device == PCI_DEVICE_ID_BSMB) || 3802 (device == PCI_DEVICE_ID_ZMID) || 3803 (device == PCI_DEVICE_ID_ZSMB) || 3804 (device == PCI_DEVICE_ID_SAT_MID) || 3805 (device == PCI_DEVICE_ID_SAT_SMB) || 3806 (device == PCI_DEVICE_ID_RFLY)) 3807 return 1; 3808 else 3809 return 0; 3810 } 3811 3812 /* 3813 * Determine if an IOCB failed because of a link event or firmware reset. 3814 */ 3815 3816 static inline int 3817 lpfc_error_lost_link(IOCB_t *iocbp) 3818 { 3819 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT && 3820 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED || 3821 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN || 3822 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN)); 3823 } 3824 3825 #define MENLO_TRANSPORT_TYPE 0xfe 3826 #define MENLO_CONTEXT 0 3827 #define MENLO_PU 3 3828 #define MENLO_TIMEOUT 30 3829 #define SETVAR_MLOMNT 0x103107 3830 #define SETVAR_MLORST 0x103007 3831 3832 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */ 3833