1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2004-2005 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 #define FDMI_DID 0xfffffaU 22 #define NameServer_DID 0xfffffcU 23 #define SCR_DID 0xfffffdU 24 #define Fabric_DID 0xfffffeU 25 #define Bcast_DID 0xffffffU 26 #define Mask_DID 0xffffffU 27 #define CT_DID_MASK 0xffff00U 28 #define Fabric_DID_MASK 0xfff000U 29 #define WELL_KNOWN_DID_MASK 0xfffff0U 30 31 #define PT2PT_LocalID 1 32 #define PT2PT_RemoteID 2 33 34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 36 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */ 37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 38 39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 40 0 */ 41 42 #define FCELSSIZE 1024 /* maximum ELS transfer size */ 43 44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 45 #define LPFC_IP_RING 1 /* ring 1 for IP commands */ 46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 47 #define LPFC_FCP_NEXT_RING 3 48 49 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 50 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 51 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 IP command ring entries */ 52 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 IP response ring entries */ 53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 55 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 56 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 57 #define SLI2_IOCB_CMD_R3_ENTRIES 0 58 #define SLI2_IOCB_RSP_R3_ENTRIES 0 59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 61 62 /* Common Transport structures and definitions */ 63 64 union CtRevisionId { 65 /* Structure is in Big Endian format */ 66 struct { 67 uint32_t Revision:8; 68 uint32_t InId:24; 69 } bits; 70 uint32_t word; 71 }; 72 73 union CtCommandResponse { 74 /* Structure is in Big Endian format */ 75 struct { 76 uint32_t CmdRsp:16; 77 uint32_t Size:16; 78 } bits; 79 uint32_t word; 80 }; 81 82 struct lpfc_sli_ct_request { 83 /* Structure is in Big Endian format */ 84 union CtRevisionId RevisionId; 85 uint8_t FsType; 86 uint8_t FsSubType; 87 uint8_t Options; 88 uint8_t Rsrvd1; 89 union CtCommandResponse CommandResponse; 90 uint8_t Rsrvd2; 91 uint8_t ReasonCode; 92 uint8_t Explanation; 93 uint8_t VendorUnique; 94 95 union { 96 uint32_t PortID; 97 struct gid { 98 uint8_t PortType; /* for GID_PT requests */ 99 uint8_t DomainScope; 100 uint8_t AreaScope; 101 uint8_t Fc4Type; /* for GID_FT requests */ 102 } gid; 103 struct rft { 104 uint32_t PortId; /* For RFT_ID requests */ 105 106 #ifdef __BIG_ENDIAN_BITFIELD 107 uint32_t rsvd0:16; 108 uint32_t rsvd1:7; 109 uint32_t fcpReg:1; /* Type 8 */ 110 uint32_t rsvd2:2; 111 uint32_t ipReg:1; /* Type 5 */ 112 uint32_t rsvd3:5; 113 #else /* __LITTLE_ENDIAN_BITFIELD */ 114 uint32_t rsvd0:16; 115 uint32_t fcpReg:1; /* Type 8 */ 116 uint32_t rsvd1:7; 117 uint32_t rsvd3:5; 118 uint32_t ipReg:1; /* Type 5 */ 119 uint32_t rsvd2:2; 120 #endif 121 122 uint32_t rsvd[7]; 123 } rft; 124 struct rnn { 125 uint32_t PortId; /* For RNN_ID requests */ 126 uint8_t wwnn[8]; 127 } rnn; 128 struct rsnn { /* For RSNN_ID requests */ 129 uint8_t wwnn[8]; 130 uint8_t len; 131 uint8_t symbname[255]; 132 } rsnn; 133 } un; 134 }; 135 136 #define SLI_CT_REVISION 1 137 #define GID_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 260) 138 #define RFT_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 228) 139 #define RNN_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 252) 140 #define RSNN_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request)) 141 142 /* 143 * FsType Definitions 144 */ 145 146 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 147 #define SLI_CT_TIME_SERVICE 0xFB 148 #define SLI_CT_DIRECTORY_SERVICE 0xFC 149 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 150 151 /* 152 * Directory Service Subtypes 153 */ 154 155 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 156 157 /* 158 * Response Codes 159 */ 160 161 #define SLI_CT_RESPONSE_FS_RJT 0x8001 162 #define SLI_CT_RESPONSE_FS_ACC 0x8002 163 164 /* 165 * Reason Codes 166 */ 167 168 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 169 #define SLI_CT_INVALID_COMMAND 0x01 170 #define SLI_CT_INVALID_VERSION 0x02 171 #define SLI_CT_LOGICAL_ERROR 0x03 172 #define SLI_CT_INVALID_IU_SIZE 0x04 173 #define SLI_CT_LOGICAL_BUSY 0x05 174 #define SLI_CT_PROTOCOL_ERROR 0x07 175 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 176 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 177 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 178 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 179 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 180 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 181 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 182 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 183 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 184 #define SLI_CT_VENDOR_UNIQUE 0xff 185 186 /* 187 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 188 */ 189 190 #define SLI_CT_NO_PORT_ID 0x01 191 #define SLI_CT_NO_PORT_NAME 0x02 192 #define SLI_CT_NO_NODE_NAME 0x03 193 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 194 #define SLI_CT_NO_IP_ADDRESS 0x05 195 #define SLI_CT_NO_IPA 0x06 196 #define SLI_CT_NO_FC4_TYPES 0x07 197 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 198 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 199 #define SLI_CT_NO_PORT_TYPE 0x0A 200 #define SLI_CT_ACCESS_DENIED 0x10 201 #define SLI_CT_INVALID_PORT_ID 0x11 202 #define SLI_CT_DATABASE_EMPTY 0x12 203 204 /* 205 * Name Server Command Codes 206 */ 207 208 #define SLI_CTNS_GA_NXT 0x0100 209 #define SLI_CTNS_GPN_ID 0x0112 210 #define SLI_CTNS_GNN_ID 0x0113 211 #define SLI_CTNS_GCS_ID 0x0114 212 #define SLI_CTNS_GFT_ID 0x0117 213 #define SLI_CTNS_GSPN_ID 0x0118 214 #define SLI_CTNS_GPT_ID 0x011A 215 #define SLI_CTNS_GID_PN 0x0121 216 #define SLI_CTNS_GID_NN 0x0131 217 #define SLI_CTNS_GIP_NN 0x0135 218 #define SLI_CTNS_GIPA_NN 0x0136 219 #define SLI_CTNS_GSNN_NN 0x0139 220 #define SLI_CTNS_GNN_IP 0x0153 221 #define SLI_CTNS_GIPA_IP 0x0156 222 #define SLI_CTNS_GID_FT 0x0171 223 #define SLI_CTNS_GID_PT 0x01A1 224 #define SLI_CTNS_RPN_ID 0x0212 225 #define SLI_CTNS_RNN_ID 0x0213 226 #define SLI_CTNS_RCS_ID 0x0214 227 #define SLI_CTNS_RFT_ID 0x0217 228 #define SLI_CTNS_RSPN_ID 0x0218 229 #define SLI_CTNS_RPT_ID 0x021A 230 #define SLI_CTNS_RIP_NN 0x0235 231 #define SLI_CTNS_RIPA_NN 0x0236 232 #define SLI_CTNS_RSNN_NN 0x0239 233 #define SLI_CTNS_DA_ID 0x0300 234 235 /* 236 * Port Types 237 */ 238 239 #define SLI_CTPT_N_PORT 0x01 240 #define SLI_CTPT_NL_PORT 0x02 241 #define SLI_CTPT_FNL_PORT 0x03 242 #define SLI_CTPT_IP 0x04 243 #define SLI_CTPT_FCP 0x08 244 #define SLI_CTPT_NX_PORT 0x7F 245 #define SLI_CTPT_F_PORT 0x81 246 #define SLI_CTPT_FL_PORT 0x82 247 #define SLI_CTPT_E_PORT 0x84 248 249 #define SLI_CT_LAST_ENTRY 0x80000000 250 251 /* Fibre Channel Service Parameter definitions */ 252 253 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 254 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 255 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 256 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 257 258 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 259 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 260 #define FC_PH3 0x20 /* FC-PH-3 version */ 261 262 #define FF_FRAME_SIZE 2048 263 264 struct lpfc_name { 265 #ifdef __BIG_ENDIAN_BITFIELD 266 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 267 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 8:11 of IEEE ext */ 268 #else /* __LITTLE_ENDIAN_BITFIELD */ 269 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 8:11 of IEEE ext */ 270 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 271 #endif 272 273 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 274 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 275 #define NAME_FC_TYPE 0x3 /* FC native name type */ 276 #define NAME_IP_TYPE 0x4 /* IP address */ 277 #define NAME_CCITT_TYPE 0xC 278 #define NAME_CCITT_GR_TYPE 0xE 279 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE extended Lsb */ 280 uint8_t IEEE[6]; /* FC IEEE address */ 281 }; 282 283 struct csp { 284 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 285 uint8_t fcphLow; 286 uint8_t bbCreditMsb; 287 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 288 289 #ifdef __BIG_ENDIAN_BITFIELD 290 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */ 291 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 292 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */ 293 uint16_t fPort:1; /* FC Word 1, bit 28 */ 294 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 295 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 296 uint16_t multicast:1; /* FC Word 1, bit 25 */ 297 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 298 299 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 300 uint16_t simplex:1; /* FC Word 1, bit 22 */ 301 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 302 uint16_t dhd:1; /* FC Word 1, bit 18 */ 303 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 304 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 305 #else /* __LITTLE_ENDIAN_BITFIELD */ 306 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 307 uint16_t multicast:1; /* FC Word 1, bit 25 */ 308 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 309 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 310 uint16_t fPort:1; /* FC Word 1, bit 28 */ 311 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */ 312 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 313 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */ 314 315 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 316 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 317 uint16_t dhd:1; /* FC Word 1, bit 18 */ 318 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 319 uint16_t simplex:1; /* FC Word 1, bit 22 */ 320 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 321 #endif 322 323 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 324 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 325 union { 326 struct { 327 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 328 329 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 330 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 331 332 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 333 } nPort; 334 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 335 } w2; 336 337 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 338 }; 339 340 struct class_parms { 341 #ifdef __BIG_ENDIAN_BITFIELD 342 uint8_t classValid:1; /* FC Word 0, bit 31 */ 343 uint8_t intermix:1; /* FC Word 0, bit 30 */ 344 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 345 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 346 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 347 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 348 #else /* __LITTLE_ENDIAN_BITFIELD */ 349 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 350 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 351 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 352 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 353 uint8_t intermix:1; /* FC Word 0, bit 30 */ 354 uint8_t classValid:1; /* FC Word 0, bit 31 */ 355 356 #endif 357 358 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 359 360 #ifdef __BIG_ENDIAN_BITFIELD 361 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 362 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 363 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 364 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 365 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 366 #else /* __LITTLE_ENDIAN_BITFIELD */ 367 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 368 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 369 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 370 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 371 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 372 #endif 373 374 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 375 376 #ifdef __BIG_ENDIAN_BITFIELD 377 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 378 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 379 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 380 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 381 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 382 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 383 #else /* __LITTLE_ENDIAN_BITFIELD */ 384 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 385 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 386 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 387 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 388 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 389 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 390 #endif 391 392 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 393 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 394 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 395 396 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 397 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 398 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 399 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 400 401 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 402 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 403 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 404 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 405 }; 406 407 struct serv_parm { /* Structure is in Big Endian format */ 408 struct csp cmn; 409 struct lpfc_name portName; 410 struct lpfc_name nodeName; 411 struct class_parms cls1; 412 struct class_parms cls2; 413 struct class_parms cls3; 414 struct class_parms cls4; 415 uint8_t vendorVersion[16]; 416 }; 417 418 /* 419 * Extended Link Service LS_COMMAND codes (Payload Word 0) 420 */ 421 #ifdef __BIG_ENDIAN_BITFIELD 422 #define ELS_CMD_MASK 0xffff0000 423 #define ELS_RSP_MASK 0xff000000 424 #define ELS_CMD_LS_RJT 0x01000000 425 #define ELS_CMD_ACC 0x02000000 426 #define ELS_CMD_PLOGI 0x03000000 427 #define ELS_CMD_FLOGI 0x04000000 428 #define ELS_CMD_LOGO 0x05000000 429 #define ELS_CMD_ABTX 0x06000000 430 #define ELS_CMD_RCS 0x07000000 431 #define ELS_CMD_RES 0x08000000 432 #define ELS_CMD_RSS 0x09000000 433 #define ELS_CMD_RSI 0x0A000000 434 #define ELS_CMD_ESTS 0x0B000000 435 #define ELS_CMD_ESTC 0x0C000000 436 #define ELS_CMD_ADVC 0x0D000000 437 #define ELS_CMD_RTV 0x0E000000 438 #define ELS_CMD_RLS 0x0F000000 439 #define ELS_CMD_ECHO 0x10000000 440 #define ELS_CMD_TEST 0x11000000 441 #define ELS_CMD_RRQ 0x12000000 442 #define ELS_CMD_PRLI 0x20100014 443 #define ELS_CMD_PRLO 0x21100014 444 #define ELS_CMD_PDISC 0x50000000 445 #define ELS_CMD_FDISC 0x51000000 446 #define ELS_CMD_ADISC 0x52000000 447 #define ELS_CMD_FARP 0x54000000 448 #define ELS_CMD_FARPR 0x55000000 449 #define ELS_CMD_FAN 0x60000000 450 #define ELS_CMD_RSCN 0x61040000 451 #define ELS_CMD_SCR 0x62000000 452 #define ELS_CMD_RNID 0x78000000 453 #else /* __LITTLE_ENDIAN_BITFIELD */ 454 #define ELS_CMD_MASK 0xffff 455 #define ELS_RSP_MASK 0xff 456 #define ELS_CMD_LS_RJT 0x01 457 #define ELS_CMD_ACC 0x02 458 #define ELS_CMD_PLOGI 0x03 459 #define ELS_CMD_FLOGI 0x04 460 #define ELS_CMD_LOGO 0x05 461 #define ELS_CMD_ABTX 0x06 462 #define ELS_CMD_RCS 0x07 463 #define ELS_CMD_RES 0x08 464 #define ELS_CMD_RSS 0x09 465 #define ELS_CMD_RSI 0x0A 466 #define ELS_CMD_ESTS 0x0B 467 #define ELS_CMD_ESTC 0x0C 468 #define ELS_CMD_ADVC 0x0D 469 #define ELS_CMD_RTV 0x0E 470 #define ELS_CMD_RLS 0x0F 471 #define ELS_CMD_ECHO 0x10 472 #define ELS_CMD_TEST 0x11 473 #define ELS_CMD_RRQ 0x12 474 #define ELS_CMD_PRLI 0x14001020 475 #define ELS_CMD_PRLO 0x14001021 476 #define ELS_CMD_PDISC 0x50 477 #define ELS_CMD_FDISC 0x51 478 #define ELS_CMD_ADISC 0x52 479 #define ELS_CMD_FARP 0x54 480 #define ELS_CMD_FARPR 0x55 481 #define ELS_CMD_FAN 0x60 482 #define ELS_CMD_RSCN 0x0461 483 #define ELS_CMD_SCR 0x62 484 #define ELS_CMD_RNID 0x78 485 #endif 486 487 /* 488 * LS_RJT Payload Definition 489 */ 490 491 struct ls_rjt { /* Structure is in Big Endian format */ 492 union { 493 uint32_t lsRjtError; 494 struct { 495 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 496 497 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 498 /* LS_RJT reason codes */ 499 #define LSRJT_INVALID_CMD 0x01 500 #define LSRJT_LOGICAL_ERR 0x03 501 #define LSRJT_LOGICAL_BSY 0x05 502 #define LSRJT_PROTOCOL_ERR 0x07 503 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 504 #define LSRJT_CMD_UNSUPPORTED 0x0B 505 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 506 507 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 508 /* LS_RJT reason explanation */ 509 #define LSEXP_NOTHING_MORE 0x00 510 #define LSEXP_SPARM_OPTIONS 0x01 511 #define LSEXP_SPARM_ICTL 0x03 512 #define LSEXP_SPARM_RCTL 0x05 513 #define LSEXP_SPARM_RCV_SIZE 0x07 514 #define LSEXP_SPARM_CONCUR_SEQ 0x09 515 #define LSEXP_SPARM_CREDIT 0x0B 516 #define LSEXP_INVALID_PNAME 0x0D 517 #define LSEXP_INVALID_NNAME 0x0E 518 #define LSEXP_INVALID_CSP 0x0F 519 #define LSEXP_INVALID_ASSOC_HDR 0x11 520 #define LSEXP_ASSOC_HDR_REQ 0x13 521 #define LSEXP_INVALID_O_SID 0x15 522 #define LSEXP_INVALID_OX_RX 0x17 523 #define LSEXP_CMD_IN_PROGRESS 0x19 524 #define LSEXP_INVALID_NPORT_ID 0x1F 525 #define LSEXP_INVALID_SEQ_ID 0x21 526 #define LSEXP_INVALID_XCHG 0x23 527 #define LSEXP_INACTIVE_XCHG 0x25 528 #define LSEXP_RQ_REQUIRED 0x27 529 #define LSEXP_OUT_OF_RESOURCE 0x29 530 #define LSEXP_CANT_GIVE_DATA 0x2A 531 #define LSEXP_REQ_UNSUPPORTED 0x2C 532 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 533 } b; 534 } un; 535 }; 536 537 /* 538 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 539 */ 540 541 typedef struct _LOGO { /* Structure is in Big Endian format */ 542 union { 543 uint32_t nPortId32; /* Access nPortId as a word */ 544 struct { 545 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 546 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 547 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 548 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 549 } b; 550 } un; 551 struct lpfc_name portName; /* N_port name field */ 552 } LOGO; 553 554 /* 555 * FCP Login (PRLI Request / ACC) Payload Definition 556 */ 557 558 #define PRLX_PAGE_LEN 0x10 559 #define TPRLO_PAGE_LEN 0x14 560 561 typedef struct _PRLI { /* Structure is in Big Endian format */ 562 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 563 564 #define PRLI_FCP_TYPE 0x08 565 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 566 567 #ifdef __BIG_ENDIAN_BITFIELD 568 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 569 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 570 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 571 572 /* ACC = imagePairEstablished */ 573 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 574 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 575 #else /* __LITTLE_ENDIAN_BITFIELD */ 576 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 577 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 578 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 579 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 580 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 581 /* ACC = imagePairEstablished */ 582 #endif 583 584 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 585 #define PRLI_NO_RESOURCES 0x2 586 #define PRLI_INIT_INCOMPLETE 0x3 587 #define PRLI_NO_SUCH_PA 0x4 588 #define PRLI_PREDEF_CONFIG 0x5 589 #define PRLI_PARTIAL_SUCCESS 0x6 590 #define PRLI_INVALID_PAGE_CNT 0x7 591 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 592 593 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 594 595 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 596 597 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 598 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 599 600 #ifdef __BIG_ENDIAN_BITFIELD 601 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 602 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 603 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 604 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 605 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 606 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 607 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 608 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 609 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 610 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 611 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 612 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 613 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 614 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 615 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 616 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 617 #else /* __LITTLE_ENDIAN_BITFIELD */ 618 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 619 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 620 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 621 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 622 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 623 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 624 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 625 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 626 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 627 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 628 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 629 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 630 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 631 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 632 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 633 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 634 #endif 635 } PRLI; 636 637 /* 638 * FCP Logout (PRLO Request / ACC) Payload Definition 639 */ 640 641 typedef struct _PRLO { /* Structure is in Big Endian format */ 642 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 643 644 #define PRLO_FCP_TYPE 0x08 645 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 646 647 #ifdef __BIG_ENDIAN_BITFIELD 648 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 649 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 650 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 651 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 652 #else /* __LITTLE_ENDIAN_BITFIELD */ 653 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 654 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 655 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 656 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 657 #endif 658 659 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 660 #define PRLO_NO_SUCH_IMAGE 0x4 661 #define PRLO_INVALID_PAGE_CNT 0x7 662 663 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 664 665 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 666 667 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 668 669 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 670 } PRLO; 671 672 typedef struct _ADISC { /* Structure is in Big Endian format */ 673 uint32_t hardAL_PA; 674 struct lpfc_name portName; 675 struct lpfc_name nodeName; 676 uint32_t DID; 677 } ADISC; 678 679 typedef struct _FARP { /* Structure is in Big Endian format */ 680 uint32_t Mflags:8; 681 uint32_t Odid:24; 682 #define FARP_NO_ACTION 0 /* FARP information enclosed, no 683 action */ 684 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 685 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 686 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 687 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 688 supported */ 689 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 690 supported */ 691 uint32_t Rflags:8; 692 uint32_t Rdid:24; 693 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 694 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 695 struct lpfc_name OportName; 696 struct lpfc_name OnodeName; 697 struct lpfc_name RportName; 698 struct lpfc_name RnodeName; 699 uint8_t Oipaddr[16]; 700 uint8_t Ripaddr[16]; 701 } FARP; 702 703 typedef struct _FAN { /* Structure is in Big Endian format */ 704 uint32_t Fdid; 705 struct lpfc_name FportName; 706 struct lpfc_name FnodeName; 707 } FAN; 708 709 typedef struct _SCR { /* Structure is in Big Endian format */ 710 uint8_t resvd1; 711 uint8_t resvd2; 712 uint8_t resvd3; 713 uint8_t Function; 714 #define SCR_FUNC_FABRIC 0x01 715 #define SCR_FUNC_NPORT 0x02 716 #define SCR_FUNC_FULL 0x03 717 #define SCR_CLEAR 0xff 718 } SCR; 719 720 typedef struct _RNID_TOP_DISC { 721 struct lpfc_name portName; 722 uint8_t resvd[8]; 723 uint32_t unitType; 724 #define RNID_HBA 0x7 725 #define RNID_HOST 0xa 726 #define RNID_DRIVER 0xd 727 uint32_t physPort; 728 uint32_t attachedNodes; 729 uint16_t ipVersion; 730 #define RNID_IPV4 0x1 731 #define RNID_IPV6 0x2 732 uint16_t UDPport; 733 uint8_t ipAddr[16]; 734 uint16_t resvd1; 735 uint16_t flags; 736 #define RNID_TD_SUPPORT 0x1 737 #define RNID_LP_VALID 0x2 738 } RNID_TOP_DISC; 739 740 typedef struct _RNID { /* Structure is in Big Endian format */ 741 uint8_t Format; 742 #define RNID_TOPOLOGY_DISC 0xdf 743 uint8_t CommonLen; 744 uint8_t resvd1; 745 uint8_t SpecificLen; 746 struct lpfc_name portName; 747 struct lpfc_name nodeName; 748 union { 749 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 750 } un; 751 } RNID; 752 753 typedef struct _RRQ { /* Structure is in Big Endian format */ 754 uint32_t SID; 755 uint16_t Oxid; 756 uint16_t Rxid; 757 uint8_t resv[32]; /* optional association hdr */ 758 } RRQ; 759 760 /* This is used for RSCN command */ 761 typedef struct _D_ID { /* Structure is in Big Endian format */ 762 union { 763 uint32_t word; 764 struct { 765 #ifdef __BIG_ENDIAN_BITFIELD 766 uint8_t resv; 767 uint8_t domain; 768 uint8_t area; 769 uint8_t id; 770 #else /* __LITTLE_ENDIAN_BITFIELD */ 771 uint8_t id; 772 uint8_t area; 773 uint8_t domain; 774 uint8_t resv; 775 #endif 776 } b; 777 } un; 778 } D_ID; 779 780 /* 781 * Structure to define all ELS Payload types 782 */ 783 784 typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 785 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 786 uint8_t elsByte1; 787 uint8_t elsByte2; 788 uint8_t elsByte3; 789 union { 790 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 791 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 792 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 793 PRLI prli; /* Payload for PRLI/ACC */ 794 PRLO prlo; /* Payload for PRLO/ACC */ 795 ADISC adisc; /* Payload for ADISC/ACC */ 796 FARP farp; /* Payload for FARP/ACC */ 797 FAN fan; /* Payload for FAN */ 798 SCR scr; /* Payload for SCR/ACC */ 799 RRQ rrq; /* Payload for RRQ */ 800 RNID rnid; /* Payload for RNID */ 801 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 802 } un; 803 } ELS_PKT; 804 805 /* 806 * FDMI 807 * HBA MAnagement Operations Command Codes 808 */ 809 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 810 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 811 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 812 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 813 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 814 #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */ 815 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 816 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 817 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 818 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 819 820 /* 821 * Management Service Subtypes 822 */ 823 #define SLI_CT_FDMI_Subtypes 0x10 824 825 /* 826 * HBA Management Service Reject Code 827 */ 828 #define REJECT_CODE 0x9 /* Unable to perform command request */ 829 830 /* 831 * HBA Management Service Reject Reason Code 832 * Please refer to the Reason Codes above 833 */ 834 835 /* 836 * HBA Attribute Types 837 */ 838 #define NODE_NAME 0x1 839 #define MANUFACTURER 0x2 840 #define SERIAL_NUMBER 0x3 841 #define MODEL 0x4 842 #define MODEL_DESCRIPTION 0x5 843 #define HARDWARE_VERSION 0x6 844 #define DRIVER_VERSION 0x7 845 #define OPTION_ROM_VERSION 0x8 846 #define FIRMWARE_VERSION 0x9 847 #define OS_NAME_VERSION 0xa 848 #define MAX_CT_PAYLOAD_LEN 0xb 849 850 /* 851 * Port Attrubute Types 852 */ 853 #define SUPPORTED_FC4_TYPES 0x1 854 #define SUPPORTED_SPEED 0x2 855 #define PORT_SPEED 0x3 856 #define MAX_FRAME_SIZE 0x4 857 #define OS_DEVICE_NAME 0x5 858 #define HOST_NAME 0x6 859 860 union AttributesDef { 861 /* Structure is in Big Endian format */ 862 struct { 863 uint32_t AttrType:16; 864 uint32_t AttrLen:16; 865 } bits; 866 uint32_t word; 867 }; 868 869 870 /* 871 * HBA Attribute Entry (8 - 260 bytes) 872 */ 873 typedef struct { 874 union AttributesDef ad; 875 union { 876 uint32_t VendorSpecific; 877 uint8_t Manufacturer[64]; 878 uint8_t SerialNumber[64]; 879 uint8_t Model[256]; 880 uint8_t ModelDescription[256]; 881 uint8_t HardwareVersion[256]; 882 uint8_t DriverVersion[256]; 883 uint8_t OptionROMVersion[256]; 884 uint8_t FirmwareVersion[256]; 885 struct lpfc_name NodeName; 886 uint8_t SupportFC4Types[32]; 887 uint32_t SupportSpeed; 888 uint32_t PortSpeed; 889 uint32_t MaxFrameSize; 890 uint8_t OsDeviceName[256]; 891 uint8_t OsNameVersion[256]; 892 uint32_t MaxCTPayloadLen; 893 uint8_t HostName[256]; 894 } un; 895 } ATTRIBUTE_ENTRY; 896 897 /* 898 * HBA Attribute Block 899 */ 900 typedef struct { 901 uint32_t EntryCnt; /* Number of HBA attribute entries */ 902 ATTRIBUTE_ENTRY Entry; /* Variable-length array */ 903 } ATTRIBUTE_BLOCK; 904 905 /* 906 * Port Entry 907 */ 908 typedef struct { 909 struct lpfc_name PortName; 910 } PORT_ENTRY; 911 912 /* 913 * HBA Identifier 914 */ 915 typedef struct { 916 struct lpfc_name PortName; 917 } HBA_IDENTIFIER; 918 919 /* 920 * Registered Port List Format 921 */ 922 typedef struct { 923 uint32_t EntryCnt; 924 PORT_ENTRY pe; /* Variable-length array */ 925 } REG_PORT_LIST; 926 927 /* 928 * Register HBA(RHBA) 929 */ 930 typedef struct { 931 HBA_IDENTIFIER hi; 932 REG_PORT_LIST rpl; /* variable-length array */ 933 /* ATTRIBUTE_BLOCK ab; */ 934 } REG_HBA; 935 936 /* 937 * Register HBA Attributes (RHAT) 938 */ 939 typedef struct { 940 struct lpfc_name HBA_PortName; 941 ATTRIBUTE_BLOCK ab; 942 } REG_HBA_ATTRIBUTE; 943 944 /* 945 * Register Port Attributes (RPA) 946 */ 947 typedef struct { 948 struct lpfc_name PortName; 949 ATTRIBUTE_BLOCK ab; 950 } REG_PORT_ATTRIBUTE; 951 952 /* 953 * Get Registered HBA List (GRHL) Accept Payload Format 954 */ 955 typedef struct { 956 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */ 957 struct lpfc_name HBA_PortName; /* Variable-length array */ 958 } GRHL_ACC_PAYLOAD; 959 960 /* 961 * Get Registered Port List (GRPL) Accept Payload Format 962 */ 963 typedef struct { 964 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */ 965 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */ 966 } GRPL_ACC_PAYLOAD; 967 968 /* 969 * Get Port Attributes (GPAT) Accept Payload Format 970 */ 971 972 typedef struct { 973 ATTRIBUTE_BLOCK pab; 974 } GPAT_ACC_PAYLOAD; 975 976 977 /* 978 * Begin HBA configuration parameters. 979 * The PCI configuration register BAR assignments are: 980 * BAR0, offset 0x10 - SLIM base memory address 981 * BAR1, offset 0x14 - SLIM base memory high address 982 * BAR2, offset 0x18 - REGISTER base memory address 983 * BAR3, offset 0x1c - REGISTER base memory high address 984 * BAR4, offset 0x20 - BIU I/O registers 985 * BAR5, offset 0x24 - REGISTER base io high address 986 */ 987 988 /* Number of rings currently used and available. */ 989 #define MAX_CONFIGURED_RINGS 3 990 #define MAX_RINGS 4 991 992 /* IOCB / Mailbox is owned by FireFly */ 993 #define OWN_CHIP 1 994 995 /* IOCB / Mailbox is owned by Host */ 996 #define OWN_HOST 0 997 998 /* Number of 4-byte words in an IOCB. */ 999 #define IOCB_WORD_SZ 8 1000 1001 /* defines for type field in fc header */ 1002 #define FC_ELS_DATA 0x1 1003 #define FC_LLC_SNAP 0x5 1004 #define FC_FCP_DATA 0x8 1005 #define FC_COMMON_TRANSPORT_ULP 0x20 1006 1007 /* defines for rctl field in fc header */ 1008 #define FC_DEV_DATA 0x0 1009 #define FC_UNSOL_CTL 0x2 1010 #define FC_SOL_CTL 0x3 1011 #define FC_UNSOL_DATA 0x4 1012 #define FC_FCP_CMND 0x6 1013 #define FC_ELS_REQ 0x22 1014 #define FC_ELS_RSP 0x23 1015 1016 /* network headers for Dfctl field */ 1017 #define FC_NET_HDR 0x20 1018 1019 /* Start FireFly Register definitions */ 1020 #define PCI_VENDOR_ID_EMULEX 0x10df 1021 #define PCI_DEVICE_ID_FIREFLY 0x1ae5 1022 #define PCI_DEVICE_ID_SUPERFLY 0xf700 1023 #define PCI_DEVICE_ID_DRAGONFLY 0xf800 1024 #define PCI_DEVICE_ID_RFLY 0xf095 1025 #define PCI_DEVICE_ID_PFLY 0xf098 1026 #define PCI_DEVICE_ID_TFLY 0xf0a5 1027 #define PCI_DEVICE_ID_CENTAUR 0xf900 1028 #define PCI_DEVICE_ID_PEGASUS 0xf980 1029 #define PCI_DEVICE_ID_THOR 0xfa00 1030 #define PCI_DEVICE_ID_VIPER 0xfb00 1031 #define PCI_DEVICE_ID_HELIOS 0xfd00 1032 #define PCI_DEVICE_ID_BMID 0xf0d5 1033 #define PCI_DEVICE_ID_BSMB 0xf0d1 1034 #define PCI_DEVICE_ID_ZEPHYR 0xfe00 1035 #define PCI_DEVICE_ID_ZMID 0xf0e5 1036 #define PCI_DEVICE_ID_ZSMB 0xf0e1 1037 #define PCI_DEVICE_ID_LP101 0xf0a1 1038 #define PCI_DEVICE_ID_LP10000S 0xfc00 1039 1040 #define JEDEC_ID_ADDRESS 0x0080001c 1041 #define FIREFLY_JEDEC_ID 0x1ACC 1042 #define SUPERFLY_JEDEC_ID 0x0020 1043 #define DRAGONFLY_JEDEC_ID 0x0021 1044 #define DRAGONFLY_V2_JEDEC_ID 0x0025 1045 #define CENTAUR_2G_JEDEC_ID 0x0026 1046 #define CENTAUR_1G_JEDEC_ID 0x0028 1047 #define PEGASUS_ORION_JEDEC_ID 0x0036 1048 #define PEGASUS_JEDEC_ID 0x0038 1049 #define THOR_JEDEC_ID 0x0012 1050 #define HELIOS_JEDEC_ID 0x0364 1051 #define ZEPHYR_JEDEC_ID 0x0577 1052 #define VIPER_JEDEC_ID 0x4838 1053 1054 #define JEDEC_ID_MASK 0x0FFFF000 1055 #define JEDEC_ID_SHIFT 12 1056 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1057 1058 typedef struct { /* FireFly BIU registers */ 1059 uint32_t hostAtt; /* See definitions for Host Attention 1060 register */ 1061 uint32_t chipAtt; /* See definitions for Chip Attention 1062 register */ 1063 uint32_t hostStatus; /* See definitions for Host Status register */ 1064 uint32_t hostControl; /* See definitions for Host Control register */ 1065 uint32_t buiConfig; /* See definitions for BIU configuration 1066 register */ 1067 } FF_REGS; 1068 1069 /* IO Register size in bytes */ 1070 #define FF_REG_AREA_SIZE 256 1071 1072 /* Host Attention Register */ 1073 1074 #define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1075 1076 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1077 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1078 #define HA_R0ATT 0x00000008 /* Bit 3 */ 1079 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1080 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1081 #define HA_R1ATT 0x00000080 /* Bit 7 */ 1082 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1083 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1084 #define HA_R2ATT 0x00000800 /* Bit 11 */ 1085 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1086 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1087 #define HA_R3ATT 0x00008000 /* Bit 15 */ 1088 #define HA_LATT 0x20000000 /* Bit 29 */ 1089 #define HA_MBATT 0x40000000 /* Bit 30 */ 1090 #define HA_ERATT 0x80000000 /* Bit 31 */ 1091 1092 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1093 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1094 #define HA_RXATT 0x00000008 /* Bit 3 */ 1095 #define HA_RXMASK 0x0000000f 1096 1097 /* Chip Attention Register */ 1098 1099 #define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1100 1101 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1102 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1103 #define CA_R0ATT 0x00000008 /* Bit 3 */ 1104 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1105 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1106 #define CA_R1ATT 0x00000080 /* Bit 7 */ 1107 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1108 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1109 #define CA_R2ATT 0x00000800 /* Bit 11 */ 1110 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1111 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1112 #define CA_R3ATT 0x00008000 /* Bit 15 */ 1113 #define CA_MBATT 0x40000000 /* Bit 30 */ 1114 1115 /* Host Status Register */ 1116 1117 #define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1118 1119 #define HS_MBRDY 0x00400000 /* Bit 22 */ 1120 #define HS_FFRDY 0x00800000 /* Bit 23 */ 1121 #define HS_FFER8 0x01000000 /* Bit 24 */ 1122 #define HS_FFER7 0x02000000 /* Bit 25 */ 1123 #define HS_FFER6 0x04000000 /* Bit 26 */ 1124 #define HS_FFER5 0x08000000 /* Bit 27 */ 1125 #define HS_FFER4 0x10000000 /* Bit 28 */ 1126 #define HS_FFER3 0x20000000 /* Bit 29 */ 1127 #define HS_FFER2 0x40000000 /* Bit 30 */ 1128 #define HS_FFER1 0x80000000 /* Bit 31 */ 1129 #define HS_FFERM 0xFF000000 /* Mask for error bits 31:24 */ 1130 1131 /* Host Control Register */ 1132 1133 #define HC_REG_OFFSET 12 /* Word offset from register base address */ 1134 1135 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1136 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1137 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1138 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1139 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1140 #define HC_INITHBI 0x02000000 /* Bit 25 */ 1141 #define HC_INITMB 0x04000000 /* Bit 26 */ 1142 #define HC_INITFF 0x08000000 /* Bit 27 */ 1143 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1144 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1145 1146 /* Mailbox Commands */ 1147 #define MBX_SHUTDOWN 0x00 /* terminate testing */ 1148 #define MBX_LOAD_SM 0x01 1149 #define MBX_READ_NV 0x02 1150 #define MBX_WRITE_NV 0x03 1151 #define MBX_RUN_BIU_DIAG 0x04 1152 #define MBX_INIT_LINK 0x05 1153 #define MBX_DOWN_LINK 0x06 1154 #define MBX_CONFIG_LINK 0x07 1155 #define MBX_CONFIG_RING 0x09 1156 #define MBX_RESET_RING 0x0A 1157 #define MBX_READ_CONFIG 0x0B 1158 #define MBX_READ_RCONFIG 0x0C 1159 #define MBX_READ_SPARM 0x0D 1160 #define MBX_READ_STATUS 0x0E 1161 #define MBX_READ_RPI 0x0F 1162 #define MBX_READ_XRI 0x10 1163 #define MBX_READ_REV 0x11 1164 #define MBX_READ_LNK_STAT 0x12 1165 #define MBX_REG_LOGIN 0x13 1166 #define MBX_UNREG_LOGIN 0x14 1167 #define MBX_READ_LA 0x15 1168 #define MBX_CLEAR_LA 0x16 1169 #define MBX_DUMP_MEMORY 0x17 1170 #define MBX_DUMP_CONTEXT 0x18 1171 #define MBX_RUN_DIAGS 0x19 1172 #define MBX_RESTART 0x1A 1173 #define MBX_UPDATE_CFG 0x1B 1174 #define MBX_DOWN_LOAD 0x1C 1175 #define MBX_DEL_LD_ENTRY 0x1D 1176 #define MBX_RUN_PROGRAM 0x1E 1177 #define MBX_SET_MASK 0x20 1178 #define MBX_SET_SLIM 0x21 1179 #define MBX_UNREG_D_ID 0x23 1180 #define MBX_CONFIG_FARP 0x25 1181 1182 #define MBX_LOAD_AREA 0x81 1183 #define MBX_RUN_BIU_DIAG64 0x84 1184 #define MBX_CONFIG_PORT 0x88 1185 #define MBX_READ_SPARM64 0x8D 1186 #define MBX_READ_RPI64 0x8F 1187 #define MBX_REG_LOGIN64 0x93 1188 #define MBX_READ_LA64 0x95 1189 1190 #define MBX_FLASH_WR_ULA 0x98 1191 #define MBX_SET_DEBUG 0x99 1192 #define MBX_LOAD_EXP_ROM 0x9C 1193 1194 #define MBX_MAX_CMDS 0x9D 1195 #define MBX_SLI2_CMD_MASK 0x80 1196 1197 /* IOCB Commands */ 1198 1199 #define CMD_RCV_SEQUENCE_CX 0x01 1200 #define CMD_XMIT_SEQUENCE_CR 0x02 1201 #define CMD_XMIT_SEQUENCE_CX 0x03 1202 #define CMD_XMIT_BCAST_CN 0x04 1203 #define CMD_XMIT_BCAST_CX 0x05 1204 #define CMD_QUE_RING_BUF_CN 0x06 1205 #define CMD_QUE_XRI_BUF_CX 0x07 1206 #define CMD_IOCB_CONTINUE_CN 0x08 1207 #define CMD_RET_XRI_BUF_CX 0x09 1208 #define CMD_ELS_REQUEST_CR 0x0A 1209 #define CMD_ELS_REQUEST_CX 0x0B 1210 #define CMD_RCV_ELS_REQ_CX 0x0D 1211 #define CMD_ABORT_XRI_CN 0x0E 1212 #define CMD_ABORT_XRI_CX 0x0F 1213 #define CMD_CLOSE_XRI_CN 0x10 1214 #define CMD_CLOSE_XRI_CX 0x11 1215 #define CMD_CREATE_XRI_CR 0x12 1216 #define CMD_CREATE_XRI_CX 0x13 1217 #define CMD_GET_RPI_CN 0x14 1218 #define CMD_XMIT_ELS_RSP_CX 0x15 1219 #define CMD_GET_RPI_CR 0x16 1220 #define CMD_XRI_ABORTED_CX 0x17 1221 #define CMD_FCP_IWRITE_CR 0x18 1222 #define CMD_FCP_IWRITE_CX 0x19 1223 #define CMD_FCP_IREAD_CR 0x1A 1224 #define CMD_FCP_IREAD_CX 0x1B 1225 #define CMD_FCP_ICMND_CR 0x1C 1226 #define CMD_FCP_ICMND_CX 0x1D 1227 1228 #define CMD_ADAPTER_MSG 0x20 1229 #define CMD_ADAPTER_DUMP 0x22 1230 1231 /* SLI_2 IOCB Command Set */ 1232 1233 #define CMD_RCV_SEQUENCE64_CX 0x81 1234 #define CMD_XMIT_SEQUENCE64_CR 0x82 1235 #define CMD_XMIT_SEQUENCE64_CX 0x83 1236 #define CMD_XMIT_BCAST64_CN 0x84 1237 #define CMD_XMIT_BCAST64_CX 0x85 1238 #define CMD_QUE_RING_BUF64_CN 0x86 1239 #define CMD_QUE_XRI_BUF64_CX 0x87 1240 #define CMD_IOCB_CONTINUE64_CN 0x88 1241 #define CMD_RET_XRI_BUF64_CX 0x89 1242 #define CMD_ELS_REQUEST64_CR 0x8A 1243 #define CMD_ELS_REQUEST64_CX 0x8B 1244 #define CMD_ABORT_MXRI64_CN 0x8C 1245 #define CMD_RCV_ELS_REQ64_CX 0x8D 1246 #define CMD_XMIT_ELS_RSP64_CX 0x95 1247 #define CMD_FCP_IWRITE64_CR 0x98 1248 #define CMD_FCP_IWRITE64_CX 0x99 1249 #define CMD_FCP_IREAD64_CR 0x9A 1250 #define CMD_FCP_IREAD64_CX 0x9B 1251 #define CMD_FCP_ICMND64_CR 0x9C 1252 #define CMD_FCP_ICMND64_CX 0x9D 1253 1254 #define CMD_GEN_REQUEST64_CR 0xC2 1255 #define CMD_GEN_REQUEST64_CX 0xC3 1256 1257 #define CMD_MAX_IOCB_CMD 0xE6 1258 #define CMD_IOCB_MASK 0xff 1259 1260 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 1261 iocb */ 1262 #define LPFC_MAX_ADPTMSG 32 /* max msg data */ 1263 /* 1264 * Define Status 1265 */ 1266 #define MBX_SUCCESS 0 1267 #define MBXERR_NUM_RINGS 1 1268 #define MBXERR_NUM_IOCBS 2 1269 #define MBXERR_IOCBS_EXCEEDED 3 1270 #define MBXERR_BAD_RING_NUMBER 4 1271 #define MBXERR_MASK_ENTRIES_RANGE 5 1272 #define MBXERR_MASKS_EXCEEDED 6 1273 #define MBXERR_BAD_PROFILE 7 1274 #define MBXERR_BAD_DEF_CLASS 8 1275 #define MBXERR_BAD_MAX_RESPONDER 9 1276 #define MBXERR_BAD_MAX_ORIGINATOR 10 1277 #define MBXERR_RPI_REGISTERED 11 1278 #define MBXERR_RPI_FULL 12 1279 #define MBXERR_NO_RESOURCES 13 1280 #define MBXERR_BAD_RCV_LENGTH 14 1281 #define MBXERR_DMA_ERROR 15 1282 #define MBXERR_ERROR 16 1283 #define MBX_NOT_FINISHED 255 1284 1285 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 1286 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 1287 1288 /* 1289 * Begin Structure Definitions for Mailbox Commands 1290 */ 1291 1292 typedef struct { 1293 #ifdef __BIG_ENDIAN_BITFIELD 1294 uint8_t tval; 1295 uint8_t tmask; 1296 uint8_t rval; 1297 uint8_t rmask; 1298 #else /* __LITTLE_ENDIAN_BITFIELD */ 1299 uint8_t rmask; 1300 uint8_t rval; 1301 uint8_t tmask; 1302 uint8_t tval; 1303 #endif 1304 } RR_REG; 1305 1306 struct ulp_bde { 1307 uint32_t bdeAddress; 1308 #ifdef __BIG_ENDIAN_BITFIELD 1309 uint32_t bdeReserved:4; 1310 uint32_t bdeAddrHigh:4; 1311 uint32_t bdeSize:24; 1312 #else /* __LITTLE_ENDIAN_BITFIELD */ 1313 uint32_t bdeSize:24; 1314 uint32_t bdeAddrHigh:4; 1315 uint32_t bdeReserved:4; 1316 #endif 1317 }; 1318 1319 struct ulp_bde64 { /* SLI-2 */ 1320 union ULP_BDE_TUS { 1321 uint32_t w; 1322 struct { 1323 #ifdef __BIG_ENDIAN_BITFIELD 1324 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 1325 VALUE !! */ 1326 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 1327 #else /* __LITTLE_ENDIAN_BITFIELD */ 1328 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 1329 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 1330 VALUE !! */ 1331 #endif 1332 1333 #define BUFF_USE_RSVD 0x01 /* bdeFlags */ 1334 #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */ 1335 #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */ 1336 #define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, 0=xmit 1337 buffer */ 1338 #define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr 0=64 bit 1339 addr */ 1340 #define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */ 1341 #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */ 1342 #define BUFF_TYPE_INVALID 0x80 /* "" "" */ 1343 } f; 1344 } tus; 1345 uint32_t addrLow; 1346 uint32_t addrHigh; 1347 }; 1348 #define BDE64_SIZE_WORD 0 1349 #define BPL64_SIZE_WORD 0x40 1350 1351 typedef struct ULP_BDL { /* SLI-2 */ 1352 #ifdef __BIG_ENDIAN_BITFIELD 1353 uint32_t bdeFlags:8; /* BDL Flags */ 1354 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1355 #else /* __LITTLE_ENDIAN_BITFIELD */ 1356 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1357 uint32_t bdeFlags:8; /* BDL Flags */ 1358 #endif 1359 1360 uint32_t addrLow; /* Address 0:31 */ 1361 uint32_t addrHigh; /* Address 32:63 */ 1362 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1363 } ULP_BDL; 1364 1365 /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 1366 1367 typedef struct { 1368 #ifdef __BIG_ENDIAN_BITFIELD 1369 uint32_t rsvd2:25; 1370 uint32_t acknowledgment:1; 1371 uint32_t version:1; 1372 uint32_t erase_or_prog:1; 1373 uint32_t update_flash:1; 1374 uint32_t update_ram:1; 1375 uint32_t method:1; 1376 uint32_t load_cmplt:1; 1377 #else /* __LITTLE_ENDIAN_BITFIELD */ 1378 uint32_t load_cmplt:1; 1379 uint32_t method:1; 1380 uint32_t update_ram:1; 1381 uint32_t update_flash:1; 1382 uint32_t erase_or_prog:1; 1383 uint32_t version:1; 1384 uint32_t acknowledgment:1; 1385 uint32_t rsvd2:25; 1386 #endif 1387 1388 uint32_t dl_to_adr_low; 1389 uint32_t dl_to_adr_high; 1390 uint32_t dl_len; 1391 union { 1392 uint32_t dl_from_mbx_offset; 1393 struct ulp_bde dl_from_bde; 1394 struct ulp_bde64 dl_from_bde64; 1395 } un; 1396 1397 } LOAD_SM_VAR; 1398 1399 /* Structure for MB Command READ_NVPARM (02) */ 1400 1401 typedef struct { 1402 uint32_t rsvd1[3]; /* Read as all one's */ 1403 uint32_t rsvd2; /* Read as all zero's */ 1404 uint32_t portname[2]; /* N_PORT name */ 1405 uint32_t nodename[2]; /* NODE name */ 1406 1407 #ifdef __BIG_ENDIAN_BITFIELD 1408 uint32_t pref_DID:24; 1409 uint32_t hardAL_PA:8; 1410 #else /* __LITTLE_ENDIAN_BITFIELD */ 1411 uint32_t hardAL_PA:8; 1412 uint32_t pref_DID:24; 1413 #endif 1414 1415 uint32_t rsvd3[21]; /* Read as all one's */ 1416 } READ_NV_VAR; 1417 1418 /* Structure for MB Command WRITE_NVPARMS (03) */ 1419 1420 typedef struct { 1421 uint32_t rsvd1[3]; /* Must be all one's */ 1422 uint32_t rsvd2; /* Must be all zero's */ 1423 uint32_t portname[2]; /* N_PORT name */ 1424 uint32_t nodename[2]; /* NODE name */ 1425 1426 #ifdef __BIG_ENDIAN_BITFIELD 1427 uint32_t pref_DID:24; 1428 uint32_t hardAL_PA:8; 1429 #else /* __LITTLE_ENDIAN_BITFIELD */ 1430 uint32_t hardAL_PA:8; 1431 uint32_t pref_DID:24; 1432 #endif 1433 1434 uint32_t rsvd3[21]; /* Must be all one's */ 1435 } WRITE_NV_VAR; 1436 1437 /* Structure for MB Command RUN_BIU_DIAG (04) */ 1438 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 1439 1440 typedef struct { 1441 uint32_t rsvd1; 1442 union { 1443 struct { 1444 struct ulp_bde xmit_bde; 1445 struct ulp_bde rcv_bde; 1446 } s1; 1447 struct { 1448 struct ulp_bde64 xmit_bde64; 1449 struct ulp_bde64 rcv_bde64; 1450 } s2; 1451 } un; 1452 } BIU_DIAG_VAR; 1453 1454 /* Structure for MB Command INIT_LINK (05) */ 1455 1456 typedef struct { 1457 #ifdef __BIG_ENDIAN_BITFIELD 1458 uint32_t rsvd1:24; 1459 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1460 #else /* __LITTLE_ENDIAN_BITFIELD */ 1461 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1462 uint32_t rsvd1:24; 1463 #endif 1464 1465 #ifdef __BIG_ENDIAN_BITFIELD 1466 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1467 uint8_t rsvd2; 1468 uint16_t link_flags; 1469 #else /* __LITTLE_ENDIAN_BITFIELD */ 1470 uint16_t link_flags; 1471 uint8_t rsvd2; 1472 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1473 #endif 1474 1475 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 1476 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 1477 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 1478 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 1479 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 1480 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 1481 1482 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 1483 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 1484 1485 uint32_t link_speed; 1486 #define LINK_SPEED_AUTO 0 /* Auto selection */ 1487 #define LINK_SPEED_1G 1 /* 1 Gigabaud */ 1488 #define LINK_SPEED_2G 2 /* 2 Gigabaud */ 1489 #define LINK_SPEED_4G 4 /* 4 Gigabaud */ 1490 #define LINK_SPEED_8G 8 /* 4 Gigabaud */ 1491 #define LINK_SPEED_10G 16 /* 10 Gigabaud */ 1492 1493 } INIT_LINK_VAR; 1494 1495 /* Structure for MB Command DOWN_LINK (06) */ 1496 1497 typedef struct { 1498 uint32_t rsvd1; 1499 } DOWN_LINK_VAR; 1500 1501 /* Structure for MB Command CONFIG_LINK (07) */ 1502 1503 typedef struct { 1504 #ifdef __BIG_ENDIAN_BITFIELD 1505 uint32_t cr:1; 1506 uint32_t ci:1; 1507 uint32_t cr_delay:6; 1508 uint32_t cr_count:8; 1509 uint32_t rsvd1:8; 1510 uint32_t MaxBBC:8; 1511 #else /* __LITTLE_ENDIAN_BITFIELD */ 1512 uint32_t MaxBBC:8; 1513 uint32_t rsvd1:8; 1514 uint32_t cr_count:8; 1515 uint32_t cr_delay:6; 1516 uint32_t ci:1; 1517 uint32_t cr:1; 1518 #endif 1519 1520 uint32_t myId; 1521 uint32_t rsvd2; 1522 uint32_t edtov; 1523 uint32_t arbtov; 1524 uint32_t ratov; 1525 uint32_t rttov; 1526 uint32_t altov; 1527 uint32_t crtov; 1528 uint32_t citov; 1529 #ifdef __BIG_ENDIAN_BITFIELD 1530 uint32_t rrq_enable:1; 1531 uint32_t rrq_immed:1; 1532 uint32_t rsvd4:29; 1533 uint32_t ack0_enable:1; 1534 #else /* __LITTLE_ENDIAN_BITFIELD */ 1535 uint32_t ack0_enable:1; 1536 uint32_t rsvd4:29; 1537 uint32_t rrq_immed:1; 1538 uint32_t rrq_enable:1; 1539 #endif 1540 } CONFIG_LINK; 1541 1542 /* Structure for MB Command PART_SLIM (08) 1543 * will be removed since SLI1 is no longer supported! 1544 */ 1545 typedef struct { 1546 #ifdef __BIG_ENDIAN_BITFIELD 1547 uint16_t offCiocb; 1548 uint16_t numCiocb; 1549 uint16_t offRiocb; 1550 uint16_t numRiocb; 1551 #else /* __LITTLE_ENDIAN_BITFIELD */ 1552 uint16_t numCiocb; 1553 uint16_t offCiocb; 1554 uint16_t numRiocb; 1555 uint16_t offRiocb; 1556 #endif 1557 } RING_DEF; 1558 1559 typedef struct { 1560 #ifdef __BIG_ENDIAN_BITFIELD 1561 uint32_t unused1:24; 1562 uint32_t numRing:8; 1563 #else /* __LITTLE_ENDIAN_BITFIELD */ 1564 uint32_t numRing:8; 1565 uint32_t unused1:24; 1566 #endif 1567 1568 RING_DEF ringdef[4]; 1569 uint32_t hbainit; 1570 } PART_SLIM_VAR; 1571 1572 /* Structure for MB Command CONFIG_RING (09) */ 1573 1574 typedef struct { 1575 #ifdef __BIG_ENDIAN_BITFIELD 1576 uint32_t unused2:6; 1577 uint32_t recvSeq:1; 1578 uint32_t recvNotify:1; 1579 uint32_t numMask:8; 1580 uint32_t profile:8; 1581 uint32_t unused1:4; 1582 uint32_t ring:4; 1583 #else /* __LITTLE_ENDIAN_BITFIELD */ 1584 uint32_t ring:4; 1585 uint32_t unused1:4; 1586 uint32_t profile:8; 1587 uint32_t numMask:8; 1588 uint32_t recvNotify:1; 1589 uint32_t recvSeq:1; 1590 uint32_t unused2:6; 1591 #endif 1592 1593 #ifdef __BIG_ENDIAN_BITFIELD 1594 uint16_t maxRespXchg; 1595 uint16_t maxOrigXchg; 1596 #else /* __LITTLE_ENDIAN_BITFIELD */ 1597 uint16_t maxOrigXchg; 1598 uint16_t maxRespXchg; 1599 #endif 1600 1601 RR_REG rrRegs[6]; 1602 } CONFIG_RING_VAR; 1603 1604 /* Structure for MB Command RESET_RING (10) */ 1605 1606 typedef struct { 1607 uint32_t ring_no; 1608 } RESET_RING_VAR; 1609 1610 /* Structure for MB Command READ_CONFIG (11) */ 1611 1612 typedef struct { 1613 #ifdef __BIG_ENDIAN_BITFIELD 1614 uint32_t cr:1; 1615 uint32_t ci:1; 1616 uint32_t cr_delay:6; 1617 uint32_t cr_count:8; 1618 uint32_t InitBBC:8; 1619 uint32_t MaxBBC:8; 1620 #else /* __LITTLE_ENDIAN_BITFIELD */ 1621 uint32_t MaxBBC:8; 1622 uint32_t InitBBC:8; 1623 uint32_t cr_count:8; 1624 uint32_t cr_delay:6; 1625 uint32_t ci:1; 1626 uint32_t cr:1; 1627 #endif 1628 1629 #ifdef __BIG_ENDIAN_BITFIELD 1630 uint32_t topology:8; 1631 uint32_t myDid:24; 1632 #else /* __LITTLE_ENDIAN_BITFIELD */ 1633 uint32_t myDid:24; 1634 uint32_t topology:8; 1635 #endif 1636 1637 /* Defines for topology (defined previously) */ 1638 #ifdef __BIG_ENDIAN_BITFIELD 1639 uint32_t AR:1; 1640 uint32_t IR:1; 1641 uint32_t rsvd1:29; 1642 uint32_t ack0:1; 1643 #else /* __LITTLE_ENDIAN_BITFIELD */ 1644 uint32_t ack0:1; 1645 uint32_t rsvd1:29; 1646 uint32_t IR:1; 1647 uint32_t AR:1; 1648 #endif 1649 1650 uint32_t edtov; 1651 uint32_t arbtov; 1652 uint32_t ratov; 1653 uint32_t rttov; 1654 uint32_t altov; 1655 uint32_t lmt; 1656 #define LMT_RESERVED 0x0 /* Not used */ 1657 #define LMT_266_10bit 0x1 /* 265.625 Mbaud 10 bit iface */ 1658 #define LMT_532_10bit 0x2 /* 531.25 Mbaud 10 bit iface */ 1659 #define LMT_1063_20bit 0x3 /* 1062.5 Mbaud 20 bit iface */ 1660 #define LMT_1063_10bit 0x4 /* 1062.5 Mbaud 10 bit iface */ 1661 #define LMT_2125_10bit 0x8 /* 2125 Mbaud 10 bit iface */ 1662 #define LMT_4250_10bit 0x40 /* 4250 Mbaud 10 bit iface */ 1663 1664 uint32_t rsvd2; 1665 uint32_t rsvd3; 1666 uint32_t max_xri; 1667 uint32_t max_iocb; 1668 uint32_t max_rpi; 1669 uint32_t avail_xri; 1670 uint32_t avail_iocb; 1671 uint32_t avail_rpi; 1672 uint32_t default_rpi; 1673 } READ_CONFIG_VAR; 1674 1675 /* Structure for MB Command READ_RCONFIG (12) */ 1676 1677 typedef struct { 1678 #ifdef __BIG_ENDIAN_BITFIELD 1679 uint32_t rsvd2:7; 1680 uint32_t recvNotify:1; 1681 uint32_t numMask:8; 1682 uint32_t profile:8; 1683 uint32_t rsvd1:4; 1684 uint32_t ring:4; 1685 #else /* __LITTLE_ENDIAN_BITFIELD */ 1686 uint32_t ring:4; 1687 uint32_t rsvd1:4; 1688 uint32_t profile:8; 1689 uint32_t numMask:8; 1690 uint32_t recvNotify:1; 1691 uint32_t rsvd2:7; 1692 #endif 1693 1694 #ifdef __BIG_ENDIAN_BITFIELD 1695 uint16_t maxResp; 1696 uint16_t maxOrig; 1697 #else /* __LITTLE_ENDIAN_BITFIELD */ 1698 uint16_t maxOrig; 1699 uint16_t maxResp; 1700 #endif 1701 1702 RR_REG rrRegs[6]; 1703 1704 #ifdef __BIG_ENDIAN_BITFIELD 1705 uint16_t cmdRingOffset; 1706 uint16_t cmdEntryCnt; 1707 uint16_t rspRingOffset; 1708 uint16_t rspEntryCnt; 1709 uint16_t nextCmdOffset; 1710 uint16_t rsvd3; 1711 uint16_t nextRspOffset; 1712 uint16_t rsvd4; 1713 #else /* __LITTLE_ENDIAN_BITFIELD */ 1714 uint16_t cmdEntryCnt; 1715 uint16_t cmdRingOffset; 1716 uint16_t rspEntryCnt; 1717 uint16_t rspRingOffset; 1718 uint16_t rsvd3; 1719 uint16_t nextCmdOffset; 1720 uint16_t rsvd4; 1721 uint16_t nextRspOffset; 1722 #endif 1723 } READ_RCONF_VAR; 1724 1725 /* Structure for MB Command READ_SPARM (13) */ 1726 /* Structure for MB Command READ_SPARM64 (0x8D) */ 1727 1728 typedef struct { 1729 uint32_t rsvd1; 1730 uint32_t rsvd2; 1731 union { 1732 struct ulp_bde sp; /* This BDE points to struct serv_parm 1733 structure */ 1734 struct ulp_bde64 sp64; 1735 } un; 1736 } READ_SPARM_VAR; 1737 1738 /* Structure for MB Command READ_STATUS (14) */ 1739 1740 typedef struct { 1741 #ifdef __BIG_ENDIAN_BITFIELD 1742 uint32_t rsvd1:31; 1743 uint32_t clrCounters:1; 1744 uint16_t activeXriCnt; 1745 uint16_t activeRpiCnt; 1746 #else /* __LITTLE_ENDIAN_BITFIELD */ 1747 uint32_t clrCounters:1; 1748 uint32_t rsvd1:31; 1749 uint16_t activeRpiCnt; 1750 uint16_t activeXriCnt; 1751 #endif 1752 1753 uint32_t xmitByteCnt; 1754 uint32_t rcvByteCnt; 1755 uint32_t xmitFrameCnt; 1756 uint32_t rcvFrameCnt; 1757 uint32_t xmitSeqCnt; 1758 uint32_t rcvSeqCnt; 1759 uint32_t totalOrigExchanges; 1760 uint32_t totalRespExchanges; 1761 uint32_t rcvPbsyCnt; 1762 uint32_t rcvFbsyCnt; 1763 } READ_STATUS_VAR; 1764 1765 /* Structure for MB Command READ_RPI (15) */ 1766 /* Structure for MB Command READ_RPI64 (0x8F) */ 1767 1768 typedef struct { 1769 #ifdef __BIG_ENDIAN_BITFIELD 1770 uint16_t nextRpi; 1771 uint16_t reqRpi; 1772 uint32_t rsvd2:8; 1773 uint32_t DID:24; 1774 #else /* __LITTLE_ENDIAN_BITFIELD */ 1775 uint16_t reqRpi; 1776 uint16_t nextRpi; 1777 uint32_t DID:24; 1778 uint32_t rsvd2:8; 1779 #endif 1780 1781 union { 1782 struct ulp_bde sp; 1783 struct ulp_bde64 sp64; 1784 } un; 1785 1786 } READ_RPI_VAR; 1787 1788 /* Structure for MB Command READ_XRI (16) */ 1789 1790 typedef struct { 1791 #ifdef __BIG_ENDIAN_BITFIELD 1792 uint16_t nextXri; 1793 uint16_t reqXri; 1794 uint16_t rsvd1; 1795 uint16_t rpi; 1796 uint32_t rsvd2:8; 1797 uint32_t DID:24; 1798 uint32_t rsvd3:8; 1799 uint32_t SID:24; 1800 uint32_t rsvd4; 1801 uint8_t seqId; 1802 uint8_t rsvd5; 1803 uint16_t seqCount; 1804 uint16_t oxId; 1805 uint16_t rxId; 1806 uint32_t rsvd6:30; 1807 uint32_t si:1; 1808 uint32_t exchOrig:1; 1809 #else /* __LITTLE_ENDIAN_BITFIELD */ 1810 uint16_t reqXri; 1811 uint16_t nextXri; 1812 uint16_t rpi; 1813 uint16_t rsvd1; 1814 uint32_t DID:24; 1815 uint32_t rsvd2:8; 1816 uint32_t SID:24; 1817 uint32_t rsvd3:8; 1818 uint32_t rsvd4; 1819 uint16_t seqCount; 1820 uint8_t rsvd5; 1821 uint8_t seqId; 1822 uint16_t rxId; 1823 uint16_t oxId; 1824 uint32_t exchOrig:1; 1825 uint32_t si:1; 1826 uint32_t rsvd6:30; 1827 #endif 1828 } READ_XRI_VAR; 1829 1830 /* Structure for MB Command READ_REV (17) */ 1831 1832 typedef struct { 1833 #ifdef __BIG_ENDIAN_BITFIELD 1834 uint32_t cv:1; 1835 uint32_t rr:1; 1836 uint32_t rsvd1:29; 1837 uint32_t rv:1; 1838 #else /* __LITTLE_ENDIAN_BITFIELD */ 1839 uint32_t rv:1; 1840 uint32_t rsvd1:29; 1841 uint32_t rr:1; 1842 uint32_t cv:1; 1843 #endif 1844 1845 uint32_t biuRev; 1846 uint32_t smRev; 1847 union { 1848 uint32_t smFwRev; 1849 struct { 1850 #ifdef __BIG_ENDIAN_BITFIELD 1851 uint8_t ProgType; 1852 uint8_t ProgId; 1853 uint16_t ProgVer:4; 1854 uint16_t ProgRev:4; 1855 uint16_t ProgFixLvl:2; 1856 uint16_t ProgDistType:2; 1857 uint16_t DistCnt:4; 1858 #else /* __LITTLE_ENDIAN_BITFIELD */ 1859 uint16_t DistCnt:4; 1860 uint16_t ProgDistType:2; 1861 uint16_t ProgFixLvl:2; 1862 uint16_t ProgRev:4; 1863 uint16_t ProgVer:4; 1864 uint8_t ProgId; 1865 uint8_t ProgType; 1866 #endif 1867 1868 } b; 1869 } un; 1870 uint32_t endecRev; 1871 #ifdef __BIG_ENDIAN_BITFIELD 1872 uint8_t feaLevelHigh; 1873 uint8_t feaLevelLow; 1874 uint8_t fcphHigh; 1875 uint8_t fcphLow; 1876 #else /* __LITTLE_ENDIAN_BITFIELD */ 1877 uint8_t fcphLow; 1878 uint8_t fcphHigh; 1879 uint8_t feaLevelLow; 1880 uint8_t feaLevelHigh; 1881 #endif 1882 1883 uint32_t postKernRev; 1884 uint32_t opFwRev; 1885 uint8_t opFwName[16]; 1886 uint32_t sli1FwRev; 1887 uint8_t sli1FwName[16]; 1888 uint32_t sli2FwRev; 1889 uint8_t sli2FwName[16]; 1890 uint32_t rsvd2; 1891 uint32_t RandomData[7]; 1892 } READ_REV_VAR; 1893 1894 /* Structure for MB Command READ_LINK_STAT (18) */ 1895 1896 typedef struct { 1897 uint32_t rsvd1; 1898 uint32_t linkFailureCnt; 1899 uint32_t lossSyncCnt; 1900 1901 uint32_t lossSignalCnt; 1902 uint32_t primSeqErrCnt; 1903 uint32_t invalidXmitWord; 1904 uint32_t crcCnt; 1905 uint32_t primSeqTimeout; 1906 uint32_t elasticOverrun; 1907 uint32_t arbTimeout; 1908 } READ_LNK_VAR; 1909 1910 /* Structure for MB Command REG_LOGIN (19) */ 1911 /* Structure for MB Command REG_LOGIN64 (0x93) */ 1912 1913 typedef struct { 1914 #ifdef __BIG_ENDIAN_BITFIELD 1915 uint16_t rsvd1; 1916 uint16_t rpi; 1917 uint32_t rsvd2:8; 1918 uint32_t did:24; 1919 #else /* __LITTLE_ENDIAN_BITFIELD */ 1920 uint16_t rpi; 1921 uint16_t rsvd1; 1922 uint32_t did:24; 1923 uint32_t rsvd2:8; 1924 #endif 1925 1926 union { 1927 struct ulp_bde sp; 1928 struct ulp_bde64 sp64; 1929 } un; 1930 1931 } REG_LOGIN_VAR; 1932 1933 /* Word 30 contents for REG_LOGIN */ 1934 typedef union { 1935 struct { 1936 #ifdef __BIG_ENDIAN_BITFIELD 1937 uint16_t rsvd1:12; 1938 uint16_t wd30_class:4; 1939 uint16_t xri; 1940 #else /* __LITTLE_ENDIAN_BITFIELD */ 1941 uint16_t xri; 1942 uint16_t wd30_class:4; 1943 uint16_t rsvd1:12; 1944 #endif 1945 } f; 1946 uint32_t word; 1947 } REG_WD30; 1948 1949 /* Structure for MB Command UNREG_LOGIN (20) */ 1950 1951 typedef struct { 1952 #ifdef __BIG_ENDIAN_BITFIELD 1953 uint16_t rsvd1; 1954 uint16_t rpi; 1955 #else /* __LITTLE_ENDIAN_BITFIELD */ 1956 uint16_t rpi; 1957 uint16_t rsvd1; 1958 #endif 1959 } UNREG_LOGIN_VAR; 1960 1961 /* Structure for MB Command UNREG_D_ID (0x23) */ 1962 1963 typedef struct { 1964 uint32_t did; 1965 } UNREG_D_ID_VAR; 1966 1967 /* Structure for MB Command READ_LA (21) */ 1968 /* Structure for MB Command READ_LA64 (0x95) */ 1969 1970 typedef struct { 1971 uint32_t eventTag; /* Event tag */ 1972 #ifdef __BIG_ENDIAN_BITFIELD 1973 uint32_t rsvd1:22; 1974 uint32_t pb:1; 1975 uint32_t il:1; 1976 uint32_t attType:8; 1977 #else /* __LITTLE_ENDIAN_BITFIELD */ 1978 uint32_t attType:8; 1979 uint32_t il:1; 1980 uint32_t pb:1; 1981 uint32_t rsvd1:22; 1982 #endif 1983 1984 #define AT_RESERVED 0x00 /* Reserved - attType */ 1985 #define AT_LINK_UP 0x01 /* Link is up */ 1986 #define AT_LINK_DOWN 0x02 /* Link is down */ 1987 1988 #ifdef __BIG_ENDIAN_BITFIELD 1989 uint8_t granted_AL_PA; 1990 uint8_t lipAlPs; 1991 uint8_t lipType; 1992 uint8_t topology; 1993 #else /* __LITTLE_ENDIAN_BITFIELD */ 1994 uint8_t topology; 1995 uint8_t lipType; 1996 uint8_t lipAlPs; 1997 uint8_t granted_AL_PA; 1998 #endif 1999 2000 #define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 2001 #define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 2002 2003 union { 2004 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer 2005 to */ 2006 /* store the LILP AL_PA position map into */ 2007 struct ulp_bde64 lilpBde64; 2008 } un; 2009 2010 #ifdef __BIG_ENDIAN_BITFIELD 2011 uint32_t Dlu:1; 2012 uint32_t Dtf:1; 2013 uint32_t Drsvd2:14; 2014 uint32_t DlnkSpeed:8; 2015 uint32_t DnlPort:4; 2016 uint32_t Dtx:2; 2017 uint32_t Drx:2; 2018 #else /* __LITTLE_ENDIAN_BITFIELD */ 2019 uint32_t Drx:2; 2020 uint32_t Dtx:2; 2021 uint32_t DnlPort:4; 2022 uint32_t DlnkSpeed:8; 2023 uint32_t Drsvd2:14; 2024 uint32_t Dtf:1; 2025 uint32_t Dlu:1; 2026 #endif 2027 2028 #ifdef __BIG_ENDIAN_BITFIELD 2029 uint32_t Ulu:1; 2030 uint32_t Utf:1; 2031 uint32_t Ursvd2:14; 2032 uint32_t UlnkSpeed:8; 2033 uint32_t UnlPort:4; 2034 uint32_t Utx:2; 2035 uint32_t Urx:2; 2036 #else /* __LITTLE_ENDIAN_BITFIELD */ 2037 uint32_t Urx:2; 2038 uint32_t Utx:2; 2039 uint32_t UnlPort:4; 2040 uint32_t UlnkSpeed:8; 2041 uint32_t Ursvd2:14; 2042 uint32_t Utf:1; 2043 uint32_t Ulu:1; 2044 #endif 2045 2046 #define LA_UNKNW_LINK 0x0 /* lnkSpeed */ 2047 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */ 2048 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */ 2049 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */ 2050 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */ 2051 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */ 2052 2053 } READ_LA_VAR; 2054 2055 /* Structure for MB Command CLEAR_LA (22) */ 2056 2057 typedef struct { 2058 uint32_t eventTag; /* Event tag */ 2059 uint32_t rsvd1; 2060 } CLEAR_LA_VAR; 2061 2062 /* Structure for MB Command DUMP */ 2063 2064 typedef struct { 2065 #ifdef __BIG_ENDIAN_BITFIELD 2066 uint32_t rsvd:25; 2067 uint32_t ra:1; 2068 uint32_t co:1; 2069 uint32_t cv:1; 2070 uint32_t type:4; 2071 uint32_t entry_index:16; 2072 uint32_t region_id:16; 2073 #else /* __LITTLE_ENDIAN_BITFIELD */ 2074 uint32_t type:4; 2075 uint32_t cv:1; 2076 uint32_t co:1; 2077 uint32_t ra:1; 2078 uint32_t rsvd:25; 2079 uint32_t region_id:16; 2080 uint32_t entry_index:16; 2081 #endif 2082 2083 uint32_t rsvd1; 2084 uint32_t word_cnt; 2085 uint32_t resp_offset; 2086 } DUMP_VAR; 2087 2088 #define DMP_MEM_REG 0x1 2089 #define DMP_NV_PARAMS 0x2 2090 2091 #define DMP_REGION_VPD 0xe 2092 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 2093 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 2094 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 2095 2096 /* Structure for MB Command CONFIG_PORT (0x88) */ 2097 2098 typedef struct { 2099 uint32_t pcbLen; 2100 uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 2101 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 2102 uint32_t hbainit[5]; 2103 } CONFIG_PORT_VAR; 2104 2105 /* SLI-2 Port Control Block */ 2106 2107 /* SLIM POINTER */ 2108 #define SLIMOFF 0x30 /* WORD */ 2109 2110 typedef struct _SLI2_RDSC { 2111 uint32_t cmdEntries; 2112 uint32_t cmdAddrLow; 2113 uint32_t cmdAddrHigh; 2114 2115 uint32_t rspEntries; 2116 uint32_t rspAddrLow; 2117 uint32_t rspAddrHigh; 2118 } SLI2_RDSC; 2119 2120 typedef struct _PCB { 2121 #ifdef __BIG_ENDIAN_BITFIELD 2122 uint32_t type:8; 2123 #define TYPE_NATIVE_SLI2 0x01; 2124 uint32_t feature:8; 2125 #define FEATURE_INITIAL_SLI2 0x01; 2126 uint32_t rsvd:12; 2127 uint32_t maxRing:4; 2128 #else /* __LITTLE_ENDIAN_BITFIELD */ 2129 uint32_t maxRing:4; 2130 uint32_t rsvd:12; 2131 uint32_t feature:8; 2132 #define FEATURE_INITIAL_SLI2 0x01; 2133 uint32_t type:8; 2134 #define TYPE_NATIVE_SLI2 0x01; 2135 #endif 2136 2137 uint32_t mailBoxSize; 2138 uint32_t mbAddrLow; 2139 uint32_t mbAddrHigh; 2140 2141 uint32_t hgpAddrLow; 2142 uint32_t hgpAddrHigh; 2143 2144 uint32_t pgpAddrLow; 2145 uint32_t pgpAddrHigh; 2146 SLI2_RDSC rdsc[MAX_RINGS]; 2147 } PCB_t; 2148 2149 /* NEW_FEATURE */ 2150 typedef struct { 2151 #ifdef __BIG_ENDIAN_BITFIELD 2152 uint32_t rsvd0:27; 2153 uint32_t discardFarp:1; 2154 uint32_t IPEnable:1; 2155 uint32_t nodeName:1; 2156 uint32_t portName:1; 2157 uint32_t filterEnable:1; 2158 #else /* __LITTLE_ENDIAN_BITFIELD */ 2159 uint32_t filterEnable:1; 2160 uint32_t portName:1; 2161 uint32_t nodeName:1; 2162 uint32_t IPEnable:1; 2163 uint32_t discardFarp:1; 2164 uint32_t rsvd:27; 2165 #endif 2166 2167 uint8_t portname[8]; /* Used to be struct lpfc_name */ 2168 uint8_t nodename[8]; 2169 uint32_t rsvd1; 2170 uint32_t rsvd2; 2171 uint32_t rsvd3; 2172 uint32_t IPAddress; 2173 } CONFIG_FARP_VAR; 2174 2175 /* Union of all Mailbox Command types */ 2176 #define MAILBOX_CMD_WSIZE 32 2177 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 2178 2179 typedef union { 2180 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; 2181 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 2182 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 2183 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 2184 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 2185 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 2186 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 2187 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 2188 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 2189 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 2190 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 2191 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 2192 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 2193 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 2194 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 2195 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 2196 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 2197 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 2198 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 2199 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 2200 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 2201 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */ 2202 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 2203 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 2204 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 2205 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) NEW_FEATURE */ 2206 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 2207 } MAILVARIANTS; 2208 2209 /* 2210 * SLI-2 specific structures 2211 */ 2212 2213 struct lpfc_hgp { 2214 __le32 cmdPutInx; 2215 __le32 rspGetInx; 2216 }; 2217 2218 struct lpfc_pgp { 2219 __le32 cmdGetInx; 2220 __le32 rspPutInx; 2221 }; 2222 2223 typedef struct _SLI2_DESC { 2224 struct lpfc_hgp host[MAX_RINGS]; 2225 uint32_t unused1[16]; 2226 struct lpfc_pgp port[MAX_RINGS]; 2227 } SLI2_DESC; 2228 2229 typedef union { 2230 SLI2_DESC s2; 2231 } SLI_VAR; 2232 2233 typedef struct { 2234 #ifdef __BIG_ENDIAN_BITFIELD 2235 uint16_t mbxStatus; 2236 uint8_t mbxCommand; 2237 uint8_t mbxReserved:6; 2238 uint8_t mbxHc:1; 2239 uint8_t mbxOwner:1; /* Low order bit first word */ 2240 #else /* __LITTLE_ENDIAN_BITFIELD */ 2241 uint8_t mbxOwner:1; /* Low order bit first word */ 2242 uint8_t mbxHc:1; 2243 uint8_t mbxReserved:6; 2244 uint8_t mbxCommand; 2245 uint16_t mbxStatus; 2246 #endif 2247 2248 MAILVARIANTS un; 2249 SLI_VAR us; 2250 } MAILBOX_t; 2251 2252 /* 2253 * Begin Structure Definitions for IOCB Commands 2254 */ 2255 2256 typedef struct { 2257 #ifdef __BIG_ENDIAN_BITFIELD 2258 uint8_t statAction; 2259 uint8_t statRsn; 2260 uint8_t statBaExp; 2261 uint8_t statLocalError; 2262 #else /* __LITTLE_ENDIAN_BITFIELD */ 2263 uint8_t statLocalError; 2264 uint8_t statBaExp; 2265 uint8_t statRsn; 2266 uint8_t statAction; 2267 #endif 2268 /* statRsn P/F_RJT reason codes */ 2269 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 2270 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 2271 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 2272 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 2273 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 2274 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 2275 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 2276 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 2277 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 2278 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 2279 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 2280 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 2281 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 2282 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 2283 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 2284 #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 2285 #define RJT_XCHG_ERR 0x11 /* Exchange error */ 2286 #define RJT_PROT_ERR 0x12 /* Protocol error */ 2287 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 2288 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 2289 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 2290 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 2291 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 2292 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 2293 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 2294 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 2295 2296 #define IOERR_SUCCESS 0x00 /* statLocalError */ 2297 #define IOERR_MISSING_CONTINUE 0x01 2298 #define IOERR_SEQUENCE_TIMEOUT 0x02 2299 #define IOERR_INTERNAL_ERROR 0x03 2300 #define IOERR_INVALID_RPI 0x04 2301 #define IOERR_NO_XRI 0x05 2302 #define IOERR_ILLEGAL_COMMAND 0x06 2303 #define IOERR_XCHG_DROPPED 0x07 2304 #define IOERR_ILLEGAL_FIELD 0x08 2305 #define IOERR_BAD_CONTINUE 0x09 2306 #define IOERR_TOO_MANY_BUFFERS 0x0A 2307 #define IOERR_RCV_BUFFER_WAITING 0x0B 2308 #define IOERR_NO_CONNECTION 0x0C 2309 #define IOERR_TX_DMA_FAILED 0x0D 2310 #define IOERR_RX_DMA_FAILED 0x0E 2311 #define IOERR_ILLEGAL_FRAME 0x0F 2312 #define IOERR_EXTRA_DATA 0x10 2313 #define IOERR_NO_RESOURCES 0x11 2314 #define IOERR_RESERVED 0x12 2315 #define IOERR_ILLEGAL_LENGTH 0x13 2316 #define IOERR_UNSUPPORTED_FEATURE 0x14 2317 #define IOERR_ABORT_IN_PROGRESS 0x15 2318 #define IOERR_ABORT_REQUESTED 0x16 2319 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 2320 #define IOERR_LOOP_OPEN_FAILURE 0x18 2321 #define IOERR_RING_RESET 0x19 2322 #define IOERR_LINK_DOWN 0x1A 2323 #define IOERR_CORRUPTED_DATA 0x1B 2324 #define IOERR_CORRUPTED_RPI 0x1C 2325 #define IOERR_OUT_OF_ORDER_DATA 0x1D 2326 #define IOERR_OUT_OF_ORDER_ACK 0x1E 2327 #define IOERR_DUP_FRAME 0x1F 2328 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 2329 #define IOERR_BAD_HOST_ADDRESS 0x21 2330 #define IOERR_RCV_HDRBUF_WAITING 0x22 2331 #define IOERR_MISSING_HDR_BUFFER 0x23 2332 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 2333 #define IOERR_ABORTMULT_REQUESTED 0x25 2334 #define IOERR_BUFFER_SHORTAGE 0x28 2335 #define IOERR_DEFAULT 0x29 2336 #define IOERR_CNT 0x2A 2337 2338 #define IOERR_DRVR_MASK 0x100 2339 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 2340 #define IOERR_SLI_BRESET 0x102 2341 #define IOERR_SLI_ABORTED 0x103 2342 } PARM_ERR; 2343 2344 typedef union { 2345 struct { 2346 #ifdef __BIG_ENDIAN_BITFIELD 2347 uint8_t Rctl; /* R_CTL field */ 2348 uint8_t Type; /* TYPE field */ 2349 uint8_t Dfctl; /* DF_CTL field */ 2350 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 2351 #else /* __LITTLE_ENDIAN_BITFIELD */ 2352 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 2353 uint8_t Dfctl; /* DF_CTL field */ 2354 uint8_t Type; /* TYPE field */ 2355 uint8_t Rctl; /* R_CTL field */ 2356 #endif 2357 2358 #define BC 0x02 /* Broadcast Received - Fctl */ 2359 #define SI 0x04 /* Sequence Initiative */ 2360 #define LA 0x08 /* Ignore Link Attention state */ 2361 #define LS 0x80 /* Last Sequence */ 2362 } hcsw; 2363 uint32_t reserved; 2364 } WORD5; 2365 2366 /* IOCB Command template for a generic response */ 2367 typedef struct { 2368 uint32_t reserved[4]; 2369 PARM_ERR perr; 2370 } GENERIC_RSP; 2371 2372 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 2373 typedef struct { 2374 struct ulp_bde xrsqbde[2]; 2375 uint32_t xrsqRo; /* Starting Relative Offset */ 2376 WORD5 w5; /* Header control/status word */ 2377 } XR_SEQ_FIELDS; 2378 2379 /* IOCB Command template for ELS_REQUEST */ 2380 typedef struct { 2381 struct ulp_bde elsReq; 2382 struct ulp_bde elsRsp; 2383 2384 #ifdef __BIG_ENDIAN_BITFIELD 2385 uint32_t word4Rsvd:7; 2386 uint32_t fl:1; 2387 uint32_t myID:24; 2388 uint32_t word5Rsvd:8; 2389 uint32_t remoteID:24; 2390 #else /* __LITTLE_ENDIAN_BITFIELD */ 2391 uint32_t myID:24; 2392 uint32_t fl:1; 2393 uint32_t word4Rsvd:7; 2394 uint32_t remoteID:24; 2395 uint32_t word5Rsvd:8; 2396 #endif 2397 } ELS_REQUEST; 2398 2399 /* IOCB Command template for RCV_ELS_REQ */ 2400 typedef struct { 2401 struct ulp_bde elsReq[2]; 2402 uint32_t parmRo; 2403 2404 #ifdef __BIG_ENDIAN_BITFIELD 2405 uint32_t word5Rsvd:8; 2406 uint32_t remoteID:24; 2407 #else /* __LITTLE_ENDIAN_BITFIELD */ 2408 uint32_t remoteID:24; 2409 uint32_t word5Rsvd:8; 2410 #endif 2411 } RCV_ELS_REQ; 2412 2413 /* IOCB Command template for ABORT / CLOSE_XRI */ 2414 typedef struct { 2415 uint32_t rsvd[3]; 2416 uint32_t abortType; 2417 #define ABORT_TYPE_ABTX 0x00000000 2418 #define ABORT_TYPE_ABTS 0x00000001 2419 uint32_t parm; 2420 #ifdef __BIG_ENDIAN_BITFIELD 2421 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 2422 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 2423 #else /* __LITTLE_ENDIAN_BITFIELD */ 2424 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 2425 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 2426 #endif 2427 } AC_XRI; 2428 2429 /* IOCB Command template for ABORT_MXRI64 */ 2430 typedef struct { 2431 uint32_t rsvd[3]; 2432 uint32_t abortType; 2433 uint32_t parm; 2434 uint32_t iotag32; 2435 } A_MXRI64; 2436 2437 /* IOCB Command template for GET_RPI */ 2438 typedef struct { 2439 uint32_t rsvd[4]; 2440 uint32_t parmRo; 2441 #ifdef __BIG_ENDIAN_BITFIELD 2442 uint32_t word5Rsvd:8; 2443 uint32_t remoteID:24; 2444 #else /* __LITTLE_ENDIAN_BITFIELD */ 2445 uint32_t remoteID:24; 2446 uint32_t word5Rsvd:8; 2447 #endif 2448 } GET_RPI; 2449 2450 /* IOCB Command template for all FCP Initiator commands */ 2451 typedef struct { 2452 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 2453 struct ulp_bde fcpi_rsp; /* Rcv buffer */ 2454 uint32_t fcpi_parm; 2455 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 2456 } FCPI_FIELDS; 2457 2458 /* IOCB Command template for all FCP Target commands */ 2459 typedef struct { 2460 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 2461 uint32_t fcpt_Offset; 2462 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 2463 } FCPT_FIELDS; 2464 2465 /* SLI-2 IOCB structure definitions */ 2466 2467 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 2468 typedef struct { 2469 ULP_BDL bdl; 2470 uint32_t xrsqRo; /* Starting Relative Offset */ 2471 WORD5 w5; /* Header control/status word */ 2472 } XMT_SEQ_FIELDS64; 2473 2474 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 2475 typedef struct { 2476 struct ulp_bde64 rcvBde; 2477 uint32_t rsvd1; 2478 uint32_t xrsqRo; /* Starting Relative Offset */ 2479 WORD5 w5; /* Header control/status word */ 2480 } RCV_SEQ_FIELDS64; 2481 2482 /* IOCB Command template for ELS_REQUEST64 */ 2483 typedef struct { 2484 ULP_BDL bdl; 2485 #ifdef __BIG_ENDIAN_BITFIELD 2486 uint32_t word4Rsvd:7; 2487 uint32_t fl:1; 2488 uint32_t myID:24; 2489 uint32_t word5Rsvd:8; 2490 uint32_t remoteID:24; 2491 #else /* __LITTLE_ENDIAN_BITFIELD */ 2492 uint32_t myID:24; 2493 uint32_t fl:1; 2494 uint32_t word4Rsvd:7; 2495 uint32_t remoteID:24; 2496 uint32_t word5Rsvd:8; 2497 #endif 2498 } ELS_REQUEST64; 2499 2500 /* IOCB Command template for GEN_REQUEST64 */ 2501 typedef struct { 2502 ULP_BDL bdl; 2503 uint32_t xrsqRo; /* Starting Relative Offset */ 2504 WORD5 w5; /* Header control/status word */ 2505 } GEN_REQUEST64; 2506 2507 /* IOCB Command template for RCV_ELS_REQ64 */ 2508 typedef struct { 2509 struct ulp_bde64 elsReq; 2510 uint32_t rcvd1; 2511 uint32_t parmRo; 2512 2513 #ifdef __BIG_ENDIAN_BITFIELD 2514 uint32_t word5Rsvd:8; 2515 uint32_t remoteID:24; 2516 #else /* __LITTLE_ENDIAN_BITFIELD */ 2517 uint32_t remoteID:24; 2518 uint32_t word5Rsvd:8; 2519 #endif 2520 } RCV_ELS_REQ64; 2521 2522 /* IOCB Command template for all 64 bit FCP Initiator commands */ 2523 typedef struct { 2524 ULP_BDL bdl; 2525 uint32_t fcpi_parm; 2526 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 2527 } FCPI_FIELDS64; 2528 2529 /* IOCB Command template for all 64 bit FCP Target commands */ 2530 typedef struct { 2531 ULP_BDL bdl; 2532 uint32_t fcpt_Offset; 2533 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 2534 } FCPT_FIELDS64; 2535 2536 typedef struct _IOCB { /* IOCB structure */ 2537 union { 2538 GENERIC_RSP grsp; /* Generic response */ 2539 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 2540 struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 2541 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 2542 AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 2543 A_MXRI64 amxri; /* abort multiple xri command overlay */ 2544 GET_RPI getrpi; /* GET_RPI template */ 2545 FCPI_FIELDS fcpi; /* FCP Initiator template */ 2546 FCPT_FIELDS fcpt; /* FCP target template */ 2547 2548 /* SLI-2 structures */ 2549 2550 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 2551 bde_64s */ 2552 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 2553 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 2554 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 2555 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 2556 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 2557 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 2558 2559 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 2560 } un; 2561 union { 2562 struct { 2563 #ifdef __BIG_ENDIAN_BITFIELD 2564 uint16_t ulpContext; /* High order bits word 6 */ 2565 uint16_t ulpIoTag; /* Low order bits word 6 */ 2566 #else /* __LITTLE_ENDIAN_BITFIELD */ 2567 uint16_t ulpIoTag; /* Low order bits word 6 */ 2568 uint16_t ulpContext; /* High order bits word 6 */ 2569 #endif 2570 } t1; 2571 struct { 2572 #ifdef __BIG_ENDIAN_BITFIELD 2573 uint16_t ulpContext; /* High order bits word 6 */ 2574 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 2575 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 2576 #else /* __LITTLE_ENDIAN_BITFIELD */ 2577 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 2578 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 2579 uint16_t ulpContext; /* High order bits word 6 */ 2580 #endif 2581 } t2; 2582 } un1; 2583 #define ulpContext un1.t1.ulpContext 2584 #define ulpIoTag un1.t1.ulpIoTag 2585 #define ulpIoTag0 un1.t2.ulpIoTag0 2586 2587 #ifdef __BIG_ENDIAN_BITFIELD 2588 uint32_t ulpTimeout:8; 2589 uint32_t ulpXS:1; 2590 uint32_t ulpFCP2Rcvy:1; 2591 uint32_t ulpPU:2; 2592 uint32_t ulpIr:1; 2593 uint32_t ulpClass:3; 2594 uint32_t ulpCommand:8; 2595 uint32_t ulpStatus:4; 2596 uint32_t ulpBdeCount:2; 2597 uint32_t ulpLe:1; 2598 uint32_t ulpOwner:1; /* Low order bit word 7 */ 2599 #else /* __LITTLE_ENDIAN_BITFIELD */ 2600 uint32_t ulpOwner:1; /* Low order bit word 7 */ 2601 uint32_t ulpLe:1; 2602 uint32_t ulpBdeCount:2; 2603 uint32_t ulpStatus:4; 2604 uint32_t ulpCommand:8; 2605 uint32_t ulpClass:3; 2606 uint32_t ulpIr:1; 2607 uint32_t ulpPU:2; 2608 uint32_t ulpFCP2Rcvy:1; 2609 uint32_t ulpXS:1; 2610 uint32_t ulpTimeout:8; 2611 #endif 2612 2613 #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 2614 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 2615 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 2616 #define CLASS1 0 /* Class 1 */ 2617 #define CLASS2 1 /* Class 2 */ 2618 #define CLASS3 2 /* Class 3 */ 2619 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 2620 2621 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 2622 #define IOSTAT_FCP_RSP_ERROR 0x1 2623 #define IOSTAT_REMOTE_STOP 0x2 2624 #define IOSTAT_LOCAL_REJECT 0x3 2625 #define IOSTAT_NPORT_RJT 0x4 2626 #define IOSTAT_FABRIC_RJT 0x5 2627 #define IOSTAT_NPORT_BSY 0x6 2628 #define IOSTAT_FABRIC_BSY 0x7 2629 #define IOSTAT_INTERMED_RSP 0x8 2630 #define IOSTAT_LS_RJT 0x9 2631 #define IOSTAT_BA_RJT 0xA 2632 #define IOSTAT_RSVD1 0xB 2633 #define IOSTAT_RSVD2 0xC 2634 #define IOSTAT_RSVD3 0xD 2635 #define IOSTAT_RSVD4 0xE 2636 #define IOSTAT_RSVD5 0xF 2637 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 2638 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 2639 #define IOSTAT_CNT 0x11 2640 2641 } IOCB_t; 2642 2643 2644 #define SLI1_SLIM_SIZE (4 * 1024) 2645 2646 /* Up to 498 IOCBs will fit into 16k 2647 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 2648 */ 2649 #define SLI2_SLIM_SIZE (16 * 1024) 2650 2651 /* Maximum IOCBs that will fit in SLI2 slim */ 2652 #define MAX_SLI2_IOCB 498 2653 2654 struct lpfc_sli2_slim { 2655 MAILBOX_t mbx; 2656 PCB_t pcb; 2657 IOCB_t IOCBs[MAX_SLI2_IOCB]; 2658 }; 2659 2660 /******************************************************************* 2661 This macro check PCI device to allow special handling for LC HBAs. 2662 2663 Parameters: 2664 device : struct pci_dev 's device field 2665 2666 return 1 => TRUE 2667 0 => FALSE 2668 *******************************************************************/ 2669 static inline int 2670 lpfc_is_LC_HBA(unsigned short device) 2671 { 2672 if ((device == PCI_DEVICE_ID_TFLY) || 2673 (device == PCI_DEVICE_ID_PFLY) || 2674 (device == PCI_DEVICE_ID_LP101) || 2675 (device == PCI_DEVICE_ID_BMID) || 2676 (device == PCI_DEVICE_ID_BSMB) || 2677 (device == PCI_DEVICE_ID_ZMID) || 2678 (device == PCI_DEVICE_ID_ZSMB) || 2679 (device == PCI_DEVICE_ID_RFLY)) 2680 return 1; 2681 else 2682 return 0; 2683 } 2684