1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2025 Arm Ltd. 3 4 #ifndef MPAM_INTERNAL_H 5 #define MPAM_INTERNAL_H 6 7 #include <linux/arm_mpam.h> 8 #include <linux/cpumask.h> 9 #include <linux/io.h> 10 #include <linux/llist.h> 11 #include <linux/mutex.h> 12 #include <linux/srcu.h> 13 #include <linux/spinlock.h> 14 #include <linux/types.h> 15 16 #define MPAM_MSC_MAX_NUM_RIS 16 17 18 struct platform_device; 19 20 /* 21 * Structures protected by SRCU may not be freed for a surprising amount of 22 * time (especially if perf is running). To ensure the MPAM error interrupt can 23 * tear down all the structures, build a list of objects that can be garbage 24 * collected once synchronize_srcu() has returned. 25 * If pdev is non-NULL, use devm_kfree(). 26 */ 27 struct mpam_garbage { 28 /* member of mpam_garbage */ 29 struct llist_node llist; 30 31 void *to_free; 32 struct platform_device *pdev; 33 }; 34 35 struct mpam_msc { 36 /* member of mpam_all_msc */ 37 struct list_head all_msc_list; 38 39 int id; 40 struct platform_device *pdev; 41 42 /* Not modified after mpam_is_enabled() becomes true */ 43 enum mpam_msc_iface iface; 44 u32 nrdy_usec; 45 cpumask_t accessibility; 46 47 /* 48 * probe_lock is only taken during discovery. After discovery these 49 * properties become read-only and the lists are protected by SRCU. 50 */ 51 struct mutex probe_lock; 52 bool probed; 53 u16 partid_max; 54 u8 pmg_max; 55 unsigned long ris_idxs; 56 u32 ris_max; 57 58 /* mpam_msc_ris of this component */ 59 struct list_head ris; 60 61 /* 62 * part_sel_lock protects access to the MSC hardware registers that are 63 * affected by MPAMCFG_PART_SEL. (including the ID registers that vary 64 * by RIS). 65 * If needed, take msc->probe_lock first. 66 */ 67 struct mutex part_sel_lock; 68 69 /* 70 * mon_sel_lock protects access to the MSC hardware registers that are 71 * affected by MPAMCFG_MON_SEL, and the mbwu_state. 72 * Access to mon_sel is needed from both process and interrupt contexts, 73 * but is complicated by firmware-backed platforms that can't make any 74 * access unless they can sleep. 75 * Always use the mpam_mon_sel_lock() helpers. 76 * Accesses to mon_sel need to be able to fail if they occur in the wrong 77 * context. 78 * If needed, take msc->probe_lock first. 79 */ 80 raw_spinlock_t _mon_sel_lock; 81 unsigned long _mon_sel_flags; 82 83 void __iomem *mapped_hwpage; 84 size_t mapped_hwpage_sz; 85 86 struct mpam_garbage garbage; 87 }; 88 89 /* Returning false here means accesses to mon_sel must fail and report an error. */ 90 static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc) 91 { 92 /* Locking will require updating to support a firmware backed interface */ 93 if (WARN_ON_ONCE(msc->iface != MPAM_IFACE_MMIO)) 94 return false; 95 96 raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags); 97 return true; 98 } 99 100 static inline void mpam_mon_sel_unlock(struct mpam_msc *msc) 101 { 102 raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags); 103 } 104 105 static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc) 106 { 107 lockdep_assert_held_once(&msc->_mon_sel_lock); 108 } 109 110 static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc) 111 { 112 raw_spin_lock_init(&msc->_mon_sel_lock); 113 } 114 115 struct mpam_class { 116 /* mpam_components in this class */ 117 struct list_head components; 118 119 cpumask_t affinity; 120 121 u8 level; 122 enum mpam_class_types type; 123 124 /* member of mpam_classes */ 125 struct list_head classes_list; 126 127 struct mpam_garbage garbage; 128 }; 129 130 struct mpam_component { 131 u32 comp_id; 132 133 /* mpam_vmsc in this component */ 134 struct list_head vmsc; 135 136 cpumask_t affinity; 137 138 /* member of mpam_class:components */ 139 struct list_head class_list; 140 141 /* parent: */ 142 struct mpam_class *class; 143 144 struct mpam_garbage garbage; 145 }; 146 147 struct mpam_vmsc { 148 /* member of mpam_component:vmsc_list */ 149 struct list_head comp_list; 150 151 /* mpam_msc_ris in this vmsc */ 152 struct list_head ris; 153 154 /* All RIS in this vMSC are members of this MSC */ 155 struct mpam_msc *msc; 156 157 /* parent: */ 158 struct mpam_component *comp; 159 160 struct mpam_garbage garbage; 161 }; 162 163 struct mpam_msc_ris { 164 u8 ris_idx; 165 166 cpumask_t affinity; 167 168 /* member of mpam_vmsc:ris */ 169 struct list_head vmsc_list; 170 171 /* member of mpam_msc:ris */ 172 struct list_head msc_list; 173 174 /* parent: */ 175 struct mpam_vmsc *vmsc; 176 177 struct mpam_garbage garbage; 178 }; 179 180 /* List of all classes - protected by srcu*/ 181 extern struct srcu_struct mpam_srcu; 182 extern struct list_head mpam_classes; 183 184 /* System wide partid/pmg values */ 185 extern u16 mpam_partid_max; 186 extern u8 mpam_pmg_max; 187 188 /* Scheduled work callback to enable mpam once all MSC have been probed */ 189 void mpam_enable(struct work_struct *work); 190 void mpam_disable(struct work_struct *work); 191 192 int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, 193 cpumask_t *affinity); 194 195 /* 196 * MPAM MSCs have the following register layout. See: 197 * Arm Memory System Resource Partitioning and Monitoring (MPAM) System 198 * Component Specification. 199 * https://developer.arm.com/documentation/ihi0099/aa/ 200 */ 201 #define MPAM_ARCHITECTURE_V1 0x10 202 203 /* Memory mapped control pages */ 204 /* ID Register offsets in the memory mapped page */ 205 #define MPAMF_IDR 0x0000 /* features id register */ 206 #define MPAMF_IIDR 0x0018 /* implementer id register */ 207 #define MPAMF_AIDR 0x0020 /* architectural id register */ 208 #define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */ 209 #define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */ 210 #define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */ 211 #define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */ 212 #define MPAMF_PRI_IDR 0x0048 /* priority partitioning */ 213 #define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */ 214 #define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */ 215 #define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */ 216 #define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */ 217 218 /* Configuration and Status Register offsets in the memory mapped page */ 219 #define MPAMCFG_PART_SEL 0x0100 /* partid to configure */ 220 #define MPAMCFG_CPBM 0x1000 /* cache-portion config */ 221 #define MPAMCFG_CMAX 0x0108 /* cache-capacity config */ 222 #define MPAMCFG_CMIN 0x0110 /* cache-capacity config */ 223 #define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */ 224 #define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */ 225 #define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */ 226 #define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */ 227 #define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */ 228 #define MPAMCFG_PRI 0x0400 /* priority partitioning config */ 229 #define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */ 230 #define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */ 231 232 #define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */ 233 #define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */ 234 #define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */ 235 #define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */ 236 #define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */ 237 #define MSMON_CSU 0x0840 /* current cache-usage */ 238 #define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */ 239 #define MSMON_MBWU 0x0860 /* current mem-bw usage value */ 240 #define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */ 241 #define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */ 242 #define MSMON_MBWU_L_CAPTURE 0x0890 /* last long mem-bw value captured */ 243 #define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */ 244 #define MPAMF_ESR 0x00F8 /* error status register */ 245 #define MPAMF_ECR 0x00F0 /* error control register */ 246 247 /* MPAMF_IDR - MPAM features ID register */ 248 #define MPAMF_IDR_PARTID_MAX GENMASK(15, 0) 249 #define MPAMF_IDR_PMG_MAX GENMASK(23, 16) 250 #define MPAMF_IDR_HAS_CCAP_PART BIT(24) 251 #define MPAMF_IDR_HAS_CPOR_PART BIT(25) 252 #define MPAMF_IDR_HAS_MBW_PART BIT(26) 253 #define MPAMF_IDR_HAS_PRI_PART BIT(27) 254 #define MPAMF_IDR_EXT BIT(28) 255 #define MPAMF_IDR_HAS_IMPL_IDR BIT(29) 256 #define MPAMF_IDR_HAS_MSMON BIT(30) 257 #define MPAMF_IDR_HAS_PARTID_NRW BIT(31) 258 #define MPAMF_IDR_HAS_RIS BIT(32) 259 #define MPAMF_IDR_HAS_EXTD_ESR BIT(38) 260 #define MPAMF_IDR_HAS_ESR BIT(39) 261 #define MPAMF_IDR_RIS_MAX GENMASK(59, 56) 262 263 /* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */ 264 #define MPAMF_MSMON_IDR_MSMON_CSU BIT(16) 265 #define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17) 266 #define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31) 267 268 /* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */ 269 #define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0) 270 271 /* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */ 272 #define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0) 273 #define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8) 274 #define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28) 275 #define MPAMF_CCAP_IDR_HAS_CMIN BIT(29) 276 #define MPAMF_CCAP_IDR_NO_CMAX BIT(30) 277 #define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31) 278 279 /* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */ 280 #define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0) 281 #define MPAMF_MBW_IDR_HAS_MIN BIT(10) 282 #define MPAMF_MBW_IDR_HAS_MAX BIT(11) 283 #define MPAMF_MBW_IDR_HAS_PBM BIT(12) 284 #define MPAMF_MBW_IDR_HAS_PROP BIT(13) 285 #define MPAMF_MBW_IDR_WINDWR BIT(14) 286 #define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16) 287 288 /* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */ 289 #define MPAMF_PRI_IDR_HAS_INTPRI BIT(0) 290 #define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1) 291 #define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4) 292 #define MPAMF_PRI_IDR_HAS_DSPRI BIT(16) 293 #define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17) 294 #define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20) 295 296 /* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */ 297 #define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0) 298 #define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24) 299 #define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25) 300 #define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26) 301 #define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27) 302 #define MPAMF_CSUMON_IDR_HAS_XCL BIT(29) 303 #define MPAMF_CSUMON_IDR_CSU_RO BIT(30) 304 #define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31) 305 306 /* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */ 307 #define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0) 308 #define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28) 309 #define MPAMF_MBWUMON_IDR_LWD BIT(29) 310 #define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30) 311 #define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31) 312 313 /* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */ 314 #define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0) 315 316 /* MPAMF_IIDR - MPAM implementation ID register */ 317 #define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0) 318 #define MPAMF_IIDR_REVISION GENMASK(15, 12) 319 #define MPAMF_IIDR_VARIANT GENMASK(19, 16) 320 #define MPAMF_IIDR_PRODUCTID GENMASK(31, 20) 321 322 /* MPAMF_AIDR - MPAM architecture ID register */ 323 #define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0) 324 #define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4) 325 326 /* MPAMCFG_PART_SEL - MPAM partition configuration selection register */ 327 #define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0) 328 #define MPAMCFG_PART_SEL_INTERNAL BIT(16) 329 #define MPAMCFG_PART_SEL_RIS GENMASK(27, 24) 330 331 /* MPAMCFG_CASSOC - MPAM cache maximum associativity partition configuration register */ 332 #define MPAMCFG_CASSOC_CASSOC GENMASK(15, 0) 333 334 /* MPAMCFG_CMAX - MPAM cache capacity configuration register */ 335 #define MPAMCFG_CMAX_SOFTLIM BIT(31) 336 #define MPAMCFG_CMAX_CMAX GENMASK(15, 0) 337 338 /* MPAMCFG_CMIN - MPAM cache capacity configuration register */ 339 #define MPAMCFG_CMIN_CMIN GENMASK(15, 0) 340 341 /* 342 * MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configuration 343 * register 344 */ 345 #define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0) 346 347 /* 348 * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration 349 * register 350 */ 351 #define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0) 352 #define MPAMCFG_MBW_MAX_HARDLIM BIT(31) 353 354 /* 355 * MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width 356 * register 357 */ 358 #define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0) 359 #define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8) 360 361 /* MPAMCFG_PRI - MPAM priority partitioning configuration register */ 362 #define MPAMCFG_PRI_INTPRI GENMASK(15, 0) 363 #define MPAMCFG_PRI_DSPRI GENMASK(31, 16) 364 365 /* 366 * MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning 367 * configuration register 368 */ 369 #define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0) 370 #define MPAMCFG_MBW_PROP_EN BIT(31) 371 372 /* 373 * MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration register 374 */ 375 #define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0) 376 #define MPAMCFG_INTPARTID_INTERNAL BIT(16) 377 378 /* MSMON_CFG_MON_SEL - Memory system performance monitor selection register */ 379 #define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0) 380 #define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24) 381 382 /* MPAMF_ESR - MPAM Error Status Register */ 383 #define MPAMF_ESR_PARTID_MON GENMASK(15, 0) 384 #define MPAMF_ESR_PMG GENMASK(23, 16) 385 #define MPAMF_ESR_ERRCODE GENMASK(27, 24) 386 #define MPAMF_ESR_OVRWR BIT(31) 387 #define MPAMF_ESR_RIS GENMASK(35, 32) 388 389 /* MPAMF_ECR - MPAM Error Control Register */ 390 #define MPAMF_ECR_INTEN BIT(0) 391 392 /* Error conditions in accessing memory mapped registers */ 393 #define MPAM_ERRCODE_NONE 0 394 #define MPAM_ERRCODE_PARTID_SEL_RANGE 1 395 #define MPAM_ERRCODE_REQ_PARTID_RANGE 2 396 #define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3 397 #define MPAM_ERRCODE_REQ_PMG_RANGE 4 398 #define MPAM_ERRCODE_MONITOR_RANGE 5 399 #define MPAM_ERRCODE_INTPARTID_RANGE 6 400 #define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7 401 #define MPAM_ERRCODE_UNDEFINED_RIS_PART_SEL 8 402 #define MPAM_ERRCODE_RIS_NO_CONTROL 9 403 #define MPAM_ERRCODE_UNDEFINED_RIS_MON_SEL 10 404 #define MPAM_ERRCODE_RIS_NO_MONITOR 11 405 406 /* 407 * MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache storage 408 * usage monitor control register 409 * MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory 410 * bandwidth usage monitor control register 411 */ 412 #define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0) 413 #define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L BIT(15) 414 #define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16) 415 #define MSMON_CFG_x_CTL_MATCH_PMG BIT(17) 416 #define MSMON_CFG_MBWU_CTL_SCLEN BIT(19) 417 #define MSMON_CFG_x_CTL_SUBTYPE GENMASK(22, 20) 418 #define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24) 419 #define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25) 420 #define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26) 421 #define MSMON_CFG_x_CTL_CAPT_RESET BIT(27) 422 #define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28) 423 #define MSMON_CFG_x_CTL_EN BIT(31) 424 425 #define MSMON_CFG_MBWU_CTL_TYPE_MBWU 0x42 426 #define MSMON_CFG_CSU_CTL_TYPE_CSU 0x43 427 428 /* 429 * MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage 430 * usage monitor filter register 431 * MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory 432 * bandwidth usage monitor filter register 433 */ 434 #define MSMON_CFG_x_FLT_PARTID GENMASK(15, 0) 435 #define MSMON_CFG_x_FLT_PMG GENMASK(23, 16) 436 437 #define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30) 438 #define MSMON_CFG_CSU_FLT_XCL BIT(31) 439 440 /* 441 * MSMON_CSU - Memory system performance monitor cache storage usage monitor 442 * register 443 * MSMON_CSU_CAPTURE - Memory system performance monitor cache storage usage 444 * capture register 445 * MSMON_MBWU - Memory system performance monitor memory bandwidth usage 446 * monitor register 447 * MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage 448 * capture register 449 */ 450 #define MSMON___VALUE GENMASK(30, 0) 451 #define MSMON___NRDY BIT(31) 452 #define MSMON___L_NRDY BIT(63) 453 #define MSMON___L_VALUE GENMASK(43, 0) 454 #define MSMON___LWD_VALUE GENMASK(62, 0) 455 456 /* 457 * MSMON_CAPT_EVNT - Memory system performance monitoring capture event 458 * generation register 459 */ 460 #define MSMON_CAPT_EVNT_NOW BIT(0) 461 462 #endif /* MPAM_INTERNAL_H */ 463