1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2025 Arm Ltd. 3 4 #ifndef MPAM_INTERNAL_H 5 #define MPAM_INTERNAL_H 6 7 #include <linux/arm_mpam.h> 8 #include <linux/atomic.h> 9 #include <linux/bitmap.h> 10 #include <linux/cpumask.h> 11 #include <linux/io.h> 12 #include <linux/jump_label.h> 13 #include <linux/llist.h> 14 #include <linux/mutex.h> 15 #include <linux/srcu.h> 16 #include <linux/spinlock.h> 17 #include <linux/srcu.h> 18 #include <linux/types.h> 19 20 #define MPAM_MSC_MAX_NUM_RIS 16 21 22 struct platform_device; 23 24 DECLARE_STATIC_KEY_FALSE(mpam_enabled); 25 26 static inline bool mpam_is_enabled(void) 27 { 28 return static_branch_likely(&mpam_enabled); 29 } 30 31 /* 32 * Structures protected by SRCU may not be freed for a surprising amount of 33 * time (especially if perf is running). To ensure the MPAM error interrupt can 34 * tear down all the structures, build a list of objects that can be garbage 35 * collected once synchronize_srcu() has returned. 36 * If pdev is non-NULL, use devm_kfree(). 37 */ 38 struct mpam_garbage { 39 /* member of mpam_garbage */ 40 struct llist_node llist; 41 42 void *to_free; 43 struct platform_device *pdev; 44 }; 45 46 struct mpam_msc { 47 /* member of mpam_all_msc */ 48 struct list_head all_msc_list; 49 50 int id; 51 struct platform_device *pdev; 52 53 /* Not modified after mpam_is_enabled() becomes true */ 54 enum mpam_msc_iface iface; 55 u32 nrdy_usec; 56 cpumask_t accessibility; 57 bool has_extd_esr; 58 59 int reenable_error_ppi; 60 struct mpam_msc * __percpu *error_dev_id; 61 62 atomic_t online_refs; 63 64 /* 65 * probe_lock is only taken during discovery. After discovery these 66 * properties become read-only and the lists are protected by SRCU. 67 */ 68 struct mutex probe_lock; 69 bool probed; 70 u16 partid_max; 71 u8 pmg_max; 72 unsigned long ris_idxs; 73 u32 ris_max; 74 75 /* 76 * error_irq_lock is taken when registering/unregistering the error 77 * interrupt and maniupulating the below flags. 78 */ 79 struct mutex error_irq_lock; 80 bool error_irq_req; 81 bool error_irq_hw_enabled; 82 83 /* mpam_msc_ris of this component */ 84 struct list_head ris; 85 86 /* 87 * part_sel_lock protects access to the MSC hardware registers that are 88 * affected by MPAMCFG_PART_SEL. (including the ID registers that vary 89 * by RIS). 90 * If needed, take msc->probe_lock first. 91 */ 92 struct mutex part_sel_lock; 93 94 /* cfg_lock protects the msc configuration. */ 95 struct mutex cfg_lock; 96 97 /* 98 * mon_sel_lock protects access to the MSC hardware registers that are 99 * affected by MPAMCFG_MON_SEL, and the mbwu_state. 100 * Access to mon_sel is needed from both process and interrupt contexts, 101 * but is complicated by firmware-backed platforms that can't make any 102 * access unless they can sleep. 103 * Always use the mpam_mon_sel_lock() helpers. 104 * Accesses to mon_sel need to be able to fail if they occur in the wrong 105 * context. 106 * If needed, take msc->probe_lock first. 107 */ 108 raw_spinlock_t _mon_sel_lock; 109 unsigned long _mon_sel_flags; 110 111 void __iomem *mapped_hwpage; 112 size_t mapped_hwpage_sz; 113 114 struct mpam_garbage garbage; 115 }; 116 117 /* Returning false here means accesses to mon_sel must fail and report an error. */ 118 static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc) 119 { 120 /* Locking will require updating to support a firmware backed interface */ 121 if (WARN_ON_ONCE(msc->iface != MPAM_IFACE_MMIO)) 122 return false; 123 124 raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags); 125 return true; 126 } 127 128 static inline void mpam_mon_sel_unlock(struct mpam_msc *msc) 129 { 130 raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags); 131 } 132 133 static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc) 134 { 135 lockdep_assert_held_once(&msc->_mon_sel_lock); 136 } 137 138 static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc) 139 { 140 raw_spin_lock_init(&msc->_mon_sel_lock); 141 } 142 143 /* Bits for mpam features bitmaps */ 144 enum mpam_device_features { 145 mpam_feat_cpor_part, 146 mpam_feat_cmax_softlim, 147 mpam_feat_cmax_cmax, 148 mpam_feat_cmax_cmin, 149 mpam_feat_cmax_cassoc, 150 mpam_feat_mbw_part, 151 mpam_feat_mbw_min, 152 mpam_feat_mbw_max, 153 mpam_feat_mbw_prop, 154 mpam_feat_intpri_part, 155 mpam_feat_intpri_part_0_low, 156 mpam_feat_dspri_part, 157 mpam_feat_dspri_part_0_low, 158 mpam_feat_msmon, 159 mpam_feat_msmon_csu, 160 mpam_feat_msmon_csu_capture, 161 mpam_feat_msmon_csu_xcl, 162 mpam_feat_msmon_csu_hw_nrdy, 163 mpam_feat_msmon_mbwu, 164 mpam_feat_msmon_mbwu_capture, 165 mpam_feat_msmon_mbwu_rwbw, 166 mpam_feat_msmon_mbwu_hw_nrdy, 167 mpam_feat_partid_nrw, 168 MPAM_FEATURE_LAST 169 }; 170 171 struct mpam_props { 172 DECLARE_BITMAP(features, MPAM_FEATURE_LAST); 173 174 u16 cpbm_wd; 175 u16 mbw_pbm_bits; 176 u16 bwa_wd; 177 u16 cmax_wd; 178 u16 cassoc_wd; 179 u16 intpri_wd; 180 u16 dspri_wd; 181 u16 num_csu_mon; 182 u16 num_mbwu_mon; 183 }; 184 185 #define mpam_has_feature(_feat, x) test_bit(_feat, (x)->features) 186 #define mpam_set_feature(_feat, x) set_bit(_feat, (x)->features) 187 #define mpam_clear_feature(_feat, x) clear_bit(_feat, (x)->features) 188 189 struct mpam_class { 190 /* mpam_components in this class */ 191 struct list_head components; 192 193 cpumask_t affinity; 194 195 struct mpam_props props; 196 u32 nrdy_usec; 197 u8 level; 198 enum mpam_class_types type; 199 200 /* member of mpam_classes */ 201 struct list_head classes_list; 202 203 struct ida ida_csu_mon; 204 struct ida ida_mbwu_mon; 205 206 struct mpam_garbage garbage; 207 }; 208 209 struct mpam_config { 210 /* Which configuration values are valid. */ 211 DECLARE_BITMAP(features, MPAM_FEATURE_LAST); 212 213 u32 cpbm; 214 u32 mbw_pbm; 215 u16 mbw_max; 216 217 bool reset_cpbm; 218 bool reset_mbw_pbm; 219 bool reset_mbw_max; 220 221 struct mpam_garbage garbage; 222 }; 223 224 struct mpam_component { 225 u32 comp_id; 226 227 /* mpam_vmsc in this component */ 228 struct list_head vmsc; 229 230 cpumask_t affinity; 231 232 /* 233 * Array of configuration values, indexed by partid. 234 * Read from cpuhp callbacks, hold the cpuhp lock when writing. 235 */ 236 struct mpam_config *cfg; 237 238 /* member of mpam_class:components */ 239 struct list_head class_list; 240 241 /* parent: */ 242 struct mpam_class *class; 243 244 struct mpam_garbage garbage; 245 }; 246 247 struct mpam_vmsc { 248 /* member of mpam_component:vmsc_list */ 249 struct list_head comp_list; 250 251 /* mpam_msc_ris in this vmsc */ 252 struct list_head ris; 253 254 struct mpam_props props; 255 256 /* All RIS in this vMSC are members of this MSC */ 257 struct mpam_msc *msc; 258 259 /* parent: */ 260 struct mpam_component *comp; 261 262 struct mpam_garbage garbage; 263 }; 264 265 struct mpam_msc_ris { 266 u8 ris_idx; 267 u64 idr; 268 struct mpam_props props; 269 bool in_reset_state; 270 271 cpumask_t affinity; 272 273 /* member of mpam_vmsc:ris */ 274 struct list_head vmsc_list; 275 276 /* member of mpam_msc:ris */ 277 struct list_head msc_list; 278 279 /* parent: */ 280 struct mpam_vmsc *vmsc; 281 282 struct mpam_garbage garbage; 283 }; 284 285 static inline int mpam_alloc_csu_mon(struct mpam_class *class) 286 { 287 struct mpam_props *cprops = &class->props; 288 289 if (!mpam_has_feature(mpam_feat_msmon_csu, cprops)) 290 return -EOPNOTSUPP; 291 292 return ida_alloc_max(&class->ida_csu_mon, cprops->num_csu_mon - 1, 293 GFP_KERNEL); 294 } 295 296 static inline void mpam_free_csu_mon(struct mpam_class *class, int csu_mon) 297 { 298 ida_free(&class->ida_csu_mon, csu_mon); 299 } 300 301 static inline int mpam_alloc_mbwu_mon(struct mpam_class *class) 302 { 303 struct mpam_props *cprops = &class->props; 304 305 if (!mpam_has_feature(mpam_feat_msmon_mbwu, cprops)) 306 return -EOPNOTSUPP; 307 308 return ida_alloc_max(&class->ida_mbwu_mon, cprops->num_mbwu_mon - 1, 309 GFP_KERNEL); 310 } 311 312 static inline void mpam_free_mbwu_mon(struct mpam_class *class, int mbwu_mon) 313 { 314 ida_free(&class->ida_mbwu_mon, mbwu_mon); 315 } 316 317 /* List of all classes - protected by srcu*/ 318 extern struct srcu_struct mpam_srcu; 319 extern struct list_head mpam_classes; 320 321 /* System wide partid/pmg values */ 322 extern u16 mpam_partid_max; 323 extern u8 mpam_pmg_max; 324 325 /* Scheduled work callback to enable mpam once all MSC have been probed */ 326 void mpam_enable(struct work_struct *work); 327 void mpam_disable(struct work_struct *work); 328 329 int mpam_apply_config(struct mpam_component *comp, u16 partid, 330 struct mpam_config *cfg); 331 332 int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, 333 cpumask_t *affinity); 334 335 /* 336 * MPAM MSCs have the following register layout. See: 337 * Arm Memory System Resource Partitioning and Monitoring (MPAM) System 338 * Component Specification. 339 * https://developer.arm.com/documentation/ihi0099/aa/ 340 */ 341 #define MPAM_ARCHITECTURE_V1 0x10 342 343 /* Memory mapped control pages */ 344 /* ID Register offsets in the memory mapped page */ 345 #define MPAMF_IDR 0x0000 /* features id register */ 346 #define MPAMF_IIDR 0x0018 /* implementer id register */ 347 #define MPAMF_AIDR 0x0020 /* architectural id register */ 348 #define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */ 349 #define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */ 350 #define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */ 351 #define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */ 352 #define MPAMF_PRI_IDR 0x0048 /* priority partitioning */ 353 #define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */ 354 #define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */ 355 #define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */ 356 #define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */ 357 358 /* Configuration and Status Register offsets in the memory mapped page */ 359 #define MPAMCFG_PART_SEL 0x0100 /* partid to configure */ 360 #define MPAMCFG_CPBM 0x1000 /* cache-portion config */ 361 #define MPAMCFG_CMAX 0x0108 /* cache-capacity config */ 362 #define MPAMCFG_CMIN 0x0110 /* cache-capacity config */ 363 #define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */ 364 #define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */ 365 #define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */ 366 #define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */ 367 #define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */ 368 #define MPAMCFG_PRI 0x0400 /* priority partitioning config */ 369 #define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */ 370 #define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */ 371 372 #define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */ 373 #define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */ 374 #define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */ 375 #define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */ 376 #define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */ 377 #define MSMON_CSU 0x0840 /* current cache-usage */ 378 #define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */ 379 #define MSMON_MBWU 0x0860 /* current mem-bw usage value */ 380 #define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */ 381 #define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */ 382 #define MSMON_MBWU_L_CAPTURE 0x0890 /* last long mem-bw value captured */ 383 #define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */ 384 #define MPAMF_ESR 0x00F8 /* error status register */ 385 #define MPAMF_ECR 0x00F0 /* error control register */ 386 387 /* MPAMF_IDR - MPAM features ID register */ 388 #define MPAMF_IDR_PARTID_MAX GENMASK(15, 0) 389 #define MPAMF_IDR_PMG_MAX GENMASK(23, 16) 390 #define MPAMF_IDR_HAS_CCAP_PART BIT(24) 391 #define MPAMF_IDR_HAS_CPOR_PART BIT(25) 392 #define MPAMF_IDR_HAS_MBW_PART BIT(26) 393 #define MPAMF_IDR_HAS_PRI_PART BIT(27) 394 #define MPAMF_IDR_EXT BIT(28) 395 #define MPAMF_IDR_HAS_IMPL_IDR BIT(29) 396 #define MPAMF_IDR_HAS_MSMON BIT(30) 397 #define MPAMF_IDR_HAS_PARTID_NRW BIT(31) 398 #define MPAMF_IDR_HAS_RIS BIT(32) 399 #define MPAMF_IDR_HAS_EXTD_ESR BIT(38) 400 #define MPAMF_IDR_HAS_ESR BIT(39) 401 #define MPAMF_IDR_RIS_MAX GENMASK(59, 56) 402 403 /* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */ 404 #define MPAMF_MSMON_IDR_MSMON_CSU BIT(16) 405 #define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17) 406 #define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31) 407 408 /* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */ 409 #define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0) 410 411 /* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */ 412 #define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0) 413 #define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8) 414 #define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28) 415 #define MPAMF_CCAP_IDR_HAS_CMIN BIT(29) 416 #define MPAMF_CCAP_IDR_NO_CMAX BIT(30) 417 #define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31) 418 419 /* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */ 420 #define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0) 421 #define MPAMF_MBW_IDR_HAS_MIN BIT(10) 422 #define MPAMF_MBW_IDR_HAS_MAX BIT(11) 423 #define MPAMF_MBW_IDR_HAS_PBM BIT(12) 424 #define MPAMF_MBW_IDR_HAS_PROP BIT(13) 425 #define MPAMF_MBW_IDR_WINDWR BIT(14) 426 #define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16) 427 428 /* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */ 429 #define MPAMF_PRI_IDR_HAS_INTPRI BIT(0) 430 #define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1) 431 #define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4) 432 #define MPAMF_PRI_IDR_HAS_DSPRI BIT(16) 433 #define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17) 434 #define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20) 435 436 /* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */ 437 #define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0) 438 #define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24) 439 #define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25) 440 #define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26) 441 #define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27) 442 #define MPAMF_CSUMON_IDR_HAS_XCL BIT(29) 443 #define MPAMF_CSUMON_IDR_CSU_RO BIT(30) 444 #define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31) 445 446 /* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */ 447 #define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0) 448 #define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28) 449 #define MPAMF_MBWUMON_IDR_LWD BIT(29) 450 #define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30) 451 #define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31) 452 453 /* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */ 454 #define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0) 455 456 /* MPAMF_IIDR - MPAM implementation ID register */ 457 #define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0) 458 #define MPAMF_IIDR_REVISION GENMASK(15, 12) 459 #define MPAMF_IIDR_VARIANT GENMASK(19, 16) 460 #define MPAMF_IIDR_PRODUCTID GENMASK(31, 20) 461 462 /* MPAMF_AIDR - MPAM architecture ID register */ 463 #define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0) 464 #define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4) 465 466 /* MPAMCFG_PART_SEL - MPAM partition configuration selection register */ 467 #define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0) 468 #define MPAMCFG_PART_SEL_INTERNAL BIT(16) 469 #define MPAMCFG_PART_SEL_RIS GENMASK(27, 24) 470 471 /* MPAMCFG_CASSOC - MPAM cache maximum associativity partition configuration register */ 472 #define MPAMCFG_CASSOC_CASSOC GENMASK(15, 0) 473 474 /* MPAMCFG_CMAX - MPAM cache capacity configuration register */ 475 #define MPAMCFG_CMAX_SOFTLIM BIT(31) 476 #define MPAMCFG_CMAX_CMAX GENMASK(15, 0) 477 478 /* MPAMCFG_CMIN - MPAM cache capacity configuration register */ 479 #define MPAMCFG_CMIN_CMIN GENMASK(15, 0) 480 481 /* 482 * MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configuration 483 * register 484 */ 485 #define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0) 486 487 /* 488 * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration 489 * register 490 */ 491 #define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0) 492 #define MPAMCFG_MBW_MAX_HARDLIM BIT(31) 493 494 /* 495 * MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width 496 * register 497 */ 498 #define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0) 499 #define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8) 500 501 /* MPAMCFG_PRI - MPAM priority partitioning configuration register */ 502 #define MPAMCFG_PRI_INTPRI GENMASK(15, 0) 503 #define MPAMCFG_PRI_DSPRI GENMASK(31, 16) 504 505 /* 506 * MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning 507 * configuration register 508 */ 509 #define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0) 510 #define MPAMCFG_MBW_PROP_EN BIT(31) 511 512 /* 513 * MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration register 514 */ 515 #define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0) 516 #define MPAMCFG_INTPARTID_INTERNAL BIT(16) 517 518 /* MSMON_CFG_MON_SEL - Memory system performance monitor selection register */ 519 #define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0) 520 #define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24) 521 522 /* MPAMF_ESR - MPAM Error Status Register */ 523 #define MPAMF_ESR_PARTID_MON GENMASK(15, 0) 524 #define MPAMF_ESR_PMG GENMASK(23, 16) 525 #define MPAMF_ESR_ERRCODE GENMASK(27, 24) 526 #define MPAMF_ESR_OVRWR BIT(31) 527 #define MPAMF_ESR_RIS GENMASK(35, 32) 528 529 /* MPAMF_ECR - MPAM Error Control Register */ 530 #define MPAMF_ECR_INTEN BIT(0) 531 532 /* Error conditions in accessing memory mapped registers */ 533 #define MPAM_ERRCODE_NONE 0 534 #define MPAM_ERRCODE_PARTID_SEL_RANGE 1 535 #define MPAM_ERRCODE_REQ_PARTID_RANGE 2 536 #define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3 537 #define MPAM_ERRCODE_REQ_PMG_RANGE 4 538 #define MPAM_ERRCODE_MONITOR_RANGE 5 539 #define MPAM_ERRCODE_INTPARTID_RANGE 6 540 #define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7 541 #define MPAM_ERRCODE_UNDEFINED_RIS_PART_SEL 8 542 #define MPAM_ERRCODE_RIS_NO_CONTROL 9 543 #define MPAM_ERRCODE_UNDEFINED_RIS_MON_SEL 10 544 #define MPAM_ERRCODE_RIS_NO_MONITOR 11 545 546 /* 547 * MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache storage 548 * usage monitor control register 549 * MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory 550 * bandwidth usage monitor control register 551 */ 552 #define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0) 553 #define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L BIT(15) 554 #define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16) 555 #define MSMON_CFG_x_CTL_MATCH_PMG BIT(17) 556 #define MSMON_CFG_MBWU_CTL_SCLEN BIT(19) 557 #define MSMON_CFG_x_CTL_SUBTYPE GENMASK(22, 20) 558 #define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24) 559 #define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25) 560 #define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26) 561 #define MSMON_CFG_x_CTL_CAPT_RESET BIT(27) 562 #define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28) 563 #define MSMON_CFG_x_CTL_EN BIT(31) 564 565 #define MSMON_CFG_MBWU_CTL_TYPE_MBWU 0x42 566 #define MSMON_CFG_CSU_CTL_TYPE_CSU 0x43 567 568 /* 569 * MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage 570 * usage monitor filter register 571 * MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory 572 * bandwidth usage monitor filter register 573 */ 574 #define MSMON_CFG_x_FLT_PARTID GENMASK(15, 0) 575 #define MSMON_CFG_x_FLT_PMG GENMASK(23, 16) 576 577 #define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30) 578 #define MSMON_CFG_CSU_FLT_XCL BIT(31) 579 580 /* 581 * MSMON_CSU - Memory system performance monitor cache storage usage monitor 582 * register 583 * MSMON_CSU_CAPTURE - Memory system performance monitor cache storage usage 584 * capture register 585 * MSMON_MBWU - Memory system performance monitor memory bandwidth usage 586 * monitor register 587 * MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage 588 * capture register 589 */ 590 #define MSMON___VALUE GENMASK(30, 0) 591 #define MSMON___NRDY BIT(31) 592 #define MSMON___L_NRDY BIT(63) 593 #define MSMON___L_VALUE GENMASK(43, 0) 594 #define MSMON___LWD_VALUE GENMASK(62, 0) 595 596 /* 597 * MSMON_CAPT_EVNT - Memory system performance monitoring capture event 598 * generation register 599 */ 600 #define MSMON_CAPT_EVNT_NOW BIT(0) 601 602 #endif /* MPAM_INTERNAL_H */ 603