1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2025 Arm Ltd. 3 4 #ifndef MPAM_INTERNAL_H 5 #define MPAM_INTERNAL_H 6 7 #include <linux/arm_mpam.h> 8 #include <linux/atomic.h> 9 #include <linux/bitmap.h> 10 #include <linux/cpumask.h> 11 #include <linux/io.h> 12 #include <linux/llist.h> 13 #include <linux/mutex.h> 14 #include <linux/srcu.h> 15 #include <linux/spinlock.h> 16 #include <linux/srcu.h> 17 #include <linux/types.h> 18 19 #define MPAM_MSC_MAX_NUM_RIS 16 20 21 struct platform_device; 22 23 /* 24 * Structures protected by SRCU may not be freed for a surprising amount of 25 * time (especially if perf is running). To ensure the MPAM error interrupt can 26 * tear down all the structures, build a list of objects that can be garbage 27 * collected once synchronize_srcu() has returned. 28 * If pdev is non-NULL, use devm_kfree(). 29 */ 30 struct mpam_garbage { 31 /* member of mpam_garbage */ 32 struct llist_node llist; 33 34 void *to_free; 35 struct platform_device *pdev; 36 }; 37 38 struct mpam_msc { 39 /* member of mpam_all_msc */ 40 struct list_head all_msc_list; 41 42 int id; 43 struct platform_device *pdev; 44 45 /* Not modified after mpam_is_enabled() becomes true */ 46 enum mpam_msc_iface iface; 47 u32 nrdy_usec; 48 cpumask_t accessibility; 49 bool has_extd_esr; 50 51 int reenable_error_ppi; 52 struct mpam_msc * __percpu *error_dev_id; 53 54 atomic_t online_refs; 55 56 /* 57 * probe_lock is only taken during discovery. After discovery these 58 * properties become read-only and the lists are protected by SRCU. 59 */ 60 struct mutex probe_lock; 61 bool probed; 62 u16 partid_max; 63 u8 pmg_max; 64 unsigned long ris_idxs; 65 u32 ris_max; 66 67 /* 68 * error_irq_lock is taken when registering/unregistering the error 69 * interrupt and maniupulating the below flags. 70 */ 71 struct mutex error_irq_lock; 72 bool error_irq_req; 73 bool error_irq_hw_enabled; 74 75 /* mpam_msc_ris of this component */ 76 struct list_head ris; 77 78 /* 79 * part_sel_lock protects access to the MSC hardware registers that are 80 * affected by MPAMCFG_PART_SEL. (including the ID registers that vary 81 * by RIS). 82 * If needed, take msc->probe_lock first. 83 */ 84 struct mutex part_sel_lock; 85 86 /* 87 * mon_sel_lock protects access to the MSC hardware registers that are 88 * affected by MPAMCFG_MON_SEL, and the mbwu_state. 89 * Access to mon_sel is needed from both process and interrupt contexts, 90 * but is complicated by firmware-backed platforms that can't make any 91 * access unless they can sleep. 92 * Always use the mpam_mon_sel_lock() helpers. 93 * Accesses to mon_sel need to be able to fail if they occur in the wrong 94 * context. 95 * If needed, take msc->probe_lock first. 96 */ 97 raw_spinlock_t _mon_sel_lock; 98 unsigned long _mon_sel_flags; 99 100 void __iomem *mapped_hwpage; 101 size_t mapped_hwpage_sz; 102 103 struct mpam_garbage garbage; 104 }; 105 106 /* Returning false here means accesses to mon_sel must fail and report an error. */ 107 static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc) 108 { 109 /* Locking will require updating to support a firmware backed interface */ 110 if (WARN_ON_ONCE(msc->iface != MPAM_IFACE_MMIO)) 111 return false; 112 113 raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags); 114 return true; 115 } 116 117 static inline void mpam_mon_sel_unlock(struct mpam_msc *msc) 118 { 119 raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags); 120 } 121 122 static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc) 123 { 124 lockdep_assert_held_once(&msc->_mon_sel_lock); 125 } 126 127 static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc) 128 { 129 raw_spin_lock_init(&msc->_mon_sel_lock); 130 } 131 132 /* Bits for mpam features bitmaps */ 133 enum mpam_device_features { 134 mpam_feat_cpor_part, 135 mpam_feat_mbw_part, 136 mpam_feat_mbw_min, 137 mpam_feat_mbw_max, 138 mpam_feat_msmon, 139 mpam_feat_msmon_csu, 140 mpam_feat_msmon_csu_hw_nrdy, 141 mpam_feat_msmon_mbwu, 142 mpam_feat_msmon_mbwu_hw_nrdy, 143 MPAM_FEATURE_LAST 144 }; 145 146 struct mpam_props { 147 DECLARE_BITMAP(features, MPAM_FEATURE_LAST); 148 149 u16 cpbm_wd; 150 u16 mbw_pbm_bits; 151 u16 bwa_wd; 152 u16 num_csu_mon; 153 u16 num_mbwu_mon; 154 }; 155 156 #define mpam_has_feature(_feat, x) test_bit(_feat, (x)->features) 157 #define mpam_set_feature(_feat, x) set_bit(_feat, (x)->features) 158 #define mpam_clear_feature(_feat, x) clear_bit(_feat, (x)->features) 159 160 struct mpam_class { 161 /* mpam_components in this class */ 162 struct list_head components; 163 164 cpumask_t affinity; 165 166 struct mpam_props props; 167 u32 nrdy_usec; 168 u8 level; 169 enum mpam_class_types type; 170 171 /* member of mpam_classes */ 172 struct list_head classes_list; 173 174 struct mpam_garbage garbage; 175 }; 176 177 struct mpam_component { 178 u32 comp_id; 179 180 /* mpam_vmsc in this component */ 181 struct list_head vmsc; 182 183 cpumask_t affinity; 184 185 /* member of mpam_class:components */ 186 struct list_head class_list; 187 188 /* parent: */ 189 struct mpam_class *class; 190 191 struct mpam_garbage garbage; 192 }; 193 194 struct mpam_vmsc { 195 /* member of mpam_component:vmsc_list */ 196 struct list_head comp_list; 197 198 /* mpam_msc_ris in this vmsc */ 199 struct list_head ris; 200 201 struct mpam_props props; 202 203 /* All RIS in this vMSC are members of this MSC */ 204 struct mpam_msc *msc; 205 206 /* parent: */ 207 struct mpam_component *comp; 208 209 struct mpam_garbage garbage; 210 }; 211 212 struct mpam_msc_ris { 213 u8 ris_idx; 214 u64 idr; 215 struct mpam_props props; 216 bool in_reset_state; 217 218 cpumask_t affinity; 219 220 /* member of mpam_vmsc:ris */ 221 struct list_head vmsc_list; 222 223 /* member of mpam_msc:ris */ 224 struct list_head msc_list; 225 226 /* parent: */ 227 struct mpam_vmsc *vmsc; 228 229 struct mpam_garbage garbage; 230 }; 231 232 /* List of all classes - protected by srcu*/ 233 extern struct srcu_struct mpam_srcu; 234 extern struct list_head mpam_classes; 235 236 /* System wide partid/pmg values */ 237 extern u16 mpam_partid_max; 238 extern u8 mpam_pmg_max; 239 240 /* Scheduled work callback to enable mpam once all MSC have been probed */ 241 void mpam_enable(struct work_struct *work); 242 void mpam_disable(struct work_struct *work); 243 244 int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, 245 cpumask_t *affinity); 246 247 /* 248 * MPAM MSCs have the following register layout. See: 249 * Arm Memory System Resource Partitioning and Monitoring (MPAM) System 250 * Component Specification. 251 * https://developer.arm.com/documentation/ihi0099/aa/ 252 */ 253 #define MPAM_ARCHITECTURE_V1 0x10 254 255 /* Memory mapped control pages */ 256 /* ID Register offsets in the memory mapped page */ 257 #define MPAMF_IDR 0x0000 /* features id register */ 258 #define MPAMF_IIDR 0x0018 /* implementer id register */ 259 #define MPAMF_AIDR 0x0020 /* architectural id register */ 260 #define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */ 261 #define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */ 262 #define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */ 263 #define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */ 264 #define MPAMF_PRI_IDR 0x0048 /* priority partitioning */ 265 #define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */ 266 #define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */ 267 #define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */ 268 #define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */ 269 270 /* Configuration and Status Register offsets in the memory mapped page */ 271 #define MPAMCFG_PART_SEL 0x0100 /* partid to configure */ 272 #define MPAMCFG_CPBM 0x1000 /* cache-portion config */ 273 #define MPAMCFG_CMAX 0x0108 /* cache-capacity config */ 274 #define MPAMCFG_CMIN 0x0110 /* cache-capacity config */ 275 #define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */ 276 #define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */ 277 #define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */ 278 #define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */ 279 #define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */ 280 #define MPAMCFG_PRI 0x0400 /* priority partitioning config */ 281 #define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */ 282 #define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */ 283 284 #define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */ 285 #define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */ 286 #define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */ 287 #define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */ 288 #define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */ 289 #define MSMON_CSU 0x0840 /* current cache-usage */ 290 #define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */ 291 #define MSMON_MBWU 0x0860 /* current mem-bw usage value */ 292 #define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */ 293 #define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */ 294 #define MSMON_MBWU_L_CAPTURE 0x0890 /* last long mem-bw value captured */ 295 #define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */ 296 #define MPAMF_ESR 0x00F8 /* error status register */ 297 #define MPAMF_ECR 0x00F0 /* error control register */ 298 299 /* MPAMF_IDR - MPAM features ID register */ 300 #define MPAMF_IDR_PARTID_MAX GENMASK(15, 0) 301 #define MPAMF_IDR_PMG_MAX GENMASK(23, 16) 302 #define MPAMF_IDR_HAS_CCAP_PART BIT(24) 303 #define MPAMF_IDR_HAS_CPOR_PART BIT(25) 304 #define MPAMF_IDR_HAS_MBW_PART BIT(26) 305 #define MPAMF_IDR_HAS_PRI_PART BIT(27) 306 #define MPAMF_IDR_EXT BIT(28) 307 #define MPAMF_IDR_HAS_IMPL_IDR BIT(29) 308 #define MPAMF_IDR_HAS_MSMON BIT(30) 309 #define MPAMF_IDR_HAS_PARTID_NRW BIT(31) 310 #define MPAMF_IDR_HAS_RIS BIT(32) 311 #define MPAMF_IDR_HAS_EXTD_ESR BIT(38) 312 #define MPAMF_IDR_HAS_ESR BIT(39) 313 #define MPAMF_IDR_RIS_MAX GENMASK(59, 56) 314 315 /* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */ 316 #define MPAMF_MSMON_IDR_MSMON_CSU BIT(16) 317 #define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17) 318 #define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31) 319 320 /* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */ 321 #define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0) 322 323 /* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */ 324 #define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0) 325 #define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8) 326 #define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28) 327 #define MPAMF_CCAP_IDR_HAS_CMIN BIT(29) 328 #define MPAMF_CCAP_IDR_NO_CMAX BIT(30) 329 #define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31) 330 331 /* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */ 332 #define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0) 333 #define MPAMF_MBW_IDR_HAS_MIN BIT(10) 334 #define MPAMF_MBW_IDR_HAS_MAX BIT(11) 335 #define MPAMF_MBW_IDR_HAS_PBM BIT(12) 336 #define MPAMF_MBW_IDR_HAS_PROP BIT(13) 337 #define MPAMF_MBW_IDR_WINDWR BIT(14) 338 #define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16) 339 340 /* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */ 341 #define MPAMF_PRI_IDR_HAS_INTPRI BIT(0) 342 #define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1) 343 #define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4) 344 #define MPAMF_PRI_IDR_HAS_DSPRI BIT(16) 345 #define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17) 346 #define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20) 347 348 /* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */ 349 #define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0) 350 #define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24) 351 #define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25) 352 #define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26) 353 #define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27) 354 #define MPAMF_CSUMON_IDR_HAS_XCL BIT(29) 355 #define MPAMF_CSUMON_IDR_CSU_RO BIT(30) 356 #define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31) 357 358 /* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */ 359 #define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0) 360 #define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28) 361 #define MPAMF_MBWUMON_IDR_LWD BIT(29) 362 #define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30) 363 #define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31) 364 365 /* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */ 366 #define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0) 367 368 /* MPAMF_IIDR - MPAM implementation ID register */ 369 #define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0) 370 #define MPAMF_IIDR_REVISION GENMASK(15, 12) 371 #define MPAMF_IIDR_VARIANT GENMASK(19, 16) 372 #define MPAMF_IIDR_PRODUCTID GENMASK(31, 20) 373 374 /* MPAMF_AIDR - MPAM architecture ID register */ 375 #define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0) 376 #define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4) 377 378 /* MPAMCFG_PART_SEL - MPAM partition configuration selection register */ 379 #define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0) 380 #define MPAMCFG_PART_SEL_INTERNAL BIT(16) 381 #define MPAMCFG_PART_SEL_RIS GENMASK(27, 24) 382 383 /* MPAMCFG_CASSOC - MPAM cache maximum associativity partition configuration register */ 384 #define MPAMCFG_CASSOC_CASSOC GENMASK(15, 0) 385 386 /* MPAMCFG_CMAX - MPAM cache capacity configuration register */ 387 #define MPAMCFG_CMAX_SOFTLIM BIT(31) 388 #define MPAMCFG_CMAX_CMAX GENMASK(15, 0) 389 390 /* MPAMCFG_CMIN - MPAM cache capacity configuration register */ 391 #define MPAMCFG_CMIN_CMIN GENMASK(15, 0) 392 393 /* 394 * MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configuration 395 * register 396 */ 397 #define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0) 398 399 /* 400 * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration 401 * register 402 */ 403 #define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0) 404 #define MPAMCFG_MBW_MAX_HARDLIM BIT(31) 405 406 /* 407 * MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width 408 * register 409 */ 410 #define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0) 411 #define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8) 412 413 /* MPAMCFG_PRI - MPAM priority partitioning configuration register */ 414 #define MPAMCFG_PRI_INTPRI GENMASK(15, 0) 415 #define MPAMCFG_PRI_DSPRI GENMASK(31, 16) 416 417 /* 418 * MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning 419 * configuration register 420 */ 421 #define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0) 422 #define MPAMCFG_MBW_PROP_EN BIT(31) 423 424 /* 425 * MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration register 426 */ 427 #define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0) 428 #define MPAMCFG_INTPARTID_INTERNAL BIT(16) 429 430 /* MSMON_CFG_MON_SEL - Memory system performance monitor selection register */ 431 #define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0) 432 #define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24) 433 434 /* MPAMF_ESR - MPAM Error Status Register */ 435 #define MPAMF_ESR_PARTID_MON GENMASK(15, 0) 436 #define MPAMF_ESR_PMG GENMASK(23, 16) 437 #define MPAMF_ESR_ERRCODE GENMASK(27, 24) 438 #define MPAMF_ESR_OVRWR BIT(31) 439 #define MPAMF_ESR_RIS GENMASK(35, 32) 440 441 /* MPAMF_ECR - MPAM Error Control Register */ 442 #define MPAMF_ECR_INTEN BIT(0) 443 444 /* Error conditions in accessing memory mapped registers */ 445 #define MPAM_ERRCODE_NONE 0 446 #define MPAM_ERRCODE_PARTID_SEL_RANGE 1 447 #define MPAM_ERRCODE_REQ_PARTID_RANGE 2 448 #define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3 449 #define MPAM_ERRCODE_REQ_PMG_RANGE 4 450 #define MPAM_ERRCODE_MONITOR_RANGE 5 451 #define MPAM_ERRCODE_INTPARTID_RANGE 6 452 #define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7 453 #define MPAM_ERRCODE_UNDEFINED_RIS_PART_SEL 8 454 #define MPAM_ERRCODE_RIS_NO_CONTROL 9 455 #define MPAM_ERRCODE_UNDEFINED_RIS_MON_SEL 10 456 #define MPAM_ERRCODE_RIS_NO_MONITOR 11 457 458 /* 459 * MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache storage 460 * usage monitor control register 461 * MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory 462 * bandwidth usage monitor control register 463 */ 464 #define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0) 465 #define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L BIT(15) 466 #define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16) 467 #define MSMON_CFG_x_CTL_MATCH_PMG BIT(17) 468 #define MSMON_CFG_MBWU_CTL_SCLEN BIT(19) 469 #define MSMON_CFG_x_CTL_SUBTYPE GENMASK(22, 20) 470 #define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24) 471 #define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25) 472 #define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26) 473 #define MSMON_CFG_x_CTL_CAPT_RESET BIT(27) 474 #define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28) 475 #define MSMON_CFG_x_CTL_EN BIT(31) 476 477 #define MSMON_CFG_MBWU_CTL_TYPE_MBWU 0x42 478 #define MSMON_CFG_CSU_CTL_TYPE_CSU 0x43 479 480 /* 481 * MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage 482 * usage monitor filter register 483 * MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory 484 * bandwidth usage monitor filter register 485 */ 486 #define MSMON_CFG_x_FLT_PARTID GENMASK(15, 0) 487 #define MSMON_CFG_x_FLT_PMG GENMASK(23, 16) 488 489 #define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30) 490 #define MSMON_CFG_CSU_FLT_XCL BIT(31) 491 492 /* 493 * MSMON_CSU - Memory system performance monitor cache storage usage monitor 494 * register 495 * MSMON_CSU_CAPTURE - Memory system performance monitor cache storage usage 496 * capture register 497 * MSMON_MBWU - Memory system performance monitor memory bandwidth usage 498 * monitor register 499 * MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage 500 * capture register 501 */ 502 #define MSMON___VALUE GENMASK(30, 0) 503 #define MSMON___NRDY BIT(31) 504 #define MSMON___L_NRDY BIT(63) 505 #define MSMON___L_VALUE GENMASK(43, 0) 506 #define MSMON___LWD_VALUE GENMASK(62, 0) 507 508 /* 509 * MSMON_CAPT_EVNT - Memory system performance monitoring capture event 510 * generation register 511 */ 512 #define MSMON_CAPT_EVNT_NOW BIT(0) 513 514 #endif /* MPAM_INTERNAL_H */ 515