1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2025 Arm Ltd. 3 4 #ifndef MPAM_INTERNAL_H 5 #define MPAM_INTERNAL_H 6 7 #include <linux/arm_mpam.h> 8 #include <linux/atomic.h> 9 #include <linux/bitmap.h> 10 #include <linux/cpumask.h> 11 #include <linux/io.h> 12 #include <linux/jump_label.h> 13 #include <linux/llist.h> 14 #include <linux/mutex.h> 15 #include <linux/srcu.h> 16 #include <linux/spinlock.h> 17 #include <linux/srcu.h> 18 #include <linux/types.h> 19 20 #define MPAM_MSC_MAX_NUM_RIS 16 21 22 struct platform_device; 23 24 DECLARE_STATIC_KEY_FALSE(mpam_enabled); 25 26 static inline bool mpam_is_enabled(void) 27 { 28 return static_branch_likely(&mpam_enabled); 29 } 30 31 /* 32 * Structures protected by SRCU may not be freed for a surprising amount of 33 * time (especially if perf is running). To ensure the MPAM error interrupt can 34 * tear down all the structures, build a list of objects that can be garbage 35 * collected once synchronize_srcu() has returned. 36 * If pdev is non-NULL, use devm_kfree(). 37 */ 38 struct mpam_garbage { 39 /* member of mpam_garbage */ 40 struct llist_node llist; 41 42 void *to_free; 43 struct platform_device *pdev; 44 }; 45 46 struct mpam_msc { 47 /* member of mpam_all_msc */ 48 struct list_head all_msc_list; 49 50 int id; 51 struct platform_device *pdev; 52 53 /* Not modified after mpam_is_enabled() becomes true */ 54 enum mpam_msc_iface iface; 55 u32 nrdy_usec; 56 cpumask_t accessibility; 57 bool has_extd_esr; 58 59 int reenable_error_ppi; 60 struct mpam_msc * __percpu *error_dev_id; 61 62 atomic_t online_refs; 63 64 /* 65 * probe_lock is only taken during discovery. After discovery these 66 * properties become read-only and the lists are protected by SRCU. 67 */ 68 struct mutex probe_lock; 69 bool probed; 70 u16 partid_max; 71 u8 pmg_max; 72 unsigned long ris_idxs; 73 u32 ris_max; 74 75 /* 76 * error_irq_lock is taken when registering/unregistering the error 77 * interrupt and maniupulating the below flags. 78 */ 79 struct mutex error_irq_lock; 80 bool error_irq_req; 81 bool error_irq_hw_enabled; 82 83 /* mpam_msc_ris of this component */ 84 struct list_head ris; 85 86 /* 87 * part_sel_lock protects access to the MSC hardware registers that are 88 * affected by MPAMCFG_PART_SEL. (including the ID registers that vary 89 * by RIS). 90 * If needed, take msc->probe_lock first. 91 */ 92 struct mutex part_sel_lock; 93 94 /* 95 * cfg_lock protects the msc configuration and guards against mbwu_state 96 * save and restore racing. 97 */ 98 struct mutex cfg_lock; 99 100 /* 101 * mon_sel_lock protects access to the MSC hardware registers that are 102 * affected by MPAMCFG_MON_SEL, and the mbwu_state. 103 * Access to mon_sel is needed from both process and interrupt contexts, 104 * but is complicated by firmware-backed platforms that can't make any 105 * access unless they can sleep. 106 * Always use the mpam_mon_sel_lock() helpers. 107 * Accesses to mon_sel need to be able to fail if they occur in the wrong 108 * context. 109 * If needed, take msc->probe_lock first. 110 */ 111 raw_spinlock_t _mon_sel_lock; 112 unsigned long _mon_sel_flags; 113 114 void __iomem *mapped_hwpage; 115 size_t mapped_hwpage_sz; 116 117 struct mpam_garbage garbage; 118 }; 119 120 /* Returning false here means accesses to mon_sel must fail and report an error. */ 121 static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc) 122 { 123 /* Locking will require updating to support a firmware backed interface */ 124 if (WARN_ON_ONCE(msc->iface != MPAM_IFACE_MMIO)) 125 return false; 126 127 raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags); 128 return true; 129 } 130 131 static inline void mpam_mon_sel_unlock(struct mpam_msc *msc) 132 { 133 raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags); 134 } 135 136 static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc) 137 { 138 lockdep_assert_held_once(&msc->_mon_sel_lock); 139 } 140 141 static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc) 142 { 143 raw_spin_lock_init(&msc->_mon_sel_lock); 144 } 145 146 /* Bits for mpam features bitmaps */ 147 enum mpam_device_features { 148 mpam_feat_cpor_part, 149 mpam_feat_cmax_softlim, 150 mpam_feat_cmax_cmax, 151 mpam_feat_cmax_cmin, 152 mpam_feat_cmax_cassoc, 153 mpam_feat_mbw_part, 154 mpam_feat_mbw_min, 155 mpam_feat_mbw_max, 156 mpam_feat_mbw_prop, 157 mpam_feat_intpri_part, 158 mpam_feat_intpri_part_0_low, 159 mpam_feat_dspri_part, 160 mpam_feat_dspri_part_0_low, 161 mpam_feat_msmon, 162 mpam_feat_msmon_csu, 163 mpam_feat_msmon_csu_capture, 164 mpam_feat_msmon_csu_xcl, 165 mpam_feat_msmon_csu_hw_nrdy, 166 mpam_feat_msmon_mbwu, 167 mpam_feat_msmon_mbwu_capture, 168 mpam_feat_msmon_mbwu_rwbw, 169 mpam_feat_msmon_mbwu_hw_nrdy, 170 mpam_feat_partid_nrw, 171 MPAM_FEATURE_LAST 172 }; 173 174 struct mpam_props { 175 DECLARE_BITMAP(features, MPAM_FEATURE_LAST); 176 177 u16 cpbm_wd; 178 u16 mbw_pbm_bits; 179 u16 bwa_wd; 180 u16 cmax_wd; 181 u16 cassoc_wd; 182 u16 intpri_wd; 183 u16 dspri_wd; 184 u16 num_csu_mon; 185 u16 num_mbwu_mon; 186 }; 187 188 #define mpam_has_feature(_feat, x) test_bit(_feat, (x)->features) 189 #define mpam_set_feature(_feat, x) set_bit(_feat, (x)->features) 190 #define mpam_clear_feature(_feat, x) clear_bit(_feat, (x)->features) 191 192 /* The values for MSMON_CFG_MBWU_FLT.RWBW */ 193 enum mon_filter_options { 194 COUNT_BOTH = 0, 195 COUNT_WRITE = 1, 196 COUNT_READ = 2, 197 }; 198 199 struct mon_cfg { 200 u16 mon; 201 u8 pmg; 202 bool match_pmg; 203 bool csu_exclude_clean; 204 u32 partid; 205 enum mon_filter_options opts; 206 }; 207 208 /* Changes to msmon_mbwu_state are protected by the msc's mon_sel_lock. */ 209 struct msmon_mbwu_state { 210 bool enabled; 211 struct mon_cfg cfg; 212 213 /* 214 * The value to add to the new reading to account for power management. 215 */ 216 u64 correction; 217 218 struct mpam_garbage garbage; 219 }; 220 221 struct mpam_class { 222 /* mpam_components in this class */ 223 struct list_head components; 224 225 cpumask_t affinity; 226 227 struct mpam_props props; 228 u32 nrdy_usec; 229 u8 level; 230 enum mpam_class_types type; 231 232 /* member of mpam_classes */ 233 struct list_head classes_list; 234 235 struct ida ida_csu_mon; 236 struct ida ida_mbwu_mon; 237 238 struct mpam_garbage garbage; 239 }; 240 241 struct mpam_config { 242 /* Which configuration values are valid. */ 243 DECLARE_BITMAP(features, MPAM_FEATURE_LAST); 244 245 u32 cpbm; 246 u32 mbw_pbm; 247 u16 mbw_max; 248 249 bool reset_cpbm; 250 bool reset_mbw_pbm; 251 bool reset_mbw_max; 252 253 struct mpam_garbage garbage; 254 }; 255 256 struct mpam_component { 257 u32 comp_id; 258 259 /* mpam_vmsc in this component */ 260 struct list_head vmsc; 261 262 cpumask_t affinity; 263 264 /* 265 * Array of configuration values, indexed by partid. 266 * Read from cpuhp callbacks, hold the cpuhp lock when writing. 267 */ 268 struct mpam_config *cfg; 269 270 /* member of mpam_class:components */ 271 struct list_head class_list; 272 273 /* parent: */ 274 struct mpam_class *class; 275 276 struct mpam_garbage garbage; 277 }; 278 279 struct mpam_vmsc { 280 /* member of mpam_component:vmsc_list */ 281 struct list_head comp_list; 282 283 /* mpam_msc_ris in this vmsc */ 284 struct list_head ris; 285 286 struct mpam_props props; 287 288 /* All RIS in this vMSC are members of this MSC */ 289 struct mpam_msc *msc; 290 291 /* parent: */ 292 struct mpam_component *comp; 293 294 struct mpam_garbage garbage; 295 }; 296 297 struct mpam_msc_ris { 298 u8 ris_idx; 299 u64 idr; 300 struct mpam_props props; 301 bool in_reset_state; 302 303 cpumask_t affinity; 304 305 /* member of mpam_vmsc:ris */ 306 struct list_head vmsc_list; 307 308 /* member of mpam_msc:ris */ 309 struct list_head msc_list; 310 311 /* parent: */ 312 struct mpam_vmsc *vmsc; 313 314 /* msmon mbwu configuration is preserved over reset */ 315 struct msmon_mbwu_state *mbwu_state; 316 317 struct mpam_garbage garbage; 318 }; 319 320 static inline int mpam_alloc_csu_mon(struct mpam_class *class) 321 { 322 struct mpam_props *cprops = &class->props; 323 324 if (!mpam_has_feature(mpam_feat_msmon_csu, cprops)) 325 return -EOPNOTSUPP; 326 327 return ida_alloc_max(&class->ida_csu_mon, cprops->num_csu_mon - 1, 328 GFP_KERNEL); 329 } 330 331 static inline void mpam_free_csu_mon(struct mpam_class *class, int csu_mon) 332 { 333 ida_free(&class->ida_csu_mon, csu_mon); 334 } 335 336 static inline int mpam_alloc_mbwu_mon(struct mpam_class *class) 337 { 338 struct mpam_props *cprops = &class->props; 339 340 if (!mpam_has_feature(mpam_feat_msmon_mbwu, cprops)) 341 return -EOPNOTSUPP; 342 343 return ida_alloc_max(&class->ida_mbwu_mon, cprops->num_mbwu_mon - 1, 344 GFP_KERNEL); 345 } 346 347 static inline void mpam_free_mbwu_mon(struct mpam_class *class, int mbwu_mon) 348 { 349 ida_free(&class->ida_mbwu_mon, mbwu_mon); 350 } 351 352 /* List of all classes - protected by srcu*/ 353 extern struct srcu_struct mpam_srcu; 354 extern struct list_head mpam_classes; 355 356 /* System wide partid/pmg values */ 357 extern u16 mpam_partid_max; 358 extern u8 mpam_pmg_max; 359 360 /* Scheduled work callback to enable mpam once all MSC have been probed */ 361 void mpam_enable(struct work_struct *work); 362 void mpam_disable(struct work_struct *work); 363 364 int mpam_apply_config(struct mpam_component *comp, u16 partid, 365 struct mpam_config *cfg); 366 367 int mpam_msmon_read(struct mpam_component *comp, struct mon_cfg *ctx, 368 enum mpam_device_features, u64 *val); 369 370 int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, 371 cpumask_t *affinity); 372 373 /* 374 * MPAM MSCs have the following register layout. See: 375 * Arm Memory System Resource Partitioning and Monitoring (MPAM) System 376 * Component Specification. 377 * https://developer.arm.com/documentation/ihi0099/aa/ 378 */ 379 #define MPAM_ARCHITECTURE_V1 0x10 380 381 /* Memory mapped control pages */ 382 /* ID Register offsets in the memory mapped page */ 383 #define MPAMF_IDR 0x0000 /* features id register */ 384 #define MPAMF_IIDR 0x0018 /* implementer id register */ 385 #define MPAMF_AIDR 0x0020 /* architectural id register */ 386 #define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */ 387 #define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */ 388 #define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */ 389 #define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */ 390 #define MPAMF_PRI_IDR 0x0048 /* priority partitioning */ 391 #define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */ 392 #define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */ 393 #define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */ 394 #define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */ 395 396 /* Configuration and Status Register offsets in the memory mapped page */ 397 #define MPAMCFG_PART_SEL 0x0100 /* partid to configure */ 398 #define MPAMCFG_CPBM 0x1000 /* cache-portion config */ 399 #define MPAMCFG_CMAX 0x0108 /* cache-capacity config */ 400 #define MPAMCFG_CMIN 0x0110 /* cache-capacity config */ 401 #define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */ 402 #define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */ 403 #define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */ 404 #define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */ 405 #define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */ 406 #define MPAMCFG_PRI 0x0400 /* priority partitioning config */ 407 #define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */ 408 #define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */ 409 410 #define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */ 411 #define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */ 412 #define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */ 413 #define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */ 414 #define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */ 415 #define MSMON_CSU 0x0840 /* current cache-usage */ 416 #define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */ 417 #define MSMON_MBWU 0x0860 /* current mem-bw usage value */ 418 #define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */ 419 #define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */ 420 #define MSMON_MBWU_L_CAPTURE 0x0890 /* last long mem-bw value captured */ 421 #define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */ 422 #define MPAMF_ESR 0x00F8 /* error status register */ 423 #define MPAMF_ECR 0x00F0 /* error control register */ 424 425 /* MPAMF_IDR - MPAM features ID register */ 426 #define MPAMF_IDR_PARTID_MAX GENMASK(15, 0) 427 #define MPAMF_IDR_PMG_MAX GENMASK(23, 16) 428 #define MPAMF_IDR_HAS_CCAP_PART BIT(24) 429 #define MPAMF_IDR_HAS_CPOR_PART BIT(25) 430 #define MPAMF_IDR_HAS_MBW_PART BIT(26) 431 #define MPAMF_IDR_HAS_PRI_PART BIT(27) 432 #define MPAMF_IDR_EXT BIT(28) 433 #define MPAMF_IDR_HAS_IMPL_IDR BIT(29) 434 #define MPAMF_IDR_HAS_MSMON BIT(30) 435 #define MPAMF_IDR_HAS_PARTID_NRW BIT(31) 436 #define MPAMF_IDR_HAS_RIS BIT(32) 437 #define MPAMF_IDR_HAS_EXTD_ESR BIT(38) 438 #define MPAMF_IDR_HAS_ESR BIT(39) 439 #define MPAMF_IDR_RIS_MAX GENMASK(59, 56) 440 441 /* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */ 442 #define MPAMF_MSMON_IDR_MSMON_CSU BIT(16) 443 #define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17) 444 #define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31) 445 446 /* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */ 447 #define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0) 448 449 /* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */ 450 #define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0) 451 #define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8) 452 #define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28) 453 #define MPAMF_CCAP_IDR_HAS_CMIN BIT(29) 454 #define MPAMF_CCAP_IDR_NO_CMAX BIT(30) 455 #define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31) 456 457 /* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */ 458 #define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0) 459 #define MPAMF_MBW_IDR_HAS_MIN BIT(10) 460 #define MPAMF_MBW_IDR_HAS_MAX BIT(11) 461 #define MPAMF_MBW_IDR_HAS_PBM BIT(12) 462 #define MPAMF_MBW_IDR_HAS_PROP BIT(13) 463 #define MPAMF_MBW_IDR_WINDWR BIT(14) 464 #define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16) 465 466 /* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */ 467 #define MPAMF_PRI_IDR_HAS_INTPRI BIT(0) 468 #define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1) 469 #define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4) 470 #define MPAMF_PRI_IDR_HAS_DSPRI BIT(16) 471 #define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17) 472 #define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20) 473 474 /* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */ 475 #define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0) 476 #define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24) 477 #define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25) 478 #define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26) 479 #define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27) 480 #define MPAMF_CSUMON_IDR_HAS_XCL BIT(29) 481 #define MPAMF_CSUMON_IDR_CSU_RO BIT(30) 482 #define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31) 483 484 /* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */ 485 #define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0) 486 #define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28) 487 #define MPAMF_MBWUMON_IDR_LWD BIT(29) 488 #define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30) 489 #define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31) 490 491 /* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */ 492 #define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0) 493 494 /* MPAMF_IIDR - MPAM implementation ID register */ 495 #define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0) 496 #define MPAMF_IIDR_REVISION GENMASK(15, 12) 497 #define MPAMF_IIDR_VARIANT GENMASK(19, 16) 498 #define MPAMF_IIDR_PRODUCTID GENMASK(31, 20) 499 500 /* MPAMF_AIDR - MPAM architecture ID register */ 501 #define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0) 502 #define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4) 503 504 /* MPAMCFG_PART_SEL - MPAM partition configuration selection register */ 505 #define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0) 506 #define MPAMCFG_PART_SEL_INTERNAL BIT(16) 507 #define MPAMCFG_PART_SEL_RIS GENMASK(27, 24) 508 509 /* MPAMCFG_CASSOC - MPAM cache maximum associativity partition configuration register */ 510 #define MPAMCFG_CASSOC_CASSOC GENMASK(15, 0) 511 512 /* MPAMCFG_CMAX - MPAM cache capacity configuration register */ 513 #define MPAMCFG_CMAX_SOFTLIM BIT(31) 514 #define MPAMCFG_CMAX_CMAX GENMASK(15, 0) 515 516 /* MPAMCFG_CMIN - MPAM cache capacity configuration register */ 517 #define MPAMCFG_CMIN_CMIN GENMASK(15, 0) 518 519 /* 520 * MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configuration 521 * register 522 */ 523 #define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0) 524 525 /* 526 * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration 527 * register 528 */ 529 #define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0) 530 #define MPAMCFG_MBW_MAX_HARDLIM BIT(31) 531 532 /* 533 * MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width 534 * register 535 */ 536 #define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0) 537 #define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8) 538 539 /* MPAMCFG_PRI - MPAM priority partitioning configuration register */ 540 #define MPAMCFG_PRI_INTPRI GENMASK(15, 0) 541 #define MPAMCFG_PRI_DSPRI GENMASK(31, 16) 542 543 /* 544 * MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning 545 * configuration register 546 */ 547 #define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0) 548 #define MPAMCFG_MBW_PROP_EN BIT(31) 549 550 /* 551 * MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration register 552 */ 553 #define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0) 554 #define MPAMCFG_INTPARTID_INTERNAL BIT(16) 555 556 /* MSMON_CFG_MON_SEL - Memory system performance monitor selection register */ 557 #define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0) 558 #define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24) 559 560 /* MPAMF_ESR - MPAM Error Status Register */ 561 #define MPAMF_ESR_PARTID_MON GENMASK(15, 0) 562 #define MPAMF_ESR_PMG GENMASK(23, 16) 563 #define MPAMF_ESR_ERRCODE GENMASK(27, 24) 564 #define MPAMF_ESR_OVRWR BIT(31) 565 #define MPAMF_ESR_RIS GENMASK(35, 32) 566 567 /* MPAMF_ECR - MPAM Error Control Register */ 568 #define MPAMF_ECR_INTEN BIT(0) 569 570 /* Error conditions in accessing memory mapped registers */ 571 #define MPAM_ERRCODE_NONE 0 572 #define MPAM_ERRCODE_PARTID_SEL_RANGE 1 573 #define MPAM_ERRCODE_REQ_PARTID_RANGE 2 574 #define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3 575 #define MPAM_ERRCODE_REQ_PMG_RANGE 4 576 #define MPAM_ERRCODE_MONITOR_RANGE 5 577 #define MPAM_ERRCODE_INTPARTID_RANGE 6 578 #define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7 579 #define MPAM_ERRCODE_UNDEFINED_RIS_PART_SEL 8 580 #define MPAM_ERRCODE_RIS_NO_CONTROL 9 581 #define MPAM_ERRCODE_UNDEFINED_RIS_MON_SEL 10 582 #define MPAM_ERRCODE_RIS_NO_MONITOR 11 583 584 /* 585 * MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache storage 586 * usage monitor control register 587 * MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory 588 * bandwidth usage monitor control register 589 */ 590 #define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0) 591 #define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L BIT(15) 592 #define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16) 593 #define MSMON_CFG_x_CTL_MATCH_PMG BIT(17) 594 #define MSMON_CFG_MBWU_CTL_SCLEN BIT(19) 595 #define MSMON_CFG_x_CTL_SUBTYPE GENMASK(22, 20) 596 #define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24) 597 #define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25) 598 #define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26) 599 #define MSMON_CFG_x_CTL_CAPT_RESET BIT(27) 600 #define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28) 601 #define MSMON_CFG_x_CTL_EN BIT(31) 602 603 #define MSMON_CFG_MBWU_CTL_TYPE_MBWU 0x42 604 #define MSMON_CFG_CSU_CTL_TYPE_CSU 0x43 605 606 /* 607 * MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage 608 * usage monitor filter register 609 * MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory 610 * bandwidth usage monitor filter register 611 */ 612 #define MSMON_CFG_x_FLT_PARTID GENMASK(15, 0) 613 #define MSMON_CFG_x_FLT_PMG GENMASK(23, 16) 614 615 #define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30) 616 #define MSMON_CFG_CSU_FLT_XCL BIT(31) 617 618 /* 619 * MSMON_CSU - Memory system performance monitor cache storage usage monitor 620 * register 621 * MSMON_CSU_CAPTURE - Memory system performance monitor cache storage usage 622 * capture register 623 * MSMON_MBWU - Memory system performance monitor memory bandwidth usage 624 * monitor register 625 * MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage 626 * capture register 627 */ 628 #define MSMON___VALUE GENMASK(30, 0) 629 #define MSMON___NRDY BIT(31) 630 #define MSMON___L_NRDY BIT(63) 631 #define MSMON___L_VALUE GENMASK(43, 0) 632 #define MSMON___LWD_VALUE GENMASK(62, 0) 633 634 /* 635 * MSMON_CAPT_EVNT - Memory system performance monitoring capture event 636 * generation register 637 */ 638 #define MSMON_CAPT_EVNT_NOW BIT(0) 639 640 #endif /* MPAM_INTERNAL_H */ 641