1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2025 Arm Ltd. 3 4 #ifndef MPAM_INTERNAL_H 5 #define MPAM_INTERNAL_H 6 7 #include <linux/arm_mpam.h> 8 #include <linux/atomic.h> 9 #include <linux/bitmap.h> 10 #include <linux/cpumask.h> 11 #include <linux/io.h> 12 #include <linux/jump_label.h> 13 #include <linux/llist.h> 14 #include <linux/mutex.h> 15 #include <linux/srcu.h> 16 #include <linux/spinlock.h> 17 #include <linux/srcu.h> 18 #include <linux/types.h> 19 20 #define MPAM_MSC_MAX_NUM_RIS 16 21 22 struct platform_device; 23 24 DECLARE_STATIC_KEY_FALSE(mpam_enabled); 25 26 static inline bool mpam_is_enabled(void) 27 { 28 return static_branch_likely(&mpam_enabled); 29 } 30 31 /* 32 * Structures protected by SRCU may not be freed for a surprising amount of 33 * time (especially if perf is running). To ensure the MPAM error interrupt can 34 * tear down all the structures, build a list of objects that can be garbage 35 * collected once synchronize_srcu() has returned. 36 * If pdev is non-NULL, use devm_kfree(). 37 */ 38 struct mpam_garbage { 39 /* member of mpam_garbage */ 40 struct llist_node llist; 41 42 void *to_free; 43 struct platform_device *pdev; 44 }; 45 46 struct mpam_msc { 47 /* member of mpam_all_msc */ 48 struct list_head all_msc_list; 49 50 int id; 51 struct platform_device *pdev; 52 53 /* Not modified after mpam_is_enabled() becomes true */ 54 enum mpam_msc_iface iface; 55 u32 nrdy_usec; 56 cpumask_t accessibility; 57 bool has_extd_esr; 58 59 int reenable_error_ppi; 60 struct mpam_msc * __percpu *error_dev_id; 61 62 atomic_t online_refs; 63 64 /* 65 * probe_lock is only taken during discovery. After discovery these 66 * properties become read-only and the lists are protected by SRCU. 67 */ 68 struct mutex probe_lock; 69 bool probed; 70 u16 partid_max; 71 u8 pmg_max; 72 unsigned long ris_idxs; 73 u32 ris_max; 74 75 /* 76 * error_irq_lock is taken when registering/unregistering the error 77 * interrupt and maniupulating the below flags. 78 */ 79 struct mutex error_irq_lock; 80 bool error_irq_req; 81 bool error_irq_hw_enabled; 82 83 /* mpam_msc_ris of this component */ 84 struct list_head ris; 85 86 /* 87 * part_sel_lock protects access to the MSC hardware registers that are 88 * affected by MPAMCFG_PART_SEL. (including the ID registers that vary 89 * by RIS). 90 * If needed, take msc->probe_lock first. 91 */ 92 struct mutex part_sel_lock; 93 94 /* 95 * mon_sel_lock protects access to the MSC hardware registers that are 96 * affected by MPAMCFG_MON_SEL, and the mbwu_state. 97 * Access to mon_sel is needed from both process and interrupt contexts, 98 * but is complicated by firmware-backed platforms that can't make any 99 * access unless they can sleep. 100 * Always use the mpam_mon_sel_lock() helpers. 101 * Accesses to mon_sel need to be able to fail if they occur in the wrong 102 * context. 103 * If needed, take msc->probe_lock first. 104 */ 105 raw_spinlock_t _mon_sel_lock; 106 unsigned long _mon_sel_flags; 107 108 void __iomem *mapped_hwpage; 109 size_t mapped_hwpage_sz; 110 111 struct mpam_garbage garbage; 112 }; 113 114 /* Returning false here means accesses to mon_sel must fail and report an error. */ 115 static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc) 116 { 117 /* Locking will require updating to support a firmware backed interface */ 118 if (WARN_ON_ONCE(msc->iface != MPAM_IFACE_MMIO)) 119 return false; 120 121 raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags); 122 return true; 123 } 124 125 static inline void mpam_mon_sel_unlock(struct mpam_msc *msc) 126 { 127 raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags); 128 } 129 130 static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc) 131 { 132 lockdep_assert_held_once(&msc->_mon_sel_lock); 133 } 134 135 static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc) 136 { 137 raw_spin_lock_init(&msc->_mon_sel_lock); 138 } 139 140 /* Bits for mpam features bitmaps */ 141 enum mpam_device_features { 142 mpam_feat_cpor_part, 143 mpam_feat_mbw_part, 144 mpam_feat_mbw_min, 145 mpam_feat_mbw_max, 146 mpam_feat_msmon, 147 mpam_feat_msmon_csu, 148 mpam_feat_msmon_csu_hw_nrdy, 149 mpam_feat_msmon_mbwu, 150 mpam_feat_msmon_mbwu_hw_nrdy, 151 MPAM_FEATURE_LAST 152 }; 153 154 struct mpam_props { 155 DECLARE_BITMAP(features, MPAM_FEATURE_LAST); 156 157 u16 cpbm_wd; 158 u16 mbw_pbm_bits; 159 u16 bwa_wd; 160 u16 num_csu_mon; 161 u16 num_mbwu_mon; 162 }; 163 164 #define mpam_has_feature(_feat, x) test_bit(_feat, (x)->features) 165 #define mpam_set_feature(_feat, x) set_bit(_feat, (x)->features) 166 #define mpam_clear_feature(_feat, x) clear_bit(_feat, (x)->features) 167 168 struct mpam_class { 169 /* mpam_components in this class */ 170 struct list_head components; 171 172 cpumask_t affinity; 173 174 struct mpam_props props; 175 u32 nrdy_usec; 176 u8 level; 177 enum mpam_class_types type; 178 179 /* member of mpam_classes */ 180 struct list_head classes_list; 181 182 struct mpam_garbage garbage; 183 }; 184 185 struct mpam_component { 186 u32 comp_id; 187 188 /* mpam_vmsc in this component */ 189 struct list_head vmsc; 190 191 cpumask_t affinity; 192 193 /* member of mpam_class:components */ 194 struct list_head class_list; 195 196 /* parent: */ 197 struct mpam_class *class; 198 199 struct mpam_garbage garbage; 200 }; 201 202 struct mpam_vmsc { 203 /* member of mpam_component:vmsc_list */ 204 struct list_head comp_list; 205 206 /* mpam_msc_ris in this vmsc */ 207 struct list_head ris; 208 209 struct mpam_props props; 210 211 /* All RIS in this vMSC are members of this MSC */ 212 struct mpam_msc *msc; 213 214 /* parent: */ 215 struct mpam_component *comp; 216 217 struct mpam_garbage garbage; 218 }; 219 220 struct mpam_msc_ris { 221 u8 ris_idx; 222 u64 idr; 223 struct mpam_props props; 224 bool in_reset_state; 225 226 cpumask_t affinity; 227 228 /* member of mpam_vmsc:ris */ 229 struct list_head vmsc_list; 230 231 /* member of mpam_msc:ris */ 232 struct list_head msc_list; 233 234 /* parent: */ 235 struct mpam_vmsc *vmsc; 236 237 struct mpam_garbage garbage; 238 }; 239 240 /* List of all classes - protected by srcu*/ 241 extern struct srcu_struct mpam_srcu; 242 extern struct list_head mpam_classes; 243 244 /* System wide partid/pmg values */ 245 extern u16 mpam_partid_max; 246 extern u8 mpam_pmg_max; 247 248 /* Scheduled work callback to enable mpam once all MSC have been probed */ 249 void mpam_enable(struct work_struct *work); 250 void mpam_disable(struct work_struct *work); 251 252 int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, 253 cpumask_t *affinity); 254 255 /* 256 * MPAM MSCs have the following register layout. See: 257 * Arm Memory System Resource Partitioning and Monitoring (MPAM) System 258 * Component Specification. 259 * https://developer.arm.com/documentation/ihi0099/aa/ 260 */ 261 #define MPAM_ARCHITECTURE_V1 0x10 262 263 /* Memory mapped control pages */ 264 /* ID Register offsets in the memory mapped page */ 265 #define MPAMF_IDR 0x0000 /* features id register */ 266 #define MPAMF_IIDR 0x0018 /* implementer id register */ 267 #define MPAMF_AIDR 0x0020 /* architectural id register */ 268 #define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */ 269 #define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */ 270 #define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */ 271 #define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */ 272 #define MPAMF_PRI_IDR 0x0048 /* priority partitioning */ 273 #define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */ 274 #define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */ 275 #define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */ 276 #define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */ 277 278 /* Configuration and Status Register offsets in the memory mapped page */ 279 #define MPAMCFG_PART_SEL 0x0100 /* partid to configure */ 280 #define MPAMCFG_CPBM 0x1000 /* cache-portion config */ 281 #define MPAMCFG_CMAX 0x0108 /* cache-capacity config */ 282 #define MPAMCFG_CMIN 0x0110 /* cache-capacity config */ 283 #define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */ 284 #define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */ 285 #define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */ 286 #define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */ 287 #define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */ 288 #define MPAMCFG_PRI 0x0400 /* priority partitioning config */ 289 #define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */ 290 #define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */ 291 292 #define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */ 293 #define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */ 294 #define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */ 295 #define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */ 296 #define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */ 297 #define MSMON_CSU 0x0840 /* current cache-usage */ 298 #define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */ 299 #define MSMON_MBWU 0x0860 /* current mem-bw usage value */ 300 #define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */ 301 #define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */ 302 #define MSMON_MBWU_L_CAPTURE 0x0890 /* last long mem-bw value captured */ 303 #define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */ 304 #define MPAMF_ESR 0x00F8 /* error status register */ 305 #define MPAMF_ECR 0x00F0 /* error control register */ 306 307 /* MPAMF_IDR - MPAM features ID register */ 308 #define MPAMF_IDR_PARTID_MAX GENMASK(15, 0) 309 #define MPAMF_IDR_PMG_MAX GENMASK(23, 16) 310 #define MPAMF_IDR_HAS_CCAP_PART BIT(24) 311 #define MPAMF_IDR_HAS_CPOR_PART BIT(25) 312 #define MPAMF_IDR_HAS_MBW_PART BIT(26) 313 #define MPAMF_IDR_HAS_PRI_PART BIT(27) 314 #define MPAMF_IDR_EXT BIT(28) 315 #define MPAMF_IDR_HAS_IMPL_IDR BIT(29) 316 #define MPAMF_IDR_HAS_MSMON BIT(30) 317 #define MPAMF_IDR_HAS_PARTID_NRW BIT(31) 318 #define MPAMF_IDR_HAS_RIS BIT(32) 319 #define MPAMF_IDR_HAS_EXTD_ESR BIT(38) 320 #define MPAMF_IDR_HAS_ESR BIT(39) 321 #define MPAMF_IDR_RIS_MAX GENMASK(59, 56) 322 323 /* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */ 324 #define MPAMF_MSMON_IDR_MSMON_CSU BIT(16) 325 #define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17) 326 #define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31) 327 328 /* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */ 329 #define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0) 330 331 /* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */ 332 #define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0) 333 #define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8) 334 #define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28) 335 #define MPAMF_CCAP_IDR_HAS_CMIN BIT(29) 336 #define MPAMF_CCAP_IDR_NO_CMAX BIT(30) 337 #define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31) 338 339 /* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */ 340 #define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0) 341 #define MPAMF_MBW_IDR_HAS_MIN BIT(10) 342 #define MPAMF_MBW_IDR_HAS_MAX BIT(11) 343 #define MPAMF_MBW_IDR_HAS_PBM BIT(12) 344 #define MPAMF_MBW_IDR_HAS_PROP BIT(13) 345 #define MPAMF_MBW_IDR_WINDWR BIT(14) 346 #define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16) 347 348 /* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */ 349 #define MPAMF_PRI_IDR_HAS_INTPRI BIT(0) 350 #define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1) 351 #define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4) 352 #define MPAMF_PRI_IDR_HAS_DSPRI BIT(16) 353 #define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17) 354 #define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20) 355 356 /* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */ 357 #define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0) 358 #define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24) 359 #define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25) 360 #define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26) 361 #define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27) 362 #define MPAMF_CSUMON_IDR_HAS_XCL BIT(29) 363 #define MPAMF_CSUMON_IDR_CSU_RO BIT(30) 364 #define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31) 365 366 /* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */ 367 #define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0) 368 #define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28) 369 #define MPAMF_MBWUMON_IDR_LWD BIT(29) 370 #define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30) 371 #define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31) 372 373 /* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */ 374 #define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0) 375 376 /* MPAMF_IIDR - MPAM implementation ID register */ 377 #define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0) 378 #define MPAMF_IIDR_REVISION GENMASK(15, 12) 379 #define MPAMF_IIDR_VARIANT GENMASK(19, 16) 380 #define MPAMF_IIDR_PRODUCTID GENMASK(31, 20) 381 382 /* MPAMF_AIDR - MPAM architecture ID register */ 383 #define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0) 384 #define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4) 385 386 /* MPAMCFG_PART_SEL - MPAM partition configuration selection register */ 387 #define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0) 388 #define MPAMCFG_PART_SEL_INTERNAL BIT(16) 389 #define MPAMCFG_PART_SEL_RIS GENMASK(27, 24) 390 391 /* MPAMCFG_CASSOC - MPAM cache maximum associativity partition configuration register */ 392 #define MPAMCFG_CASSOC_CASSOC GENMASK(15, 0) 393 394 /* MPAMCFG_CMAX - MPAM cache capacity configuration register */ 395 #define MPAMCFG_CMAX_SOFTLIM BIT(31) 396 #define MPAMCFG_CMAX_CMAX GENMASK(15, 0) 397 398 /* MPAMCFG_CMIN - MPAM cache capacity configuration register */ 399 #define MPAMCFG_CMIN_CMIN GENMASK(15, 0) 400 401 /* 402 * MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configuration 403 * register 404 */ 405 #define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0) 406 407 /* 408 * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration 409 * register 410 */ 411 #define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0) 412 #define MPAMCFG_MBW_MAX_HARDLIM BIT(31) 413 414 /* 415 * MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width 416 * register 417 */ 418 #define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0) 419 #define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8) 420 421 /* MPAMCFG_PRI - MPAM priority partitioning configuration register */ 422 #define MPAMCFG_PRI_INTPRI GENMASK(15, 0) 423 #define MPAMCFG_PRI_DSPRI GENMASK(31, 16) 424 425 /* 426 * MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning 427 * configuration register 428 */ 429 #define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0) 430 #define MPAMCFG_MBW_PROP_EN BIT(31) 431 432 /* 433 * MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration register 434 */ 435 #define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0) 436 #define MPAMCFG_INTPARTID_INTERNAL BIT(16) 437 438 /* MSMON_CFG_MON_SEL - Memory system performance monitor selection register */ 439 #define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0) 440 #define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24) 441 442 /* MPAMF_ESR - MPAM Error Status Register */ 443 #define MPAMF_ESR_PARTID_MON GENMASK(15, 0) 444 #define MPAMF_ESR_PMG GENMASK(23, 16) 445 #define MPAMF_ESR_ERRCODE GENMASK(27, 24) 446 #define MPAMF_ESR_OVRWR BIT(31) 447 #define MPAMF_ESR_RIS GENMASK(35, 32) 448 449 /* MPAMF_ECR - MPAM Error Control Register */ 450 #define MPAMF_ECR_INTEN BIT(0) 451 452 /* Error conditions in accessing memory mapped registers */ 453 #define MPAM_ERRCODE_NONE 0 454 #define MPAM_ERRCODE_PARTID_SEL_RANGE 1 455 #define MPAM_ERRCODE_REQ_PARTID_RANGE 2 456 #define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3 457 #define MPAM_ERRCODE_REQ_PMG_RANGE 4 458 #define MPAM_ERRCODE_MONITOR_RANGE 5 459 #define MPAM_ERRCODE_INTPARTID_RANGE 6 460 #define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7 461 #define MPAM_ERRCODE_UNDEFINED_RIS_PART_SEL 8 462 #define MPAM_ERRCODE_RIS_NO_CONTROL 9 463 #define MPAM_ERRCODE_UNDEFINED_RIS_MON_SEL 10 464 #define MPAM_ERRCODE_RIS_NO_MONITOR 11 465 466 /* 467 * MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache storage 468 * usage monitor control register 469 * MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory 470 * bandwidth usage monitor control register 471 */ 472 #define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0) 473 #define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L BIT(15) 474 #define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16) 475 #define MSMON_CFG_x_CTL_MATCH_PMG BIT(17) 476 #define MSMON_CFG_MBWU_CTL_SCLEN BIT(19) 477 #define MSMON_CFG_x_CTL_SUBTYPE GENMASK(22, 20) 478 #define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24) 479 #define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25) 480 #define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26) 481 #define MSMON_CFG_x_CTL_CAPT_RESET BIT(27) 482 #define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28) 483 #define MSMON_CFG_x_CTL_EN BIT(31) 484 485 #define MSMON_CFG_MBWU_CTL_TYPE_MBWU 0x42 486 #define MSMON_CFG_CSU_CTL_TYPE_CSU 0x43 487 488 /* 489 * MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage 490 * usage monitor filter register 491 * MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory 492 * bandwidth usage monitor filter register 493 */ 494 #define MSMON_CFG_x_FLT_PARTID GENMASK(15, 0) 495 #define MSMON_CFG_x_FLT_PMG GENMASK(23, 16) 496 497 #define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30) 498 #define MSMON_CFG_CSU_FLT_XCL BIT(31) 499 500 /* 501 * MSMON_CSU - Memory system performance monitor cache storage usage monitor 502 * register 503 * MSMON_CSU_CAPTURE - Memory system performance monitor cache storage usage 504 * capture register 505 * MSMON_MBWU - Memory system performance monitor memory bandwidth usage 506 * monitor register 507 * MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage 508 * capture register 509 */ 510 #define MSMON___VALUE GENMASK(30, 0) 511 #define MSMON___NRDY BIT(31) 512 #define MSMON___L_NRDY BIT(63) 513 #define MSMON___L_VALUE GENMASK(43, 0) 514 #define MSMON___LWD_VALUE GENMASK(62, 0) 515 516 /* 517 * MSMON_CAPT_EVNT - Memory system performance monitoring capture event 518 * generation register 519 */ 520 #define MSMON_CAPT_EVNT_NOW BIT(0) 521 522 #endif /* MPAM_INTERNAL_H */ 523