1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/G2L Pin Control and GPIO driver core 4 * 5 * Copyright (C) 2021 Renesas Electronics Corporation. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of.h> 17 #include <linux/of_irq.h> 18 #include <linux/platform_device.h> 19 #include <linux/seq_file.h> 20 #include <linux/spinlock.h> 21 22 #include <linux/pinctrl/consumer.h> 23 #include <linux/pinctrl/pinconf-generic.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinmux.h> 27 28 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 29 30 #include "../core.h" 31 #include "../pinconf.h" 32 #include "../pinmux.h" 33 34 #define DRV_NAME "pinctrl-rzg2l" 35 36 /* 37 * Use 16 lower bits [15:0] for pin identifier 38 * Use 16 higher bits [31:16] for pin mux function 39 */ 40 #define MUX_PIN_ID_MASK GENMASK(15, 0) 41 #define MUX_FUNC_MASK GENMASK(31, 16) 42 43 /* PIN capabilities */ 44 #define PIN_CFG_IOLH_A BIT(0) 45 #define PIN_CFG_IOLH_B BIT(1) 46 #define PIN_CFG_SR BIT(2) 47 #define PIN_CFG_IEN BIT(3) 48 #define PIN_CFG_PUPD BIT(4) 49 #define PIN_CFG_IO_VMC_SD0 BIT(5) 50 #define PIN_CFG_IO_VMC_SD1 BIT(6) 51 #define PIN_CFG_IO_VMC_QSPI BIT(7) 52 #define PIN_CFG_IO_VMC_ETH0 BIT(8) 53 #define PIN_CFG_IO_VMC_ETH1 BIT(9) 54 #define PIN_CFG_FILONOFF BIT(10) 55 #define PIN_CFG_FILNUM BIT(11) 56 #define PIN_CFG_FILCLKSEL BIT(12) 57 #define PIN_CFG_IOLH_C BIT(13) 58 #define PIN_CFG_SOFT_PS BIT(14) 59 #define PIN_CFG_OEN BIT(15) 60 #define PIN_CFG_VARIABLE BIT(16) 61 #define PIN_CFG_NOGPIO_INT BIT(17) 62 63 #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ 64 (PIN_CFG_IOLH_##group | \ 65 PIN_CFG_PUPD | \ 66 PIN_CFG_FILONOFF | \ 67 PIN_CFG_FILNUM | \ 68 PIN_CFG_FILCLKSEL) 69 70 #define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \ 71 PIN_CFG_SR) 72 73 #define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \ 74 PIN_CFG_SOFT_PS) 75 76 #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \ 77 PIN_CFG_FILONOFF | \ 78 PIN_CFG_FILNUM | \ 79 PIN_CFG_FILCLKSEL) 80 81 #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(35, 28) 82 #define PIN_CFG_PIN_REG_MASK GENMASK(27, 20) 83 #define PIN_CFG_MASK GENMASK(19, 0) 84 85 /* 86 * m indicates the bitmap of supported pins, a is the register index 87 * and f is pin configuration capabilities supported. 88 */ 89 #define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \ 90 FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ 91 FIELD_PREP_CONST(PIN_CFG_MASK, (f))) 92 93 /* 94 * n indicates number of pins in the port, a is the register index 95 * and f is pin configuration capabilities supported. 96 */ 97 #define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f)) 98 99 /* 100 * BIT(63) indicates dedicated pin, p is the register index while 101 * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits 102 * (b * 8) and f is the pin configuration capabilities supported. 103 */ 104 #define RZG2L_SINGLE_PIN BIT_ULL(63) 105 #define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK(30, 24) 106 #define RZG2L_SINGLE_PIN_BITS_MASK GENMASK(22, 20) 107 108 #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ 109 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \ 110 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \ 111 FIELD_PREP_CONST(PIN_CFG_MASK, (f))) 112 113 #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ 114 FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \ 115 FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg))) 116 117 #define P(off) (0x0000 + (off)) 118 #define PM(off) (0x0100 + (off) * 2) 119 #define PMC(off) (0x0200 + (off)) 120 #define PFC(off) (0x0400 + (off) * 4) 121 #define PIN(off) (0x0800 + (off)) 122 #define IOLH(off) (0x1000 + (off) * 8) 123 #define IEN(off) (0x1800 + (off) * 8) 124 #define ISEL(off) (0x2C00 + (off) * 8) 125 #define SD_CH(off, ch) ((off) + (ch) * 4) 126 #define ETH_POC(off, ch) ((off) + (ch) * 4) 127 #define QSPI (0x3008) 128 #define ETH_MODE (0x3018) 129 130 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ 131 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ 132 #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ 133 134 #define PWPR_B0WI BIT(7) /* Bit Write Disable */ 135 #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ 136 137 #define PM_MASK 0x03 138 #define PFC_MASK 0x07 139 #define IEN_MASK 0x01 140 #define IOLH_MASK 0x03 141 142 #define PM_INPUT 0x1 143 #define PM_OUTPUT 0x2 144 145 #define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT) 146 #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) 147 148 #define RZG2L_TINT_MAX_INTERRUPT 32 149 #define RZG2L_TINT_IRQ_START_INDEX 9 150 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) 151 152 /* Read/write 8 bits register */ 153 #define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val) \ 154 do { \ 155 if (_read) \ 156 _val = readb(_addr); \ 157 else \ 158 writeb(_val, _addr); \ 159 } while (0) 160 161 /* Read/write 16 bits register */ 162 #define RZG2L_PCTRL_REG_ACCESS16(_read, _addr, _val) \ 163 do { \ 164 if (_read) \ 165 _val = readw(_addr); \ 166 else \ 167 writew(_val, _addr); \ 168 } while (0) 169 170 /* Read/write 32 bits register */ 171 #define RZG2L_PCTRL_REG_ACCESS32(_read, _addr, _val) \ 172 do { \ 173 if (_read) \ 174 _val = readl(_addr); \ 175 else \ 176 writel(_val, _addr); \ 177 } while (0) 178 179 /** 180 * struct rzg2l_register_offsets - specific register offsets 181 * @pwpr: PWPR register offset 182 * @sd_ch: SD_CH register offset 183 * @eth_poc: ETH_POC register offset 184 */ 185 struct rzg2l_register_offsets { 186 u16 pwpr; 187 u16 sd_ch; 188 u16 eth_poc; 189 }; 190 191 /** 192 * enum rzg2l_iolh_index - starting indices in IOLH specific arrays 193 * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source 194 * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source 195 * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source 196 * @RZG2L_IOLH_IDX_MAX: maximum index 197 */ 198 enum rzg2l_iolh_index { 199 RZG2L_IOLH_IDX_1V8 = 0, 200 RZG2L_IOLH_IDX_2V5 = 4, 201 RZG2L_IOLH_IDX_3V3 = 8, 202 RZG2L_IOLH_IDX_MAX = 12, 203 }; 204 205 /* Maximum number of driver strength entries per power source. */ 206 #define RZG2L_IOLH_MAX_DS_ENTRIES (4) 207 208 /** 209 * struct rzg2l_hwcfg - hardware configuration data structure 210 * @regs: hardware specific register offsets 211 * @iolh_groupa_ua: IOLH group A uA specific values 212 * @iolh_groupb_ua: IOLH group B uA specific values 213 * @iolh_groupc_ua: IOLH group C uA specific values 214 * @iolh_groupb_oi: IOLH group B output impedance specific values 215 * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported) 216 * @func_base: base number for port function (see register PFC) 217 * @oen_max_pin: the maximum pin number supporting output enable 218 * @oen_max_port: the maximum port number supporting output enable 219 */ 220 struct rzg2l_hwcfg { 221 const struct rzg2l_register_offsets regs; 222 u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX]; 223 u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX]; 224 u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX]; 225 u16 iolh_groupb_oi[4]; 226 bool drive_strength_ua; 227 u8 func_base; 228 u8 oen_max_pin; 229 u8 oen_max_port; 230 }; 231 232 struct rzg2l_dedicated_configs { 233 const char *name; 234 u64 config; 235 }; 236 237 /** 238 * struct rzg2l_variable_pin_cfg - pin data cfg 239 * @cfg: port pin configuration 240 * @port: port number 241 * @pin: port pin 242 */ 243 struct rzg2l_variable_pin_cfg { 244 u32 cfg:20; 245 u32 port:5; 246 u32 pin:3; 247 }; 248 249 struct rzg2l_pinctrl_data { 250 const char * const *port_pins; 251 const u64 *port_pin_configs; 252 unsigned int n_ports; 253 const struct rzg2l_dedicated_configs *dedicated_pins; 254 unsigned int n_port_pins; 255 unsigned int n_dedicated_pins; 256 const struct rzg2l_hwcfg *hwcfg; 257 const struct rzg2l_variable_pin_cfg *variable_pin_cfg; 258 unsigned int n_variable_pin_cfg; 259 }; 260 261 /** 262 * struct rzg2l_pinctrl_pin_settings - pin data 263 * @power_source: power source 264 * @drive_strength_ua: drive strength (in micro amps) 265 */ 266 struct rzg2l_pinctrl_pin_settings { 267 u16 power_source; 268 u16 drive_strength_ua; 269 }; 270 271 /** 272 * struct rzg2l_pinctrl_reg_cache - register cache structure (to be used in suspend/resume) 273 * @p: P registers cache 274 * @pm: PM registers cache 275 * @pmc: PMC registers cache 276 * @pfc: PFC registers cache 277 * @iolh: IOLH registers cache 278 * @ien: IEN registers cache 279 * @sd_ch: SD_CH registers cache 280 * @eth_poc: ET_POC registers cache 281 * @eth_mode: ETH_MODE register cache 282 * @qspi: QSPI registers cache 283 */ 284 struct rzg2l_pinctrl_reg_cache { 285 u8 *p; 286 u16 *pm; 287 u8 *pmc; 288 u32 *pfc; 289 u32 *iolh[2]; 290 u32 *ien[2]; 291 u8 sd_ch[2]; 292 u8 eth_poc[2]; 293 u8 eth_mode; 294 u8 qspi; 295 }; 296 297 struct rzg2l_pinctrl { 298 struct pinctrl_dev *pctl; 299 struct pinctrl_desc desc; 300 struct pinctrl_pin_desc *pins; 301 302 const struct rzg2l_pinctrl_data *data; 303 void __iomem *base; 304 struct device *dev; 305 306 struct clk *clk; 307 308 struct gpio_chip gpio_chip; 309 struct pinctrl_gpio_range gpio_range; 310 DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); 311 spinlock_t bitmap_lock; /* protect tint_slot bitmap */ 312 unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT]; 313 314 spinlock_t lock; /* lock read/write registers */ 315 struct mutex mutex; /* serialize adding groups and functions */ 316 317 struct rzg2l_pinctrl_pin_settings *settings; 318 struct rzg2l_pinctrl_reg_cache *cache; 319 struct rzg2l_pinctrl_reg_cache *dedicated_cache; 320 atomic_t wakeup_path; 321 }; 322 323 static const u16 available_ps[] = { 1800, 2500, 3300 }; 324 325 #ifdef CONFIG_RISCV 326 static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, 327 u64 pincfg, 328 unsigned int port, 329 u8 pin) 330 { 331 unsigned int i; 332 333 for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) { 334 if (pctrl->data->variable_pin_cfg[i].port == port && 335 pctrl->data->variable_pin_cfg[i].pin == pin) 336 return (pincfg & ~PIN_CFG_VARIABLE) | pctrl->data->variable_pin_cfg[i].cfg; 337 } 338 339 return 0; 340 } 341 342 static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] = { 343 { 344 .port = 20, 345 .pin = 0, 346 .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 347 PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | 348 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, 349 }, 350 { 351 .port = 20, 352 .pin = 1, 353 .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 354 PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | 355 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, 356 }, 357 { 358 .port = 20, 359 .pin = 2, 360 .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 361 PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | 362 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, 363 }, 364 { 365 .port = 20, 366 .pin = 3, 367 .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 368 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, 369 }, 370 { 371 .port = 20, 372 .pin = 4, 373 .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 374 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, 375 }, 376 { 377 .port = 20, 378 .pin = 5, 379 .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 380 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, 381 }, 382 { 383 .port = 20, 384 .pin = 6, 385 .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 386 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, 387 }, 388 { 389 .port = 20, 390 .pin = 7, 391 .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 392 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, 393 }, 394 { 395 .port = 23, 396 .pin = 1, 397 .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 398 PIN_CFG_NOGPIO_INT 399 }, 400 { 401 .port = 23, 402 .pin = 2, 403 .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 404 PIN_CFG_NOGPIO_INT, 405 }, 406 { 407 .port = 23, 408 .pin = 3, 409 .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 410 PIN_CFG_NOGPIO_INT, 411 }, 412 { 413 .port = 23, 414 .pin = 4, 415 .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 416 PIN_CFG_NOGPIO_INT, 417 }, 418 { 419 .port = 23, 420 .pin = 5, 421 .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT, 422 }, 423 { 424 .port = 24, 425 .pin = 0, 426 .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT, 427 }, 428 { 429 .port = 24, 430 .pin = 1, 431 .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 432 PIN_CFG_NOGPIO_INT, 433 }, 434 { 435 .port = 24, 436 .pin = 2, 437 .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 438 PIN_CFG_NOGPIO_INT, 439 }, 440 { 441 .port = 24, 442 .pin = 3, 443 .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 444 PIN_CFG_NOGPIO_INT, 445 }, 446 { 447 .port = 24, 448 .pin = 4, 449 .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 450 PIN_CFG_NOGPIO_INT, 451 }, 452 { 453 .port = 24, 454 .pin = 5, 455 .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 456 PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | 457 PIN_CFG_NOGPIO_INT, 458 }, 459 }; 460 #endif 461 462 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, 463 u8 pin, u8 off, u8 func) 464 { 465 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 466 unsigned long flags; 467 u32 reg; 468 469 spin_lock_irqsave(&pctrl->lock, flags); 470 471 /* Set pin to 'Non-use (Hi-Z input protection)' */ 472 reg = readw(pctrl->base + PM(off)); 473 reg &= ~(PM_MASK << (pin * 2)); 474 writew(reg, pctrl->base + PM(off)); 475 476 /* Temporarily switch to GPIO mode with PMC register */ 477 reg = readb(pctrl->base + PMC(off)); 478 writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); 479 480 /* Set the PWPR register to allow PFC register to write */ 481 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ 482 writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ 483 484 /* Select Pin function mode with PFC register */ 485 reg = readl(pctrl->base + PFC(off)); 486 reg &= ~(PFC_MASK << (pin * 4)); 487 writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); 488 489 /* Set the PWPR register to be write-protected */ 490 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ 491 writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ 492 493 /* Switch to Peripheral pin function with PMC register */ 494 reg = readb(pctrl->base + PMC(off)); 495 writeb(reg | BIT(pin), pctrl->base + PMC(off)); 496 497 spin_unlock_irqrestore(&pctrl->lock, flags); 498 }; 499 500 static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, 501 unsigned int func_selector, 502 unsigned int group_selector) 503 { 504 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 505 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 506 struct function_desc *func; 507 unsigned int i, *psel_val; 508 struct group_desc *group; 509 const unsigned int *pins; 510 511 func = pinmux_generic_get_function(pctldev, func_selector); 512 if (!func) 513 return -EINVAL; 514 group = pinctrl_generic_get_group(pctldev, group_selector); 515 if (!group) 516 return -EINVAL; 517 518 psel_val = func->data; 519 pins = group->grp.pins; 520 521 for (i = 0; i < group->grp.npins; i++) { 522 u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; 523 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 524 u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); 525 526 dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", 527 RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); 528 529 rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); 530 } 531 532 return 0; 533 }; 534 535 static int rzg2l_map_add_config(struct pinctrl_map *map, 536 const char *group_or_pin, 537 enum pinctrl_map_type type, 538 unsigned long *configs, 539 unsigned int num_configs) 540 { 541 unsigned long *cfgs; 542 543 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), 544 GFP_KERNEL); 545 if (!cfgs) 546 return -ENOMEM; 547 548 map->type = type; 549 map->data.configs.group_or_pin = group_or_pin; 550 map->data.configs.configs = cfgs; 551 map->data.configs.num_configs = num_configs; 552 553 return 0; 554 } 555 556 static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, 557 struct device_node *np, 558 struct device_node *parent, 559 struct pinctrl_map **map, 560 unsigned int *num_maps, 561 unsigned int *index) 562 { 563 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 564 struct pinctrl_map *maps = *map; 565 unsigned int nmaps = *num_maps; 566 unsigned long *configs = NULL; 567 unsigned int *pins, *psel_val; 568 unsigned int num_pinmux = 0; 569 unsigned int idx = *index; 570 unsigned int num_pins, i; 571 unsigned int num_configs; 572 struct property *pinmux; 573 struct property *prop; 574 int ret, gsel, fsel; 575 const char **pin_fn; 576 const char *name; 577 const char *pin; 578 579 pinmux = of_find_property(np, "pinmux", NULL); 580 if (pinmux) 581 num_pinmux = pinmux->length / sizeof(u32); 582 583 ret = of_property_count_strings(np, "pins"); 584 if (ret == -EINVAL) { 585 num_pins = 0; 586 } else if (ret < 0) { 587 dev_err(pctrl->dev, "Invalid pins list in DT\n"); 588 return ret; 589 } else { 590 num_pins = ret; 591 } 592 593 if (!num_pinmux && !num_pins) 594 return 0; 595 596 if (num_pinmux && num_pins) { 597 dev_err(pctrl->dev, 598 "DT node must contain either a pinmux or pins and not both\n"); 599 return -EINVAL; 600 } 601 602 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); 603 if (ret < 0) 604 return ret; 605 606 if (num_pins && !num_configs) { 607 dev_err(pctrl->dev, "DT node must contain a config\n"); 608 ret = -ENODEV; 609 goto done; 610 } 611 612 if (num_pinmux) { 613 nmaps += 1; 614 if (num_configs) 615 nmaps += 1; 616 } 617 618 if (num_pins) 619 nmaps += num_pins; 620 621 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); 622 if (!maps) { 623 ret = -ENOMEM; 624 goto done; 625 } 626 627 *map = maps; 628 *num_maps = nmaps; 629 if (num_pins) { 630 of_property_for_each_string(np, "pins", prop, pin) { 631 ret = rzg2l_map_add_config(&maps[idx], pin, 632 PIN_MAP_TYPE_CONFIGS_PIN, 633 configs, num_configs); 634 if (ret < 0) 635 goto done; 636 637 idx++; 638 } 639 ret = 0; 640 goto done; 641 } 642 643 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); 644 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), 645 GFP_KERNEL); 646 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); 647 if (!pins || !psel_val || !pin_fn) { 648 ret = -ENOMEM; 649 goto done; 650 } 651 652 /* Collect pin locations and mux settings from DT properties */ 653 for (i = 0; i < num_pinmux; ++i) { 654 u32 value; 655 656 ret = of_property_read_u32_index(np, "pinmux", i, &value); 657 if (ret) 658 goto done; 659 pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value); 660 psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value); 661 } 662 663 if (parent) { 664 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", 665 parent, np); 666 if (!name) { 667 ret = -ENOMEM; 668 goto done; 669 } 670 } else { 671 name = np->name; 672 } 673 674 if (num_configs) { 675 ret = rzg2l_map_add_config(&maps[idx], name, 676 PIN_MAP_TYPE_CONFIGS_GROUP, 677 configs, num_configs); 678 if (ret < 0) 679 goto done; 680 681 idx++; 682 } 683 684 mutex_lock(&pctrl->mutex); 685 686 /* Register a single pin group listing all the pins we read from DT */ 687 gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL); 688 if (gsel < 0) { 689 ret = gsel; 690 goto unlock; 691 } 692 693 /* 694 * Register a single group function where the 'data' is an array PSEL 695 * register values read from DT. 696 */ 697 pin_fn[0] = name; 698 fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val); 699 if (fsel < 0) { 700 ret = fsel; 701 goto remove_group; 702 } 703 704 mutex_unlock(&pctrl->mutex); 705 706 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 707 maps[idx].data.mux.group = name; 708 maps[idx].data.mux.function = name; 709 idx++; 710 711 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); 712 ret = 0; 713 goto done; 714 715 remove_group: 716 pinctrl_generic_remove_group(pctldev, gsel); 717 unlock: 718 mutex_unlock(&pctrl->mutex); 719 done: 720 *index = idx; 721 kfree(configs); 722 return ret; 723 } 724 725 static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev, 726 struct pinctrl_map *map, 727 unsigned int num_maps) 728 { 729 unsigned int i; 730 731 if (!map) 732 return; 733 734 for (i = 0; i < num_maps; ++i) { 735 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 736 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 737 kfree(map[i].data.configs.configs); 738 } 739 kfree(map); 740 } 741 742 static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, 743 struct device_node *np, 744 struct pinctrl_map **map, 745 unsigned int *num_maps) 746 { 747 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 748 struct device_node *child; 749 unsigned int index; 750 int ret; 751 752 *map = NULL; 753 *num_maps = 0; 754 index = 0; 755 756 for_each_child_of_node(np, child) { 757 ret = rzg2l_dt_subnode_to_map(pctldev, child, np, map, 758 num_maps, &index); 759 if (ret < 0) { 760 of_node_put(child); 761 goto done; 762 } 763 } 764 765 if (*num_maps == 0) { 766 ret = rzg2l_dt_subnode_to_map(pctldev, np, NULL, map, 767 num_maps, &index); 768 if (ret < 0) 769 goto done; 770 } 771 772 if (*num_maps) 773 return 0; 774 775 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); 776 ret = -EINVAL; 777 778 done: 779 rzg2l_dt_free_map(pctldev, *map, *num_maps); 780 781 return ret; 782 } 783 784 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, 785 u64 cfg, u32 port, u8 bit) 786 { 787 u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg); 788 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 789 u64 data; 790 791 if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins) 792 return -EINVAL; 793 794 data = pctrl->data->port_pin_configs[port]; 795 if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data)) 796 return -EINVAL; 797 798 return 0; 799 } 800 801 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 802 u8 bit, u32 mask) 803 { 804 void __iomem *addr = pctrl->base + offset; 805 806 /* handle _L/_H for 32-bit register read/write */ 807 if (bit >= 4) { 808 bit -= 4; 809 addr += 4; 810 } 811 812 return (readl(addr) >> (bit * 8)) & mask; 813 } 814 815 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 816 u8 bit, u32 mask, u32 val) 817 { 818 void __iomem *addr = pctrl->base + offset; 819 unsigned long flags; 820 u32 reg; 821 822 /* handle _L/_H for 32-bit register read/write */ 823 if (bit >= 4) { 824 bit -= 4; 825 addr += 4; 826 } 827 828 spin_lock_irqsave(&pctrl->lock, flags); 829 reg = readl(addr) & ~(mask << (bit * 8)); 830 writel(reg | (val << (bit * 8)), addr); 831 spin_unlock_irqrestore(&pctrl->lock, flags); 832 } 833 834 static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps) 835 { 836 if (caps & PIN_CFG_IO_VMC_SD0) 837 return SD_CH(regs->sd_ch, 0); 838 if (caps & PIN_CFG_IO_VMC_SD1) 839 return SD_CH(regs->sd_ch, 1); 840 if (caps & PIN_CFG_IO_VMC_ETH0) 841 return ETH_POC(regs->eth_poc, 0); 842 if (caps & PIN_CFG_IO_VMC_ETH1) 843 return ETH_POC(regs->eth_poc, 1); 844 if (caps & PIN_CFG_IO_VMC_QSPI) 845 return QSPI; 846 847 return -EINVAL; 848 } 849 850 static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps) 851 { 852 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 853 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 854 int pwr_reg; 855 u8 val; 856 857 if (caps & PIN_CFG_SOFT_PS) 858 return pctrl->settings[pin].power_source; 859 860 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); 861 if (pwr_reg < 0) 862 return pwr_reg; 863 864 val = readb(pctrl->base + pwr_reg); 865 switch (val) { 866 case PVDD_1800: 867 return 1800; 868 case PVDD_2500: 869 return 2500; 870 case PVDD_3300: 871 return 3300; 872 default: 873 /* Should not happen. */ 874 return -EINVAL; 875 } 876 } 877 878 static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps) 879 { 880 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 881 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 882 int pwr_reg; 883 u8 val; 884 885 if (caps & PIN_CFG_SOFT_PS) { 886 pctrl->settings[pin].power_source = ps; 887 return 0; 888 } 889 890 switch (ps) { 891 case 1800: 892 val = PVDD_1800; 893 break; 894 case 2500: 895 if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) 896 return -EINVAL; 897 val = PVDD_2500; 898 break; 899 case 3300: 900 val = PVDD_3300; 901 break; 902 default: 903 return -EINVAL; 904 } 905 906 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); 907 if (pwr_reg < 0) 908 return pwr_reg; 909 910 writeb(val, pctrl->base + pwr_reg); 911 pctrl->settings[pin].power_source = ps; 912 913 return 0; 914 } 915 916 static bool rzg2l_ps_is_supported(u16 ps) 917 { 918 unsigned int i; 919 920 for (i = 0; i < ARRAY_SIZE(available_ps); i++) { 921 if (available_ps[i] == ps) 922 return true; 923 } 924 925 return false; 926 } 927 928 static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps) 929 { 930 unsigned int i; 931 932 for (i = 0; i < ARRAY_SIZE(available_ps); i++) { 933 if (available_ps[i] == ps) 934 break; 935 } 936 937 /* 938 * We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have 939 * RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source 940 */ 941 return i * RZG2L_IOLH_MAX_DS_ENTRIES; 942 } 943 944 static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val) 945 { 946 if (caps & PIN_CFG_IOLH_A) 947 return hwcfg->iolh_groupa_ua[val]; 948 949 if (caps & PIN_CFG_IOLH_B) 950 return hwcfg->iolh_groupb_ua[val]; 951 952 if (caps & PIN_CFG_IOLH_C) 953 return hwcfg->iolh_groupc_ua[val]; 954 955 /* Should not happen. */ 956 return 0; 957 } 958 959 static int rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg *hwcfg, u32 caps, 960 enum rzg2l_iolh_index ps_index, u16 ua) 961 { 962 const u16 *array = NULL; 963 unsigned int i; 964 965 if (caps & PIN_CFG_IOLH_A) 966 array = &hwcfg->iolh_groupa_ua[ps_index]; 967 968 if (caps & PIN_CFG_IOLH_B) 969 array = &hwcfg->iolh_groupb_ua[ps_index]; 970 971 if (caps & PIN_CFG_IOLH_C) 972 array = &hwcfg->iolh_groupc_ua[ps_index]; 973 974 if (!array) 975 return -EINVAL; 976 977 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { 978 if (array[i] == ua) 979 return i; 980 } 981 982 return -EINVAL; 983 } 984 985 static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, 986 enum rzg2l_iolh_index iolh_idx, 987 u16 ds) 988 { 989 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 990 const u16 *array = NULL; 991 unsigned int i; 992 993 if (caps & PIN_CFG_IOLH_A) 994 array = hwcfg->iolh_groupa_ua; 995 996 if (caps & PIN_CFG_IOLH_B) 997 array = hwcfg->iolh_groupb_ua; 998 999 if (caps & PIN_CFG_IOLH_C) 1000 array = hwcfg->iolh_groupc_ua; 1001 1002 /* Should not happen. */ 1003 if (!array) 1004 return false; 1005 1006 if (!array[iolh_idx]) 1007 return false; 1008 1009 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { 1010 if (array[iolh_idx + i] == ds) 1011 return true; 1012 } 1013 1014 return false; 1015 } 1016 1017 static bool rzg2l_oen_is_supported(u32 caps, u8 pin, u8 max_pin) 1018 { 1019 if (!(caps & PIN_CFG_OEN)) 1020 return false; 1021 1022 if (pin > max_pin) 1023 return false; 1024 1025 return true; 1026 } 1027 1028 static u8 rzg2l_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port) 1029 { 1030 if (pin) 1031 pin *= 2; 1032 1033 if (offset / RZG2L_PINS_PER_PORT == max_port) 1034 pin += 1; 1035 1036 return pin; 1037 } 1038 1039 static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin) 1040 { 1041 u8 max_port = pctrl->data->hwcfg->oen_max_port; 1042 u8 max_pin = pctrl->data->hwcfg->oen_max_pin; 1043 u8 bit; 1044 1045 if (!rzg2l_oen_is_supported(caps, pin, max_pin)) 1046 return 0; 1047 1048 bit = rzg2l_pin_to_oen_bit(offset, pin, max_port); 1049 1050 return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); 1051 } 1052 1053 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen) 1054 { 1055 u8 max_port = pctrl->data->hwcfg->oen_max_port; 1056 u8 max_pin = pctrl->data->hwcfg->oen_max_pin; 1057 unsigned long flags; 1058 u8 val, bit; 1059 1060 if (!rzg2l_oen_is_supported(caps, pin, max_pin)) 1061 return -EINVAL; 1062 1063 bit = rzg2l_pin_to_oen_bit(offset, pin, max_port); 1064 1065 spin_lock_irqsave(&pctrl->lock, flags); 1066 val = readb(pctrl->base + ETH_MODE); 1067 if (oen) 1068 val &= ~BIT(bit); 1069 else 1070 val |= BIT(bit); 1071 writeb(val, pctrl->base + ETH_MODE); 1072 spin_unlock_irqrestore(&pctrl->lock, flags); 1073 1074 return 0; 1075 } 1076 1077 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 1078 unsigned int _pin, 1079 unsigned long *config) 1080 { 1081 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1082 enum pin_config_param param = pinconf_to_config_param(*config); 1083 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1084 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 1085 u64 *pin_data = pin->drv_data; 1086 unsigned int arg = 0; 1087 u32 off, cfg; 1088 int ret; 1089 u8 bit; 1090 1091 if (!pin_data) 1092 return -EINVAL; 1093 1094 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1095 cfg = FIELD_GET(PIN_CFG_MASK, *pin_data); 1096 if (*pin_data & RZG2L_SINGLE_PIN) { 1097 bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); 1098 } else { 1099 bit = RZG2L_PIN_ID_TO_PIN(_pin); 1100 1101 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 1102 return -EINVAL; 1103 } 1104 1105 switch (param) { 1106 case PIN_CONFIG_INPUT_ENABLE: 1107 if (!(cfg & PIN_CFG_IEN)) 1108 return -EINVAL; 1109 arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK); 1110 if (!arg) 1111 return -EINVAL; 1112 break; 1113 1114 case PIN_CONFIG_OUTPUT_ENABLE: 1115 arg = rzg2l_read_oen(pctrl, cfg, _pin, bit); 1116 if (!arg) 1117 return -EINVAL; 1118 break; 1119 1120 case PIN_CONFIG_POWER_SOURCE: 1121 ret = rzg2l_get_power_source(pctrl, _pin, cfg); 1122 if (ret < 0) 1123 return ret; 1124 arg = ret; 1125 break; 1126 1127 case PIN_CONFIG_DRIVE_STRENGTH: { 1128 unsigned int index; 1129 1130 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) 1131 return -EINVAL; 1132 1133 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1134 /* 1135 * Drive strenght mA is supported only by group A and only 1136 * for 3V3 port source. 1137 */ 1138 arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000; 1139 break; 1140 } 1141 1142 case PIN_CONFIG_DRIVE_STRENGTH_UA: { 1143 enum rzg2l_iolh_index iolh_idx; 1144 u8 val; 1145 1146 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || 1147 !hwcfg->drive_strength_ua) 1148 return -EINVAL; 1149 1150 ret = rzg2l_get_power_source(pctrl, _pin, cfg); 1151 if (ret < 0) 1152 return ret; 1153 iolh_idx = rzg2l_ps_to_iolh_idx(ret); 1154 val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1155 arg = rzg2l_iolh_val_to_ua(hwcfg, cfg, iolh_idx + val); 1156 break; 1157 } 1158 1159 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { 1160 unsigned int index; 1161 1162 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) 1163 return -EINVAL; 1164 1165 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1166 arg = hwcfg->iolh_groupb_oi[index]; 1167 break; 1168 } 1169 1170 default: 1171 return -ENOTSUPP; 1172 } 1173 1174 *config = pinconf_to_config_packed(param, arg); 1175 1176 return 0; 1177 }; 1178 1179 static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 1180 unsigned int _pin, 1181 unsigned long *_configs, 1182 unsigned int num_configs) 1183 { 1184 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1185 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 1186 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1187 struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; 1188 u64 *pin_data = pin->drv_data; 1189 enum pin_config_param param; 1190 unsigned int i, arg, index; 1191 u32 cfg, off; 1192 int ret; 1193 u8 bit; 1194 1195 if (!pin_data) 1196 return -EINVAL; 1197 1198 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1199 cfg = FIELD_GET(PIN_CFG_MASK, *pin_data); 1200 if (*pin_data & RZG2L_SINGLE_PIN) { 1201 bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); 1202 } else { 1203 bit = RZG2L_PIN_ID_TO_PIN(_pin); 1204 1205 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 1206 return -EINVAL; 1207 } 1208 1209 for (i = 0; i < num_configs; i++) { 1210 param = pinconf_to_config_param(_configs[i]); 1211 switch (param) { 1212 case PIN_CONFIG_INPUT_ENABLE: 1213 arg = pinconf_to_config_argument(_configs[i]); 1214 1215 if (!(cfg & PIN_CFG_IEN)) 1216 return -EINVAL; 1217 1218 rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg); 1219 break; 1220 1221 case PIN_CONFIG_OUTPUT_ENABLE: 1222 arg = pinconf_to_config_argument(_configs[i]); 1223 ret = rzg2l_write_oen(pctrl, cfg, _pin, bit, !!arg); 1224 if (ret) 1225 return ret; 1226 break; 1227 1228 case PIN_CONFIG_POWER_SOURCE: 1229 settings.power_source = pinconf_to_config_argument(_configs[i]); 1230 break; 1231 1232 case PIN_CONFIG_DRIVE_STRENGTH: 1233 arg = pinconf_to_config_argument(_configs[i]); 1234 1235 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) 1236 return -EINVAL; 1237 1238 for (index = RZG2L_IOLH_IDX_3V3; 1239 index < RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES; index++) { 1240 if (arg == (hwcfg->iolh_groupa_ua[index] / 1000)) 1241 break; 1242 } 1243 if (index == (RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES)) 1244 return -EINVAL; 1245 1246 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); 1247 break; 1248 1249 case PIN_CONFIG_DRIVE_STRENGTH_UA: 1250 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || 1251 !hwcfg->drive_strength_ua) 1252 return -EINVAL; 1253 1254 settings.drive_strength_ua = pinconf_to_config_argument(_configs[i]); 1255 break; 1256 1257 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: 1258 arg = pinconf_to_config_argument(_configs[i]); 1259 1260 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) 1261 return -EINVAL; 1262 1263 for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) { 1264 if (arg == hwcfg->iolh_groupb_oi[index]) 1265 break; 1266 } 1267 if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi)) 1268 return -EINVAL; 1269 1270 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); 1271 break; 1272 1273 default: 1274 return -EOPNOTSUPP; 1275 } 1276 } 1277 1278 /* Apply power source. */ 1279 if (settings.power_source != pctrl->settings[_pin].power_source) { 1280 ret = rzg2l_ps_is_supported(settings.power_source); 1281 if (!ret) 1282 return -EINVAL; 1283 1284 /* Apply power source. */ 1285 ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source); 1286 if (ret) 1287 return ret; 1288 } 1289 1290 /* Apply drive strength. */ 1291 if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) { 1292 enum rzg2l_iolh_index iolh_idx; 1293 int val; 1294 1295 iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source); 1296 ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx, 1297 settings.drive_strength_ua); 1298 if (!ret) 1299 return -EINVAL; 1300 1301 /* Get register value for this PS/DS tuple. */ 1302 val = rzg2l_iolh_ua_to_val(hwcfg, cfg, iolh_idx, settings.drive_strength_ua); 1303 if (val < 0) 1304 return val; 1305 1306 /* Apply drive strength. */ 1307 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val); 1308 pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua; 1309 } 1310 1311 return 0; 1312 } 1313 1314 static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, 1315 unsigned int group, 1316 unsigned long *configs, 1317 unsigned int num_configs) 1318 { 1319 const unsigned int *pins; 1320 unsigned int i, npins; 1321 int ret; 1322 1323 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 1324 if (ret) 1325 return ret; 1326 1327 for (i = 0; i < npins; i++) { 1328 ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs, 1329 num_configs); 1330 if (ret) 1331 return ret; 1332 } 1333 1334 return 0; 1335 }; 1336 1337 static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, 1338 unsigned int group, 1339 unsigned long *config) 1340 { 1341 const unsigned int *pins; 1342 unsigned int i, npins, prev_config = 0; 1343 int ret; 1344 1345 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 1346 if (ret) 1347 return ret; 1348 1349 for (i = 0; i < npins; i++) { 1350 ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config); 1351 if (ret) 1352 return ret; 1353 1354 /* Check config matching between to pin */ 1355 if (i && prev_config != *config) 1356 return -EOPNOTSUPP; 1357 1358 prev_config = *config; 1359 } 1360 1361 return 0; 1362 }; 1363 1364 static const struct pinctrl_ops rzg2l_pinctrl_pctlops = { 1365 .get_groups_count = pinctrl_generic_get_group_count, 1366 .get_group_name = pinctrl_generic_get_group_name, 1367 .get_group_pins = pinctrl_generic_get_group_pins, 1368 .dt_node_to_map = rzg2l_dt_node_to_map, 1369 .dt_free_map = rzg2l_dt_free_map, 1370 }; 1371 1372 static const struct pinmux_ops rzg2l_pinctrl_pmxops = { 1373 .get_functions_count = pinmux_generic_get_function_count, 1374 .get_function_name = pinmux_generic_get_function_name, 1375 .get_function_groups = pinmux_generic_get_function_groups, 1376 .set_mux = rzg2l_pinctrl_set_mux, 1377 .strict = true, 1378 }; 1379 1380 static const struct pinconf_ops rzg2l_pinctrl_confops = { 1381 .is_generic = true, 1382 .pin_config_get = rzg2l_pinctrl_pinconf_get, 1383 .pin_config_set = rzg2l_pinctrl_pinconf_set, 1384 .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set, 1385 .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get, 1386 .pin_config_config_dbg_show = pinconf_generic_dump_config, 1387 }; 1388 1389 static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) 1390 { 1391 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1392 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1393 u64 *pin_data = pin_desc->drv_data; 1394 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1395 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 1396 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1397 unsigned long flags; 1398 u8 reg8; 1399 int ret; 1400 1401 ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit); 1402 if (ret) 1403 return ret; 1404 1405 ret = pinctrl_gpio_request(chip, offset); 1406 if (ret) 1407 return ret; 1408 1409 spin_lock_irqsave(&pctrl->lock, flags); 1410 1411 /* Select GPIO mode in PMC Register */ 1412 reg8 = readb(pctrl->base + PMC(off)); 1413 reg8 &= ~BIT(bit); 1414 writeb(reg8, pctrl->base + PMC(off)); 1415 1416 spin_unlock_irqrestore(&pctrl->lock, flags); 1417 1418 return 0; 1419 } 1420 1421 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, 1422 bool output) 1423 { 1424 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1425 u64 *pin_data = pin_desc->drv_data; 1426 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1427 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1428 unsigned long flags; 1429 u16 reg16; 1430 1431 spin_lock_irqsave(&pctrl->lock, flags); 1432 1433 reg16 = readw(pctrl->base + PM(off)); 1434 reg16 &= ~(PM_MASK << (bit * 2)); 1435 1436 reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); 1437 writew(reg16, pctrl->base + PM(off)); 1438 1439 spin_unlock_irqrestore(&pctrl->lock, flags); 1440 } 1441 1442 static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1443 { 1444 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1445 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1446 u64 *pin_data = pin_desc->drv_data; 1447 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1448 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1449 1450 if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) { 1451 u16 reg16; 1452 1453 reg16 = readw(pctrl->base + PM(off)); 1454 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 1455 if (reg16 == PM_OUTPUT) 1456 return GPIO_LINE_DIRECTION_OUT; 1457 } 1458 1459 return GPIO_LINE_DIRECTION_IN; 1460 } 1461 1462 static int rzg2l_gpio_direction_input(struct gpio_chip *chip, 1463 unsigned int offset) 1464 { 1465 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1466 1467 rzg2l_gpio_set_direction(pctrl, offset, false); 1468 1469 return 0; 1470 } 1471 1472 static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, 1473 int value) 1474 { 1475 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1476 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1477 u64 *pin_data = pin_desc->drv_data; 1478 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1479 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1480 unsigned long flags; 1481 u8 reg8; 1482 1483 spin_lock_irqsave(&pctrl->lock, flags); 1484 1485 reg8 = readb(pctrl->base + P(off)); 1486 1487 if (value) 1488 writeb(reg8 | BIT(bit), pctrl->base + P(off)); 1489 else 1490 writeb(reg8 & ~BIT(bit), pctrl->base + P(off)); 1491 1492 spin_unlock_irqrestore(&pctrl->lock, flags); 1493 } 1494 1495 static int rzg2l_gpio_direction_output(struct gpio_chip *chip, 1496 unsigned int offset, int value) 1497 { 1498 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1499 1500 rzg2l_gpio_set(chip, offset, value); 1501 rzg2l_gpio_set_direction(pctrl, offset, true); 1502 1503 return 0; 1504 } 1505 1506 static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) 1507 { 1508 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1509 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1510 u64 *pin_data = pin_desc->drv_data; 1511 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1512 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1513 u16 reg16; 1514 1515 reg16 = readw(pctrl->base + PM(off)); 1516 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 1517 1518 if (reg16 == PM_INPUT) 1519 return !!(readb(pctrl->base + PIN(off)) & BIT(bit)); 1520 else if (reg16 == PM_OUTPUT) 1521 return !!(readb(pctrl->base + P(off)) & BIT(bit)); 1522 else 1523 return -EINVAL; 1524 } 1525 1526 static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) 1527 { 1528 unsigned int virq; 1529 1530 pinctrl_gpio_free(chip, offset); 1531 1532 virq = irq_find_mapping(chip->irq.domain, offset); 1533 if (virq) 1534 irq_dispose_mapping(virq); 1535 1536 /* 1537 * Set the GPIO as an input to ensure that the next GPIO request won't 1538 * drive the GPIO pin as an output. 1539 */ 1540 rzg2l_gpio_direction_input(chip, offset); 1541 } 1542 1543 static const char * const rzg2l_gpio_names[] = { 1544 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", 1545 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", 1546 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", 1547 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", 1548 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", 1549 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", 1550 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", 1551 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", 1552 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", 1553 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", 1554 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", 1555 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", 1556 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", 1557 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", 1558 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", 1559 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", 1560 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", 1561 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", 1562 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", 1563 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", 1564 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", 1565 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", 1566 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", 1567 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", 1568 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", 1569 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", 1570 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", 1571 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", 1572 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", 1573 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", 1574 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", 1575 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", 1576 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", 1577 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", 1578 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", 1579 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", 1580 "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7", 1581 "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7", 1582 "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7", 1583 "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7", 1584 "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7", 1585 "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7", 1586 "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7", 1587 "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7", 1588 "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7", 1589 "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7", 1590 "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7", 1591 "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7", 1592 "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", 1593 }; 1594 1595 static const u64 r9a07g044_gpio_configs[] = { 1596 RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), 1597 RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), 1598 RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), 1599 RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS), 1600 RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS), 1601 RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS), 1602 RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS), 1603 RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS), 1604 RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS), 1605 RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS), 1606 RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS), 1607 RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS), 1608 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 1609 RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS), 1610 RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), 1611 RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), 1612 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 1613 RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), 1614 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), 1615 RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), 1616 RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1617 RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1618 RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1619 RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1620 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1621 RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1622 RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1623 RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1624 RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1625 RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1626 RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1627 RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1628 RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1629 RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1630 RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1631 RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1632 RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1633 RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1634 RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), 1635 RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), 1636 RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), 1637 RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS), 1638 RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS), 1639 RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS), 1640 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS), 1641 RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS), 1642 RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS), 1643 RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS), 1644 RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), 1645 }; 1646 1647 static const u64 r9a07g043_gpio_configs[] = { 1648 RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), 1649 RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1650 RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1651 RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1652 RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1653 RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS), 1654 RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS), 1655 RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1656 RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1657 RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1658 RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1659 RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS), 1660 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 1661 RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS), 1662 RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS), 1663 RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS), 1664 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 1665 RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), 1666 RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), 1667 #ifdef CONFIG_RISCV 1668 /* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */ 1669 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 1670 PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | 1671 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */ 1672 RZG2L_GPIO_PORT_PACK(8, 0x07, PIN_CFG_VARIABLE), /* P20 */ 1673 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 1674 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */ 1675 RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 1676 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */ 1677 RZG2L_GPIO_PORT_SPARSE_PACK(0x3e, 0x0a, PIN_CFG_VARIABLE), /* P23 */ 1678 RZG2L_GPIO_PORT_PACK(6, 0x0b, PIN_CFG_VARIABLE), /* P24 */ 1679 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_FILONOFF | 1680 PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | 1681 PIN_CFG_NOGPIO_INT), /* P25 */ 1682 0x0, /* P26 */ 1683 0x0, /* P27 */ 1684 RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO_INT), /* P28 */ 1685 #endif 1686 }; 1687 1688 static const u64 r9a08g045_gpio_configs[] = { 1689 RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ 1690 RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1691 PIN_CFG_IO_VMC_ETH0)) | 1692 PIN_CFG_OEN | PIN_CFG_IEN, /* P1 */ 1693 RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1694 PIN_CFG_IO_VMC_ETH0)), /* P2 */ 1695 RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1696 PIN_CFG_IO_VMC_ETH0)), /* P3 */ 1697 RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1698 PIN_CFG_IO_VMC_ETH0)), /* P4 */ 1699 RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */ 1700 RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */ 1701 RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1702 PIN_CFG_IO_VMC_ETH1)) | 1703 PIN_CFG_OEN | PIN_CFG_IEN, /* P7 */ 1704 RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1705 PIN_CFG_IO_VMC_ETH1)), /* P8 */ 1706 RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1707 PIN_CFG_IO_VMC_ETH1)), /* P9 */ 1708 RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1709 PIN_CFG_IO_VMC_ETH1)), /* P10 */ 1710 RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */ 1711 RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */ 1712 RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */ 1713 RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */ 1714 RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */ 1715 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */ 1716 RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */ 1717 RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */ 1718 }; 1719 1720 static const struct { 1721 struct rzg2l_dedicated_configs common[35]; 1722 struct rzg2l_dedicated_configs rzg2l_pins[7]; 1723 } rzg2l_dedicated_pins = { 1724 .common = { 1725 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, 1726 (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, 1727 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, 1728 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 1729 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, 1730 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 1731 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, 1732 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, 1733 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, 1734 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 1735 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, 1736 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1737 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, 1738 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 1739 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, 1740 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1741 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, 1742 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1743 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, 1744 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1745 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, 1746 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1747 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, 1748 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1749 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, 1750 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1751 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, 1752 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1753 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, 1754 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1755 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, 1756 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, 1757 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, 1758 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1759 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, 1760 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1761 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, 1762 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1763 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, 1764 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1765 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, 1766 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1767 { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, 1768 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1769 { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, 1770 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1771 { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, 1772 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1773 { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, 1774 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1775 { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, 1776 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1777 { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, 1778 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1779 { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, 1780 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1781 { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, 1782 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1783 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, 1784 { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, 1785 { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, 1786 { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, 1787 { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, 1788 }, 1789 .rzg2l_pins = { 1790 { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1791 { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, 1792 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1793 { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, 1794 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1795 { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, 1796 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1797 { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, 1798 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1799 { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, 1800 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1801 { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, 1802 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1803 } 1804 }; 1805 1806 static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = { 1807 { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | 1808 PIN_CFG_FILCLKSEL)) }, 1809 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN | 1810 PIN_CFG_SOFT_PS)) }, 1811 { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) }, 1812 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) }, 1813 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, 1814 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1815 PIN_CFG_IO_VMC_SD0)) }, 1816 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, 1817 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1818 PIN_CFG_IO_VMC_SD0)) }, 1819 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1820 PIN_CFG_IO_VMC_SD0)) }, 1821 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1822 PIN_CFG_IO_VMC_SD0)) }, 1823 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1824 PIN_CFG_IO_VMC_SD0)) }, 1825 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1826 PIN_CFG_IO_VMC_SD0)) }, 1827 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1828 PIN_CFG_IO_VMC_SD0)) }, 1829 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1830 PIN_CFG_IO_VMC_SD0)) }, 1831 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1832 PIN_CFG_IO_VMC_SD0)) }, 1833 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) }, 1834 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1835 PIN_CFG_IO_VMC_SD1)) }, 1836 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1837 PIN_CFG_IO_VMC_SD1)) }, 1838 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1839 PIN_CFG_IO_VMC_SD1)) }, 1840 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1841 PIN_CFG_IO_VMC_SD1)) }, 1842 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1843 PIN_CFG_IO_VMC_SD1)) }, 1844 }; 1845 1846 static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) 1847 { 1848 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; 1849 const struct rzg2l_pinctrl_data *data = pctrl->data; 1850 u64 *pin_data = pin_desc->drv_data; 1851 unsigned int gpioint; 1852 unsigned int i; 1853 u32 port, bit; 1854 1855 if (*pin_data & PIN_CFG_NOGPIO_INT) 1856 return -EINVAL; 1857 1858 port = virq / 8; 1859 bit = virq % 8; 1860 1861 if (port >= data->n_ports || 1862 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port]))) 1863 return -EINVAL; 1864 1865 gpioint = bit; 1866 for (i = 0; i < port; i++) 1867 gpioint += hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[i])); 1868 1869 return gpioint; 1870 } 1871 1872 static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, 1873 unsigned int hwirq, bool enable) 1874 { 1875 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; 1876 u64 *pin_data = pin_desc->drv_data; 1877 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1878 u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); 1879 unsigned long flags; 1880 void __iomem *addr; 1881 1882 addr = pctrl->base + ISEL(off); 1883 if (bit >= 4) { 1884 bit -= 4; 1885 addr += 4; 1886 } 1887 1888 spin_lock_irqsave(&pctrl->lock, flags); 1889 if (enable) 1890 writel(readl(addr) | BIT(bit * 8), addr); 1891 else 1892 writel(readl(addr) & ~BIT(bit * 8), addr); 1893 spin_unlock_irqrestore(&pctrl->lock, flags); 1894 } 1895 1896 static void rzg2l_gpio_irq_disable(struct irq_data *d) 1897 { 1898 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1899 unsigned int hwirq = irqd_to_hwirq(d); 1900 1901 irq_chip_disable_parent(d); 1902 gpiochip_disable_irq(gc, hwirq); 1903 } 1904 1905 static void rzg2l_gpio_irq_enable(struct irq_data *d) 1906 { 1907 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1908 unsigned int hwirq = irqd_to_hwirq(d); 1909 1910 gpiochip_enable_irq(gc, hwirq); 1911 irq_chip_enable_parent(d); 1912 } 1913 1914 static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type) 1915 { 1916 return irq_chip_set_type_parent(d, type); 1917 } 1918 1919 static void rzg2l_gpio_irqc_eoi(struct irq_data *d) 1920 { 1921 irq_chip_eoi_parent(d); 1922 } 1923 1924 static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) 1925 { 1926 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 1927 1928 seq_printf(p, dev_name(gc->parent)); 1929 } 1930 1931 static int rzg2l_gpio_irq_set_wake(struct irq_data *data, unsigned int on) 1932 { 1933 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 1934 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 1935 int ret; 1936 1937 /* It should not happen. */ 1938 if (!data->parent_data) 1939 return -EOPNOTSUPP; 1940 1941 ret = irq_chip_set_wake_parent(data, on); 1942 if (ret) 1943 return ret; 1944 1945 if (on) 1946 atomic_inc(&pctrl->wakeup_path); 1947 else 1948 atomic_dec(&pctrl->wakeup_path); 1949 1950 return 0; 1951 } 1952 1953 static const struct irq_chip rzg2l_gpio_irqchip = { 1954 .name = "rzg2l-gpio", 1955 .irq_disable = rzg2l_gpio_irq_disable, 1956 .irq_enable = rzg2l_gpio_irq_enable, 1957 .irq_mask = irq_chip_mask_parent, 1958 .irq_unmask = irq_chip_unmask_parent, 1959 .irq_set_type = rzg2l_gpio_irq_set_type, 1960 .irq_eoi = rzg2l_gpio_irqc_eoi, 1961 .irq_print_chip = rzg2l_gpio_irq_print_chip, 1962 .irq_set_affinity = irq_chip_set_affinity_parent, 1963 .irq_set_wake = rzg2l_gpio_irq_set_wake, 1964 .flags = IRQCHIP_IMMUTABLE, 1965 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1966 }; 1967 1968 static int rzg2l_gpio_interrupt_input_mode(struct gpio_chip *chip, unsigned int offset) 1969 { 1970 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1971 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1972 u64 *pin_data = pin_desc->drv_data; 1973 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1974 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1975 u8 reg8; 1976 int ret; 1977 1978 reg8 = readb(pctrl->base + PMC(off)); 1979 if (reg8 & BIT(bit)) { 1980 ret = rzg2l_gpio_request(chip, offset); 1981 if (ret) 1982 return ret; 1983 } 1984 1985 return rzg2l_gpio_direction_input(chip, offset); 1986 } 1987 1988 static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 1989 unsigned int child, 1990 unsigned int child_type, 1991 unsigned int *parent, 1992 unsigned int *parent_type) 1993 { 1994 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 1995 unsigned long flags; 1996 int gpioint, irq; 1997 int ret; 1998 1999 gpioint = rzg2l_gpio_get_gpioint(child, pctrl); 2000 if (gpioint < 0) 2001 return gpioint; 2002 2003 ret = rzg2l_gpio_interrupt_input_mode(gc, child); 2004 if (ret) 2005 return ret; 2006 2007 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 2008 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); 2009 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 2010 if (irq < 0) { 2011 ret = -ENOSPC; 2012 goto err; 2013 } 2014 2015 rzg2l_gpio_irq_endisable(pctrl, child, true); 2016 pctrl->hwirq[irq] = child; 2017 irq += RZG2L_TINT_IRQ_START_INDEX; 2018 2019 /* All these interrupts are level high in the CPU */ 2020 *parent_type = IRQ_TYPE_LEVEL_HIGH; 2021 *parent = RZG2L_PACK_HWIRQ(gpioint, irq); 2022 return 0; 2023 2024 err: 2025 rzg2l_gpio_free(gc, child); 2026 return ret; 2027 } 2028 2029 static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip, 2030 union gpio_irq_fwspec *gfwspec, 2031 unsigned int parent_hwirq, 2032 unsigned int parent_type) 2033 { 2034 struct irq_fwspec *fwspec = &gfwspec->fwspec; 2035 2036 fwspec->fwnode = chip->irq.parent_domain->fwnode; 2037 fwspec->param_count = 2; 2038 fwspec->param[0] = parent_hwirq; 2039 fwspec->param[1] = parent_type; 2040 2041 return 0; 2042 } 2043 2044 static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) 2045 { 2046 struct irq_domain *domain = pctrl->gpio_chip.irq.domain; 2047 2048 for (unsigned int i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { 2049 struct irq_data *data; 2050 unsigned long flags; 2051 unsigned int virq; 2052 int ret; 2053 2054 if (!pctrl->hwirq[i]) 2055 continue; 2056 2057 virq = irq_find_mapping(domain, pctrl->hwirq[i]); 2058 if (!virq) { 2059 dev_crit(pctrl->dev, "Failed to find IRQ mapping for hwirq %u\n", 2060 pctrl->hwirq[i]); 2061 continue; 2062 } 2063 2064 data = irq_domain_get_irq_data(domain, virq); 2065 if (!data) { 2066 dev_crit(pctrl->dev, "Failed to get IRQ data for virq=%u\n", virq); 2067 continue; 2068 } 2069 2070 /* 2071 * This has to be atomically executed to protect against a concurrent 2072 * interrupt. 2073 */ 2074 spin_lock_irqsave(&pctrl->lock, flags); 2075 ret = rzg2l_gpio_irq_set_type(data, irqd_get_trigger_type(data)); 2076 if (!ret && !irqd_irq_disabled(data)) 2077 rzg2l_gpio_irq_enable(data); 2078 spin_unlock_irqrestore(&pctrl->lock, flags); 2079 2080 if (ret) 2081 dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq); 2082 } 2083 } 2084 2085 static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, 2086 unsigned int nr_irqs) 2087 { 2088 struct irq_data *d; 2089 2090 d = irq_domain_get_irq_data(domain, virq); 2091 if (d) { 2092 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 2093 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 2094 irq_hw_number_t hwirq = irqd_to_hwirq(d); 2095 unsigned long flags; 2096 unsigned int i; 2097 2098 for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { 2099 if (pctrl->hwirq[i] == hwirq) { 2100 rzg2l_gpio_irq_endisable(pctrl, hwirq, false); 2101 rzg2l_gpio_free(gc, hwirq); 2102 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 2103 bitmap_release_region(pctrl->tint_slot, i, get_order(1)); 2104 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 2105 pctrl->hwirq[i] = 0; 2106 break; 2107 } 2108 } 2109 } 2110 irq_domain_free_irqs_common(domain, virq, nr_irqs); 2111 } 2112 2113 static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, 2114 unsigned long *valid_mask, 2115 unsigned int ngpios) 2116 { 2117 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 2118 struct gpio_chip *chip = &pctrl->gpio_chip; 2119 unsigned int offset; 2120 2121 /* Forbid unused lines to be mapped as IRQs */ 2122 for (offset = 0; offset < chip->ngpio; offset++) { 2123 u32 port, bit; 2124 2125 port = offset / 8; 2126 bit = offset % 8; 2127 2128 if (port >= pctrl->data->n_ports || 2129 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, 2130 pctrl->data->port_pin_configs[port]))) 2131 clear_bit(offset, valid_mask); 2132 } 2133 } 2134 2135 static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) 2136 { 2137 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; 2138 struct rzg2l_pinctrl_reg_cache *cache, *dedicated_cache; 2139 2140 cache = devm_kzalloc(pctrl->dev, sizeof(*cache), GFP_KERNEL); 2141 if (!cache) 2142 return -ENOMEM; 2143 2144 dedicated_cache = devm_kzalloc(pctrl->dev, sizeof(*dedicated_cache), GFP_KERNEL); 2145 if (!dedicated_cache) 2146 return -ENOMEM; 2147 2148 cache->p = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->p), GFP_KERNEL); 2149 if (!cache->p) 2150 return -ENOMEM; 2151 2152 cache->pm = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pm), GFP_KERNEL); 2153 if (!cache->pm) 2154 return -ENOMEM; 2155 2156 cache->pmc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pmc), GFP_KERNEL); 2157 if (!cache->pmc) 2158 return -ENOMEM; 2159 2160 cache->pfc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pfc), GFP_KERNEL); 2161 if (!cache->pfc) 2162 return -ENOMEM; 2163 2164 for (u8 i = 0; i < 2; i++) { 2165 u32 n_dedicated_pins = pctrl->data->n_dedicated_pins; 2166 2167 cache->iolh[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->iolh[i]), 2168 GFP_KERNEL); 2169 if (!cache->iolh[i]) 2170 return -ENOMEM; 2171 2172 cache->ien[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->ien[i]), 2173 GFP_KERNEL); 2174 if (!cache->ien[i]) 2175 return -ENOMEM; 2176 2177 /* Allocate dedicated cache. */ 2178 dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, 2179 sizeof(*dedicated_cache->iolh[i]), 2180 GFP_KERNEL); 2181 if (!dedicated_cache->iolh[i]) 2182 return -ENOMEM; 2183 2184 dedicated_cache->ien[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, 2185 sizeof(*dedicated_cache->ien[i]), 2186 GFP_KERNEL); 2187 if (!dedicated_cache->ien[i]) 2188 return -ENOMEM; 2189 } 2190 2191 pctrl->cache = cache; 2192 pctrl->dedicated_cache = dedicated_cache; 2193 2194 return 0; 2195 } 2196 2197 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) 2198 { 2199 struct device_node *np = pctrl->dev->of_node; 2200 struct gpio_chip *chip = &pctrl->gpio_chip; 2201 const char *name = dev_name(pctrl->dev); 2202 struct irq_domain *parent_domain; 2203 struct of_phandle_args of_args; 2204 struct device_node *parent_np; 2205 struct gpio_irq_chip *girq; 2206 int ret; 2207 2208 parent_np = of_irq_find_parent(np); 2209 if (!parent_np) 2210 return -ENXIO; 2211 2212 parent_domain = irq_find_host(parent_np); 2213 of_node_put(parent_np); 2214 if (!parent_domain) 2215 return -EPROBE_DEFER; 2216 2217 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); 2218 if (ret) { 2219 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); 2220 return ret; 2221 } 2222 2223 if (of_args.args[0] != 0 || of_args.args[1] != 0 || 2224 of_args.args[2] != pctrl->data->n_port_pins) { 2225 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); 2226 return -EINVAL; 2227 } 2228 2229 chip->names = pctrl->data->port_pins; 2230 chip->request = rzg2l_gpio_request; 2231 chip->free = rzg2l_gpio_free; 2232 chip->get_direction = rzg2l_gpio_get_direction; 2233 chip->direction_input = rzg2l_gpio_direction_input; 2234 chip->direction_output = rzg2l_gpio_direction_output; 2235 chip->get = rzg2l_gpio_get; 2236 chip->set = rzg2l_gpio_set; 2237 chip->label = name; 2238 chip->parent = pctrl->dev; 2239 chip->owner = THIS_MODULE; 2240 chip->base = -1; 2241 chip->ngpio = of_args.args[2]; 2242 2243 girq = &chip->irq; 2244 gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip); 2245 girq->fwnode = of_node_to_fwnode(np); 2246 girq->parent_domain = parent_domain; 2247 girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; 2248 girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec; 2249 girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; 2250 girq->init_valid_mask = rzg2l_init_irq_valid_mask; 2251 2252 pctrl->gpio_range.id = 0; 2253 pctrl->gpio_range.pin_base = 0; 2254 pctrl->gpio_range.base = 0; 2255 pctrl->gpio_range.npins = chip->ngpio; 2256 pctrl->gpio_range.name = chip->label; 2257 pctrl->gpio_range.gc = chip; 2258 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 2259 if (ret) { 2260 dev_err(pctrl->dev, "failed to add GPIO controller\n"); 2261 return ret; 2262 } 2263 2264 dev_dbg(pctrl->dev, "Registered gpio controller\n"); 2265 2266 return 0; 2267 } 2268 2269 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) 2270 { 2271 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 2272 struct pinctrl_pin_desc *pins; 2273 unsigned int i, j; 2274 u64 *pin_data; 2275 int ret; 2276 2277 pctrl->desc.name = DRV_NAME; 2278 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; 2279 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; 2280 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; 2281 pctrl->desc.confops = &rzg2l_pinctrl_confops; 2282 pctrl->desc.owner = THIS_MODULE; 2283 2284 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); 2285 if (!pins) 2286 return -ENOMEM; 2287 2288 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, 2289 sizeof(*pin_data), GFP_KERNEL); 2290 if (!pin_data) 2291 return -ENOMEM; 2292 2293 pctrl->pins = pins; 2294 pctrl->desc.pins = pins; 2295 2296 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { 2297 pins[i].number = i; 2298 pins[i].name = pctrl->data->port_pins[i]; 2299 if (i && !(i % RZG2L_PINS_PER_PORT)) 2300 j++; 2301 pin_data[i] = pctrl->data->port_pin_configs[j]; 2302 #ifdef CONFIG_RISCV 2303 if (pin_data[i] & PIN_CFG_VARIABLE) 2304 pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl, 2305 pin_data[i], 2306 j, 2307 i % RZG2L_PINS_PER_PORT); 2308 #endif 2309 pins[i].drv_data = &pin_data[i]; 2310 } 2311 2312 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { 2313 unsigned int index = pctrl->data->n_port_pins + i; 2314 2315 pins[index].number = index; 2316 pins[index].name = pctrl->data->dedicated_pins[i].name; 2317 pin_data[index] = pctrl->data->dedicated_pins[i].config; 2318 pins[index].drv_data = &pin_data[index]; 2319 } 2320 2321 pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings), 2322 GFP_KERNEL); 2323 if (!pctrl->settings) 2324 return -ENOMEM; 2325 2326 for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) { 2327 if (pin_data[i] & PIN_CFG_SOFT_PS) { 2328 pctrl->settings[i].power_source = 3300; 2329 } else { 2330 ret = rzg2l_get_power_source(pctrl, i, pin_data[i]); 2331 if (ret < 0) 2332 continue; 2333 pctrl->settings[i].power_source = ret; 2334 } 2335 } 2336 2337 ret = rzg2l_pinctrl_reg_cache_alloc(pctrl); 2338 if (ret) 2339 return ret; 2340 2341 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, 2342 &pctrl->pctl); 2343 if (ret) { 2344 dev_err(pctrl->dev, "pinctrl registration failed\n"); 2345 return ret; 2346 } 2347 2348 ret = pinctrl_enable(pctrl->pctl); 2349 if (ret) { 2350 dev_err(pctrl->dev, "pinctrl enable failed\n"); 2351 return ret; 2352 } 2353 2354 ret = rzg2l_gpio_register(pctrl); 2355 if (ret) { 2356 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret); 2357 return ret; 2358 } 2359 2360 return 0; 2361 } 2362 2363 static int rzg2l_pinctrl_probe(struct platform_device *pdev) 2364 { 2365 struct rzg2l_pinctrl *pctrl; 2366 int ret; 2367 2368 BUILD_BUG_ON(ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT > 2369 ARRAY_SIZE(rzg2l_gpio_names)); 2370 2371 BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT > 2372 ARRAY_SIZE(rzg2l_gpio_names)); 2373 2374 BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT > 2375 ARRAY_SIZE(rzg2l_gpio_names)); 2376 2377 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 2378 if (!pctrl) 2379 return -ENOMEM; 2380 2381 pctrl->dev = &pdev->dev; 2382 2383 pctrl->data = of_device_get_match_data(&pdev->dev); 2384 if (!pctrl->data) 2385 return -EINVAL; 2386 2387 pctrl->base = devm_platform_ioremap_resource(pdev, 0); 2388 if (IS_ERR(pctrl->base)) 2389 return PTR_ERR(pctrl->base); 2390 2391 pctrl->clk = devm_clk_get_enabled(pctrl->dev, NULL); 2392 if (IS_ERR(pctrl->clk)) { 2393 return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->clk), 2394 "failed to enable GPIO clk\n"); 2395 } 2396 2397 spin_lock_init(&pctrl->lock); 2398 spin_lock_init(&pctrl->bitmap_lock); 2399 mutex_init(&pctrl->mutex); 2400 atomic_set(&pctrl->wakeup_path, 0); 2401 2402 platform_set_drvdata(pdev, pctrl); 2403 2404 ret = rzg2l_pinctrl_register(pctrl); 2405 if (ret) 2406 return ret; 2407 2408 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); 2409 return 0; 2410 } 2411 2412 static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspend) 2413 { 2414 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; 2415 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 2416 2417 for (u32 port = 0; port < nports; port++) { 2418 bool has_iolh, has_ien; 2419 u32 off, caps; 2420 u8 pincnt; 2421 u64 cfg; 2422 2423 cfg = pctrl->data->port_pin_configs[port]; 2424 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 2425 pincnt = hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg)); 2426 2427 caps = FIELD_GET(PIN_CFG_MASK, cfg); 2428 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); 2429 has_ien = !!(caps & PIN_CFG_IEN); 2430 2431 if (suspend) 2432 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]); 2433 2434 /* 2435 * Now cache the registers or set them in the order suggested by 2436 * HW manual (section "Operation for GPIO Function"). 2437 */ 2438 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]); 2439 if (has_iolh) { 2440 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), 2441 cache->iolh[0][port]); 2442 if (pincnt >= 4) { 2443 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off) + 4, 2444 cache->iolh[1][port]); 2445 } 2446 } 2447 2448 RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]); 2449 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]); 2450 2451 if (has_ien) { 2452 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), 2453 cache->ien[0][port]); 2454 if (pincnt >= 4) { 2455 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off) + 4, 2456 cache->ien[1][port]); 2457 } 2458 } 2459 } 2460 } 2461 2462 static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend) 2463 { 2464 struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache; 2465 2466 /* 2467 * Make sure entries in pctrl->data->n_dedicated_pins[] having the same 2468 * port offset are close together. 2469 */ 2470 for (u32 i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) { 2471 bool has_iolh, has_ien; 2472 u32 off, next_off = 0; 2473 u64 cfg, next_cfg; 2474 u8 pincnt; 2475 2476 cfg = pctrl->data->dedicated_pins[i].config; 2477 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 2478 if (i + 1 < pctrl->data->n_dedicated_pins) { 2479 next_cfg = pctrl->data->dedicated_pins[i + 1].config; 2480 next_off = RZG2L_PIN_CFG_TO_PORT_OFFSET(next_cfg); 2481 } 2482 2483 if (off == next_off) { 2484 /* Gather caps of all port pins. */ 2485 caps |= FIELD_GET(PIN_CFG_MASK, cfg); 2486 continue; 2487 } 2488 2489 /* And apply them in a single shot. */ 2490 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); 2491 has_ien = !!(caps & PIN_CFG_IEN); 2492 pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg)); 2493 2494 if (has_iolh) { 2495 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), 2496 cache->iolh[0][i]); 2497 } 2498 if (has_ien) { 2499 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), 2500 cache->ien[0][i]); 2501 } 2502 2503 if (pincnt >= 4) { 2504 if (has_iolh) { 2505 RZG2L_PCTRL_REG_ACCESS32(suspend, 2506 pctrl->base + IOLH(off) + 4, 2507 cache->iolh[1][i]); 2508 } 2509 if (has_ien) { 2510 RZG2L_PCTRL_REG_ACCESS32(suspend, 2511 pctrl->base + IEN(off) + 4, 2512 cache->ien[1][i]); 2513 } 2514 } 2515 caps = 0; 2516 } 2517 } 2518 2519 static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) 2520 { 2521 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; 2522 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 2523 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 2524 2525 /* Set the PWPR register to allow PFC register to write. */ 2526 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ 2527 writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ 2528 2529 /* Restore port registers. */ 2530 for (u32 port = 0; port < nports; port++) { 2531 unsigned long pinmap; 2532 u8 pmc = 0, max_pin; 2533 u32 off, pfc = 0; 2534 u64 cfg; 2535 u16 pm; 2536 u8 pin; 2537 2538 cfg = pctrl->data->port_pin_configs[port]; 2539 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 2540 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg); 2541 max_pin = fls(pinmap); 2542 2543 pm = readw(pctrl->base + PM(off)); 2544 for_each_set_bit(pin, &pinmap, max_pin) { 2545 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 2546 2547 /* Nothing to do if PFC was not configured before. */ 2548 if (!(cache->pmc[port] & BIT(pin))) 2549 continue; 2550 2551 /* Set pin to 'Non-use (Hi-Z input protection)' */ 2552 pm &= ~(PM_MASK << (pin * 2)); 2553 writew(pm, pctrl->base + PM(off)); 2554 2555 /* Temporarily switch to GPIO mode with PMC register */ 2556 pmc &= ~BIT(pin); 2557 writeb(pmc, pctrl->base + PMC(off)); 2558 2559 /* Select Pin function mode. */ 2560 pfc &= ~(PFC_MASK << (pin * 4)); 2561 pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4))); 2562 writel(pfc, pctrl->base + PFC(off)); 2563 2564 /* Switch to Peripheral pin function. */ 2565 pmc |= BIT(pin); 2566 writeb(pmc, pctrl->base + PMC(off)); 2567 } 2568 } 2569 2570 /* Set the PWPR register to be write-protected. */ 2571 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ 2572 writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ 2573 } 2574 2575 static int rzg2l_pinctrl_suspend_noirq(struct device *dev) 2576 { 2577 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); 2578 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 2579 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 2580 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 2581 2582 rzg2l_pinctrl_pm_setup_regs(pctrl, true); 2583 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true); 2584 2585 for (u8 i = 0; i < 2; i++) { 2586 cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); 2587 cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); 2588 } 2589 2590 cache->qspi = readb(pctrl->base + QSPI); 2591 cache->eth_mode = readb(pctrl->base + ETH_MODE); 2592 2593 if (!atomic_read(&pctrl->wakeup_path)) 2594 clk_disable_unprepare(pctrl->clk); 2595 else 2596 device_set_wakeup_path(dev); 2597 2598 return 0; 2599 } 2600 2601 static int rzg2l_pinctrl_resume_noirq(struct device *dev) 2602 { 2603 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); 2604 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 2605 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 2606 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 2607 int ret; 2608 2609 if (!atomic_read(&pctrl->wakeup_path)) { 2610 ret = clk_prepare_enable(pctrl->clk); 2611 if (ret) 2612 return ret; 2613 } 2614 2615 writeb(cache->qspi, pctrl->base + QSPI); 2616 writeb(cache->eth_mode, pctrl->base + ETH_MODE); 2617 for (u8 i = 0; i < 2; i++) { 2618 writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); 2619 writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); 2620 } 2621 2622 rzg2l_pinctrl_pm_setup_pfc(pctrl); 2623 rzg2l_pinctrl_pm_setup_regs(pctrl, false); 2624 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, false); 2625 rzg2l_gpio_irq_restore(pctrl); 2626 2627 return 0; 2628 } 2629 2630 static const struct rzg2l_hwcfg rzg2l_hwcfg = { 2631 .regs = { 2632 .pwpr = 0x3014, 2633 .sd_ch = 0x3000, 2634 .eth_poc = 0x300c, 2635 }, 2636 .iolh_groupa_ua = { 2637 /* 3v3 power source */ 2638 [RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000, 2639 }, 2640 .iolh_groupb_oi = { 100, 66, 50, 33, }, 2641 }; 2642 2643 static const struct rzg2l_hwcfg rzg3s_hwcfg = { 2644 .regs = { 2645 .pwpr = 0x3000, 2646 .sd_ch = 0x3004, 2647 .eth_poc = 0x3010, 2648 }, 2649 .iolh_groupa_ua = { 2650 /* 1v8 power source */ 2651 [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000, 2652 /* 3v3 power source */ 2653 [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000, 2654 }, 2655 .iolh_groupb_ua = { 2656 /* 1v8 power source */ 2657 [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000, 2658 /* 3v3 power source */ 2659 [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000, 2660 }, 2661 .iolh_groupc_ua = { 2662 /* 1v8 power source */ 2663 [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800, 2664 /* 2v5 source */ 2665 [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100, 2666 /* 3v3 power source */ 2667 [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050, 2668 }, 2669 .drive_strength_ua = true, 2670 .func_base = 1, 2671 .oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */ 2672 .oen_max_port = 7, /* P7_1 is the maximum OEN port. */ 2673 }; 2674 2675 static struct rzg2l_pinctrl_data r9a07g043_data = { 2676 .port_pins = rzg2l_gpio_names, 2677 .port_pin_configs = r9a07g043_gpio_configs, 2678 .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs), 2679 .dedicated_pins = rzg2l_dedicated_pins.common, 2680 .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, 2681 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), 2682 .hwcfg = &rzg2l_hwcfg, 2683 #ifdef CONFIG_RISCV 2684 .variable_pin_cfg = r9a07g043f_variable_pin_cfg, 2685 .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg), 2686 #endif 2687 }; 2688 2689 static struct rzg2l_pinctrl_data r9a07g044_data = { 2690 .port_pins = rzg2l_gpio_names, 2691 .port_pin_configs = r9a07g044_gpio_configs, 2692 .n_ports = ARRAY_SIZE(r9a07g044_gpio_configs), 2693 .dedicated_pins = rzg2l_dedicated_pins.common, 2694 .n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT, 2695 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + 2696 ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), 2697 .hwcfg = &rzg2l_hwcfg, 2698 }; 2699 2700 static struct rzg2l_pinctrl_data r9a08g045_data = { 2701 .port_pins = rzg2l_gpio_names, 2702 .port_pin_configs = r9a08g045_gpio_configs, 2703 .n_ports = ARRAY_SIZE(r9a08g045_gpio_configs), 2704 .dedicated_pins = rzg3s_dedicated_pins, 2705 .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT, 2706 .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins), 2707 .hwcfg = &rzg3s_hwcfg, 2708 }; 2709 2710 static const struct of_device_id rzg2l_pinctrl_of_table[] = { 2711 { 2712 .compatible = "renesas,r9a07g043-pinctrl", 2713 .data = &r9a07g043_data, 2714 }, 2715 { 2716 .compatible = "renesas,r9a07g044-pinctrl", 2717 .data = &r9a07g044_data, 2718 }, 2719 { 2720 .compatible = "renesas,r9a08g045-pinctrl", 2721 .data = &r9a08g045_data, 2722 }, 2723 { /* sentinel */ } 2724 }; 2725 2726 static const struct dev_pm_ops rzg2l_pinctrl_pm_ops = { 2727 NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg2l_pinctrl_suspend_noirq, rzg2l_pinctrl_resume_noirq) 2728 }; 2729 2730 static struct platform_driver rzg2l_pinctrl_driver = { 2731 .driver = { 2732 .name = DRV_NAME, 2733 .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table), 2734 .pm = pm_sleep_ptr(&rzg2l_pinctrl_pm_ops), 2735 }, 2736 .probe = rzg2l_pinctrl_probe, 2737 }; 2738 2739 static int __init rzg2l_pinctrl_init(void) 2740 { 2741 return platform_driver_register(&rzg2l_pinctrl_driver); 2742 } 2743 core_initcall(rzg2l_pinctrl_init); 2744 2745 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 2746 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family"); 2747