1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support 4 * 5 * Copyright (C) 2022 9elements GmbH 6 * Authors: Patrick Rudolph <patrick.rudolph@9elements.com> 7 * Naresh Solanki <Naresh.Solanki@9elements.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/bitmap.h> 12 #include <linux/dmi.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/i2c.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/mod_devicetable.h> 19 #include <linux/module.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/seq_file.h> 24 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/pinctrl/pinconf.h> 27 #include <linux/pinctrl/pinconf-generic.h> 28 #include <linux/pinctrl/pinctrl.h> 29 #include <linux/pinctrl/pinmux.h> 30 31 /* Fast access registers */ 32 #define CY8C95X0_INPUT 0x00 33 #define CY8C95X0_OUTPUT 0x08 34 #define CY8C95X0_INTSTATUS 0x10 35 36 #define CY8C95X0_INPUT_(x) (CY8C95X0_INPUT + (x)) 37 #define CY8C95X0_OUTPUT_(x) (CY8C95X0_OUTPUT + (x)) 38 #define CY8C95X0_INTSTATUS_(x) (CY8C95X0_INTSTATUS + (x)) 39 40 /* Port Select configures the port */ 41 #define CY8C95X0_PORTSEL 0x18 42 /* Port settings, write PORTSEL first */ 43 #define CY8C95X0_INTMASK 0x19 44 #define CY8C95X0_PWMSEL 0x1A 45 #define CY8C95X0_INVERT 0x1B 46 #define CY8C95X0_DIRECTION 0x1C 47 /* Drive mode register change state on writing '1' */ 48 #define CY8C95X0_DRV_PU 0x1D 49 #define CY8C95X0_DRV_PD 0x1E 50 #define CY8C95X0_DRV_ODH 0x1F 51 #define CY8C95X0_DRV_ODL 0x20 52 #define CY8C95X0_DRV_PP_FAST 0x21 53 #define CY8C95X0_DRV_PP_SLOW 0x22 54 #define CY8C95X0_DRV_HIZ 0x23 55 #define CY8C95X0_DEVID 0x2E 56 #define CY8C95X0_WATCHDOG 0x2F 57 #define CY8C95X0_COMMAND 0x30 58 59 #define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x)) 60 61 static const struct i2c_device_id cy8c95x0_id[] = { 62 { "cy8c9520", 20, }, 63 { "cy8c9540", 40, }, 64 { "cy8c9560", 60, }, 65 { } 66 }; 67 MODULE_DEVICE_TABLE(i2c, cy8c95x0_id); 68 69 #define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio)) 70 71 static const struct of_device_id cy8c95x0_dt_ids[] = { 72 { .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), }, 73 { .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), }, 74 { .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), }, 75 { } 76 }; 77 MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids); 78 79 static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true }; 80 81 static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = { 82 { "irq-gpios", &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER }, 83 { } 84 }; 85 86 static int cy8c95x0_acpi_get_irq(struct device *dev) 87 { 88 int ret; 89 90 ret = devm_acpi_dev_add_driver_gpios(dev, cy8c95x0_acpi_irq_gpios); 91 if (ret) 92 dev_warn(dev, "can't add GPIO ACPI mapping\n"); 93 94 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0); 95 if (ret < 0) 96 return ret; 97 98 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret); 99 return ret; 100 } 101 102 static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = { 103 { 104 /* 105 * On Intel Galileo Gen 1 board the IRQ pin is provided 106 * as an absolute number instead of being relative. 107 * Since first controller (gpio-sch.c) and second 108 * (gpio-dwapb.c) are at the fixed bases, we may safely 109 * refer to the number in the global space to get an IRQ 110 * out of it. 111 */ 112 .matches = { 113 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), 114 }, 115 }, 116 {} 117 }; 118 119 #define MAX_BANK 8 120 #define BANK_SZ 8 121 #define MAX_LINE (MAX_BANK * BANK_SZ) 122 123 #define CY8C95X0_GPIO_MASK GENMASK(7, 0) 124 125 /** 126 * struct cy8c95x0_pinctrl - driver data 127 * @regmap: Device's regmap 128 * @irq_lock: IRQ bus lock 129 * @i2c_lock: Mutex for the device internal mux register 130 * @irq_mask: I/O bits affected by interrupts 131 * @irq_trig_raise: I/O bits affected by raising voltage level 132 * @irq_trig_fall: I/O bits affected by falling voltage level 133 * @irq_trig_low: I/O bits affected by a low voltage level 134 * @irq_trig_high: I/O bits affected by a high voltage level 135 * @push_pull: I/O bits configured as push pull driver 136 * @shiftmask: Mask used to compensate for Gport2 width 137 * @nport: Number of Gports in this chip 138 * @gpio_chip: gpiolib chip 139 * @driver_data: private driver data 140 * @regulator: Pointer to the regulator for the IC 141 * @dev: struct device 142 * @pctldev: pin controller device 143 * @pinctrl_desc: pin controller description 144 * @name: Chip controller name 145 * @tpin: Total number of pins 146 * @gpio_reset: GPIO line handler that can reset the IC 147 */ 148 struct cy8c95x0_pinctrl { 149 struct regmap *regmap; 150 struct mutex irq_lock; 151 struct mutex i2c_lock; 152 DECLARE_BITMAP(irq_mask, MAX_LINE); 153 DECLARE_BITMAP(irq_trig_raise, MAX_LINE); 154 DECLARE_BITMAP(irq_trig_fall, MAX_LINE); 155 DECLARE_BITMAP(irq_trig_low, MAX_LINE); 156 DECLARE_BITMAP(irq_trig_high, MAX_LINE); 157 DECLARE_BITMAP(push_pull, MAX_LINE); 158 DECLARE_BITMAP(shiftmask, MAX_LINE); 159 int nport; 160 struct gpio_chip gpio_chip; 161 unsigned long driver_data; 162 struct regulator *regulator; 163 struct device *dev; 164 struct pinctrl_dev *pctldev; 165 struct pinctrl_desc pinctrl_desc; 166 char name[32]; 167 unsigned int tpin; 168 struct gpio_desc *gpio_reset; 169 }; 170 171 static const struct pinctrl_pin_desc cy8c9560_pins[] = { 172 PINCTRL_PIN(0, "gp00"), 173 PINCTRL_PIN(1, "gp01"), 174 PINCTRL_PIN(2, "gp02"), 175 PINCTRL_PIN(3, "gp03"), 176 PINCTRL_PIN(4, "gp04"), 177 PINCTRL_PIN(5, "gp05"), 178 PINCTRL_PIN(6, "gp06"), 179 PINCTRL_PIN(7, "gp07"), 180 181 PINCTRL_PIN(8, "gp10"), 182 PINCTRL_PIN(9, "gp11"), 183 PINCTRL_PIN(10, "gp12"), 184 PINCTRL_PIN(11, "gp13"), 185 PINCTRL_PIN(12, "gp14"), 186 PINCTRL_PIN(13, "gp15"), 187 PINCTRL_PIN(14, "gp16"), 188 PINCTRL_PIN(15, "gp17"), 189 190 PINCTRL_PIN(16, "gp20"), 191 PINCTRL_PIN(17, "gp21"), 192 PINCTRL_PIN(18, "gp22"), 193 PINCTRL_PIN(19, "gp23"), 194 195 PINCTRL_PIN(20, "gp30"), 196 PINCTRL_PIN(21, "gp31"), 197 PINCTRL_PIN(22, "gp32"), 198 PINCTRL_PIN(23, "gp33"), 199 PINCTRL_PIN(24, "gp34"), 200 PINCTRL_PIN(25, "gp35"), 201 PINCTRL_PIN(26, "gp36"), 202 PINCTRL_PIN(27, "gp37"), 203 204 PINCTRL_PIN(28, "gp40"), 205 PINCTRL_PIN(29, "gp41"), 206 PINCTRL_PIN(30, "gp42"), 207 PINCTRL_PIN(31, "gp43"), 208 PINCTRL_PIN(32, "gp44"), 209 PINCTRL_PIN(33, "gp45"), 210 PINCTRL_PIN(34, "gp46"), 211 PINCTRL_PIN(35, "gp47"), 212 213 PINCTRL_PIN(36, "gp50"), 214 PINCTRL_PIN(37, "gp51"), 215 PINCTRL_PIN(38, "gp52"), 216 PINCTRL_PIN(39, "gp53"), 217 PINCTRL_PIN(40, "gp54"), 218 PINCTRL_PIN(41, "gp55"), 219 PINCTRL_PIN(42, "gp56"), 220 PINCTRL_PIN(43, "gp57"), 221 222 PINCTRL_PIN(44, "gp60"), 223 PINCTRL_PIN(45, "gp61"), 224 PINCTRL_PIN(46, "gp62"), 225 PINCTRL_PIN(47, "gp63"), 226 PINCTRL_PIN(48, "gp64"), 227 PINCTRL_PIN(49, "gp65"), 228 PINCTRL_PIN(50, "gp66"), 229 PINCTRL_PIN(51, "gp67"), 230 231 PINCTRL_PIN(52, "gp70"), 232 PINCTRL_PIN(53, "gp71"), 233 PINCTRL_PIN(54, "gp72"), 234 PINCTRL_PIN(55, "gp73"), 235 PINCTRL_PIN(56, "gp74"), 236 PINCTRL_PIN(57, "gp75"), 237 PINCTRL_PIN(58, "gp76"), 238 PINCTRL_PIN(59, "gp77"), 239 }; 240 241 static const char * const cy8c95x0_groups[] = { 242 "gp00", 243 "gp01", 244 "gp02", 245 "gp03", 246 "gp04", 247 "gp05", 248 "gp06", 249 "gp07", 250 251 "gp10", 252 "gp11", 253 "gp12", 254 "gp13", 255 "gp14", 256 "gp15", 257 "gp16", 258 "gp17", 259 260 "gp20", 261 "gp21", 262 "gp22", 263 "gp23", 264 265 "gp30", 266 "gp31", 267 "gp32", 268 "gp33", 269 "gp34", 270 "gp35", 271 "gp36", 272 "gp37", 273 274 "gp40", 275 "gp41", 276 "gp42", 277 "gp43", 278 "gp44", 279 "gp45", 280 "gp46", 281 "gp47", 282 283 "gp50", 284 "gp51", 285 "gp52", 286 "gp53", 287 "gp54", 288 "gp55", 289 "gp56", 290 "gp57", 291 292 "gp60", 293 "gp61", 294 "gp62", 295 "gp63", 296 "gp64", 297 "gp65", 298 "gp66", 299 "gp67", 300 301 "gp70", 302 "gp71", 303 "gp72", 304 "gp73", 305 "gp74", 306 "gp75", 307 "gp76", 308 "gp77", 309 }; 310 311 static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, 312 unsigned int pin, bool input); 313 314 static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin) 315 { 316 /* Account for GPORT2 which only has 4 bits */ 317 return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ; 318 } 319 320 static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin) 321 { 322 /* Account for GPORT2 which only has 4 bits */ 323 return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ); 324 } 325 326 static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg) 327 { 328 switch (reg) { 329 case 0x24 ... 0x27: 330 return false; 331 default: 332 return true; 333 } 334 } 335 336 static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg) 337 { 338 switch (reg) { 339 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): 340 return false; 341 case CY8C95X0_DEVID: 342 return false; 343 case 0x24 ... 0x27: 344 return false; 345 default: 346 return true; 347 } 348 } 349 350 static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg) 351 { 352 switch (reg) { 353 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): 354 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): 355 case CY8C95X0_INTMASK: 356 case CY8C95X0_INVERT: 357 case CY8C95X0_PWMSEL: 358 case CY8C95X0_DIRECTION: 359 case CY8C95X0_DRV_PU: 360 case CY8C95X0_DRV_PD: 361 case CY8C95X0_DRV_ODH: 362 case CY8C95X0_DRV_ODL: 363 case CY8C95X0_DRV_PP_FAST: 364 case CY8C95X0_DRV_PP_SLOW: 365 case CY8C95X0_DRV_HIZ: 366 return true; 367 default: 368 return false; 369 } 370 } 371 372 static bool cy8c95x0_precious_register(struct device *dev, unsigned int reg) 373 { 374 switch (reg) { 375 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): 376 return true; 377 default: 378 return false; 379 } 380 } 381 382 static const struct reg_default cy8c95x0_reg_defaults[] = { 383 { CY8C95X0_OUTPUT_(0), GENMASK(7, 0) }, 384 { CY8C95X0_OUTPUT_(1), GENMASK(7, 0) }, 385 { CY8C95X0_OUTPUT_(2), GENMASK(7, 0) }, 386 { CY8C95X0_OUTPUT_(3), GENMASK(7, 0) }, 387 { CY8C95X0_OUTPUT_(4), GENMASK(7, 0) }, 388 { CY8C95X0_OUTPUT_(5), GENMASK(7, 0) }, 389 { CY8C95X0_OUTPUT_(6), GENMASK(7, 0) }, 390 { CY8C95X0_OUTPUT_(7), GENMASK(7, 0) }, 391 { CY8C95X0_PORTSEL, 0 }, 392 { CY8C95X0_PWMSEL, 0 }, 393 }; 394 395 static const struct regmap_config cy8c95x0_i2c_regmap = { 396 .reg_bits = 8, 397 .val_bits = 8, 398 399 .reg_defaults = cy8c95x0_reg_defaults, 400 .num_reg_defaults = ARRAY_SIZE(cy8c95x0_reg_defaults), 401 402 .readable_reg = cy8c95x0_readable_register, 403 .writeable_reg = cy8c95x0_writeable_register, 404 .volatile_reg = cy8c95x0_volatile_register, 405 .precious_reg = cy8c95x0_precious_register, 406 407 .cache_type = REGCACHE_FLAT, 408 .max_register = CY8C95X0_COMMAND, 409 }; 410 411 static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, 412 unsigned long *val, unsigned long *mask) 413 { 414 DECLARE_BITMAP(tmask, MAX_LINE); 415 DECLARE_BITMAP(tval, MAX_LINE); 416 int write_val; 417 int ret = 0; 418 int i, off = 0; 419 u8 bits; 420 421 /* Add the 4 bit gap of Gport2 */ 422 bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE); 423 bitmap_shift_left(tmask, tmask, 4, MAX_LINE); 424 bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3); 425 426 bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE); 427 bitmap_shift_left(tval, tval, 4, MAX_LINE); 428 bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3); 429 430 mutex_lock(&chip->i2c_lock); 431 for (i = 0; i < chip->nport; i++) { 432 /* Skip over unused banks */ 433 bits = bitmap_get_value8(tmask, i * BANK_SZ); 434 if (!bits) 435 continue; 436 437 switch (reg) { 438 /* Muxed registers */ 439 case CY8C95X0_INTMASK: 440 case CY8C95X0_PWMSEL: 441 case CY8C95X0_INVERT: 442 case CY8C95X0_DIRECTION: 443 case CY8C95X0_DRV_PU: 444 case CY8C95X0_DRV_PD: 445 case CY8C95X0_DRV_ODH: 446 case CY8C95X0_DRV_ODL: 447 case CY8C95X0_DRV_PP_FAST: 448 case CY8C95X0_DRV_PP_SLOW: 449 case CY8C95X0_DRV_HIZ: 450 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i); 451 if (ret < 0) 452 goto out; 453 off = reg; 454 break; 455 /* Direct access registers */ 456 case CY8C95X0_INPUT: 457 case CY8C95X0_OUTPUT: 458 case CY8C95X0_INTSTATUS: 459 off = reg + i; 460 break; 461 default: 462 ret = -EINVAL; 463 goto out; 464 } 465 466 write_val = bitmap_get_value8(tval, i * BANK_SZ); 467 468 ret = regmap_update_bits(chip->regmap, off, bits, write_val); 469 if (ret < 0) 470 goto out; 471 } 472 out: 473 mutex_unlock(&chip->i2c_lock); 474 475 if (ret < 0) 476 dev_err(chip->dev, "failed writing register %d: err %d\n", off, ret); 477 478 return ret; 479 } 480 481 static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, 482 unsigned long *val, unsigned long *mask) 483 { 484 DECLARE_BITMAP(tmask, MAX_LINE); 485 DECLARE_BITMAP(tval, MAX_LINE); 486 DECLARE_BITMAP(tmp, MAX_LINE); 487 int read_val; 488 int ret = 0; 489 int i, off = 0; 490 u8 bits; 491 492 /* Add the 4 bit gap of Gport2 */ 493 bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE); 494 bitmap_shift_left(tmask, tmask, 4, MAX_LINE); 495 bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3); 496 497 bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE); 498 bitmap_shift_left(tval, tval, 4, MAX_LINE); 499 bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3); 500 501 mutex_lock(&chip->i2c_lock); 502 for (i = 0; i < chip->nport; i++) { 503 /* Skip over unused banks */ 504 bits = bitmap_get_value8(tmask, i * BANK_SZ); 505 if (!bits) 506 continue; 507 508 switch (reg) { 509 /* Muxed registers */ 510 case CY8C95X0_INTMASK: 511 case CY8C95X0_PWMSEL: 512 case CY8C95X0_INVERT: 513 case CY8C95X0_DIRECTION: 514 case CY8C95X0_DRV_PU: 515 case CY8C95X0_DRV_PD: 516 case CY8C95X0_DRV_ODH: 517 case CY8C95X0_DRV_ODL: 518 case CY8C95X0_DRV_PP_FAST: 519 case CY8C95X0_DRV_PP_SLOW: 520 case CY8C95X0_DRV_HIZ: 521 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i); 522 if (ret < 0) 523 goto out; 524 off = reg; 525 break; 526 /* Direct access registers */ 527 case CY8C95X0_INPUT: 528 case CY8C95X0_OUTPUT: 529 case CY8C95X0_INTSTATUS: 530 off = reg + i; 531 break; 532 default: 533 ret = -EINVAL; 534 goto out; 535 } 536 537 ret = regmap_read(chip->regmap, off, &read_val); 538 if (ret < 0) 539 goto out; 540 541 read_val &= bits; 542 read_val |= bitmap_get_value8(tval, i * BANK_SZ) & ~bits; 543 bitmap_set_value8(tval, read_val, i * BANK_SZ); 544 } 545 546 /* Fill the 4 bit gap of Gport2 */ 547 bitmap_shift_right(tmp, tval, 4, MAX_LINE); 548 bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE); 549 550 out: 551 mutex_unlock(&chip->i2c_lock); 552 553 if (ret < 0) 554 dev_err(chip->dev, "failed reading register %d: err %d\n", off, ret); 555 556 return ret; 557 } 558 559 static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off) 560 { 561 return pinctrl_gpio_direction_input(gc, off); 562 } 563 564 static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc, 565 unsigned int off, int val) 566 { 567 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 568 u8 port = cypress_get_port(chip, off); 569 u8 outreg = CY8C95X0_OUTPUT_(port); 570 u8 bit = cypress_get_pin_mask(chip, off); 571 int ret; 572 573 /* Set output level */ 574 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 575 if (ret) 576 return ret; 577 578 return pinctrl_gpio_direction_output(gc, off); 579 } 580 581 static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off) 582 { 583 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 584 u8 inreg = CY8C95X0_INPUT_(cypress_get_port(chip, off)); 585 u8 bit = cypress_get_pin_mask(chip, off); 586 u32 reg_val; 587 int ret; 588 589 ret = regmap_read(chip->regmap, inreg, ®_val); 590 if (ret < 0) { 591 /* 592 * NOTE: 593 * Diagnostic already emitted; that's all we should 594 * do unless gpio_*_value_cansleep() calls become different 595 * from their nonsleeping siblings (and report faults). 596 */ 597 return 0; 598 } 599 600 return !!(reg_val & bit); 601 } 602 603 static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off, 604 int val) 605 { 606 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 607 u8 outreg = CY8C95X0_OUTPUT_(cypress_get_port(chip, off)); 608 u8 bit = cypress_get_pin_mask(chip, off); 609 610 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 611 } 612 613 static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off) 614 { 615 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 616 u8 port = cypress_get_port(chip, off); 617 u8 bit = cypress_get_pin_mask(chip, off); 618 u32 reg_val; 619 int ret; 620 621 mutex_lock(&chip->i2c_lock); 622 623 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); 624 if (ret < 0) 625 goto out; 626 627 ret = regmap_read(chip->regmap, CY8C95X0_DIRECTION, ®_val); 628 if (ret < 0) 629 goto out; 630 631 mutex_unlock(&chip->i2c_lock); 632 633 if (reg_val & bit) 634 return GPIO_LINE_DIRECTION_IN; 635 636 return GPIO_LINE_DIRECTION_OUT; 637 out: 638 mutex_unlock(&chip->i2c_lock); 639 return ret; 640 } 641 642 static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip, 643 unsigned int off, 644 unsigned long *config) 645 { 646 enum pin_config_param param = pinconf_to_config_param(*config); 647 u8 port = cypress_get_port(chip, off); 648 u8 bit = cypress_get_pin_mask(chip, off); 649 unsigned int reg; 650 u32 reg_val; 651 u16 arg = 0; 652 int ret; 653 654 mutex_lock(&chip->i2c_lock); 655 656 /* Select port */ 657 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); 658 if (ret < 0) 659 goto out; 660 661 switch (param) { 662 case PIN_CONFIG_BIAS_PULL_UP: 663 reg = CY8C95X0_DRV_PU; 664 break; 665 case PIN_CONFIG_BIAS_PULL_DOWN: 666 reg = CY8C95X0_DRV_PD; 667 break; 668 case PIN_CONFIG_BIAS_DISABLE: 669 reg = CY8C95X0_DRV_HIZ; 670 break; 671 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 672 reg = CY8C95X0_DRV_ODL; 673 break; 674 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 675 reg = CY8C95X0_DRV_ODH; 676 break; 677 case PIN_CONFIG_DRIVE_PUSH_PULL: 678 reg = CY8C95X0_DRV_PP_FAST; 679 break; 680 case PIN_CONFIG_INPUT_ENABLE: 681 reg = CY8C95X0_DIRECTION; 682 break; 683 case PIN_CONFIG_MODE_PWM: 684 reg = CY8C95X0_PWMSEL; 685 break; 686 case PIN_CONFIG_OUTPUT: 687 reg = CY8C95X0_OUTPUT_(port); 688 break; 689 case PIN_CONFIG_OUTPUT_ENABLE: 690 reg = CY8C95X0_DIRECTION; 691 break; 692 693 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 694 case PIN_CONFIG_BIAS_BUS_HOLD: 695 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 696 case PIN_CONFIG_DRIVE_STRENGTH: 697 case PIN_CONFIG_DRIVE_STRENGTH_UA: 698 case PIN_CONFIG_INPUT_DEBOUNCE: 699 case PIN_CONFIG_INPUT_SCHMITT: 700 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 701 case PIN_CONFIG_MODE_LOW_POWER: 702 case PIN_CONFIG_PERSIST_STATE: 703 case PIN_CONFIG_POWER_SOURCE: 704 case PIN_CONFIG_SKEW_DELAY: 705 case PIN_CONFIG_SLEEP_HARDWARE_STATE: 706 case PIN_CONFIG_SLEW_RATE: 707 default: 708 ret = -ENOTSUPP; 709 goto out; 710 } 711 /* 712 * Writing 1 to one of the drive mode registers will automatically 713 * clear conflicting set bits in the other drive mode registers. 714 */ 715 ret = regmap_read(chip->regmap, reg, ®_val); 716 if (reg_val & bit) 717 arg = 1; 718 if (param == PIN_CONFIG_OUTPUT_ENABLE) 719 arg = !arg; 720 721 *config = pinconf_to_config_packed(param, (u16)arg); 722 out: 723 mutex_unlock(&chip->i2c_lock); 724 725 return ret; 726 } 727 728 static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip, 729 unsigned int off, 730 unsigned long config) 731 { 732 u8 port = cypress_get_port(chip, off); 733 u8 bit = cypress_get_pin_mask(chip, off); 734 unsigned long param = pinconf_to_config_param(config); 735 unsigned long arg = pinconf_to_config_argument(config); 736 unsigned int reg; 737 int ret; 738 739 mutex_lock(&chip->i2c_lock); 740 741 /* Select port */ 742 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); 743 if (ret < 0) 744 goto out; 745 746 switch (param) { 747 case PIN_CONFIG_BIAS_PULL_UP: 748 __clear_bit(off, chip->push_pull); 749 reg = CY8C95X0_DRV_PU; 750 break; 751 case PIN_CONFIG_BIAS_PULL_DOWN: 752 __clear_bit(off, chip->push_pull); 753 reg = CY8C95X0_DRV_PD; 754 break; 755 case PIN_CONFIG_BIAS_DISABLE: 756 __clear_bit(off, chip->push_pull); 757 reg = CY8C95X0_DRV_HIZ; 758 break; 759 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 760 __clear_bit(off, chip->push_pull); 761 reg = CY8C95X0_DRV_ODL; 762 break; 763 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 764 __clear_bit(off, chip->push_pull); 765 reg = CY8C95X0_DRV_ODH; 766 break; 767 case PIN_CONFIG_DRIVE_PUSH_PULL: 768 __set_bit(off, chip->push_pull); 769 reg = CY8C95X0_DRV_PP_FAST; 770 break; 771 case PIN_CONFIG_MODE_PWM: 772 reg = CY8C95X0_PWMSEL; 773 break; 774 case PIN_CONFIG_OUTPUT_ENABLE: 775 ret = cy8c95x0_pinmux_direction(chip, off, !arg); 776 goto out; 777 case PIN_CONFIG_INPUT_ENABLE: 778 ret = cy8c95x0_pinmux_direction(chip, off, arg); 779 goto out; 780 default: 781 ret = -ENOTSUPP; 782 goto out; 783 } 784 /* 785 * Writing 1 to one of the drive mode registers will automatically 786 * clear conflicting set bits in the other drive mode registers. 787 */ 788 ret = regmap_write_bits(chip->regmap, reg, bit, bit); 789 790 out: 791 mutex_unlock(&chip->i2c_lock); 792 return ret; 793 } 794 795 static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc, 796 unsigned long *mask, unsigned long *bits) 797 { 798 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 799 800 return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, bits, mask); 801 } 802 803 static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc, 804 unsigned long *mask, unsigned long *bits) 805 { 806 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 807 808 cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask); 809 } 810 811 static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc) 812 { 813 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 814 struct device *dev = chip->dev; 815 int ret; 816 817 ret = gpiochip_add_pin_range(gc, dev_name(dev), 0, 0, chip->tpin); 818 if (ret) 819 dev_err(dev, "failed to add GPIO pin range\n"); 820 821 return ret; 822 } 823 824 static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip) 825 { 826 struct gpio_chip *gc = &chip->gpio_chip; 827 828 gc->request = gpiochip_generic_request; 829 gc->free = gpiochip_generic_free; 830 gc->direction_input = cy8c95x0_gpio_direction_input; 831 gc->direction_output = cy8c95x0_gpio_direction_output; 832 gc->get = cy8c95x0_gpio_get_value; 833 gc->set = cy8c95x0_gpio_set_value; 834 gc->get_direction = cy8c95x0_gpio_get_direction; 835 gc->get_multiple = cy8c95x0_gpio_get_multiple; 836 gc->set_multiple = cy8c95x0_gpio_set_multiple; 837 gc->set_config = gpiochip_generic_config; 838 gc->can_sleep = true; 839 gc->add_pin_ranges = cy8c95x0_add_pin_ranges; 840 841 gc->base = -1; 842 gc->ngpio = chip->tpin; 843 844 gc->parent = chip->dev; 845 gc->owner = THIS_MODULE; 846 gc->names = NULL; 847 848 gc->label = dev_name(chip->dev); 849 850 return devm_gpiochip_add_data(chip->dev, gc, chip); 851 } 852 853 static void cy8c95x0_irq_mask(struct irq_data *d) 854 { 855 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 856 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 857 irq_hw_number_t hwirq = irqd_to_hwirq(d); 858 859 set_bit(hwirq, chip->irq_mask); 860 gpiochip_disable_irq(gc, hwirq); 861 } 862 863 static void cy8c95x0_irq_unmask(struct irq_data *d) 864 { 865 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 866 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 867 irq_hw_number_t hwirq = irqd_to_hwirq(d); 868 869 gpiochip_enable_irq(gc, hwirq); 870 clear_bit(hwirq, chip->irq_mask); 871 } 872 873 static void cy8c95x0_irq_bus_lock(struct irq_data *d) 874 { 875 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 876 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 877 878 mutex_lock(&chip->irq_lock); 879 } 880 881 static void cy8c95x0_irq_bus_sync_unlock(struct irq_data *d) 882 { 883 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 884 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 885 DECLARE_BITMAP(ones, MAX_LINE); 886 DECLARE_BITMAP(irq_mask, MAX_LINE); 887 DECLARE_BITMAP(reg_direction, MAX_LINE); 888 889 bitmap_fill(ones, MAX_LINE); 890 891 cy8c95x0_write_regs_mask(chip, CY8C95X0_INTMASK, chip->irq_mask, ones); 892 893 /* Switch direction to input if needed */ 894 cy8c95x0_read_regs_mask(chip, CY8C95X0_DIRECTION, reg_direction, chip->irq_mask); 895 bitmap_or(irq_mask, chip->irq_mask, reg_direction, MAX_LINE); 896 bitmap_complement(irq_mask, irq_mask, MAX_LINE); 897 898 /* Look for any newly setup interrupt */ 899 cy8c95x0_write_regs_mask(chip, CY8C95X0_DIRECTION, ones, irq_mask); 900 901 mutex_unlock(&chip->irq_lock); 902 } 903 904 static int cy8c95x0_irq_set_type(struct irq_data *d, unsigned int type) 905 { 906 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 907 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 908 irq_hw_number_t hwirq = irqd_to_hwirq(d); 909 unsigned int trig_type; 910 911 switch (type) { 912 case IRQ_TYPE_EDGE_RISING: 913 case IRQ_TYPE_EDGE_FALLING: 914 case IRQ_TYPE_EDGE_BOTH: 915 trig_type = type; 916 break; 917 case IRQ_TYPE_LEVEL_HIGH: 918 trig_type = IRQ_TYPE_EDGE_RISING; 919 break; 920 case IRQ_TYPE_LEVEL_LOW: 921 trig_type = IRQ_TYPE_EDGE_FALLING; 922 break; 923 default: 924 dev_err(chip->dev, "irq %d: unsupported type %d\n", d->irq, type); 925 return -EINVAL; 926 } 927 928 assign_bit(hwirq, chip->irq_trig_fall, trig_type & IRQ_TYPE_EDGE_FALLING); 929 assign_bit(hwirq, chip->irq_trig_raise, trig_type & IRQ_TYPE_EDGE_RISING); 930 assign_bit(hwirq, chip->irq_trig_low, type == IRQ_TYPE_LEVEL_LOW); 931 assign_bit(hwirq, chip->irq_trig_high, type == IRQ_TYPE_LEVEL_HIGH); 932 933 return 0; 934 } 935 936 static void cy8c95x0_irq_shutdown(struct irq_data *d) 937 { 938 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 939 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 940 irq_hw_number_t hwirq = irqd_to_hwirq(d); 941 942 clear_bit(hwirq, chip->irq_trig_raise); 943 clear_bit(hwirq, chip->irq_trig_fall); 944 clear_bit(hwirq, chip->irq_trig_low); 945 clear_bit(hwirq, chip->irq_trig_high); 946 } 947 948 static const struct irq_chip cy8c95x0_irqchip = { 949 .name = "cy8c95x0-irq", 950 .irq_mask = cy8c95x0_irq_mask, 951 .irq_unmask = cy8c95x0_irq_unmask, 952 .irq_bus_lock = cy8c95x0_irq_bus_lock, 953 .irq_bus_sync_unlock = cy8c95x0_irq_bus_sync_unlock, 954 .irq_set_type = cy8c95x0_irq_set_type, 955 .irq_shutdown = cy8c95x0_irq_shutdown, 956 .flags = IRQCHIP_IMMUTABLE, 957 GPIOCHIP_IRQ_RESOURCE_HELPERS, 958 }; 959 960 static bool cy8c95x0_irq_pending(struct cy8c95x0_pinctrl *chip, unsigned long *pending) 961 { 962 DECLARE_BITMAP(ones, MAX_LINE); 963 DECLARE_BITMAP(cur_stat, MAX_LINE); 964 DECLARE_BITMAP(new_stat, MAX_LINE); 965 DECLARE_BITMAP(trigger, MAX_LINE); 966 967 bitmap_fill(ones, MAX_LINE); 968 969 /* Read the current interrupt status from the device */ 970 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INTSTATUS, trigger, ones)) 971 return false; 972 973 /* Check latched inputs */ 974 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, cur_stat, trigger)) 975 return false; 976 977 /* Apply filter for rising/falling edge selection */ 978 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, 979 cur_stat, MAX_LINE); 980 981 bitmap_and(pending, new_stat, trigger, MAX_LINE); 982 983 return !bitmap_empty(pending, MAX_LINE); 984 } 985 986 static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid) 987 { 988 struct cy8c95x0_pinctrl *chip = devid; 989 struct gpio_chip *gc = &chip->gpio_chip; 990 DECLARE_BITMAP(pending, MAX_LINE); 991 int nested_irq, level; 992 bool ret; 993 994 ret = cy8c95x0_irq_pending(chip, pending); 995 if (!ret) 996 return IRQ_RETVAL(0); 997 998 ret = 0; 999 for_each_set_bit(level, pending, MAX_LINE) { 1000 /* Already accounted for 4bit gap in GPort2 */ 1001 nested_irq = irq_find_mapping(gc->irq.domain, level); 1002 1003 if (unlikely(nested_irq <= 0)) { 1004 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level); 1005 continue; 1006 } 1007 1008 if (test_bit(level, chip->irq_trig_low)) 1009 while (!cy8c95x0_gpio_get_value(gc, level)) 1010 handle_nested_irq(nested_irq); 1011 else if (test_bit(level, chip->irq_trig_high)) 1012 while (cy8c95x0_gpio_get_value(gc, level)) 1013 handle_nested_irq(nested_irq); 1014 else 1015 handle_nested_irq(nested_irq); 1016 1017 ret = 1; 1018 } 1019 1020 return IRQ_RETVAL(ret); 1021 } 1022 1023 static int cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 1024 { 1025 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1026 1027 return chip->tpin; 1028 } 1029 1030 static const char *cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 1031 unsigned int group) 1032 { 1033 return cy8c95x0_groups[group]; 1034 } 1035 1036 static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 1037 unsigned int group, 1038 const unsigned int **pins, 1039 unsigned int *num_pins) 1040 { 1041 *pins = &cy8c9560_pins[group].number; 1042 *num_pins = 1; 1043 return 0; 1044 } 1045 1046 static const char *cy8c95x0_get_fname(unsigned int selector) 1047 { 1048 if (selector == 0) 1049 return "gpio"; 1050 else 1051 return "pwm"; 1052 } 1053 1054 static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 1055 unsigned int pin) 1056 { 1057 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1058 DECLARE_BITMAP(mask, MAX_LINE); 1059 DECLARE_BITMAP(pwm, MAX_LINE); 1060 1061 bitmap_zero(mask, MAX_LINE); 1062 __set_bit(pin, mask); 1063 1064 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, pwm, mask)) { 1065 seq_puts(s, "not available"); 1066 return; 1067 } 1068 1069 seq_printf(s, "MODE:%s", cy8c95x0_get_fname(test_bit(pin, pwm))); 1070 } 1071 1072 static const struct pinctrl_ops cy8c95x0_pinctrl_ops = { 1073 .get_groups_count = cy8c95x0_pinctrl_get_groups_count, 1074 .get_group_name = cy8c95x0_pinctrl_get_group_name, 1075 .get_group_pins = cy8c95x0_pinctrl_get_group_pins, 1076 #ifdef CONFIG_OF 1077 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1078 .dt_free_map = pinconf_generic_dt_free_map, 1079 #endif 1080 .pin_dbg_show = cy8c95x0_pin_dbg_show, 1081 }; 1082 1083 static const char *cy8c95x0_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector) 1084 { 1085 return cy8c95x0_get_fname(selector); 1086 } 1087 1088 static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev) 1089 { 1090 return 2; 1091 } 1092 1093 static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, 1094 const char * const **groups, 1095 unsigned int * const num_groups) 1096 { 1097 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1098 1099 *groups = cy8c95x0_groups; 1100 *num_groups = chip->tpin; 1101 return 0; 1102 } 1103 1104 static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode) 1105 { 1106 u8 port = cypress_get_port(chip, off); 1107 u8 bit = cypress_get_pin_mask(chip, off); 1108 int ret; 1109 1110 /* Select port */ 1111 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); 1112 if (ret < 0) 1113 return ret; 1114 1115 return regmap_write_bits(chip->regmap, CY8C95X0_PWMSEL, bit, mode ? bit : 0); 1116 } 1117 1118 static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip, 1119 unsigned int selector, unsigned int group) 1120 { 1121 u8 port = cypress_get_port(chip, group); 1122 u8 bit = cypress_get_pin_mask(chip, group); 1123 int ret; 1124 1125 ret = cy8c95x0_set_mode(chip, group, selector); 1126 if (ret < 0) 1127 return ret; 1128 1129 if (selector == 0) 1130 return 0; 1131 1132 /* Set direction to output & set output to 1 so that PWM can work */ 1133 ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit); 1134 if (ret < 0) 1135 return ret; 1136 1137 return regmap_write_bits(chip->regmap, CY8C95X0_OUTPUT_(port), bit, bit); 1138 } 1139 1140 static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, 1141 unsigned int group) 1142 { 1143 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1144 int ret; 1145 1146 mutex_lock(&chip->i2c_lock); 1147 ret = cy8c95x0_pinmux_mode(chip, selector, group); 1148 mutex_unlock(&chip->i2c_lock); 1149 1150 return ret; 1151 } 1152 1153 static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev, 1154 struct pinctrl_gpio_range *range, 1155 unsigned int pin) 1156 { 1157 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1158 int ret; 1159 1160 mutex_lock(&chip->i2c_lock); 1161 ret = cy8c95x0_set_mode(chip, pin, false); 1162 mutex_unlock(&chip->i2c_lock); 1163 1164 return ret; 1165 } 1166 1167 static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, 1168 unsigned int pin, bool input) 1169 { 1170 u8 port = cypress_get_port(chip, pin); 1171 u8 bit = cypress_get_pin_mask(chip, pin); 1172 int ret; 1173 1174 /* Select port... */ 1175 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); 1176 if (ret) 1177 return ret; 1178 1179 /* ...then direction */ 1180 ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, input ? bit : 0); 1181 if (ret) 1182 return ret; 1183 1184 /* 1185 * Disable driving the pin by forcing it to HighZ. Only setting 1186 * the direction register isn't sufficient in Push-Pull mode. 1187 */ 1188 if (input && test_bit(pin, chip->push_pull)) { 1189 ret = regmap_write_bits(chip->regmap, CY8C95X0_DRV_HIZ, bit, bit); 1190 if (ret) 1191 return ret; 1192 1193 __clear_bit(pin, chip->push_pull); 1194 } 1195 1196 return 0; 1197 } 1198 1199 static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev, 1200 struct pinctrl_gpio_range *range, 1201 unsigned int pin, bool input) 1202 { 1203 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1204 int ret; 1205 1206 mutex_lock(&chip->i2c_lock); 1207 ret = cy8c95x0_pinmux_direction(chip, pin, input); 1208 mutex_unlock(&chip->i2c_lock); 1209 1210 return ret; 1211 } 1212 1213 static const struct pinmux_ops cy8c95x0_pmxops = { 1214 .get_functions_count = cy8c95x0_get_functions_count, 1215 .get_function_name = cy8c95x0_get_function_name, 1216 .get_function_groups = cy8c95x0_get_function_groups, 1217 .set_mux = cy8c95x0_set_mux, 1218 .gpio_request_enable = cy8c95x0_gpio_request_enable, 1219 .gpio_set_direction = cy8c95x0_gpio_set_direction, 1220 .strict = true, 1221 }; 1222 1223 static int cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 1224 unsigned long *config) 1225 { 1226 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1227 1228 return cy8c95x0_gpio_get_pincfg(chip, pin, config); 1229 } 1230 1231 static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1232 unsigned long *configs, unsigned int num_configs) 1233 { 1234 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1235 int ret = 0; 1236 int i; 1237 1238 for (i = 0; i < num_configs; i++) { 1239 ret = cy8c95x0_gpio_set_pincfg(chip, pin, configs[i]); 1240 if (ret) 1241 return ret; 1242 } 1243 1244 return ret; 1245 } 1246 1247 static const struct pinconf_ops cy8c95x0_pinconf_ops = { 1248 .pin_config_get = cy8c95x0_pinconf_get, 1249 .pin_config_set = cy8c95x0_pinconf_set, 1250 .is_generic = true, 1251 }; 1252 1253 static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq) 1254 { 1255 struct gpio_irq_chip *girq = &chip->gpio_chip.irq; 1256 DECLARE_BITMAP(pending_irqs, MAX_LINE); 1257 int ret; 1258 1259 mutex_init(&chip->irq_lock); 1260 1261 bitmap_zero(pending_irqs, MAX_LINE); 1262 1263 /* Read IRQ status register to clear all pending interrupts */ 1264 ret = cy8c95x0_irq_pending(chip, pending_irqs); 1265 if (ret) { 1266 dev_err(chip->dev, "failed to clear irq status register\n"); 1267 return ret; 1268 } 1269 1270 /* Mask all interrupts */ 1271 bitmap_fill(chip->irq_mask, MAX_LINE); 1272 1273 gpio_irq_chip_set_chip(girq, &cy8c95x0_irqchip); 1274 1275 /* This will let us handle the parent IRQ in the driver */ 1276 girq->parent_handler = NULL; 1277 girq->num_parents = 0; 1278 girq->parents = NULL; 1279 girq->default_type = IRQ_TYPE_NONE; 1280 girq->handler = handle_simple_irq; 1281 girq->threaded = true; 1282 1283 ret = devm_request_threaded_irq(chip->dev, irq, 1284 NULL, cy8c95x0_irq_handler, 1285 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_HIGH, 1286 dev_name(chip->dev), chip); 1287 if (ret) { 1288 dev_err(chip->dev, "failed to request irq %d\n", irq); 1289 return ret; 1290 } 1291 dev_info(chip->dev, "Registered threaded IRQ\n"); 1292 1293 return 0; 1294 } 1295 1296 static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip) 1297 { 1298 struct pinctrl_desc *pd = &chip->pinctrl_desc; 1299 1300 pd->pctlops = &cy8c95x0_pinctrl_ops; 1301 pd->confops = &cy8c95x0_pinconf_ops; 1302 pd->pmxops = &cy8c95x0_pmxops; 1303 pd->name = dev_name(chip->dev); 1304 pd->pins = cy8c9560_pins; 1305 pd->npins = chip->tpin; 1306 pd->owner = THIS_MODULE; 1307 1308 chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip); 1309 if (IS_ERR(chip->pctldev)) 1310 return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev), 1311 "can't register controller\n"); 1312 1313 return 0; 1314 } 1315 1316 static int cy8c95x0_detect(struct i2c_client *client, 1317 struct i2c_board_info *info) 1318 { 1319 struct i2c_adapter *adapter = client->adapter; 1320 int ret; 1321 const char *name; 1322 1323 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1324 return -ENODEV; 1325 1326 ret = i2c_smbus_read_byte_data(client, CY8C95X0_DEVID); 1327 if (ret < 0) 1328 return ret; 1329 switch (ret & GENMASK(7, 4)) { 1330 case 0x20: 1331 name = cy8c95x0_id[0].name; 1332 break; 1333 case 0x40: 1334 name = cy8c95x0_id[1].name; 1335 break; 1336 case 0x60: 1337 name = cy8c95x0_id[2].name; 1338 break; 1339 default: 1340 return -ENODEV; 1341 } 1342 1343 dev_info(&client->dev, "Found a %s chip at 0x%02x.\n", name, client->addr); 1344 strscpy(info->type, name, I2C_NAME_SIZE); 1345 1346 return 0; 1347 } 1348 1349 static int cy8c95x0_probe(struct i2c_client *client) 1350 { 1351 struct cy8c95x0_pinctrl *chip; 1352 struct regulator *reg; 1353 int ret; 1354 1355 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); 1356 if (!chip) 1357 return -ENOMEM; 1358 1359 chip->dev = &client->dev; 1360 1361 /* Set the device type */ 1362 chip->driver_data = (uintptr_t)i2c_get_match_data(client); 1363 if (!chip->driver_data) 1364 return -ENODEV; 1365 1366 i2c_set_clientdata(client, chip); 1367 1368 chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK; 1369 chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ); 1370 1371 switch (chip->tpin) { 1372 case 20: 1373 strscpy(chip->name, cy8c95x0_id[0].name, I2C_NAME_SIZE); 1374 break; 1375 case 40: 1376 strscpy(chip->name, cy8c95x0_id[1].name, I2C_NAME_SIZE); 1377 break; 1378 case 60: 1379 strscpy(chip->name, cy8c95x0_id[2].name, I2C_NAME_SIZE); 1380 break; 1381 default: 1382 return -ENODEV; 1383 } 1384 1385 reg = devm_regulator_get(&client->dev, "vdd"); 1386 if (IS_ERR(reg)) { 1387 if (PTR_ERR(reg) == -EPROBE_DEFER) 1388 return -EPROBE_DEFER; 1389 } else { 1390 ret = regulator_enable(reg); 1391 if (ret) { 1392 dev_err(&client->dev, "failed to enable regulator vdd: %d\n", ret); 1393 return ret; 1394 } 1395 chip->regulator = reg; 1396 } 1397 1398 /* bring the chip out of reset if reset pin is provided */ 1399 chip->gpio_reset = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH); 1400 if (IS_ERR(chip->gpio_reset)) { 1401 ret = dev_err_probe(chip->dev, PTR_ERR(chip->gpio_reset), 1402 "Failed to get GPIO 'reset'\n"); 1403 goto err_exit; 1404 } else if (chip->gpio_reset) { 1405 usleep_range(1000, 2000); 1406 gpiod_set_value_cansleep(chip->gpio_reset, 0); 1407 usleep_range(250000, 300000); 1408 1409 gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET"); 1410 } 1411 1412 chip->regmap = devm_regmap_init_i2c(client, &cy8c95x0_i2c_regmap); 1413 if (IS_ERR(chip->regmap)) { 1414 ret = PTR_ERR(chip->regmap); 1415 goto err_exit; 1416 } 1417 1418 bitmap_zero(chip->push_pull, MAX_LINE); 1419 bitmap_zero(chip->shiftmask, MAX_LINE); 1420 bitmap_set(chip->shiftmask, 0, 20); 1421 mutex_init(&chip->i2c_lock); 1422 1423 if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) { 1424 ret = cy8c95x0_acpi_get_irq(&client->dev); 1425 if (ret > 0) 1426 client->irq = ret; 1427 } 1428 1429 if (client->irq) { 1430 ret = cy8c95x0_irq_setup(chip, client->irq); 1431 if (ret) 1432 goto err_exit; 1433 } 1434 1435 ret = cy8c95x0_setup_pinctrl(chip); 1436 if (ret) 1437 goto err_exit; 1438 1439 ret = cy8c95x0_setup_gpiochip(chip); 1440 if (ret) 1441 goto err_exit; 1442 1443 return 0; 1444 1445 err_exit: 1446 if (!IS_ERR_OR_NULL(chip->regulator)) 1447 regulator_disable(chip->regulator); 1448 return ret; 1449 } 1450 1451 static void cy8c95x0_remove(struct i2c_client *client) 1452 { 1453 struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(client); 1454 1455 if (!IS_ERR_OR_NULL(chip->regulator)) 1456 regulator_disable(chip->regulator); 1457 } 1458 1459 static const struct acpi_device_id cy8c95x0_acpi_ids[] = { 1460 { "INT3490", 40, }, 1461 { } 1462 }; 1463 MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids); 1464 1465 static struct i2c_driver cy8c95x0_driver = { 1466 .driver = { 1467 .name = "cy8c95x0-pinctrl", 1468 .of_match_table = cy8c95x0_dt_ids, 1469 .acpi_match_table = cy8c95x0_acpi_ids, 1470 }, 1471 .probe = cy8c95x0_probe, 1472 .remove = cy8c95x0_remove, 1473 .id_table = cy8c95x0_id, 1474 .detect = cy8c95x0_detect, 1475 }; 1476 module_i2c_driver(cy8c95x0_driver); 1477 1478 MODULE_AUTHOR("Patrick Rudolph <patrick.rudolph@9elements.com>"); 1479 MODULE_AUTHOR("Naresh Solanki <naresh.solanki@9elements.com>"); 1480 MODULE_DESCRIPTION("Pinctrl driver for CY8C95X0"); 1481 MODULE_LICENSE("GPL"); 1482