1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd. 4 * Copyright (c) 2024 Collabora Ltd. 5 * 6 * Author: Algea Cao <algea.cao@rock-chips.com> 7 * Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> 8 */ 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/delay.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_platform.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/rational.h> 21 #include <linux/regmap.h> 22 #include <linux/reset.h> 23 24 #define GRF_HDPTX_CON0 0x00 25 #define HDPTX_I_PLL_EN BIT(7) 26 #define HDPTX_I_BIAS_EN BIT(6) 27 #define HDPTX_I_BGR_EN BIT(5) 28 #define HDPTX_MODE_SEL BIT(0) 29 #define GRF_HDPTX_STATUS 0x80 30 #define HDPTX_O_PLL_LOCK_DONE BIT(3) 31 #define HDPTX_O_PHY_CLK_RDY BIT(2) 32 #define HDPTX_O_PHY_RDY BIT(1) 33 #define HDPTX_O_SB_RDY BIT(0) 34 35 #define HDTPX_REG(_n, _min, _max) \ 36 ( \ 37 BUILD_BUG_ON_ZERO((0x##_n) < (0x##_min)) + \ 38 BUILD_BUG_ON_ZERO((0x##_n) > (0x##_max)) + \ 39 ((0x##_n) * 4) \ 40 ) 41 42 #define CMN_REG(n) HDTPX_REG(n, 0000, 00a7) 43 #define SB_REG(n) HDTPX_REG(n, 0100, 0129) 44 #define LNTOP_REG(n) HDTPX_REG(n, 0200, 0229) 45 #define LANE_REG(n) HDTPX_REG(n, 0300, 062d) 46 47 /* CMN_REG(0008) */ 48 #define OVRD_LCPLL_EN_MASK BIT(7) 49 #define LCPLL_EN_MASK BIT(6) 50 #define LCPLL_LCVCO_MODE_EN_MASK BIT(4) 51 /* CMN_REG(001e) */ 52 #define LCPLL_PI_EN_MASK BIT(5) 53 #define LCPLL_100M_CLK_EN_MASK BIT(0) 54 /* CMN_REG(0025) */ 55 #define LCPLL_PMS_IQDIV_RSTN_MASK BIT(4) 56 /* CMN_REG(0028) */ 57 #define LCPLL_SDC_FRAC_EN_MASK BIT(2) 58 #define LCPLL_SDC_FRAC_RSTN_MASK BIT(0) 59 /* CMN_REG(002d) */ 60 #define LCPLL_SDC_N_MASK GENMASK(3, 1) 61 /* CMN_REG(002e) */ 62 #define LCPLL_SDC_NUMBERATOR_MASK GENMASK(5, 0) 63 /* CMN_REG(002f) */ 64 #define LCPLL_SDC_DENOMINATOR_MASK GENMASK(7, 2) 65 #define LCPLL_SDC_NDIV_RSTN_MASK BIT(0) 66 /* CMN_REG(003c) */ 67 #define ANA_LCPLL_RESERVED7_MASK BIT(7) 68 /* CMN_REG(003d) */ 69 #define OVRD_ROPLL_EN_MASK BIT(7) 70 #define ROPLL_EN_MASK BIT(6) 71 #define ROPLL_LCVCO_EN_MASK BIT(4) 72 /* CMN_REG(0046) */ 73 #define ROPLL_ANA_CPP_CTRL_COARSE_MASK GENMASK(7, 4) 74 #define ROPLL_ANA_CPP_CTRL_FINE_MASK GENMASK(3, 0) 75 /* CMN_REG(0047) */ 76 #define ROPLL_ANA_LPF_C_SEL_COARSE_MASK GENMASK(5, 3) 77 #define ROPLL_ANA_LPF_C_SEL_FINE_MASK GENMASK(2, 0) 78 /* CMN_REG(004e) */ 79 #define ROPLL_PI_EN_MASK BIT(5) 80 /* CMN_REG(0051) */ 81 #define ROPLL_PMS_MDIV_MASK GENMASK(7, 0) 82 /* CMN_REG(0055) */ 83 #define ROPLL_PMS_MDIV_AFC_MASK GENMASK(7, 0) 84 /* CMN_REG(0059) */ 85 #define ANA_ROPLL_PMS_PDIV_MASK GENMASK(7, 4) 86 #define ANA_ROPLL_PMS_REFDIV_MASK GENMASK(3, 0) 87 /* CMN_REG(005a) */ 88 #define ROPLL_PMS_SDIV_RBR_MASK GENMASK(7, 4) 89 #define ROPLL_PMS_SDIV_HBR_MASK GENMASK(3, 0) 90 /* CMN_REG(005b) */ 91 #define ROPLL_PMS_SDIV_HBR2_MASK GENMASK(7, 4) 92 /* CMN_REG(005c) */ 93 #define ROPLL_PMS_IQDIV_RSTN_MASK BIT(5) 94 /* CMN_REG(005e) */ 95 #define ROPLL_SDM_EN_MASK BIT(6) 96 #define OVRD_ROPLL_SDM_RSTN_MASK BIT(5) 97 #define ROPLL_SDM_RSTN_MASK BIT(4) 98 #define ROPLL_SDC_FRAC_EN_RBR_MASK BIT(3) 99 #define ROPLL_SDC_FRAC_EN_HBR_MASK BIT(2) 100 #define ROPLL_SDC_FRAC_EN_HBR2_MASK BIT(1) 101 #define ROPLL_SDM_FRAC_EN_HBR3_MASK BIT(0) 102 /* CMN_REG(005f) */ 103 #define OVRD_ROPLL_SDC_RSTN_MASK BIT(5) 104 #define ROPLL_SDC_RSTN_MASK BIT(4) 105 /* CMN_REG(0060) */ 106 #define ROPLL_SDM_DENOMINATOR_MASK GENMASK(7, 0) 107 /* CMN_REG(0064) */ 108 #define ROPLL_SDM_NUM_SIGN_RBR_MASK BIT(3) 109 #define ROPLL_SDM_NUM_SIGN_HBR_MASK BIT(2) 110 #define ROPLL_SDM_NUM_SIGN_HBR2_MASK BIT(1) 111 /* CMN_REG(0065) */ 112 #define ROPLL_SDM_NUM_MASK GENMASK(7, 0) 113 /* CMN_REG(0069) */ 114 #define ROPLL_SDC_N_RBR_MASK GENMASK(2, 0) 115 /* CMN_REG(006a) */ 116 #define ROPLL_SDC_N_HBR_MASK GENMASK(5, 3) 117 #define ROPLL_SDC_N_HBR2_MASK GENMASK(2, 0) 118 /* CMN_REG(006b) */ 119 #define ROPLL_SDC_N_HBR3_MASK GENMASK(3, 1) 120 /* CMN_REG(006c) */ 121 #define ROPLL_SDC_NUM_MASK GENMASK(5, 0) 122 /* cmn_reg0070 */ 123 #define ROPLL_SDC_DENO_MASK GENMASK(5, 0) 124 /* CMN_REG(0074) */ 125 #define OVRD_ROPLL_SDC_NDIV_RSTN_MASK BIT(3) 126 #define ROPLL_SDC_NDIV_RSTN_MASK BIT(2) 127 #define OVRD_ROPLL_SSC_EN_MASK BIT(1) 128 #define ROPLL_SSC_EN_MASK BIT(0) 129 /* CMN_REG(0075) */ 130 #define ANA_ROPLL_SSC_FM_DEVIATION_MASK GENMASK(5, 0) 131 /* CMN_REG(0076) */ 132 #define ANA_ROPLL_SSC_FM_FREQ_MASK GENMASK(6, 2) 133 /* CMN_REG(0077) */ 134 #define ANA_ROPLL_SSC_CLK_DIV_SEL_MASK GENMASK(6, 3) 135 /* CMN_REG(0081) */ 136 #define OVRD_PLL_CD_CLK_EN_MASK BIT(8) 137 #define ANA_PLL_CD_TX_SER_RATE_SEL_MASK BIT(3) 138 #define ANA_PLL_CD_HSCLK_WEST_EN_MASK BIT(1) 139 #define ANA_PLL_CD_HSCLK_EAST_EN_MASK BIT(0) 140 /* CMN_REG(0082) */ 141 #define ANA_PLL_CD_VREG_GAIN_CTRL_MASK GENMASK(3, 0) 142 /* CMN_REG(0083) */ 143 #define ANA_PLL_CD_VREG_ICTRL_MASK GENMASK(6, 5) 144 /* CMN_REG(0084) */ 145 #define PLL_LCRO_CLK_SEL_MASK BIT(5) 146 /* CMN_REG(0085) */ 147 #define ANA_PLL_SYNC_LOSS_DET_MODE_MASK GENMASK(1, 0) 148 /* CMN_REG(0086) */ 149 #define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4) 150 #define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1) 151 #define PLL_PCG_CLK_EN_MASK BIT(0) 152 /* CMN_REG(0087) */ 153 #define ANA_PLL_FRL_MODE_EN_MASK BIT(3) 154 #define ANA_PLL_TX_HS_CLK_EN_MASK BIT(2) 155 /* CMN_REG(0089) */ 156 #define LCPLL_ALONE_MODE_MASK BIT(1) 157 /* CMN_REG(0095) */ 158 #define DP_TX_LINK_BW_MASK GENMASK(1, 0) 159 /* CMN_REG(0097) */ 160 #define DIG_CLK_SEL_MASK BIT(1) 161 #define LCPLL_REF BIT(1) 162 #define ROPLL_REF 0 163 /* CMN_REG(0099) */ 164 #define SSC_EN_MASK GENMASK(7, 6) 165 #define CMN_ROPLL_ALONE_MODE_MASK BIT(2) 166 #define ROPLL_ALONE_MODE BIT(2) 167 /* CMN_REG(009a) */ 168 #define HS_SPEED_SEL_MASK BIT(0) 169 #define DIV_10_CLOCK BIT(0) 170 /* CMN_REG(009b) */ 171 #define LS_SPEED_SEL_MASK BIT(4) 172 #define LINK_SYMBOL_CLOCK BIT(4) 173 #define LINK_SYMBOL_CLOCK1_2 0 174 175 /* SB_REG(0102) */ 176 #define OVRD_SB_RXTERM_EN_MASK BIT(5) 177 #define SB_RXTERM_EN_MASK BIT(4) 178 #define ANA_SB_RXTERM_OFFSP_MASK GENMASK(3, 0) 179 /* SB_REG(0103) */ 180 #define ANA_SB_RXTERM_OFFSN_MASK GENMASK(6, 3) 181 #define OVRD_SB_RX_RESCAL_DONE_MASK BIT(1) 182 #define SB_RX_RESCAL_DONE_MASK BIT(0) 183 /* SB_REG(0104) */ 184 #define OVRD_SB_EN_MASK BIT(5) 185 #define SB_EN_MASK BIT(4) 186 #define OVRD_SB_AUX_EN_MASK BIT(1) 187 #define SB_AUX_EN_MASK BIT(0) 188 /* SB_REG(0105) */ 189 #define OVRD_SB_EARC_CMDC_EN_MASK BIT(6) 190 #define SB_EARC_CMDC_EN_MASK BIT(5) 191 #define ANA_SB_TX_HLVL_PROG_MASK GENMASK(2, 0) 192 /* SB_REG(0106) */ 193 #define ANA_SB_TX_LLVL_PROG_MASK GENMASK(6, 4) 194 /* SB_REG(0109) */ 195 #define ANA_SB_DMRX_AFC_DIV_RATIO_MASK GENMASK(2, 0) 196 /* SB_REG(010d) */ 197 #define ANA_SB_DMRX_LPBK_DATA_MASK BIT(4) 198 /* SB_REG(010f) */ 199 #define OVRD_SB_VREG_EN_MASK BIT(7) 200 #define SB_VREG_EN_MASK BIT(6) 201 #define OVRD_SB_VREG_LPF_BYPASS_MASK BIT(5) 202 #define SB_VREG_LPF_BYPASS_MASK BIT(4) 203 #define ANA_SB_VREG_GAIN_CTRL_MASK GENMASK(3, 0) 204 /* SB_REG(0110) */ 205 #define ANA_SB_VREG_OUT_SEL_MASK BIT(1) 206 #define ANA_SB_VREG_REF_SEL_MASK BIT(0) 207 /* SB_REG(0113) */ 208 #define SB_RX_RCAL_OPT_CODE_MASK GENMASK(5, 4) 209 #define SB_RX_RTERM_CTRL_MASK GENMASK(3, 0) 210 /* SB_REG(0114) */ 211 #define SB_TG_SB_EN_DELAY_TIME_MASK GENMASK(5, 3) 212 #define SB_TG_RXTERM_EN_DELAY_TIME_MASK GENMASK(2, 0) 213 /* SB_REG(0115) */ 214 #define SB_READY_DELAY_TIME_MASK GENMASK(5, 3) 215 #define SB_TG_OSC_EN_DELAY_TIME_MASK GENMASK(2, 0) 216 /* SB_REG(0116) */ 217 #define AFC_RSTN_DELAY_TIME_MASK GENMASK(6, 4) 218 /* SB_REG(0117) */ 219 #define FAST_PULSE_TIME_MASK GENMASK(3, 0) 220 /* SB_REG(0118) */ 221 #define SB_TG_EARC_DMRX_RECVRD_CLK_CNT_MASK GENMASK(7, 0) 222 /* SB_REG(011a) */ 223 #define SB_TG_CNT_RUN_NO_7_0_MASK GENMASK(7, 0) 224 /* SB_REG(011b) */ 225 #define SB_EARC_SIG_DET_BYPASS_MASK BIT(4) 226 #define SB_AFC_TOL_MASK GENMASK(3, 0) 227 /* SB_REG(011c) */ 228 #define SB_AFC_STB_NUM_MASK GENMASK(3, 0) 229 /* SB_REG(011d) */ 230 #define SB_TG_OSC_CNT_MIN_MASK GENMASK(7, 0) 231 /* SB_REG(011e) */ 232 #define SB_TG_OSC_CNT_MAX_MASK GENMASK(7, 0) 233 /* SB_REG(011f) */ 234 #define SB_PWM_AFC_CTRL_MASK GENMASK(7, 2) 235 #define SB_RCAL_RSTN_MASK BIT(1) 236 /* SB_REG(0120) */ 237 #define SB_AUX_EN_IN_MASK BIT(7) 238 #define SB_EARC_EN_MASK BIT(1) 239 #define SB_EARC_AFC_EN_MASK BIT(2) 240 /* SB_REG(0123) */ 241 #define OVRD_SB_READY_MASK BIT(5) 242 #define SB_READY_MASK BIT(4) 243 244 /* LNTOP_REG(0200) */ 245 #define PROTOCOL_SEL_MASK BIT(2) 246 #define HDMI_MODE BIT(2) 247 #define HDMI_TMDS_FRL_SEL BIT(1) 248 /* LNTOP_REG(0206) */ 249 #define DATA_BUS_WIDTH_MASK GENMASK(2, 1) 250 #define DATA_BUS_WIDTH_SEL_MASK BIT(0) 251 #define DATA_BUS_36_40 BIT(0) 252 /* LNTOP_REG(0207) */ 253 #define LANE_EN_MASK 0xf 254 #define ALL_LANE_EN 0xf 255 256 /* LANE_REG(0301) */ 257 #define OVRD_LN_TX_DRV_EI_EN_MASK BIT(7) 258 #define LN_TX_DRV_EI_EN_MASK BIT(6) 259 /* LANE_REG(0303) */ 260 #define OVRD_LN_TX_DRV_LVL_CTRL_MASK BIT(5) 261 #define LN_TX_DRV_LVL_CTRL_MASK GENMASK(4, 0) 262 /* LANE_REG(0304) */ 263 #define OVRD_LN_TX_DRV_POST_LVL_CTRL_MASK BIT(4) 264 #define LN_TX_DRV_POST_LVL_CTRL_MASK GENMASK(3, 0) 265 /* LANE_REG(0305) */ 266 #define OVRD_LN_TX_DRV_PRE_LVL_CTRL_MASK BIT(6) 267 #define LN_TX_DRV_PRE_LVL_CTRL_MASK GENMASK(5, 2) 268 /* LANE_REG(0306) */ 269 #define LN_ANA_TX_DRV_IDRV_IDN_CTRL_MASK GENMASK(7, 5) 270 #define LN_ANA_TX_DRV_IDRV_IUP_CTRL_MASK GENMASK(4, 2) 271 #define LN_ANA_TX_DRV_ACCDRV_EN_MASK BIT(0) 272 /* LANE_REG(0307) */ 273 #define LN_ANA_TX_DRV_ACCDRV_POL_SEL_MASK BIT(6) 274 #define LN_ANA_TX_DRV_ACCDRV_CTRL_MASK GENMASK(5, 3) 275 /* LANE_REG(030a) */ 276 #define LN_ANA_TX_JEQ_EN_MASK BIT(4) 277 #define LN_TX_JEQ_EVEN_CTRL_RBR_MASK GENMASK(3, 0) 278 /* LANE_REG(030b) */ 279 #define LN_TX_JEQ_EVEN_CTRL_HBR_MASK GENMASK(7, 4) 280 #define LN_TX_JEQ_EVEN_CTRL_HBR2_MASK GENMASK(3, 0) 281 /* LANE_REG(030c) */ 282 #define LN_TX_JEQ_ODD_CTRL_RBR_MASK GENMASK(3, 0) 283 /* LANE_REG(030d) */ 284 #define LN_TX_JEQ_ODD_CTRL_HBR_MASK GENMASK(7, 4) 285 #define LN_TX_JEQ_ODD_CTRL_HBR2_MASK GENMASK(3, 0) 286 /* LANE_REG(0310) */ 287 #define LN_ANA_TX_SYNC_LOSS_DET_MODE_MASK GENMASK(1, 0) 288 /* LANE_REG(0311) */ 289 #define LN_TX_SER_40BIT_EN_RBR_MASK BIT(3) 290 #define LN_TX_SER_40BIT_EN_HBR_MASK BIT(2) 291 #define LN_TX_SER_40BIT_EN_HBR2_MASK BIT(1) 292 /* LANE_REG(0312) */ 293 #define LN0_TX_SER_RATE_SEL_RBR_MASK BIT(5) 294 #define LN0_TX_SER_RATE_SEL_HBR_MASK BIT(4) 295 #define LN0_TX_SER_RATE_SEL_HBR2_MASK BIT(3) 296 #define LN0_TX_SER_RATE_SEL_HBR3_MASK BIT(2) 297 /* LANE_REG(0316) */ 298 #define LN_ANA_TX_SER_VREG_GAIN_CTRL_MASK GENMASK(3, 0) 299 /* LANE_REG(031B) */ 300 #define LN_ANA_TX_RESERVED_MASK GENMASK(7, 0) 301 /* LANE_REG(031e) */ 302 #define LN_POLARITY_INV_MASK BIT(2) 303 #define LN_LANE_MODE_MASK BIT(1) 304 305 /* LANE_REG(0412) */ 306 #define LN1_TX_SER_RATE_SEL_RBR_MASK BIT(5) 307 #define LN1_TX_SER_RATE_SEL_HBR_MASK BIT(4) 308 #define LN1_TX_SER_RATE_SEL_HBR2_MASK BIT(3) 309 #define LN1_TX_SER_RATE_SEL_HBR3_MASK BIT(2) 310 311 /* LANE_REG(0512) */ 312 #define LN2_TX_SER_RATE_SEL_RBR_MASK BIT(5) 313 #define LN2_TX_SER_RATE_SEL_HBR_MASK BIT(4) 314 #define LN2_TX_SER_RATE_SEL_HBR2_MASK BIT(3) 315 #define LN2_TX_SER_RATE_SEL_HBR3_MASK BIT(2) 316 317 /* LANE_REG(0612) */ 318 #define LN3_TX_SER_RATE_SEL_RBR_MASK BIT(5) 319 #define LN3_TX_SER_RATE_SEL_HBR_MASK BIT(4) 320 #define LN3_TX_SER_RATE_SEL_HBR2_MASK BIT(3) 321 #define LN3_TX_SER_RATE_SEL_HBR3_MASK BIT(2) 322 323 #define HDMI20_MAX_RATE 600000000 324 325 enum dp_link_rate { 326 DP_BW_RBR, 327 DP_BW_HBR, 328 DP_BW_HBR2, 329 }; 330 331 struct lcpll_config { 332 u32 bit_rate; 333 u8 lcvco_mode_en; 334 u8 pi_en; 335 u8 clk_en_100m; 336 u8 pms_mdiv; 337 u8 pms_mdiv_afc; 338 u8 pms_pdiv; 339 u8 pms_refdiv; 340 u8 pms_sdiv; 341 u8 pi_cdiv_rstn; 342 u8 pi_cdiv_sel; 343 u8 sdm_en; 344 u8 sdm_rstn; 345 u8 sdc_frac_en; 346 u8 sdc_rstn; 347 u8 sdm_deno; 348 u8 sdm_num_sign; 349 u8 sdm_num; 350 u8 sdc_n; 351 u8 sdc_n2; 352 u8 sdc_num; 353 u8 sdc_deno; 354 u8 sdc_ndiv_rstn; 355 u8 ssc_en; 356 u8 ssc_fm_dev; 357 u8 ssc_fm_freq; 358 u8 ssc_clk_div_sel; 359 u8 cd_tx_ser_rate_sel; 360 }; 361 362 struct ropll_config { 363 u32 bit_rate; 364 u8 pms_mdiv; 365 u8 pms_mdiv_afc; 366 u8 pms_pdiv; 367 u8 pms_refdiv; 368 u8 pms_sdiv; 369 u8 pms_iqdiv_rstn; 370 u8 ref_clk_sel; 371 u8 sdm_en; 372 u8 sdm_rstn; 373 u8 sdc_frac_en; 374 u8 sdc_rstn; 375 u8 sdm_clk_div; 376 u8 sdm_deno; 377 u8 sdm_num_sign; 378 u8 sdm_num; 379 u8 sdc_n; 380 u8 sdc_num; 381 u8 sdc_deno; 382 u8 sdc_ndiv_rstn; 383 u8 ssc_en; 384 u8 ssc_fm_dev; 385 u8 ssc_fm_freq; 386 u8 ssc_clk_div_sel; 387 u8 ana_cpp_ctrl; 388 u8 ana_lpf_c_sel; 389 u8 cd_tx_ser_rate_sel; 390 }; 391 392 struct tx_drv_ctrl { 393 u8 tx_drv_lvl_ctrl; 394 u8 tx_drv_post_lvl_ctrl; 395 u8 ana_tx_drv_idrv_idn_ctrl; 396 u8 ana_tx_drv_idrv_iup_ctrl; 397 u8 ana_tx_drv_accdrv_en; 398 u8 ana_tx_drv_accdrv_ctrl; 399 u8 tx_drv_pre_lvl_ctrl; 400 u8 ana_tx_jeq_en; 401 u8 tx_jeq_even_ctrl; 402 u8 tx_jeq_odd_ctrl; 403 }; 404 405 enum rk_hdptx_reset { 406 RST_APB = 0, 407 RST_INIT, 408 RST_CMN, 409 RST_LANE, 410 RST_MAX 411 }; 412 413 #define MAX_HDPTX_PHY_NUM 2 414 415 struct rk_hdptx_phy_cfg { 416 unsigned int num_phys; 417 unsigned int phy_ids[MAX_HDPTX_PHY_NUM]; 418 }; 419 420 struct rk_hdptx_phy { 421 struct device *dev; 422 struct regmap *regmap; 423 struct regmap *grf; 424 425 /* PHY const config */ 426 const struct rk_hdptx_phy_cfg *cfgs; 427 int phy_id; 428 429 struct phy *phy; 430 struct phy_config *phy_cfg; 431 struct clk_bulk_data *clks; 432 int nr_clks; 433 struct reset_control_bulk_data rsts[RST_MAX]; 434 435 /* clk provider */ 436 struct clk_hw hw; 437 unsigned long rate; 438 439 atomic_t usage_count; 440 441 /* used for dp mode */ 442 unsigned int link_rate; 443 unsigned int lanes; 444 }; 445 446 static const struct ropll_config ropll_tmds_cfg[] = { 447 { 5940000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 448 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 449 { 3712500, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 450 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 451 { 2970000, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 452 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 453 { 1620000, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, 454 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 455 { 1856250, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 456 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 457 { 1540000, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1, 458 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 459 { 1485000, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5, 460 0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 461 { 1462500, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1, 462 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 463 { 1190000, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1, 464 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 465 { 1065000, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1, 466 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 467 { 1080000, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 468 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 469 { 855000, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1, 470 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 471 { 835000, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0, 472 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 473 { 928125, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 474 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 475 { 742500, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 476 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 477 { 650000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1, 478 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 479 { 337500, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5, 480 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 481 { 400000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 482 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 483 { 270000, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 484 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 485 { 251750, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1, 486 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 487 }; 488 489 static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = { 490 REG_SEQ0(CMN_REG(0009), 0x0c), 491 REG_SEQ0(CMN_REG(000a), 0x83), 492 REG_SEQ0(CMN_REG(000b), 0x06), 493 REG_SEQ0(CMN_REG(000c), 0x20), 494 REG_SEQ0(CMN_REG(000d), 0xb8), 495 REG_SEQ0(CMN_REG(000e), 0x0f), 496 REG_SEQ0(CMN_REG(000f), 0x0f), 497 REG_SEQ0(CMN_REG(0010), 0x04), 498 REG_SEQ0(CMN_REG(0011), 0x00), 499 REG_SEQ0(CMN_REG(0012), 0x26), 500 REG_SEQ0(CMN_REG(0013), 0x22), 501 REG_SEQ0(CMN_REG(0014), 0x24), 502 REG_SEQ0(CMN_REG(0015), 0x77), 503 REG_SEQ0(CMN_REG(0016), 0x08), 504 REG_SEQ0(CMN_REG(0017), 0x00), 505 REG_SEQ0(CMN_REG(0018), 0x04), 506 REG_SEQ0(CMN_REG(0019), 0x48), 507 REG_SEQ0(CMN_REG(001a), 0x01), 508 REG_SEQ0(CMN_REG(001b), 0x00), 509 REG_SEQ0(CMN_REG(001c), 0x01), 510 REG_SEQ0(CMN_REG(001d), 0x64), 511 REG_SEQ0(CMN_REG(001f), 0x00), 512 REG_SEQ0(CMN_REG(0026), 0x53), 513 REG_SEQ0(CMN_REG(0029), 0x01), 514 REG_SEQ0(CMN_REG(0030), 0x00), 515 REG_SEQ0(CMN_REG(0031), 0x20), 516 REG_SEQ0(CMN_REG(0032), 0x30), 517 REG_SEQ0(CMN_REG(0033), 0x0b), 518 REG_SEQ0(CMN_REG(0034), 0x23), 519 REG_SEQ0(CMN_REG(0035), 0x00), 520 REG_SEQ0(CMN_REG(0038), 0x00), 521 REG_SEQ0(CMN_REG(0039), 0x00), 522 REG_SEQ0(CMN_REG(003a), 0x00), 523 REG_SEQ0(CMN_REG(003b), 0x00), 524 REG_SEQ0(CMN_REG(003c), 0x80), 525 REG_SEQ0(CMN_REG(003e), 0x0c), 526 REG_SEQ0(CMN_REG(003f), 0x83), 527 REG_SEQ0(CMN_REG(0040), 0x06), 528 REG_SEQ0(CMN_REG(0041), 0x20), 529 REG_SEQ0(CMN_REG(0042), 0xb8), 530 REG_SEQ0(CMN_REG(0043), 0x00), 531 REG_SEQ0(CMN_REG(0044), 0x46), 532 REG_SEQ0(CMN_REG(0045), 0x24), 533 REG_SEQ0(CMN_REG(0046), 0xff), 534 REG_SEQ0(CMN_REG(0047), 0x00), 535 REG_SEQ0(CMN_REG(0048), 0x44), 536 REG_SEQ0(CMN_REG(0049), 0xfa), 537 REG_SEQ0(CMN_REG(004a), 0x08), 538 REG_SEQ0(CMN_REG(004b), 0x00), 539 REG_SEQ0(CMN_REG(004c), 0x01), 540 REG_SEQ0(CMN_REG(004d), 0x64), 541 REG_SEQ0(CMN_REG(004e), 0x14), 542 REG_SEQ0(CMN_REG(004f), 0x00), 543 REG_SEQ0(CMN_REG(0050), 0x00), 544 REG_SEQ0(CMN_REG(005d), 0x0c), 545 REG_SEQ0(CMN_REG(005f), 0x01), 546 REG_SEQ0(CMN_REG(006b), 0x04), 547 REG_SEQ0(CMN_REG(0073), 0x30), 548 REG_SEQ0(CMN_REG(0074), 0x00), 549 REG_SEQ0(CMN_REG(0075), 0x20), 550 REG_SEQ0(CMN_REG(0076), 0x30), 551 REG_SEQ0(CMN_REG(0077), 0x08), 552 REG_SEQ0(CMN_REG(0078), 0x0c), 553 REG_SEQ0(CMN_REG(0079), 0x00), 554 REG_SEQ0(CMN_REG(007b), 0x00), 555 REG_SEQ0(CMN_REG(007c), 0x00), 556 REG_SEQ0(CMN_REG(007d), 0x00), 557 REG_SEQ0(CMN_REG(007e), 0x00), 558 REG_SEQ0(CMN_REG(007f), 0x00), 559 REG_SEQ0(CMN_REG(0080), 0x00), 560 REG_SEQ0(CMN_REG(0081), 0x09), 561 REG_SEQ0(CMN_REG(0082), 0x04), 562 REG_SEQ0(CMN_REG(0083), 0x24), 563 REG_SEQ0(CMN_REG(0084), 0x20), 564 REG_SEQ0(CMN_REG(0085), 0x03), 565 REG_SEQ0(CMN_REG(0086), 0x01), 566 REG_SEQ0(CMN_REG(0087), 0x0c), 567 REG_SEQ0(CMN_REG(008a), 0x55), 568 REG_SEQ0(CMN_REG(008b), 0x25), 569 REG_SEQ0(CMN_REG(008c), 0x2c), 570 REG_SEQ0(CMN_REG(008d), 0x22), 571 REG_SEQ0(CMN_REG(008e), 0x14), 572 REG_SEQ0(CMN_REG(008f), 0x20), 573 REG_SEQ0(CMN_REG(0090), 0x00), 574 REG_SEQ0(CMN_REG(0091), 0x00), 575 REG_SEQ0(CMN_REG(0092), 0x00), 576 REG_SEQ0(CMN_REG(0093), 0x00), 577 REG_SEQ0(CMN_REG(009a), 0x11), 578 REG_SEQ0(CMN_REG(009b), 0x10), 579 }; 580 581 static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = { 582 REG_SEQ0(CMN_REG(0008), 0x00), 583 REG_SEQ0(CMN_REG(0011), 0x01), 584 REG_SEQ0(CMN_REG(0017), 0x20), 585 REG_SEQ0(CMN_REG(001e), 0x14), 586 REG_SEQ0(CMN_REG(0020), 0x00), 587 REG_SEQ0(CMN_REG(0021), 0x00), 588 REG_SEQ0(CMN_REG(0022), 0x11), 589 REG_SEQ0(CMN_REG(0023), 0x00), 590 REG_SEQ0(CMN_REG(0024), 0x00), 591 REG_SEQ0(CMN_REG(0025), 0x53), 592 REG_SEQ0(CMN_REG(0026), 0x00), 593 REG_SEQ0(CMN_REG(0027), 0x00), 594 REG_SEQ0(CMN_REG(0028), 0x01), 595 REG_SEQ0(CMN_REG(002a), 0x00), 596 REG_SEQ0(CMN_REG(002b), 0x00), 597 REG_SEQ0(CMN_REG(002c), 0x00), 598 REG_SEQ0(CMN_REG(002d), 0x00), 599 REG_SEQ0(CMN_REG(002e), 0x04), 600 REG_SEQ0(CMN_REG(002f), 0x00), 601 REG_SEQ0(CMN_REG(0030), 0x20), 602 REG_SEQ0(CMN_REG(0031), 0x30), 603 REG_SEQ0(CMN_REG(0032), 0x0b), 604 REG_SEQ0(CMN_REG(0033), 0x23), 605 REG_SEQ0(CMN_REG(0034), 0x00), 606 REG_SEQ0(CMN_REG(003d), 0x40), 607 REG_SEQ0(CMN_REG(0042), 0x78), 608 REG_SEQ0(CMN_REG(004e), 0x34), 609 REG_SEQ0(CMN_REG(005c), 0x25), 610 REG_SEQ0(CMN_REG(005e), 0x4f), 611 REG_SEQ0(CMN_REG(0074), 0x04), 612 REG_SEQ0(CMN_REG(0081), 0x01), 613 REG_SEQ0(CMN_REG(0087), 0x04), 614 REG_SEQ0(CMN_REG(0089), 0x00), 615 REG_SEQ0(CMN_REG(0095), 0x00), 616 REG_SEQ0(CMN_REG(0097), 0x02), 617 REG_SEQ0(CMN_REG(0099), 0x04), 618 REG_SEQ0(CMN_REG(009b), 0x00), 619 }; 620 621 static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = { 622 REG_SEQ0(SB_REG(0114), 0x00), 623 REG_SEQ0(SB_REG(0115), 0x00), 624 REG_SEQ0(SB_REG(0116), 0x00), 625 REG_SEQ0(SB_REG(0117), 0x00), 626 }; 627 628 static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] = { 629 REG_SEQ0(LNTOP_REG(0201), 0x00), 630 REG_SEQ0(LNTOP_REG(0202), 0x00), 631 REG_SEQ0(LNTOP_REG(0203), 0x0f), 632 REG_SEQ0(LNTOP_REG(0204), 0xff), 633 REG_SEQ0(LNTOP_REG(0205), 0xff), 634 }; 635 636 static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = { 637 REG_SEQ0(LNTOP_REG(0201), 0x07), 638 REG_SEQ0(LNTOP_REG(0202), 0xc1), 639 REG_SEQ0(LNTOP_REG(0203), 0xf0), 640 REG_SEQ0(LNTOP_REG(0204), 0x7c), 641 REG_SEQ0(LNTOP_REG(0205), 0x1f), 642 }; 643 644 static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = { 645 REG_SEQ0(LANE_REG(0303), 0x0c), 646 REG_SEQ0(LANE_REG(0307), 0x20), 647 REG_SEQ0(LANE_REG(030a), 0x17), 648 REG_SEQ0(LANE_REG(030b), 0x77), 649 REG_SEQ0(LANE_REG(030c), 0x77), 650 REG_SEQ0(LANE_REG(030d), 0x77), 651 REG_SEQ0(LANE_REG(030e), 0x38), 652 REG_SEQ0(LANE_REG(0310), 0x03), 653 REG_SEQ0(LANE_REG(0311), 0x0f), 654 REG_SEQ0(LANE_REG(0316), 0x02), 655 REG_SEQ0(LANE_REG(031b), 0x01), 656 REG_SEQ0(LANE_REG(031f), 0x15), 657 REG_SEQ0(LANE_REG(0320), 0xa0), 658 REG_SEQ0(LANE_REG(0403), 0x0c), 659 REG_SEQ0(LANE_REG(0407), 0x20), 660 REG_SEQ0(LANE_REG(040a), 0x17), 661 REG_SEQ0(LANE_REG(040b), 0x77), 662 REG_SEQ0(LANE_REG(040c), 0x77), 663 REG_SEQ0(LANE_REG(040d), 0x77), 664 REG_SEQ0(LANE_REG(040e), 0x38), 665 REG_SEQ0(LANE_REG(0410), 0x03), 666 REG_SEQ0(LANE_REG(0411), 0x0f), 667 REG_SEQ0(LANE_REG(0416), 0x02), 668 REG_SEQ0(LANE_REG(041b), 0x01), 669 REG_SEQ0(LANE_REG(041f), 0x15), 670 REG_SEQ0(LANE_REG(0420), 0xa0), 671 REG_SEQ0(LANE_REG(0503), 0x0c), 672 REG_SEQ0(LANE_REG(0507), 0x20), 673 REG_SEQ0(LANE_REG(050a), 0x17), 674 REG_SEQ0(LANE_REG(050b), 0x77), 675 REG_SEQ0(LANE_REG(050c), 0x77), 676 REG_SEQ0(LANE_REG(050d), 0x77), 677 REG_SEQ0(LANE_REG(050e), 0x38), 678 REG_SEQ0(LANE_REG(0510), 0x03), 679 REG_SEQ0(LANE_REG(0511), 0x0f), 680 REG_SEQ0(LANE_REG(0516), 0x02), 681 REG_SEQ0(LANE_REG(051b), 0x01), 682 REG_SEQ0(LANE_REG(051f), 0x15), 683 REG_SEQ0(LANE_REG(0520), 0xa0), 684 REG_SEQ0(LANE_REG(0603), 0x0c), 685 REG_SEQ0(LANE_REG(0607), 0x20), 686 REG_SEQ0(LANE_REG(060a), 0x17), 687 REG_SEQ0(LANE_REG(060b), 0x77), 688 REG_SEQ0(LANE_REG(060c), 0x77), 689 REG_SEQ0(LANE_REG(060d), 0x77), 690 REG_SEQ0(LANE_REG(060e), 0x38), 691 REG_SEQ0(LANE_REG(0610), 0x03), 692 REG_SEQ0(LANE_REG(0611), 0x0f), 693 REG_SEQ0(LANE_REG(0616), 0x02), 694 REG_SEQ0(LANE_REG(061b), 0x01), 695 REG_SEQ0(LANE_REG(061f), 0x15), 696 REG_SEQ0(LANE_REG(0620), 0xa0), 697 }; 698 699 static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = { 700 REG_SEQ0(LANE_REG(0312), 0x00), 701 REG_SEQ0(LANE_REG(031e), 0x00), 702 REG_SEQ0(LANE_REG(0412), 0x00), 703 REG_SEQ0(LANE_REG(041e), 0x00), 704 REG_SEQ0(LANE_REG(0512), 0x00), 705 REG_SEQ0(LANE_REG(051e), 0x00), 706 REG_SEQ0(LANE_REG(0612), 0x00), 707 REG_SEQ0(LANE_REG(061e), 0x08), 708 REG_SEQ0(LANE_REG(0303), 0x2f), 709 REG_SEQ0(LANE_REG(0403), 0x2f), 710 REG_SEQ0(LANE_REG(0503), 0x2f), 711 REG_SEQ0(LANE_REG(0603), 0x2f), 712 REG_SEQ0(LANE_REG(0305), 0x03), 713 REG_SEQ0(LANE_REG(0405), 0x03), 714 REG_SEQ0(LANE_REG(0505), 0x03), 715 REG_SEQ0(LANE_REG(0605), 0x03), 716 REG_SEQ0(LANE_REG(0306), 0x1c), 717 REG_SEQ0(LANE_REG(0406), 0x1c), 718 REG_SEQ0(LANE_REG(0506), 0x1c), 719 REG_SEQ0(LANE_REG(0606), 0x1c), 720 }; 721 722 static struct tx_drv_ctrl tx_drv_ctrl_rbr[4][4] = { 723 /* voltage swing 0, pre-emphasis 0->3 */ 724 { 725 { 0x2, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 726 { 0x4, 0x3, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 727 { 0x7, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 728 { 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 729 }, 730 731 /* voltage swing 1, pre-emphasis 0->2 */ 732 { 733 { 0x4, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 734 { 0x9, 0x5, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 735 { 0xc, 0x8, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 736 }, 737 738 /* voltage swing 2, pre-emphasis 0->1 */ 739 { 740 { 0x8, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 741 { 0xc, 0x5, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 742 }, 743 744 /* voltage swing 3, pre-emphasis 0 */ 745 { 746 { 0xb, 0x0, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 }, 747 } 748 }; 749 750 static struct tx_drv_ctrl tx_drv_ctrl_hbr[4][4] = { 751 /* voltage swing 0, pre-emphasis 0->3 */ 752 { 753 { 0x2, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 754 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 755 { 0x9, 0x8, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 756 { 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 757 }, 758 759 /* voltage swing 1, pre-emphasis 0->2 */ 760 { 761 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 762 { 0xa, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 763 { 0xc, 0x8, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 764 }, 765 766 /* voltage swing 2, pre-emphasis 0->1 */ 767 { 768 { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 769 { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 770 }, 771 772 /* voltage swing 3, pre-emphasis 0 */ 773 { 774 { 0xc, 0x1, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 }, 775 } 776 }; 777 778 static struct tx_drv_ctrl tx_drv_ctrl_hbr2[4][4] = { 779 /* voltage swing 0, pre-emphasis 0->3 */ 780 { 781 { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 782 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 783 { 0x9, 0x8, 0x4, 0x6, 0x1, 0x4, 0x0, 0x1, 0x7, 0x7 }, 784 { 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 785 }, 786 787 /* voltage swing 1, pre-emphasis 0->2 */ 788 { 789 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 790 { 0xb, 0x7, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 791 { 0xd, 0x9, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 792 }, 793 794 /* voltage swing 2, pre-emphasis 0->1 */ 795 { 796 { 0x8, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 797 { 0xc, 0x6, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 798 }, 799 800 /* voltage swing 3, pre-emphasis 0 */ 801 { 802 { 0xb, 0x0, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 }, 803 } 804 }; 805 806 static bool rk_hdptx_phy_is_rw_reg(struct device *dev, unsigned int reg) 807 { 808 switch (reg) { 809 case 0x0000 ... 0x029c: /* CMN Register */ 810 case 0x0400 ... 0x04a4: /* Sideband Register */ 811 case 0x0800 ... 0x08a4: /* Lane Top Register */ 812 case 0x0c00 ... 0x0cb4: /* Lane 0 Register */ 813 case 0x1000 ... 0x10b4: /* Lane 1 Register */ 814 case 0x1400 ... 0x14b4: /* Lane 2 Register */ 815 case 0x1800 ... 0x18b4: /* Lane 3 Register */ 816 return true; 817 } 818 819 return false; 820 } 821 822 static const struct regmap_config rk_hdptx_phy_regmap_config = { 823 .reg_bits = 32, 824 .reg_stride = 4, 825 .val_bits = 32, 826 .writeable_reg = rk_hdptx_phy_is_rw_reg, 827 .readable_reg = rk_hdptx_phy_is_rw_reg, 828 .fast_io = true, 829 .max_register = 0x18b4, 830 }; 831 832 #define rk_hdptx_multi_reg_write(hdptx, seq) \ 833 regmap_multi_reg_write((hdptx)->regmap, seq, ARRAY_SIZE(seq)) 834 835 static void rk_hdptx_pre_power_up(struct rk_hdptx_phy *hdptx) 836 { 837 u32 val; 838 839 reset_control_assert(hdptx->rsts[RST_APB].rstc); 840 usleep_range(20, 25); 841 reset_control_deassert(hdptx->rsts[RST_APB].rstc); 842 843 reset_control_assert(hdptx->rsts[RST_LANE].rstc); 844 reset_control_assert(hdptx->rsts[RST_CMN].rstc); 845 reset_control_assert(hdptx->rsts[RST_INIT].rstc); 846 847 val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16; 848 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); 849 } 850 851 static int rk_hdptx_post_enable_lane(struct rk_hdptx_phy *hdptx) 852 { 853 u32 val; 854 int ret; 855 856 reset_control_deassert(hdptx->rsts[RST_LANE].rstc); 857 858 val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | 859 HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; 860 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); 861 862 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, 863 (val & HDPTX_O_PHY_RDY) && 864 (val & HDPTX_O_PLL_LOCK_DONE), 865 100, 5000); 866 if (ret) { 867 dev_err(hdptx->dev, "Failed to get PHY lane lock: %d\n", ret); 868 return ret; 869 } 870 871 dev_dbg(hdptx->dev, "PHY lane locked\n"); 872 873 return 0; 874 } 875 876 static int rk_hdptx_post_enable_pll(struct rk_hdptx_phy *hdptx) 877 { 878 u32 val; 879 int ret; 880 881 val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | 882 HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; 883 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); 884 885 usleep_range(10, 15); 886 reset_control_deassert(hdptx->rsts[RST_INIT].rstc); 887 888 usleep_range(10, 15); 889 val = HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN; 890 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); 891 892 usleep_range(10, 15); 893 reset_control_deassert(hdptx->rsts[RST_CMN].rstc); 894 895 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, 896 val & HDPTX_O_PHY_CLK_RDY, 20, 400); 897 if (ret) { 898 dev_err(hdptx->dev, "Failed to get PHY clk ready: %d\n", ret); 899 return ret; 900 } 901 902 dev_dbg(hdptx->dev, "PHY clk ready\n"); 903 904 return 0; 905 } 906 907 static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx) 908 { 909 u32 val; 910 911 reset_control_assert(hdptx->rsts[RST_APB].rstc); 912 usleep_range(20, 30); 913 reset_control_deassert(hdptx->rsts[RST_APB].rstc); 914 915 regmap_write(hdptx->regmap, LANE_REG(0300), 0x82); 916 regmap_write(hdptx->regmap, SB_REG(010f), 0xc1); 917 regmap_write(hdptx->regmap, SB_REG(0110), 0x1); 918 regmap_write(hdptx->regmap, LANE_REG(0301), 0x80); 919 regmap_write(hdptx->regmap, LANE_REG(0401), 0x80); 920 regmap_write(hdptx->regmap, LANE_REG(0501), 0x80); 921 regmap_write(hdptx->regmap, LANE_REG(0601), 0x80); 922 923 reset_control_assert(hdptx->rsts[RST_LANE].rstc); 924 reset_control_assert(hdptx->rsts[RST_CMN].rstc); 925 reset_control_assert(hdptx->rsts[RST_INIT].rstc); 926 927 val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16; 928 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); 929 } 930 931 static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate, 932 struct ropll_config *cfg) 933 { 934 const unsigned int fout = data_rate / 2, fref = 24000; 935 unsigned long k = 0, lc, k_sub, lc_sub; 936 unsigned int fvco, sdc; 937 u32 mdiv, sdiv, n = 8; 938 939 if (fout > 0xfffffff) 940 return false; 941 942 for (sdiv = 16; sdiv >= 1; sdiv--) { 943 if (sdiv % 2 && sdiv != 1) 944 continue; 945 946 fvco = fout * sdiv; 947 948 if (fvco < 2000000 || fvco > 4000000) 949 continue; 950 951 mdiv = DIV_ROUND_UP(fvco, fref); 952 if (mdiv < 20 || mdiv > 255) 953 continue; 954 955 if (fref * mdiv - fvco) { 956 for (sdc = 264000; sdc <= 750000; sdc += fref) 957 if (sdc * n > fref * mdiv) 958 break; 959 960 if (sdc > 750000) 961 continue; 962 963 rational_best_approximation(fref * mdiv - fvco, 964 sdc / 16, 965 GENMASK(6, 0), 966 GENMASK(7, 0), 967 &k, &lc); 968 969 rational_best_approximation(sdc * n - fref * mdiv, 970 sdc, 971 GENMASK(6, 0), 972 GENMASK(7, 0), 973 &k_sub, &lc_sub); 974 } 975 976 break; 977 } 978 979 if (sdiv < 1) 980 return false; 981 982 if (cfg) { 983 cfg->pms_mdiv = mdiv; 984 cfg->pms_mdiv_afc = mdiv; 985 cfg->pms_pdiv = 1; 986 cfg->pms_refdiv = 1; 987 cfg->pms_sdiv = sdiv - 1; 988 989 cfg->sdm_en = k > 0 ? 1 : 0; 990 if (cfg->sdm_en) { 991 cfg->sdm_deno = lc; 992 cfg->sdm_num_sign = 1; 993 cfg->sdm_num = k; 994 cfg->sdc_n = n - 3; 995 cfg->sdc_num = k_sub; 996 cfg->sdc_deno = lc_sub; 997 } 998 } 999 1000 return true; 1001 } 1002 1003 static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, 1004 unsigned int rate) 1005 { 1006 const struct ropll_config *cfg = NULL; 1007 struct ropll_config rc = {0}; 1008 int i; 1009 1010 hdptx->rate = rate * 100; 1011 1012 for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) 1013 if (rate == ropll_tmds_cfg[i].bit_rate) { 1014 cfg = &ropll_tmds_cfg[i]; 1015 break; 1016 } 1017 1018 if (!cfg) { 1019 if (rk_hdptx_phy_clk_pll_calc(rate, &rc)) { 1020 cfg = &rc; 1021 } else { 1022 dev_err(hdptx->dev, "%s cannot find pll cfg\n", __func__); 1023 return -EINVAL; 1024 } 1025 } 1026 1027 dev_dbg(hdptx->dev, "mdiv=%u, sdiv=%u, sdm_en=%u, k_sign=%u, k=%u, lc=%u\n", 1028 cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en, 1029 cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno); 1030 1031 rk_hdptx_pre_power_up(hdptx); 1032 1033 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq); 1034 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_cmn_init_seq); 1035 1036 regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv); 1037 regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc); 1038 regmap_write(hdptx->regmap, CMN_REG(0059), 1039 (cfg->pms_pdiv << 4) | cfg->pms_refdiv); 1040 regmap_write(hdptx->regmap, CMN_REG(005a), cfg->pms_sdiv << 4); 1041 1042 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK, 1043 FIELD_PREP(ROPLL_SDM_EN_MASK, cfg->sdm_en)); 1044 if (!cfg->sdm_en) 1045 regmap_update_bits(hdptx->regmap, CMN_REG(005e), 0xf, 0); 1046 1047 regmap_update_bits(hdptx->regmap, CMN_REG(0064), ROPLL_SDM_NUM_SIGN_RBR_MASK, 1048 FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, cfg->sdm_num_sign)); 1049 1050 regmap_write(hdptx->regmap, CMN_REG(0060), cfg->sdm_deno); 1051 regmap_write(hdptx->regmap, CMN_REG(0065), cfg->sdm_num); 1052 1053 regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK, 1054 FIELD_PREP(ROPLL_SDC_N_RBR_MASK, cfg->sdc_n)); 1055 1056 regmap_write(hdptx->regmap, CMN_REG(006c), cfg->sdc_num); 1057 regmap_write(hdptx->regmap, CMN_REG(0070), cfg->sdc_deno); 1058 1059 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK, 1060 FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv)); 1061 1062 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN_MASK, 1063 FIELD_PREP(PLL_PCG_CLK_EN_MASK, 0x1)); 1064 1065 return rk_hdptx_post_enable_pll(hdptx); 1066 } 1067 1068 static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx, 1069 unsigned int rate) 1070 { 1071 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq); 1072 1073 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); 1074 1075 if (rate >= 3400000) { 1076 /* For 1/40 bitrate clk */ 1077 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq); 1078 } else { 1079 /* For 1/10 bitrate clk */ 1080 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_lowbr_seq); 1081 } 1082 1083 regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07); 1084 regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); 1085 1086 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq); 1087 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq); 1088 1089 return rk_hdptx_post_enable_lane(hdptx); 1090 } 1091 1092 static void rk_hdptx_dp_reset(struct rk_hdptx_phy *hdptx) 1093 { 1094 reset_control_assert(hdptx->rsts[RST_LANE].rstc); 1095 reset_control_assert(hdptx->rsts[RST_CMN].rstc); 1096 reset_control_assert(hdptx->rsts[RST_INIT].rstc); 1097 1098 reset_control_assert(hdptx->rsts[RST_APB].rstc); 1099 udelay(10); 1100 reset_control_deassert(hdptx->rsts[RST_APB].rstc); 1101 1102 regmap_update_bits(hdptx->regmap, LANE_REG(0301), 1103 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK, 1104 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) | 1105 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0)); 1106 regmap_update_bits(hdptx->regmap, LANE_REG(0401), 1107 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK, 1108 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) | 1109 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0)); 1110 regmap_update_bits(hdptx->regmap, LANE_REG(0501), 1111 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK, 1112 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) | 1113 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0)); 1114 regmap_update_bits(hdptx->regmap, LANE_REG(0601), 1115 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK, 1116 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) | 1117 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0)); 1118 1119 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1120 HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x0)); 1121 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1122 HDPTX_I_BIAS_EN << 16 | FIELD_PREP(HDPTX_I_BIAS_EN, 0x0)); 1123 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1124 HDPTX_I_BGR_EN << 16 | FIELD_PREP(HDPTX_I_BGR_EN, 0x0)); 1125 } 1126 1127 static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx, 1128 unsigned int rate) 1129 { 1130 enum phy_mode mode = phy_get_mode(hdptx->phy); 1131 u32 status; 1132 int ret; 1133 1134 if (atomic_inc_return(&hdptx->usage_count) > 1) 1135 return 0; 1136 1137 ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status); 1138 if (ret) 1139 goto dec_usage; 1140 1141 if (status & HDPTX_O_PLL_LOCK_DONE) 1142 dev_warn(hdptx->dev, "PLL locked by unknown consumer!\n"); 1143 1144 if (mode == PHY_MODE_DP) { 1145 rk_hdptx_dp_reset(hdptx); 1146 } else { 1147 if (rate) { 1148 ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate); 1149 if (ret) 1150 goto dec_usage; 1151 } 1152 } 1153 1154 return 0; 1155 1156 dec_usage: 1157 atomic_dec(&hdptx->usage_count); 1158 return ret; 1159 } 1160 1161 static int rk_hdptx_phy_consumer_put(struct rk_hdptx_phy *hdptx, bool force) 1162 { 1163 enum phy_mode mode = phy_get_mode(hdptx->phy); 1164 u32 status; 1165 int ret; 1166 1167 ret = atomic_dec_return(&hdptx->usage_count); 1168 if (ret > 0) 1169 return 0; 1170 1171 if (ret < 0) { 1172 dev_warn(hdptx->dev, "Usage count underflow!\n"); 1173 ret = -EINVAL; 1174 } else { 1175 ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status); 1176 if (!ret) { 1177 if (status & HDPTX_O_PLL_LOCK_DONE) { 1178 if (mode == PHY_MODE_DP) 1179 rk_hdptx_dp_reset(hdptx); 1180 else 1181 rk_hdptx_phy_disable(hdptx); 1182 } 1183 return 0; 1184 } else if (force) { 1185 return 0; 1186 } 1187 } 1188 1189 atomic_inc(&hdptx->usage_count); 1190 return ret; 1191 } 1192 1193 static void rk_hdptx_dp_pll_init(struct rk_hdptx_phy *hdptx) 1194 { 1195 regmap_update_bits(hdptx->regmap, CMN_REG(003c), ANA_LCPLL_RESERVED7_MASK, 1196 FIELD_PREP(ANA_LCPLL_RESERVED7_MASK, 0x1)); 1197 1198 regmap_update_bits(hdptx->regmap, CMN_REG(0046), 1199 ROPLL_ANA_CPP_CTRL_COARSE_MASK | ROPLL_ANA_CPP_CTRL_FINE_MASK, 1200 FIELD_PREP(ROPLL_ANA_CPP_CTRL_COARSE_MASK, 0xe) | 1201 FIELD_PREP(ROPLL_ANA_CPP_CTRL_FINE_MASK, 0xe)); 1202 regmap_update_bits(hdptx->regmap, CMN_REG(0047), 1203 ROPLL_ANA_LPF_C_SEL_COARSE_MASK | 1204 ROPLL_ANA_LPF_C_SEL_FINE_MASK, 1205 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_COARSE_MASK, 0x4) | 1206 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_FINE_MASK, 0x4)); 1207 1208 regmap_write(hdptx->regmap, CMN_REG(0051), FIELD_PREP(ROPLL_PMS_MDIV_MASK, 0x87)); 1209 regmap_write(hdptx->regmap, CMN_REG(0052), FIELD_PREP(ROPLL_PMS_MDIV_MASK, 0x71)); 1210 regmap_write(hdptx->regmap, CMN_REG(0053), FIELD_PREP(ROPLL_PMS_MDIV_MASK, 0x71)); 1211 1212 regmap_write(hdptx->regmap, CMN_REG(0055), 1213 FIELD_PREP(ROPLL_PMS_MDIV_AFC_MASK, 0x87)); 1214 regmap_write(hdptx->regmap, CMN_REG(0056), 1215 FIELD_PREP(ROPLL_PMS_MDIV_AFC_MASK, 0x71)); 1216 regmap_write(hdptx->regmap, CMN_REG(0057), 1217 FIELD_PREP(ROPLL_PMS_MDIV_AFC_MASK, 0x71)); 1218 1219 regmap_write(hdptx->regmap, CMN_REG(0059), 1220 FIELD_PREP(ANA_ROPLL_PMS_PDIV_MASK, 0x1) | 1221 FIELD_PREP(ANA_ROPLL_PMS_REFDIV_MASK, 0x1)); 1222 regmap_write(hdptx->regmap, CMN_REG(005a), 1223 FIELD_PREP(ROPLL_PMS_SDIV_RBR_MASK, 0x3) | 1224 FIELD_PREP(ROPLL_PMS_SDIV_HBR_MASK, 0x1)); 1225 regmap_update_bits(hdptx->regmap, CMN_REG(005b), ROPLL_PMS_SDIV_HBR2_MASK, 1226 FIELD_PREP(ROPLL_PMS_SDIV_HBR2_MASK, 0x0)); 1227 1228 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK, 1229 FIELD_PREP(ROPLL_SDM_EN_MASK, 0x1)); 1230 regmap_update_bits(hdptx->regmap, CMN_REG(005e), 1231 OVRD_ROPLL_SDM_RSTN_MASK | ROPLL_SDM_RSTN_MASK, 1232 FIELD_PREP(OVRD_ROPLL_SDM_RSTN_MASK, 0x1) | 1233 FIELD_PREP(ROPLL_SDM_RSTN_MASK, 0x1)); 1234 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDC_FRAC_EN_RBR_MASK, 1235 FIELD_PREP(ROPLL_SDC_FRAC_EN_RBR_MASK, 0x1)); 1236 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDC_FRAC_EN_HBR_MASK, 1237 FIELD_PREP(ROPLL_SDC_FRAC_EN_HBR_MASK, 0x1)); 1238 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDC_FRAC_EN_HBR2_MASK, 1239 FIELD_PREP(ROPLL_SDC_FRAC_EN_HBR2_MASK, 0x1)); 1240 1241 regmap_update_bits(hdptx->regmap, CMN_REG(005f), 1242 OVRD_ROPLL_SDC_RSTN_MASK | ROPLL_SDC_RSTN_MASK, 1243 FIELD_PREP(OVRD_ROPLL_SDC_RSTN_MASK, 0x1) | 1244 FIELD_PREP(ROPLL_SDC_RSTN_MASK, 0x1)); 1245 regmap_write(hdptx->regmap, CMN_REG(0060), 1246 FIELD_PREP(ROPLL_SDM_DENOMINATOR_MASK, 0x21)); 1247 regmap_write(hdptx->regmap, CMN_REG(0061), 1248 FIELD_PREP(ROPLL_SDM_DENOMINATOR_MASK, 0x27)); 1249 regmap_write(hdptx->regmap, CMN_REG(0062), 1250 FIELD_PREP(ROPLL_SDM_DENOMINATOR_MASK, 0x27)); 1251 1252 regmap_update_bits(hdptx->regmap, CMN_REG(0064), 1253 ROPLL_SDM_NUM_SIGN_RBR_MASK | 1254 ROPLL_SDM_NUM_SIGN_HBR_MASK | 1255 ROPLL_SDM_NUM_SIGN_HBR2_MASK, 1256 FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, 0x0) | 1257 FIELD_PREP(ROPLL_SDM_NUM_SIGN_HBR_MASK, 0x1) | 1258 FIELD_PREP(ROPLL_SDM_NUM_SIGN_HBR2_MASK, 0x1)); 1259 regmap_write(hdptx->regmap, CMN_REG(0065), 1260 FIELD_PREP(ROPLL_SDM_NUM_MASK, 0x0)); 1261 regmap_write(hdptx->regmap, CMN_REG(0066), 1262 FIELD_PREP(ROPLL_SDM_NUM_MASK, 0xd)); 1263 regmap_write(hdptx->regmap, CMN_REG(0067), 1264 FIELD_PREP(ROPLL_SDM_NUM_MASK, 0xd)); 1265 1266 regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK, 1267 FIELD_PREP(ROPLL_SDC_N_RBR_MASK, 0x2)); 1268 1269 regmap_update_bits(hdptx->regmap, CMN_REG(006a), 1270 ROPLL_SDC_N_HBR_MASK | ROPLL_SDC_N_HBR2_MASK, 1271 FIELD_PREP(ROPLL_SDC_N_HBR_MASK, 0x1) | 1272 FIELD_PREP(ROPLL_SDC_N_HBR2_MASK, 0x1)); 1273 1274 regmap_write(hdptx->regmap, CMN_REG(006c), 1275 FIELD_PREP(ROPLL_SDC_NUM_MASK, 0x3)); 1276 regmap_write(hdptx->regmap, CMN_REG(006d), 1277 FIELD_PREP(ROPLL_SDC_NUM_MASK, 0x7)); 1278 regmap_write(hdptx->regmap, CMN_REG(006e), 1279 FIELD_PREP(ROPLL_SDC_NUM_MASK, 0x7)); 1280 1281 regmap_write(hdptx->regmap, CMN_REG(0070), 1282 FIELD_PREP(ROPLL_SDC_DENO_MASK, 0x8)); 1283 regmap_write(hdptx->regmap, CMN_REG(0071), 1284 FIELD_PREP(ROPLL_SDC_DENO_MASK, 0x18)); 1285 regmap_write(hdptx->regmap, CMN_REG(0072), 1286 FIELD_PREP(ROPLL_SDC_DENO_MASK, 0x18)); 1287 1288 regmap_update_bits(hdptx->regmap, CMN_REG(0074), 1289 OVRD_ROPLL_SDC_NDIV_RSTN_MASK | ROPLL_SDC_NDIV_RSTN_MASK, 1290 FIELD_PREP(OVRD_ROPLL_SDC_NDIV_RSTN_MASK, 0x1) | 1291 FIELD_PREP(ROPLL_SDC_NDIV_RSTN_MASK, 0x1)); 1292 1293 regmap_update_bits(hdptx->regmap, CMN_REG(0077), ANA_ROPLL_SSC_CLK_DIV_SEL_MASK, 1294 FIELD_PREP(ANA_ROPLL_SSC_CLK_DIV_SEL_MASK, 0x1)); 1295 1296 regmap_update_bits(hdptx->regmap, CMN_REG(0081), ANA_PLL_CD_TX_SER_RATE_SEL_MASK, 1297 FIELD_PREP(ANA_PLL_CD_TX_SER_RATE_SEL_MASK, 0x0)); 1298 regmap_update_bits(hdptx->regmap, CMN_REG(0081), 1299 ANA_PLL_CD_HSCLK_EAST_EN_MASK | ANA_PLL_CD_HSCLK_WEST_EN_MASK, 1300 FIELD_PREP(ANA_PLL_CD_HSCLK_EAST_EN_MASK, 0x1) | 1301 FIELD_PREP(ANA_PLL_CD_HSCLK_WEST_EN_MASK, 0x0)); 1302 1303 regmap_update_bits(hdptx->regmap, CMN_REG(0082), ANA_PLL_CD_VREG_GAIN_CTRL_MASK, 1304 FIELD_PREP(ANA_PLL_CD_VREG_GAIN_CTRL_MASK, 0x4)); 1305 regmap_update_bits(hdptx->regmap, CMN_REG(0083), ANA_PLL_CD_VREG_ICTRL_MASK, 1306 FIELD_PREP(ANA_PLL_CD_VREG_ICTRL_MASK, 0x1)); 1307 regmap_update_bits(hdptx->regmap, CMN_REG(0084), PLL_LCRO_CLK_SEL_MASK, 1308 FIELD_PREP(PLL_LCRO_CLK_SEL_MASK, 0x1)); 1309 regmap_update_bits(hdptx->regmap, CMN_REG(0085), ANA_PLL_SYNC_LOSS_DET_MODE_MASK, 1310 FIELD_PREP(ANA_PLL_SYNC_LOSS_DET_MODE_MASK, 0x3)); 1311 1312 regmap_update_bits(hdptx->regmap, CMN_REG(0087), ANA_PLL_TX_HS_CLK_EN_MASK, 1313 FIELD_PREP(ANA_PLL_TX_HS_CLK_EN_MASK, 0x1)); 1314 1315 regmap_update_bits(hdptx->regmap, CMN_REG(0097), DIG_CLK_SEL_MASK, 1316 FIELD_PREP(DIG_CLK_SEL_MASK, 0x1)); 1317 1318 regmap_update_bits(hdptx->regmap, CMN_REG(0099), CMN_ROPLL_ALONE_MODE_MASK, 1319 FIELD_PREP(CMN_ROPLL_ALONE_MODE_MASK, 0x1)); 1320 regmap_update_bits(hdptx->regmap, CMN_REG(009a), HS_SPEED_SEL_MASK, 1321 FIELD_PREP(HS_SPEED_SEL_MASK, 0x1)); 1322 regmap_update_bits(hdptx->regmap, CMN_REG(009b), LS_SPEED_SEL_MASK, 1323 FIELD_PREP(LS_SPEED_SEL_MASK, 0x1)); 1324 } 1325 1326 static int rk_hdptx_dp_aux_init(struct rk_hdptx_phy *hdptx) 1327 { 1328 u32 status; 1329 int ret; 1330 1331 regmap_update_bits(hdptx->regmap, SB_REG(0102), ANA_SB_RXTERM_OFFSP_MASK, 1332 FIELD_PREP(ANA_SB_RXTERM_OFFSP_MASK, 0x3)); 1333 regmap_update_bits(hdptx->regmap, SB_REG(0103), ANA_SB_RXTERM_OFFSN_MASK, 1334 FIELD_PREP(ANA_SB_RXTERM_OFFSN_MASK, 0x3)); 1335 regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_AUX_EN_MASK, 1336 FIELD_PREP(SB_AUX_EN_MASK, 0x1)); 1337 regmap_update_bits(hdptx->regmap, SB_REG(0105), ANA_SB_TX_HLVL_PROG_MASK, 1338 FIELD_PREP(ANA_SB_TX_HLVL_PROG_MASK, 0x7)); 1339 regmap_update_bits(hdptx->regmap, SB_REG(0106), ANA_SB_TX_LLVL_PROG_MASK, 1340 FIELD_PREP(ANA_SB_TX_LLVL_PROG_MASK, 0x7)); 1341 1342 regmap_update_bits(hdptx->regmap, SB_REG(010d), ANA_SB_DMRX_LPBK_DATA_MASK, 1343 FIELD_PREP(ANA_SB_DMRX_LPBK_DATA_MASK, 0x1)); 1344 1345 regmap_update_bits(hdptx->regmap, SB_REG(010f), ANA_SB_VREG_GAIN_CTRL_MASK, 1346 FIELD_PREP(ANA_SB_VREG_GAIN_CTRL_MASK, 0x0)); 1347 regmap_update_bits(hdptx->regmap, SB_REG(0110), 1348 ANA_SB_VREG_OUT_SEL_MASK | ANA_SB_VREG_REF_SEL_MASK, 1349 FIELD_PREP(ANA_SB_VREG_OUT_SEL_MASK, 0x1) | 1350 FIELD_PREP(ANA_SB_VREG_REF_SEL_MASK, 0x1)); 1351 1352 regmap_update_bits(hdptx->regmap, SB_REG(0113), 1353 SB_RX_RCAL_OPT_CODE_MASK | SB_RX_RTERM_CTRL_MASK, 1354 FIELD_PREP(SB_RX_RCAL_OPT_CODE_MASK, 0x1) | 1355 FIELD_PREP(SB_RX_RTERM_CTRL_MASK, 0x3)); 1356 regmap_update_bits(hdptx->regmap, SB_REG(0114), 1357 SB_TG_SB_EN_DELAY_TIME_MASK | SB_TG_RXTERM_EN_DELAY_TIME_MASK, 1358 FIELD_PREP(SB_TG_SB_EN_DELAY_TIME_MASK, 0x2) | 1359 FIELD_PREP(SB_TG_RXTERM_EN_DELAY_TIME_MASK, 0x2)); 1360 regmap_update_bits(hdptx->regmap, SB_REG(0115), 1361 SB_READY_DELAY_TIME_MASK | SB_TG_OSC_EN_DELAY_TIME_MASK, 1362 FIELD_PREP(SB_READY_DELAY_TIME_MASK, 0x2) | 1363 FIELD_PREP(SB_TG_OSC_EN_DELAY_TIME_MASK, 0x2)); 1364 regmap_update_bits(hdptx->regmap, SB_REG(0116), 1365 AFC_RSTN_DELAY_TIME_MASK, 1366 FIELD_PREP(AFC_RSTN_DELAY_TIME_MASK, 0x2)); 1367 regmap_update_bits(hdptx->regmap, SB_REG(0117), 1368 FAST_PULSE_TIME_MASK, 1369 FIELD_PREP(FAST_PULSE_TIME_MASK, 0x4)); 1370 regmap_update_bits(hdptx->regmap, SB_REG(0118), 1371 SB_TG_EARC_DMRX_RECVRD_CLK_CNT_MASK, 1372 FIELD_PREP(SB_TG_EARC_DMRX_RECVRD_CLK_CNT_MASK, 0xa)); 1373 1374 regmap_update_bits(hdptx->regmap, SB_REG(011a), SB_TG_CNT_RUN_NO_7_0_MASK, 1375 FIELD_PREP(SB_TG_CNT_RUN_NO_7_0_MASK, 0x3)); 1376 regmap_update_bits(hdptx->regmap, SB_REG(011b), 1377 SB_EARC_SIG_DET_BYPASS_MASK | SB_AFC_TOL_MASK, 1378 FIELD_PREP(SB_EARC_SIG_DET_BYPASS_MASK, 0x1) | 1379 FIELD_PREP(SB_AFC_TOL_MASK, 0x3)); 1380 regmap_update_bits(hdptx->regmap, SB_REG(011c), SB_AFC_STB_NUM_MASK, 1381 FIELD_PREP(SB_AFC_STB_NUM_MASK, 0x4)); 1382 regmap_update_bits(hdptx->regmap, SB_REG(011d), SB_TG_OSC_CNT_MIN_MASK, 1383 FIELD_PREP(SB_TG_OSC_CNT_MIN_MASK, 0x67)); 1384 regmap_update_bits(hdptx->regmap, SB_REG(011e), SB_TG_OSC_CNT_MAX_MASK, 1385 FIELD_PREP(SB_TG_OSC_CNT_MAX_MASK, 0x6a)); 1386 regmap_update_bits(hdptx->regmap, SB_REG(011f), SB_PWM_AFC_CTRL_MASK, 1387 FIELD_PREP(SB_PWM_AFC_CTRL_MASK, 0x5)); 1388 regmap_update_bits(hdptx->regmap, SB_REG(011f), SB_RCAL_RSTN_MASK, 1389 FIELD_PREP(SB_RCAL_RSTN_MASK, 0x1)); 1390 regmap_update_bits(hdptx->regmap, SB_REG(0120), SB_AUX_EN_IN_MASK, 1391 FIELD_PREP(SB_AUX_EN_IN_MASK, 0x1)); 1392 1393 regmap_update_bits(hdptx->regmap, SB_REG(0102), OVRD_SB_RXTERM_EN_MASK, 1394 FIELD_PREP(OVRD_SB_RXTERM_EN_MASK, 0x1)); 1395 regmap_update_bits(hdptx->regmap, SB_REG(0103), OVRD_SB_RX_RESCAL_DONE_MASK, 1396 FIELD_PREP(OVRD_SB_RX_RESCAL_DONE_MASK, 0x1)); 1397 regmap_update_bits(hdptx->regmap, SB_REG(0104), OVRD_SB_EN_MASK, 1398 FIELD_PREP(OVRD_SB_EN_MASK, 0x1)); 1399 regmap_update_bits(hdptx->regmap, SB_REG(0104), OVRD_SB_AUX_EN_MASK, 1400 FIELD_PREP(OVRD_SB_AUX_EN_MASK, 0x1)); 1401 1402 regmap_update_bits(hdptx->regmap, SB_REG(010f), OVRD_SB_VREG_EN_MASK, 1403 FIELD_PREP(OVRD_SB_VREG_EN_MASK, 0x1)); 1404 1405 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1406 HDPTX_I_BGR_EN << 16 | FIELD_PREP(HDPTX_I_BGR_EN, 0x1)); 1407 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1408 HDPTX_I_BIAS_EN << 16 | FIELD_PREP(HDPTX_I_BIAS_EN, 0x1)); 1409 usleep_range(20, 25); 1410 1411 reset_control_deassert(hdptx->rsts[RST_INIT].rstc); 1412 usleep_range(20, 25); 1413 reset_control_deassert(hdptx->rsts[RST_CMN].rstc); 1414 usleep_range(20, 25); 1415 1416 regmap_update_bits(hdptx->regmap, SB_REG(0103), OVRD_SB_RX_RESCAL_DONE_MASK, 1417 FIELD_PREP(OVRD_SB_RX_RESCAL_DONE_MASK, 0x1)); 1418 usleep_range(100, 110); 1419 regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_EN_MASK, 1420 FIELD_PREP(SB_EN_MASK, 0x1)); 1421 usleep_range(100, 110); 1422 regmap_update_bits(hdptx->regmap, SB_REG(0102), SB_RXTERM_EN_MASK, 1423 FIELD_PREP(SB_RXTERM_EN_MASK, 0x1)); 1424 usleep_range(20, 25); 1425 regmap_update_bits(hdptx->regmap, SB_REG(010f), SB_VREG_EN_MASK, 1426 FIELD_PREP(SB_VREG_EN_MASK, 0x1)); 1427 usleep_range(20, 25); 1428 regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_AUX_EN_MASK, 1429 FIELD_PREP(SB_AUX_EN_MASK, 0x1)); 1430 usleep_range(100, 110); 1431 1432 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, 1433 status, FIELD_GET(HDPTX_O_SB_RDY, status), 1434 50, 1000); 1435 if (ret) { 1436 dev_err(hdptx->dev, "Failed to get phy sb ready: %d\n", ret); 1437 return ret; 1438 } 1439 1440 return 0; 1441 } 1442 1443 static int rk_hdptx_phy_power_on(struct phy *phy) 1444 { 1445 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); 1446 int bus_width = phy_get_bus_width(hdptx->phy); 1447 enum phy_mode mode = phy_get_mode(phy); 1448 int ret, lane; 1449 1450 /* 1451 * FIXME: Temporary workaround to pass pixel_clk_rate 1452 * from the HDMI bridge driver until phy_configure_opts_hdmi 1453 * becomes available in the PHY API. 1454 */ 1455 unsigned int rate = bus_width & 0xfffffff; 1456 1457 dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n", 1458 __func__, bus_width, rate); 1459 1460 ret = rk_hdptx_phy_consumer_get(hdptx, rate); 1461 if (ret) 1462 return ret; 1463 1464 if (mode == PHY_MODE_DP) { 1465 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1466 HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x1)); 1467 1468 for (lane = 0; lane < 4; lane++) { 1469 regmap_update_bits(hdptx->regmap, LANE_REG(031e) + 0x400 * lane, 1470 LN_POLARITY_INV_MASK | LN_LANE_MODE_MASK, 1471 FIELD_PREP(LN_POLARITY_INV_MASK, 0) | 1472 FIELD_PREP(LN_LANE_MODE_MASK, 1)); 1473 } 1474 1475 regmap_update_bits(hdptx->regmap, LNTOP_REG(0200), PROTOCOL_SEL_MASK, 1476 FIELD_PREP(PROTOCOL_SEL_MASK, 0x0)); 1477 regmap_update_bits(hdptx->regmap, LNTOP_REG(0206), DATA_BUS_WIDTH_MASK, 1478 FIELD_PREP(DATA_BUS_WIDTH_MASK, 0x1)); 1479 regmap_update_bits(hdptx->regmap, LNTOP_REG(0206), DATA_BUS_WIDTH_SEL_MASK, 1480 FIELD_PREP(DATA_BUS_WIDTH_SEL_MASK, 0x0)); 1481 1482 rk_hdptx_dp_pll_init(hdptx); 1483 1484 ret = rk_hdptx_dp_aux_init(hdptx); 1485 if (ret) 1486 rk_hdptx_phy_consumer_put(hdptx, true); 1487 } else { 1488 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1489 HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0)); 1490 1491 ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate); 1492 if (ret) 1493 rk_hdptx_phy_consumer_put(hdptx, true); 1494 } 1495 1496 return ret; 1497 } 1498 1499 static int rk_hdptx_phy_power_off(struct phy *phy) 1500 { 1501 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); 1502 1503 return rk_hdptx_phy_consumer_put(hdptx, false); 1504 } 1505 1506 static int rk_hdptx_phy_verify_config(struct rk_hdptx_phy *hdptx, 1507 struct phy_configure_opts_dp *dp) 1508 { 1509 int i; 1510 1511 if (dp->set_rate) { 1512 switch (dp->link_rate) { 1513 case 1620: 1514 case 2700: 1515 case 5400: 1516 break; 1517 default: 1518 return -EINVAL; 1519 } 1520 } 1521 1522 if (dp->set_lanes) { 1523 switch (dp->lanes) { 1524 case 1: 1525 case 2: 1526 case 4: 1527 break; 1528 default: 1529 return -EINVAL; 1530 } 1531 } 1532 1533 if (dp->set_voltages) { 1534 for (i = 0; i < hdptx->lanes; i++) { 1535 if (dp->voltage[i] > 3 || dp->pre[i] > 3) 1536 return -EINVAL; 1537 1538 if (dp->voltage[i] + dp->pre[i] > 3) 1539 return -EINVAL; 1540 } 1541 } 1542 1543 return 0; 1544 } 1545 1546 static int rk_hdptx_phy_set_rate(struct rk_hdptx_phy *hdptx, 1547 struct phy_configure_opts_dp *dp) 1548 { 1549 u32 bw, status; 1550 int ret; 1551 1552 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1553 HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x0)); 1554 1555 switch (dp->link_rate) { 1556 case 1620: 1557 bw = DP_BW_RBR; 1558 break; 1559 case 2700: 1560 bw = DP_BW_HBR; 1561 break; 1562 case 5400: 1563 bw = DP_BW_HBR2; 1564 break; 1565 default: 1566 return -EINVAL; 1567 } 1568 hdptx->link_rate = dp->link_rate; 1569 1570 regmap_update_bits(hdptx->regmap, CMN_REG(0008), OVRD_LCPLL_EN_MASK | LCPLL_EN_MASK, 1571 FIELD_PREP(OVRD_LCPLL_EN_MASK, 0x1) | 1572 FIELD_PREP(LCPLL_EN_MASK, 0x0)); 1573 1574 regmap_update_bits(hdptx->regmap, CMN_REG(003d), OVRD_ROPLL_EN_MASK | ROPLL_EN_MASK, 1575 FIELD_PREP(OVRD_ROPLL_EN_MASK, 0x1) | 1576 FIELD_PREP(ROPLL_EN_MASK, 0x1)); 1577 1578 if (dp->ssc) { 1579 regmap_update_bits(hdptx->regmap, CMN_REG(0074), 1580 OVRD_ROPLL_SSC_EN_MASK | ROPLL_SSC_EN_MASK, 1581 FIELD_PREP(OVRD_ROPLL_SSC_EN_MASK, 0x1) | 1582 FIELD_PREP(ROPLL_SSC_EN_MASK, 0x1)); 1583 regmap_write(hdptx->regmap, CMN_REG(0075), 1584 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION_MASK, 0xc)); 1585 regmap_update_bits(hdptx->regmap, CMN_REG(0076), 1586 ANA_ROPLL_SSC_FM_FREQ_MASK, 1587 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ_MASK, 0x1f)); 1588 1589 regmap_update_bits(hdptx->regmap, CMN_REG(0099), SSC_EN_MASK, 1590 FIELD_PREP(SSC_EN_MASK, 0x2)); 1591 } else { 1592 regmap_update_bits(hdptx->regmap, CMN_REG(0074), 1593 OVRD_ROPLL_SSC_EN_MASK | ROPLL_SSC_EN_MASK, 1594 FIELD_PREP(OVRD_ROPLL_SSC_EN_MASK, 0x1) | 1595 FIELD_PREP(ROPLL_SSC_EN_MASK, 0x0)); 1596 regmap_write(hdptx->regmap, CMN_REG(0075), 1597 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION_MASK, 0x20)); 1598 regmap_update_bits(hdptx->regmap, CMN_REG(0076), 1599 ANA_ROPLL_SSC_FM_FREQ_MASK, 1600 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ_MASK, 0xc)); 1601 1602 regmap_update_bits(hdptx->regmap, CMN_REG(0099), SSC_EN_MASK, 1603 FIELD_PREP(SSC_EN_MASK, 0x0)); 1604 } 1605 1606 regmap_update_bits(hdptx->regmap, CMN_REG(0095), DP_TX_LINK_BW_MASK, 1607 FIELD_PREP(DP_TX_LINK_BW_MASK, bw)); 1608 1609 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1610 HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x1)); 1611 1612 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, 1613 status, FIELD_GET(HDPTX_O_PLL_LOCK_DONE, status), 1614 50, 1000); 1615 if (ret) { 1616 dev_err(hdptx->dev, "Failed to get phy pll lock: %d\n", ret); 1617 return ret; 1618 } 1619 1620 return 0; 1621 } 1622 1623 static int rk_hdptx_phy_set_lanes(struct rk_hdptx_phy *hdptx, 1624 struct phy_configure_opts_dp *dp) 1625 { 1626 hdptx->lanes = dp->lanes; 1627 1628 regmap_update_bits(hdptx->regmap, LNTOP_REG(0207), LANE_EN_MASK, 1629 FIELD_PREP(LANE_EN_MASK, GENMASK(hdptx->lanes - 1, 0))); 1630 1631 return 0; 1632 } 1633 1634 static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx, 1635 struct phy_configure_opts_dp *dp, 1636 u8 lane) 1637 { 1638 const struct tx_drv_ctrl *ctrl; 1639 u32 offset = lane * 0x400; 1640 1641 switch (hdptx->link_rate) { 1642 case 1620: 1643 ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]]; 1644 regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset, 1645 LN_TX_JEQ_EVEN_CTRL_RBR_MASK, 1646 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR_MASK, 1647 ctrl->tx_jeq_even_ctrl)); 1648 regmap_update_bits(hdptx->regmap, LANE_REG(030c) + offset, 1649 LN_TX_JEQ_ODD_CTRL_RBR_MASK, 1650 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR_MASK, 1651 ctrl->tx_jeq_odd_ctrl)); 1652 regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset, 1653 LN_TX_SER_40BIT_EN_RBR_MASK, 1654 FIELD_PREP(LN_TX_SER_40BIT_EN_RBR_MASK, 0x1)); 1655 break; 1656 case 2700: 1657 ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]]; 1658 regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset, 1659 LN_TX_JEQ_EVEN_CTRL_HBR_MASK, 1660 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR_MASK, 1661 ctrl->tx_jeq_even_ctrl)); 1662 regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset, 1663 LN_TX_JEQ_ODD_CTRL_HBR_MASK, 1664 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR_MASK, 1665 ctrl->tx_jeq_odd_ctrl)); 1666 regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset, 1667 LN_TX_SER_40BIT_EN_HBR_MASK, 1668 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR_MASK, 0x1)); 1669 break; 1670 case 5400: 1671 default: 1672 ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]]; 1673 regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset, 1674 LN_TX_JEQ_EVEN_CTRL_HBR2_MASK, 1675 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2_MASK, 1676 ctrl->tx_jeq_even_ctrl)); 1677 regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset, 1678 LN_TX_JEQ_ODD_CTRL_HBR2_MASK, 1679 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2_MASK, 1680 ctrl->tx_jeq_odd_ctrl)); 1681 regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset, 1682 LN_TX_SER_40BIT_EN_HBR2_MASK, 1683 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2_MASK, 0x1)); 1684 break; 1685 } 1686 1687 regmap_update_bits(hdptx->regmap, LANE_REG(0303) + offset, 1688 OVRD_LN_TX_DRV_LVL_CTRL_MASK | LN_TX_DRV_LVL_CTRL_MASK, 1689 FIELD_PREP(OVRD_LN_TX_DRV_LVL_CTRL_MASK, 0x1) | 1690 FIELD_PREP(LN_TX_DRV_LVL_CTRL_MASK, 1691 ctrl->tx_drv_lvl_ctrl)); 1692 regmap_update_bits(hdptx->regmap, LANE_REG(0304) + offset, 1693 OVRD_LN_TX_DRV_POST_LVL_CTRL_MASK | 1694 LN_TX_DRV_POST_LVL_CTRL_MASK, 1695 FIELD_PREP(OVRD_LN_TX_DRV_POST_LVL_CTRL_MASK, 0x1) | 1696 FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL_MASK, 1697 ctrl->tx_drv_post_lvl_ctrl)); 1698 regmap_update_bits(hdptx->regmap, LANE_REG(0305) + offset, 1699 OVRD_LN_TX_DRV_PRE_LVL_CTRL_MASK | 1700 LN_TX_DRV_PRE_LVL_CTRL_MASK, 1701 FIELD_PREP(OVRD_LN_TX_DRV_PRE_LVL_CTRL_MASK, 0x1) | 1702 FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL_MASK, 1703 ctrl->tx_drv_pre_lvl_ctrl)); 1704 regmap_update_bits(hdptx->regmap, LANE_REG(0306) + offset, 1705 LN_ANA_TX_DRV_IDRV_IDN_CTRL_MASK | 1706 LN_ANA_TX_DRV_IDRV_IUP_CTRL_MASK | 1707 LN_ANA_TX_DRV_ACCDRV_EN_MASK, 1708 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IDN_CTRL_MASK, 1709 ctrl->ana_tx_drv_idrv_idn_ctrl) | 1710 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IUP_CTRL_MASK, 1711 ctrl->ana_tx_drv_idrv_iup_ctrl) | 1712 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_EN_MASK, 1713 ctrl->ana_tx_drv_accdrv_en)); 1714 regmap_update_bits(hdptx->regmap, LANE_REG(0307) + offset, 1715 LN_ANA_TX_DRV_ACCDRV_POL_SEL_MASK | 1716 LN_ANA_TX_DRV_ACCDRV_CTRL_MASK, 1717 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_POL_SEL_MASK, 0x1) | 1718 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_CTRL_MASK, 1719 ctrl->ana_tx_drv_accdrv_ctrl)); 1720 1721 regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset, 1722 LN_ANA_TX_JEQ_EN_MASK, 1723 FIELD_PREP(LN_ANA_TX_JEQ_EN_MASK, ctrl->ana_tx_jeq_en)); 1724 1725 regmap_update_bits(hdptx->regmap, LANE_REG(0310) + offset, 1726 LN_ANA_TX_SYNC_LOSS_DET_MODE_MASK, 1727 FIELD_PREP(LN_ANA_TX_SYNC_LOSS_DET_MODE_MASK, 0x3)); 1728 1729 regmap_update_bits(hdptx->regmap, LANE_REG(0316) + offset, 1730 LN_ANA_TX_SER_VREG_GAIN_CTRL_MASK, 1731 FIELD_PREP(LN_ANA_TX_SER_VREG_GAIN_CTRL_MASK, 0x2)); 1732 1733 regmap_update_bits(hdptx->regmap, LANE_REG(031b) + offset, 1734 LN_ANA_TX_RESERVED_MASK, 1735 FIELD_PREP(LN_ANA_TX_RESERVED_MASK, 0x1)); 1736 } 1737 1738 static int rk_hdptx_phy_set_voltages(struct rk_hdptx_phy *hdptx, 1739 struct phy_configure_opts_dp *dp) 1740 { 1741 u8 lane; 1742 u32 status; 1743 int ret; 1744 1745 for (lane = 0; lane < hdptx->lanes; lane++) 1746 rk_hdptx_phy_set_voltage(hdptx, dp, lane); 1747 1748 reset_control_deassert(hdptx->rsts[RST_LANE].rstc); 1749 1750 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, 1751 status, FIELD_GET(HDPTX_O_PHY_RDY, status), 1752 50, 5000); 1753 if (ret) { 1754 dev_err(hdptx->dev, "Failed to get phy ready: %d\n", ret); 1755 return ret; 1756 } 1757 1758 return 0; 1759 } 1760 1761 static int rk_hdptx_phy_configure(struct phy *phy, union phy_configure_opts *opts) 1762 { 1763 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); 1764 enum phy_mode mode = phy_get_mode(phy); 1765 int ret; 1766 1767 if (mode != PHY_MODE_DP) 1768 return 0; 1769 1770 ret = rk_hdptx_phy_verify_config(hdptx, &opts->dp); 1771 if (ret) { 1772 dev_err(hdptx->dev, "invalid params for phy configure\n"); 1773 return ret; 1774 } 1775 1776 if (opts->dp.set_rate) { 1777 ret = rk_hdptx_phy_set_rate(hdptx, &opts->dp); 1778 if (ret) { 1779 dev_err(hdptx->dev, "failed to set rate: %d\n", ret); 1780 return ret; 1781 } 1782 } 1783 1784 if (opts->dp.set_lanes) { 1785 ret = rk_hdptx_phy_set_lanes(hdptx, &opts->dp); 1786 if (ret) { 1787 dev_err(hdptx->dev, "failed to set lanes: %d\n", ret); 1788 return ret; 1789 } 1790 } 1791 1792 if (opts->dp.set_voltages) { 1793 ret = rk_hdptx_phy_set_voltages(hdptx, &opts->dp); 1794 if (ret) { 1795 dev_err(hdptx->dev, "failed to set voltages: %d\n", 1796 ret); 1797 return ret; 1798 } 1799 } 1800 1801 return 0; 1802 } 1803 1804 static const struct phy_ops rk_hdptx_phy_ops = { 1805 .power_on = rk_hdptx_phy_power_on, 1806 .power_off = rk_hdptx_phy_power_off, 1807 .configure = rk_hdptx_phy_configure, 1808 .owner = THIS_MODULE, 1809 }; 1810 1811 static struct rk_hdptx_phy *to_rk_hdptx_phy(struct clk_hw *hw) 1812 { 1813 return container_of(hw, struct rk_hdptx_phy, hw); 1814 } 1815 1816 static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw) 1817 { 1818 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); 1819 1820 return rk_hdptx_phy_consumer_get(hdptx, hdptx->rate / 100); 1821 } 1822 1823 static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw) 1824 { 1825 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); 1826 1827 rk_hdptx_phy_consumer_put(hdptx, true); 1828 } 1829 1830 static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw, 1831 unsigned long parent_rate) 1832 { 1833 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); 1834 1835 return hdptx->rate; 1836 } 1837 1838 static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, 1839 unsigned long *parent_rate) 1840 { 1841 u32 bit_rate = rate / 100; 1842 int i; 1843 1844 if (rate > HDMI20_MAX_RATE) 1845 return rate; 1846 1847 for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) 1848 if (bit_rate == ropll_tmds_cfg[i].bit_rate) 1849 break; 1850 1851 if (i == ARRAY_SIZE(ropll_tmds_cfg) && 1852 !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL)) 1853 return -EINVAL; 1854 1855 return rate; 1856 } 1857 1858 static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, 1859 unsigned long parent_rate) 1860 { 1861 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); 1862 1863 return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100); 1864 } 1865 1866 static const struct clk_ops hdptx_phy_clk_ops = { 1867 .prepare = rk_hdptx_phy_clk_prepare, 1868 .unprepare = rk_hdptx_phy_clk_unprepare, 1869 .recalc_rate = rk_hdptx_phy_clk_recalc_rate, 1870 .round_rate = rk_hdptx_phy_clk_round_rate, 1871 .set_rate = rk_hdptx_phy_clk_set_rate, 1872 }; 1873 1874 static int rk_hdptx_phy_clk_register(struct rk_hdptx_phy *hdptx) 1875 { 1876 struct device *dev = hdptx->dev; 1877 const char *name, *pname; 1878 struct clk *refclk; 1879 int ret; 1880 1881 refclk = devm_clk_get(dev, "ref"); 1882 if (IS_ERR(refclk)) 1883 return dev_err_probe(dev, PTR_ERR(refclk), 1884 "Failed to get ref clock\n"); 1885 1886 name = hdptx->phy_id > 0 ? "clk_hdmiphy_pixel1" : "clk_hdmiphy_pixel0"; 1887 pname = __clk_get_name(refclk); 1888 1889 hdptx->hw.init = CLK_HW_INIT(name, pname, &hdptx_phy_clk_ops, 1890 CLK_GET_RATE_NOCACHE); 1891 1892 ret = devm_clk_hw_register(dev, &hdptx->hw); 1893 if (ret) 1894 return dev_err_probe(dev, ret, "Failed to register clock\n"); 1895 1896 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &hdptx->hw); 1897 if (ret) 1898 return dev_err_probe(dev, ret, 1899 "Failed to register clk provider\n"); 1900 return 0; 1901 } 1902 1903 static int rk_hdptx_phy_runtime_suspend(struct device *dev) 1904 { 1905 struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev); 1906 1907 clk_bulk_disable_unprepare(hdptx->nr_clks, hdptx->clks); 1908 1909 return 0; 1910 } 1911 1912 static int rk_hdptx_phy_runtime_resume(struct device *dev) 1913 { 1914 struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev); 1915 int ret; 1916 1917 ret = clk_bulk_prepare_enable(hdptx->nr_clks, hdptx->clks); 1918 if (ret) 1919 dev_err(hdptx->dev, "Failed to enable clocks: %d\n", ret); 1920 1921 return ret; 1922 } 1923 1924 static int rk_hdptx_phy_probe(struct platform_device *pdev) 1925 { 1926 struct phy_provider *phy_provider; 1927 struct device *dev = &pdev->dev; 1928 struct rk_hdptx_phy *hdptx; 1929 struct resource *res; 1930 void __iomem *regs; 1931 int ret, id; 1932 1933 hdptx = devm_kzalloc(dev, sizeof(*hdptx), GFP_KERNEL); 1934 if (!hdptx) 1935 return -ENOMEM; 1936 1937 hdptx->dev = dev; 1938 1939 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1940 if (IS_ERR(regs)) 1941 return dev_err_probe(dev, PTR_ERR(regs), 1942 "Failed to ioremap resource\n"); 1943 1944 hdptx->cfgs = device_get_match_data(dev); 1945 if (!hdptx->cfgs) 1946 return dev_err_probe(dev, -EINVAL, "missing match data\n"); 1947 1948 /* find the phy-id from the io address */ 1949 hdptx->phy_id = -ENODEV; 1950 for (id = 0; id < hdptx->cfgs->num_phys; id++) { 1951 if (res->start == hdptx->cfgs->phy_ids[id]) { 1952 hdptx->phy_id = id; 1953 break; 1954 } 1955 } 1956 1957 if (hdptx->phy_id < 0) 1958 return dev_err_probe(dev, -ENODEV, "no matching device found\n"); 1959 1960 ret = devm_clk_bulk_get_all(dev, &hdptx->clks); 1961 if (ret < 0) 1962 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1963 if (ret == 0) 1964 return dev_err_probe(dev, -EINVAL, "Missing clocks\n"); 1965 1966 hdptx->nr_clks = ret; 1967 1968 hdptx->regmap = devm_regmap_init_mmio(dev, regs, 1969 &rk_hdptx_phy_regmap_config); 1970 if (IS_ERR(hdptx->regmap)) 1971 return dev_err_probe(dev, PTR_ERR(hdptx->regmap), 1972 "Failed to init regmap\n"); 1973 1974 hdptx->rsts[RST_APB].id = "apb"; 1975 hdptx->rsts[RST_INIT].id = "init"; 1976 hdptx->rsts[RST_CMN].id = "cmn"; 1977 hdptx->rsts[RST_LANE].id = "lane"; 1978 1979 ret = devm_reset_control_bulk_get_exclusive(dev, RST_MAX, hdptx->rsts); 1980 if (ret) 1981 return dev_err_probe(dev, ret, "Failed to get resets\n"); 1982 1983 hdptx->grf = syscon_regmap_lookup_by_phandle(dev->of_node, 1984 "rockchip,grf"); 1985 if (IS_ERR(hdptx->grf)) 1986 return dev_err_probe(dev, PTR_ERR(hdptx->grf), 1987 "Could not get GRF syscon\n"); 1988 1989 platform_set_drvdata(pdev, hdptx); 1990 1991 ret = devm_pm_runtime_enable(dev); 1992 if (ret) 1993 return dev_err_probe(dev, ret, "Failed to enable runtime PM\n"); 1994 1995 hdptx->phy = devm_phy_create(dev, NULL, &rk_hdptx_phy_ops); 1996 if (IS_ERR(hdptx->phy)) 1997 return dev_err_probe(dev, PTR_ERR(hdptx->phy), 1998 "Failed to create HDMI PHY\n"); 1999 2000 phy_set_drvdata(hdptx->phy, hdptx); 2001 phy_set_bus_width(hdptx->phy, 8); 2002 2003 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2004 if (IS_ERR(phy_provider)) 2005 return dev_err_probe(dev, PTR_ERR(phy_provider), 2006 "Failed to register PHY provider\n"); 2007 2008 reset_control_deassert(hdptx->rsts[RST_APB].rstc); 2009 reset_control_deassert(hdptx->rsts[RST_CMN].rstc); 2010 reset_control_deassert(hdptx->rsts[RST_INIT].rstc); 2011 2012 return rk_hdptx_phy_clk_register(hdptx); 2013 } 2014 2015 static const struct dev_pm_ops rk_hdptx_phy_pm_ops = { 2016 RUNTIME_PM_OPS(rk_hdptx_phy_runtime_suspend, 2017 rk_hdptx_phy_runtime_resume, NULL) 2018 }; 2019 2020 static const struct rk_hdptx_phy_cfg rk3576_hdptx_phy_cfgs = { 2021 .num_phys = 1, 2022 .phy_ids = { 2023 0x2b000000, 2024 }, 2025 }; 2026 2027 static const struct rk_hdptx_phy_cfg rk3588_hdptx_phy_cfgs = { 2028 .num_phys = 2, 2029 .phy_ids = { 2030 0xfed60000, 2031 0xfed70000, 2032 }, 2033 }; 2034 2035 static const struct of_device_id rk_hdptx_phy_of_match[] = { 2036 { 2037 .compatible = "rockchip,rk3576-hdptx-phy", 2038 .data = &rk3576_hdptx_phy_cfgs 2039 }, 2040 { 2041 .compatible = "rockchip,rk3588-hdptx-phy", 2042 .data = &rk3588_hdptx_phy_cfgs 2043 }, 2044 {} 2045 }; 2046 MODULE_DEVICE_TABLE(of, rk_hdptx_phy_of_match); 2047 2048 static struct platform_driver rk_hdptx_phy_driver = { 2049 .probe = rk_hdptx_phy_probe, 2050 .driver = { 2051 .name = "rockchip-hdptx-phy", 2052 .pm = &rk_hdptx_phy_pm_ops, 2053 .of_match_table = rk_hdptx_phy_of_match, 2054 }, 2055 }; 2056 module_platform_driver(rk_hdptx_phy_driver); 2057 2058 MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>"); 2059 MODULE_AUTHOR("Cristian Ciocaltea <cristian.ciocaltea@collabora.com>"); 2060 MODULE_AUTHOR("Damon Ding <damon.ding@rock-chips.com>"); 2061 MODULE_DESCRIPTION("Samsung HDMI/eDP Transmitter Combo PHY Driver"); 2062 MODULE_LICENSE("GPL"); 2063