108f13e7cSLubomir Rintel // SPDX-License-Identifier: GPL-2.0
208f13e7cSLubomir Rintel /*
308f13e7cSLubomir Rintel * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
408f13e7cSLubomir Rintel * Copyright (C) 2018,2019 Lubomir Rintel <lkundrak@v3.sk>
508f13e7cSLubomir Rintel */
608f13e7cSLubomir Rintel
708f13e7cSLubomir Rintel #include <linux/delay.h>
808f13e7cSLubomir Rintel #include <linux/io.h>
9*7559e757SRob Herring #include <linux/mod_devicetable.h>
1008f13e7cSLubomir Rintel #include <linux/module.h>
1108f13e7cSLubomir Rintel #include <linux/phy/phy.h>
1208f13e7cSLubomir Rintel #include <linux/platform_device.h>
1308f13e7cSLubomir Rintel #include <linux/soc/mmp/cputype.h>
1408f13e7cSLubomir Rintel
1508f13e7cSLubomir Rintel #define USB2_PLL_REG0 0x4
1608f13e7cSLubomir Rintel #define USB2_PLL_REG1 0x8
1708f13e7cSLubomir Rintel #define USB2_TX_REG0 0x10
1808f13e7cSLubomir Rintel #define USB2_TX_REG1 0x14
1908f13e7cSLubomir Rintel #define USB2_TX_REG2 0x18
2008f13e7cSLubomir Rintel #define USB2_RX_REG0 0x20
2108f13e7cSLubomir Rintel #define USB2_RX_REG1 0x24
2208f13e7cSLubomir Rintel #define USB2_RX_REG2 0x28
2308f13e7cSLubomir Rintel #define USB2_ANA_REG0 0x30
2408f13e7cSLubomir Rintel #define USB2_ANA_REG1 0x34
2508f13e7cSLubomir Rintel #define USB2_ANA_REG2 0x38
2608f13e7cSLubomir Rintel #define USB2_DIG_REG0 0x3C
2708f13e7cSLubomir Rintel #define USB2_DIG_REG1 0x40
2808f13e7cSLubomir Rintel #define USB2_DIG_REG2 0x44
2908f13e7cSLubomir Rintel #define USB2_DIG_REG3 0x48
3008f13e7cSLubomir Rintel #define USB2_TEST_REG0 0x4C
3108f13e7cSLubomir Rintel #define USB2_TEST_REG1 0x50
3208f13e7cSLubomir Rintel #define USB2_TEST_REG2 0x54
3308f13e7cSLubomir Rintel #define USB2_CHARGER_REG0 0x58
3408f13e7cSLubomir Rintel #define USB2_OTG_REG0 0x5C
3508f13e7cSLubomir Rintel #define USB2_PHY_MON0 0x60
3608f13e7cSLubomir Rintel #define USB2_RESETVE_REG0 0x64
3708f13e7cSLubomir Rintel #define USB2_ICID_REG0 0x78
3808f13e7cSLubomir Rintel #define USB2_ICID_REG1 0x7C
3908f13e7cSLubomir Rintel
4008f13e7cSLubomir Rintel /* USB2_PLL_REG0 */
4108f13e7cSLubomir Rintel
4208f13e7cSLubomir Rintel /* This is for Ax stepping */
4308f13e7cSLubomir Rintel #define USB2_PLL_FBDIV_SHIFT_MMP3 0
4408f13e7cSLubomir Rintel #define USB2_PLL_FBDIV_MASK_MMP3 (0xFF << 0)
4508f13e7cSLubomir Rintel
4608f13e7cSLubomir Rintel #define USB2_PLL_REFDIV_SHIFT_MMP3 8
4708f13e7cSLubomir Rintel #define USB2_PLL_REFDIV_MASK_MMP3 (0xF << 8)
4808f13e7cSLubomir Rintel
4908f13e7cSLubomir Rintel #define USB2_PLL_VDD12_SHIFT_MMP3 12
5008f13e7cSLubomir Rintel #define USB2_PLL_VDD18_SHIFT_MMP3 14
5108f13e7cSLubomir Rintel
5208f13e7cSLubomir Rintel /* This is for B0 stepping */
5308f13e7cSLubomir Rintel #define USB2_PLL_FBDIV_SHIFT_MMP3_B0 0
5408f13e7cSLubomir Rintel #define USB2_PLL_REFDIV_SHIFT_MMP3_B0 9
5508f13e7cSLubomir Rintel #define USB2_PLL_VDD18_SHIFT_MMP3_B0 14
5608f13e7cSLubomir Rintel #define USB2_PLL_FBDIV_MASK_MMP3_B0 0x01FF
5708f13e7cSLubomir Rintel #define USB2_PLL_REFDIV_MASK_MMP3_B0 0x3E00
5808f13e7cSLubomir Rintel
5908f13e7cSLubomir Rintel #define USB2_PLL_CAL12_SHIFT_MMP3 0
6008f13e7cSLubomir Rintel #define USB2_PLL_CALI12_MASK_MMP3 (0x3 << 0)
6108f13e7cSLubomir Rintel
6208f13e7cSLubomir Rintel #define USB2_PLL_VCOCAL_START_SHIFT_MMP3 2
6308f13e7cSLubomir Rintel
6408f13e7cSLubomir Rintel #define USB2_PLL_KVCO_SHIFT_MMP3 4
6508f13e7cSLubomir Rintel #define USB2_PLL_KVCO_MASK_MMP3 (0x7<<4)
6608f13e7cSLubomir Rintel
6708f13e7cSLubomir Rintel #define USB2_PLL_ICP_SHIFT_MMP3 8
6808f13e7cSLubomir Rintel #define USB2_PLL_ICP_MASK_MMP3 (0x7<<8)
6908f13e7cSLubomir Rintel
7008f13e7cSLubomir Rintel #define USB2_PLL_LOCK_BYPASS_SHIFT_MMP3 12
7108f13e7cSLubomir Rintel
7208f13e7cSLubomir Rintel #define USB2_PLL_PU_PLL_SHIFT_MMP3 13
7308f13e7cSLubomir Rintel #define USB2_PLL_PU_PLL_MASK (0x1 << 13)
7408f13e7cSLubomir Rintel
7508f13e7cSLubomir Rintel #define USB2_PLL_READY_MASK_MMP3 (0x1 << 15)
7608f13e7cSLubomir Rintel
7708f13e7cSLubomir Rintel /* USB2_TX_REG0 */
7808f13e7cSLubomir Rintel #define USB2_TX_IMPCAL_VTH_SHIFT_MMP3 8
7908f13e7cSLubomir Rintel #define USB2_TX_IMPCAL_VTH_MASK_MMP3 (0x7 << 8)
8008f13e7cSLubomir Rintel
8108f13e7cSLubomir Rintel #define USB2_TX_RCAL_START_SHIFT_MMP3 13
8208f13e7cSLubomir Rintel
8308f13e7cSLubomir Rintel /* USB2_TX_REG1 */
8408f13e7cSLubomir Rintel #define USB2_TX_CK60_PHSEL_SHIFT_MMP3 0
8508f13e7cSLubomir Rintel #define USB2_TX_CK60_PHSEL_MASK_MMP3 (0xf << 0)
8608f13e7cSLubomir Rintel
8708f13e7cSLubomir Rintel #define USB2_TX_AMP_SHIFT_MMP3 4
8808f13e7cSLubomir Rintel #define USB2_TX_AMP_MASK_MMP3 (0x7 << 4)
8908f13e7cSLubomir Rintel
9008f13e7cSLubomir Rintel #define USB2_TX_VDD12_SHIFT_MMP3 8
9108f13e7cSLubomir Rintel #define USB2_TX_VDD12_MASK_MMP3 (0x3 << 8)
9208f13e7cSLubomir Rintel
9308f13e7cSLubomir Rintel /* USB2_TX_REG2 */
9408f13e7cSLubomir Rintel #define USB2_TX_DRV_SLEWRATE_SHIFT 10
9508f13e7cSLubomir Rintel
9608f13e7cSLubomir Rintel /* USB2_RX_REG0 */
9708f13e7cSLubomir Rintel #define USB2_RX_SQ_THRESH_SHIFT_MMP3 4
9808f13e7cSLubomir Rintel #define USB2_RX_SQ_THRESH_MASK_MMP3 (0xf << 4)
9908f13e7cSLubomir Rintel
10008f13e7cSLubomir Rintel #define USB2_RX_SQ_LENGTH_SHIFT_MMP3 10
10108f13e7cSLubomir Rintel #define USB2_RX_SQ_LENGTH_MASK_MMP3 (0x3 << 10)
10208f13e7cSLubomir Rintel
10308f13e7cSLubomir Rintel /* USB2_ANA_REG1*/
10408f13e7cSLubomir Rintel #define USB2_ANA_PU_ANA_SHIFT_MMP3 14
10508f13e7cSLubomir Rintel
10608f13e7cSLubomir Rintel /* USB2_OTG_REG0 */
10708f13e7cSLubomir Rintel #define USB2_OTG_PU_OTG_SHIFT_MMP3 3
10808f13e7cSLubomir Rintel
10908f13e7cSLubomir Rintel struct mmp3_usb_phy {
11008f13e7cSLubomir Rintel struct phy *phy;
11108f13e7cSLubomir Rintel void __iomem *base;
11208f13e7cSLubomir Rintel };
11308f13e7cSLubomir Rintel
u2o_get(void __iomem * base,unsigned int offset)11408f13e7cSLubomir Rintel static unsigned int u2o_get(void __iomem *base, unsigned int offset)
11508f13e7cSLubomir Rintel {
11608f13e7cSLubomir Rintel return readl_relaxed(base + offset);
11708f13e7cSLubomir Rintel }
11808f13e7cSLubomir Rintel
u2o_set(void __iomem * base,unsigned int offset,unsigned int value)11908f13e7cSLubomir Rintel static void u2o_set(void __iomem *base, unsigned int offset,
12008f13e7cSLubomir Rintel unsigned int value)
12108f13e7cSLubomir Rintel {
12208f13e7cSLubomir Rintel u32 reg;
12308f13e7cSLubomir Rintel
12408f13e7cSLubomir Rintel reg = readl_relaxed(base + offset);
12508f13e7cSLubomir Rintel reg |= value;
12608f13e7cSLubomir Rintel writel_relaxed(reg, base + offset);
12708f13e7cSLubomir Rintel readl_relaxed(base + offset);
12808f13e7cSLubomir Rintel }
12908f13e7cSLubomir Rintel
u2o_clear(void __iomem * base,unsigned int offset,unsigned int value)13008f13e7cSLubomir Rintel static void u2o_clear(void __iomem *base, unsigned int offset,
13108f13e7cSLubomir Rintel unsigned int value)
13208f13e7cSLubomir Rintel {
13308f13e7cSLubomir Rintel u32 reg;
13408f13e7cSLubomir Rintel
13508f13e7cSLubomir Rintel reg = readl_relaxed(base + offset);
13608f13e7cSLubomir Rintel reg &= ~value;
13708f13e7cSLubomir Rintel writel_relaxed(reg, base + offset);
13808f13e7cSLubomir Rintel readl_relaxed(base + offset);
13908f13e7cSLubomir Rintel }
14008f13e7cSLubomir Rintel
mmp3_usb_phy_init(struct phy * phy)14108f13e7cSLubomir Rintel static int mmp3_usb_phy_init(struct phy *phy)
14208f13e7cSLubomir Rintel {
14308f13e7cSLubomir Rintel struct mmp3_usb_phy *mmp3_usb_phy = phy_get_drvdata(phy);
14408f13e7cSLubomir Rintel void __iomem *base = mmp3_usb_phy->base;
14508f13e7cSLubomir Rintel
14608f13e7cSLubomir Rintel if (cpu_is_mmp3_a0()) {
14708f13e7cSLubomir Rintel u2o_clear(base, USB2_PLL_REG0, (USB2_PLL_FBDIV_MASK_MMP3
14808f13e7cSLubomir Rintel | USB2_PLL_REFDIV_MASK_MMP3));
14908f13e7cSLubomir Rintel u2o_set(base, USB2_PLL_REG0,
15008f13e7cSLubomir Rintel 0xd << USB2_PLL_REFDIV_SHIFT_MMP3
15108f13e7cSLubomir Rintel | 0xf0 << USB2_PLL_FBDIV_SHIFT_MMP3);
15208f13e7cSLubomir Rintel } else if (cpu_is_mmp3_b0()) {
15308f13e7cSLubomir Rintel u2o_clear(base, USB2_PLL_REG0, USB2_PLL_REFDIV_MASK_MMP3_B0
15408f13e7cSLubomir Rintel | USB2_PLL_FBDIV_MASK_MMP3_B0);
15508f13e7cSLubomir Rintel u2o_set(base, USB2_PLL_REG0,
15608f13e7cSLubomir Rintel 0xd << USB2_PLL_REFDIV_SHIFT_MMP3_B0
15708f13e7cSLubomir Rintel | 0xf0 << USB2_PLL_FBDIV_SHIFT_MMP3_B0);
15808f13e7cSLubomir Rintel } else {
15908f13e7cSLubomir Rintel dev_err(&phy->dev, "unsupported silicon revision\n");
16008f13e7cSLubomir Rintel return -ENODEV;
16108f13e7cSLubomir Rintel }
16208f13e7cSLubomir Rintel
16308f13e7cSLubomir Rintel u2o_clear(base, USB2_PLL_REG1, USB2_PLL_PU_PLL_MASK
16408f13e7cSLubomir Rintel | USB2_PLL_ICP_MASK_MMP3
16508f13e7cSLubomir Rintel | USB2_PLL_KVCO_MASK_MMP3
16608f13e7cSLubomir Rintel | USB2_PLL_CALI12_MASK_MMP3);
16708f13e7cSLubomir Rintel u2o_set(base, USB2_PLL_REG1, 1 << USB2_PLL_PU_PLL_SHIFT_MMP3
16808f13e7cSLubomir Rintel | 1 << USB2_PLL_LOCK_BYPASS_SHIFT_MMP3
16908f13e7cSLubomir Rintel | 3 << USB2_PLL_ICP_SHIFT_MMP3
17008f13e7cSLubomir Rintel | 3 << USB2_PLL_KVCO_SHIFT_MMP3
17108f13e7cSLubomir Rintel | 3 << USB2_PLL_CAL12_SHIFT_MMP3);
17208f13e7cSLubomir Rintel
17308f13e7cSLubomir Rintel u2o_clear(base, USB2_TX_REG0, USB2_TX_IMPCAL_VTH_MASK_MMP3);
17408f13e7cSLubomir Rintel u2o_set(base, USB2_TX_REG0, 2 << USB2_TX_IMPCAL_VTH_SHIFT_MMP3);
17508f13e7cSLubomir Rintel
17608f13e7cSLubomir Rintel u2o_clear(base, USB2_TX_REG1, USB2_TX_VDD12_MASK_MMP3
17708f13e7cSLubomir Rintel | USB2_TX_AMP_MASK_MMP3
17808f13e7cSLubomir Rintel | USB2_TX_CK60_PHSEL_MASK_MMP3);
17908f13e7cSLubomir Rintel u2o_set(base, USB2_TX_REG1, 3 << USB2_TX_VDD12_SHIFT_MMP3
18008f13e7cSLubomir Rintel | 4 << USB2_TX_AMP_SHIFT_MMP3
18108f13e7cSLubomir Rintel | 4 << USB2_TX_CK60_PHSEL_SHIFT_MMP3);
18208f13e7cSLubomir Rintel
18308f13e7cSLubomir Rintel u2o_clear(base, USB2_TX_REG2, 3 << USB2_TX_DRV_SLEWRATE_SHIFT);
18408f13e7cSLubomir Rintel u2o_set(base, USB2_TX_REG2, 2 << USB2_TX_DRV_SLEWRATE_SHIFT);
18508f13e7cSLubomir Rintel
18608f13e7cSLubomir Rintel u2o_clear(base, USB2_RX_REG0, USB2_RX_SQ_THRESH_MASK_MMP3);
18708f13e7cSLubomir Rintel u2o_set(base, USB2_RX_REG0, 0xa << USB2_RX_SQ_THRESH_SHIFT_MMP3);
18808f13e7cSLubomir Rintel
18908f13e7cSLubomir Rintel u2o_set(base, USB2_ANA_REG1, 0x1 << USB2_ANA_PU_ANA_SHIFT_MMP3);
19008f13e7cSLubomir Rintel
19108f13e7cSLubomir Rintel u2o_set(base, USB2_OTG_REG0, 0x1 << USB2_OTG_PU_OTG_SHIFT_MMP3);
19208f13e7cSLubomir Rintel
19308f13e7cSLubomir Rintel return 0;
19408f13e7cSLubomir Rintel }
19508f13e7cSLubomir Rintel
mmp3_usb_phy_calibrate(struct phy * phy)19608f13e7cSLubomir Rintel static int mmp3_usb_phy_calibrate(struct phy *phy)
19708f13e7cSLubomir Rintel {
19808f13e7cSLubomir Rintel struct mmp3_usb_phy *mmp3_usb_phy = phy_get_drvdata(phy);
19908f13e7cSLubomir Rintel void __iomem *base = mmp3_usb_phy->base;
20008f13e7cSLubomir Rintel int loops;
20108f13e7cSLubomir Rintel
20208f13e7cSLubomir Rintel /*
20308f13e7cSLubomir Rintel * PLL VCO and TX Impedance Calibration Timing:
20408f13e7cSLubomir Rintel *
20508f13e7cSLubomir Rintel * _____________________________________
20608f13e7cSLubomir Rintel * PU __________|
20708f13e7cSLubomir Rintel * _____________________________
20808f13e7cSLubomir Rintel * VCOCAL START _________|
20908f13e7cSLubomir Rintel * ___
21008f13e7cSLubomir Rintel * REG_RCAL_START ________________| |________|_______
21108f13e7cSLubomir Rintel * | 200us | 400us | 40| 400us | USB PHY READY
21208f13e7cSLubomir Rintel */
21308f13e7cSLubomir Rintel
21408f13e7cSLubomir Rintel udelay(200);
21508f13e7cSLubomir Rintel u2o_set(base, USB2_PLL_REG1, 1 << USB2_PLL_VCOCAL_START_SHIFT_MMP3);
21608f13e7cSLubomir Rintel udelay(400);
21708f13e7cSLubomir Rintel u2o_set(base, USB2_TX_REG0, 1 << USB2_TX_RCAL_START_SHIFT_MMP3);
21808f13e7cSLubomir Rintel udelay(40);
21908f13e7cSLubomir Rintel u2o_clear(base, USB2_TX_REG0, 1 << USB2_TX_RCAL_START_SHIFT_MMP3);
22008f13e7cSLubomir Rintel udelay(400);
22108f13e7cSLubomir Rintel
22208f13e7cSLubomir Rintel loops = 0;
22308f13e7cSLubomir Rintel while ((u2o_get(base, USB2_PLL_REG1) & USB2_PLL_READY_MASK_MMP3) == 0) {
22408f13e7cSLubomir Rintel mdelay(1);
22508f13e7cSLubomir Rintel loops++;
22608f13e7cSLubomir Rintel if (loops > 100) {
22708f13e7cSLubomir Rintel dev_err(&phy->dev, "PLL_READY not set after 100mS.\n");
22808f13e7cSLubomir Rintel return -ETIMEDOUT;
22908f13e7cSLubomir Rintel }
23008f13e7cSLubomir Rintel }
23108f13e7cSLubomir Rintel
23208f13e7cSLubomir Rintel return 0;
23308f13e7cSLubomir Rintel }
23408f13e7cSLubomir Rintel
23508f13e7cSLubomir Rintel static const struct phy_ops mmp3_usb_phy_ops = {
23608f13e7cSLubomir Rintel .init = mmp3_usb_phy_init,
23708f13e7cSLubomir Rintel .calibrate = mmp3_usb_phy_calibrate,
23808f13e7cSLubomir Rintel .owner = THIS_MODULE,
23908f13e7cSLubomir Rintel };
24008f13e7cSLubomir Rintel
24108f13e7cSLubomir Rintel static const struct of_device_id mmp3_usb_phy_of_match[] = {
24208f13e7cSLubomir Rintel { .compatible = "marvell,mmp3-usb-phy", },
24308f13e7cSLubomir Rintel { },
24408f13e7cSLubomir Rintel };
24508f13e7cSLubomir Rintel MODULE_DEVICE_TABLE(of, mmp3_usb_phy_of_match);
24608f13e7cSLubomir Rintel
mmp3_usb_phy_probe(struct platform_device * pdev)24708f13e7cSLubomir Rintel static int mmp3_usb_phy_probe(struct platform_device *pdev)
24808f13e7cSLubomir Rintel {
24908f13e7cSLubomir Rintel struct device *dev = &pdev->dev;
25008f13e7cSLubomir Rintel struct mmp3_usb_phy *mmp3_usb_phy;
25108f13e7cSLubomir Rintel struct phy_provider *provider;
25208f13e7cSLubomir Rintel
25308f13e7cSLubomir Rintel mmp3_usb_phy = devm_kzalloc(dev, sizeof(*mmp3_usb_phy), GFP_KERNEL);
25408f13e7cSLubomir Rintel if (!mmp3_usb_phy)
25508f13e7cSLubomir Rintel return -ENOMEM;
25608f13e7cSLubomir Rintel
257ee55b501SChunfeng Yun mmp3_usb_phy->base = devm_platform_ioremap_resource(pdev, 0);
25808f13e7cSLubomir Rintel if (IS_ERR(mmp3_usb_phy->base)) {
25908f13e7cSLubomir Rintel dev_err(dev, "failed to remap PHY regs\n");
26008f13e7cSLubomir Rintel return PTR_ERR(mmp3_usb_phy->base);
26108f13e7cSLubomir Rintel }
26208f13e7cSLubomir Rintel
26308f13e7cSLubomir Rintel mmp3_usb_phy->phy = devm_phy_create(dev, NULL, &mmp3_usb_phy_ops);
26408f13e7cSLubomir Rintel if (IS_ERR(mmp3_usb_phy->phy)) {
26508f13e7cSLubomir Rintel dev_err(dev, "failed to create PHY\n");
26608f13e7cSLubomir Rintel return PTR_ERR(mmp3_usb_phy->phy);
26708f13e7cSLubomir Rintel }
26808f13e7cSLubomir Rintel
26908f13e7cSLubomir Rintel phy_set_drvdata(mmp3_usb_phy->phy, mmp3_usb_phy);
27008f13e7cSLubomir Rintel provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
27108f13e7cSLubomir Rintel if (IS_ERR(provider)) {
27208f13e7cSLubomir Rintel dev_err(dev, "failed to register PHY provider\n");
27308f13e7cSLubomir Rintel return PTR_ERR(provider);
27408f13e7cSLubomir Rintel }
27508f13e7cSLubomir Rintel
27608f13e7cSLubomir Rintel return 0;
27708f13e7cSLubomir Rintel }
27808f13e7cSLubomir Rintel
27908f13e7cSLubomir Rintel static struct platform_driver mmp3_usb_phy_driver = {
28008f13e7cSLubomir Rintel .probe = mmp3_usb_phy_probe,
28108f13e7cSLubomir Rintel .driver = {
28208f13e7cSLubomir Rintel .name = "mmp3-usb-phy",
28308f13e7cSLubomir Rintel .of_match_table = mmp3_usb_phy_of_match,
28408f13e7cSLubomir Rintel },
28508f13e7cSLubomir Rintel };
28608f13e7cSLubomir Rintel module_platform_driver(mmp3_usb_phy_driver);
28708f13e7cSLubomir Rintel
28808f13e7cSLubomir Rintel MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
28908f13e7cSLubomir Rintel MODULE_DESCRIPTION("Marvell MMP3 USB PHY Driver");
29008f13e7cSLubomir Rintel MODULE_LICENSE("GPL v2");
291