1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support routines for initializing a PCI subsystem 4 * 5 * Extruded from code written by 6 * Dave Rusling (david.rusling@reo.mts.dec.com) 7 * David Mosberger (davidm@cs.arizona.edu) 8 * David Miller (davem@redhat.com) 9 * 10 * Fixed for multiple PCI buses, 1999 Andrea Arcangeli <andrea@suse.de> 11 * 12 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 13 * Resource sorting 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/export.h> 18 #include <linux/pci.h> 19 #include <linux/errno.h> 20 #include <linux/ioport.h> 21 #include <linux/cache.h> 22 #include <linux/slab.h> 23 #include "pci.h" 24 25 static void pci_std_update_resource(struct pci_dev *dev, int resno) 26 { 27 struct pci_bus_region region; 28 bool disable; 29 u16 cmd; 30 u32 new, check, mask; 31 int reg; 32 struct resource *res = pci_resource_n(dev, resno); 33 const char *res_name = pci_resource_name(dev, resno); 34 35 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */ 36 if (dev->is_virtfn) 37 return; 38 39 /* 40 * Ignore resources for unimplemented BARs and unused resource slots 41 * for 64 bit BARs. 42 */ 43 if (!res->flags) 44 return; 45 46 if (res->flags & IORESOURCE_UNSET) 47 return; 48 49 /* 50 * Ignore non-moveable resources. This might be legacy resources for 51 * which no functional BAR register exists or another important 52 * system resource we shouldn't move around. 53 */ 54 if (res->flags & IORESOURCE_PCI_FIXED) 55 return; 56 57 pcibios_resource_to_bus(dev->bus, ®ion, res); 58 new = region.start; 59 60 if (res->flags & IORESOURCE_IO) { 61 mask = (u32)PCI_BASE_ADDRESS_IO_MASK; 62 new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK; 63 } else if (resno == PCI_ROM_RESOURCE) { 64 mask = PCI_ROM_ADDRESS_MASK; 65 } else { 66 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 67 new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK; 68 } 69 70 if (resno < PCI_ROM_RESOURCE) { 71 reg = PCI_BASE_ADDRESS_0 + 4 * resno; 72 } else if (resno == PCI_ROM_RESOURCE) { 73 74 /* 75 * Apparently some Matrox devices have ROM BARs that read 76 * as zero when disabled, so don't update ROM BARs unless 77 * they're enabled. See 78 * https://lore.kernel.org/r/43147B3D.1030309@vc.cvut.cz/ 79 * But we must update ROM BAR for buggy devices where even a 80 * disabled ROM can conflict with other BARs. 81 */ 82 if (!(res->flags & IORESOURCE_ROM_ENABLE) && 83 !dev->rom_bar_overlap) 84 return; 85 86 reg = dev->rom_base_reg; 87 if (res->flags & IORESOURCE_ROM_ENABLE) 88 new |= PCI_ROM_ADDRESS_ENABLE; 89 } else 90 return; 91 92 /* 93 * We can't update a 64-bit BAR atomically, so when possible, 94 * disable decoding so that a half-updated BAR won't conflict 95 * with another device. 96 */ 97 disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on; 98 if (disable) { 99 pci_read_config_word(dev, PCI_COMMAND, &cmd); 100 pci_write_config_word(dev, PCI_COMMAND, 101 cmd & ~PCI_COMMAND_MEMORY); 102 } 103 104 pci_write_config_dword(dev, reg, new); 105 dev->saved_config_space[reg / 4] = new; 106 pci_read_config_dword(dev, reg, &check); 107 108 if ((new ^ check) & mask) { 109 pci_err(dev, "%s: error updating (%#010x != %#010x)\n", 110 res_name, new, check); 111 } 112 113 if (res->flags & IORESOURCE_MEM_64) { 114 new = region.start >> 16 >> 16; 115 pci_write_config_dword(dev, reg + 4, new); 116 dev->saved_config_space[(reg + 4) / 4] = new; 117 pci_read_config_dword(dev, reg + 4, &check); 118 if (check != new) { 119 pci_err(dev, "%s: error updating (high %#010x != %#010x)\n", 120 res_name, new, check); 121 } 122 } 123 124 if (disable) 125 pci_write_config_word(dev, PCI_COMMAND, cmd); 126 } 127 128 void pci_update_resource(struct pci_dev *dev, int resno) 129 { 130 if (resno <= PCI_ROM_RESOURCE) 131 pci_std_update_resource(dev, resno); 132 else if (pci_resource_is_iov(resno)) 133 pci_iov_update_resource(dev, resno); 134 } 135 136 int pci_claim_resource(struct pci_dev *dev, int resource) 137 { 138 struct resource *res = &dev->resource[resource]; 139 const char *res_name = pci_resource_name(dev, resource); 140 struct resource *root, *conflict; 141 142 if (res->flags & IORESOURCE_UNSET) { 143 pci_info(dev, "%s %pR: can't claim; no address assigned\n", 144 res_name, res); 145 return -EINVAL; 146 } 147 148 /* 149 * If we have a shadow copy in RAM, the PCI device doesn't respond 150 * to the shadow range, so we don't need to claim it, and upstream 151 * bridges don't need to route the range to the device. 152 */ 153 if (res->flags & IORESOURCE_ROM_SHADOW) 154 return 0; 155 156 root = pci_find_parent_resource(dev, res); 157 if (!root) { 158 pci_info(dev, "%s %pR: can't claim; no compatible bridge window\n", 159 res_name, res); 160 res->flags |= IORESOURCE_UNSET; 161 return -EINVAL; 162 } 163 164 conflict = request_resource_conflict(root, res); 165 if (conflict) { 166 pci_info(dev, "%s %pR: can't claim; address conflict with %s %pR\n", 167 res_name, res, conflict->name, conflict); 168 res->flags |= IORESOURCE_UNSET; 169 return -EBUSY; 170 } 171 172 return 0; 173 } 174 EXPORT_SYMBOL(pci_claim_resource); 175 176 void pci_disable_bridge_window(struct pci_dev *dev) 177 { 178 /* MMIO Base/Limit */ 179 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0); 180 181 /* Prefetchable MMIO Base/Limit */ 182 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0); 183 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0); 184 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff); 185 } 186 187 /* 188 * Generic function that returns a value indicating that the device's 189 * original BIOS BAR address was not saved and so is not available for 190 * reinstatement. 191 * 192 * Can be over-ridden by architecture specific code that implements 193 * reinstatement functionality rather than leaving it disabled when 194 * normal allocation attempts fail. 195 */ 196 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx) 197 { 198 return 0; 199 } 200 201 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, 202 int resno, resource_size_t size) 203 { 204 struct resource *root, *conflict; 205 resource_size_t fw_addr, start, end; 206 const char *res_name = pci_resource_name(dev, resno); 207 208 fw_addr = pcibios_retrieve_fw_addr(dev, resno); 209 if (!fw_addr) 210 return -ENOMEM; 211 212 start = res->start; 213 end = res->end; 214 resource_set_range(res, fw_addr, size); 215 res->flags &= ~IORESOURCE_UNSET; 216 217 root = pci_find_parent_resource(dev, res); 218 if (!root) { 219 /* 220 * If dev is behind a bridge, accesses will only reach it 221 * if res is inside the relevant bridge window. 222 */ 223 if (pci_upstream_bridge(dev)) 224 return -ENXIO; 225 226 /* 227 * On the root bus, assume the host bridge will forward 228 * everything. 229 */ 230 if (res->flags & IORESOURCE_IO) 231 root = &ioport_resource; 232 else 233 root = &iomem_resource; 234 } 235 236 pci_info(dev, "%s: trying firmware assignment %pR\n", res_name, res); 237 conflict = request_resource_conflict(root, res); 238 if (conflict) { 239 pci_info(dev, "%s %pR: conflicts with %s %pR\n", res_name, res, 240 conflict->name, conflict); 241 res->start = start; 242 res->end = end; 243 res->flags |= IORESOURCE_UNSET; 244 return -EBUSY; 245 } 246 return 0; 247 } 248 249 /* 250 * For mem bridge windows, try to relocate tail remainder space to space 251 * before res->start if there's enough free space there. This enables 252 * tighter packing for resources. 253 */ 254 resource_size_t pci_align_resource(struct pci_dev *dev, 255 const struct resource *res, 256 const struct resource *empty_res, 257 resource_size_t size, 258 resource_size_t align) 259 { 260 resource_size_t remainder, start_addr; 261 262 if (!(res->flags & IORESOURCE_MEM)) 263 return res->start; 264 265 if (IS_ALIGNED(size, align)) 266 return res->start; 267 268 remainder = size - ALIGN_DOWN(size, align); 269 /* Don't mess with size that doesn't align with window size granularity */ 270 if (!IS_ALIGNED(remainder, pci_min_window_alignment(dev->bus, res->flags))) 271 return res->start; 272 /* Try to place remainder that doesn't fill align before */ 273 if (res->start < remainder) 274 return res->start; 275 start_addr = res->start - remainder; 276 if (empty_res->start > start_addr) 277 return res->start; 278 279 pci_dbg(dev, "%pR: moving candidate start address below align to %llx\n", 280 res, (unsigned long long)start_addr); 281 return start_addr; 282 } 283 284 /* 285 * We don't have to worry about legacy ISA devices, so nothing to do here. 286 * This is marked as __weak because multiple architectures define it; it should 287 * eventually go away. 288 */ 289 resource_size_t __weak pcibios_align_resource(void *data, 290 const struct resource *res, 291 const struct resource *empty_res, 292 resource_size_t size, 293 resource_size_t align) 294 { 295 struct pci_dev *dev = data; 296 297 return pci_align_resource(dev, res, empty_res, size, align); 298 } 299 300 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, 301 int resno, resource_size_t size, resource_size_t align) 302 { 303 struct resource *res = pci_resource_n(dev, resno); 304 resource_size_t min; 305 int ret; 306 307 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; 308 309 /* 310 * First, try exact prefetching match. Even if a 64-bit 311 * prefetchable bridge window is below 4GB, we can't put a 32-bit 312 * prefetchable resource in it because pbus_size_mem() assumes a 313 * 64-bit window will contain no 32-bit resources. If we assign 314 * things differently than they were sized, not everything will fit. 315 */ 316 ret = pci_bus_alloc_resource(bus, res, size, align, min, 317 IORESOURCE_PREFETCH | IORESOURCE_MEM_64, 318 pcibios_align_resource, dev); 319 if (ret == 0) 320 return 0; 321 322 /* 323 * If the prefetchable window is only 32 bits wide, we can put 324 * 64-bit prefetchable resources in it. 325 */ 326 if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) == 327 (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) { 328 ret = pci_bus_alloc_resource(bus, res, size, align, min, 329 IORESOURCE_PREFETCH, 330 pcibios_align_resource, dev); 331 if (ret == 0) 332 return 0; 333 } 334 335 /* 336 * If we didn't find a better match, we can put any memory resource 337 * in a non-prefetchable window. If this resource is 32 bits and 338 * non-prefetchable, the first call already tried the only possibility 339 * so we don't need to try again. 340 */ 341 if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) 342 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0, 343 pcibios_align_resource, dev); 344 345 return ret; 346 } 347 348 static int _pci_assign_resource(struct pci_dev *dev, int resno, 349 resource_size_t size, resource_size_t min_align) 350 { 351 struct pci_bus *bus; 352 int ret; 353 354 bus = dev->bus; 355 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) { 356 if (!bus->parent || !bus->self->transparent) 357 break; 358 bus = bus->parent; 359 } 360 361 return ret; 362 } 363 364 int pci_assign_resource(struct pci_dev *dev, int resno) 365 { 366 struct resource *res = pci_resource_n(dev, resno); 367 const char *res_name = pci_resource_name(dev, resno); 368 resource_size_t align, size; 369 int ret; 370 371 if (res->flags & IORESOURCE_PCI_FIXED) 372 return 0; 373 374 res->flags |= IORESOURCE_UNSET; 375 align = pci_resource_alignment(dev, res); 376 if (!align) { 377 pci_info(dev, "%s %pR: can't assign; bogus alignment\n", 378 res_name, res); 379 return -EINVAL; 380 } 381 382 size = resource_size(res); 383 ret = _pci_assign_resource(dev, resno, size, align); 384 385 /* 386 * If we failed to assign anything, let's try the address 387 * where firmware left it. That at least has a chance of 388 * working, which is better than just leaving it disabled. 389 */ 390 if (ret < 0) { 391 pci_info(dev, "%s %pR: can't assign; no space\n", res_name, res); 392 ret = pci_revert_fw_address(res, dev, resno, size); 393 } 394 395 if (ret < 0) { 396 pci_info(dev, "%s %pR: failed to assign\n", res_name, res); 397 return ret; 398 } 399 400 res->flags &= ~IORESOURCE_UNSET; 401 res->flags &= ~IORESOURCE_STARTALIGN; 402 if (pci_resource_is_bridge_win(resno)) 403 res->flags &= ~IORESOURCE_DISABLED; 404 405 pci_info(dev, "%s %pR: assigned\n", res_name, res); 406 if (resno < PCI_BRIDGE_RESOURCES) 407 pci_update_resource(dev, resno); 408 409 return 0; 410 } 411 EXPORT_SYMBOL(pci_assign_resource); 412 413 int pci_reassign_resource(struct pci_dev *dev, int resno, 414 resource_size_t addsize, resource_size_t min_align) 415 { 416 struct resource *res = pci_resource_n(dev, resno); 417 const char *res_name = pci_resource_name(dev, resno); 418 unsigned long flags; 419 resource_size_t new_size; 420 int ret; 421 422 if (res->flags & IORESOURCE_PCI_FIXED) 423 return 0; 424 425 flags = res->flags; 426 res->flags |= IORESOURCE_UNSET; 427 if (!res->parent) { 428 pci_info(dev, "%s %pR: can't reassign; unassigned resource\n", 429 res_name, res); 430 return -EINVAL; 431 } 432 433 new_size = resource_size(res) + addsize; 434 ret = _pci_assign_resource(dev, resno, new_size, min_align); 435 if (ret) { 436 res->flags = flags; 437 pci_info(dev, "%s %pR: failed to expand by %#llx\n", 438 res_name, res, (unsigned long long) addsize); 439 return ret; 440 } 441 442 res->flags &= ~IORESOURCE_UNSET; 443 res->flags &= ~IORESOURCE_STARTALIGN; 444 pci_info(dev, "%s %pR: reassigned; expanded by %#llx\n", 445 res_name, res, (unsigned long long) addsize); 446 if (resno < PCI_BRIDGE_RESOURCES) 447 pci_update_resource(dev, resno); 448 449 return 0; 450 } 451 452 int pci_release_resource(struct pci_dev *dev, int resno) 453 { 454 struct resource *res = pci_resource_n(dev, resno); 455 const char *res_name = pci_resource_name(dev, resno); 456 int ret; 457 458 if (!res->parent) 459 return 0; 460 461 pci_info(dev, "%s %pR: releasing\n", res_name, res); 462 463 ret = release_resource(res); 464 if (ret) 465 return ret; 466 res->end = resource_size(res) - 1; 467 res->start = 0; 468 res->flags |= IORESOURCE_UNSET; 469 470 return 0; 471 } 472 EXPORT_SYMBOL(pci_release_resource); 473 474 int pci_enable_resources(struct pci_dev *dev, int mask) 475 { 476 u16 cmd, old_cmd; 477 int i; 478 struct resource *r; 479 const char *r_name; 480 481 pci_read_config_word(dev, PCI_COMMAND, &cmd); 482 old_cmd = cmd; 483 484 pci_dev_for_each_resource(dev, r, i) { 485 if (!(mask & (1 << i))) 486 continue; 487 488 r_name = pci_resource_name(dev, i); 489 490 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 491 continue; 492 if (pci_resource_is_optional(dev, i)) 493 continue; 494 495 if (i < PCI_BRIDGE_RESOURCES) { 496 if (r->flags & IORESOURCE_UNSET) { 497 pci_err(dev, "%s %pR: not assigned; can't enable device\n", 498 r_name, r); 499 return -EINVAL; 500 } 501 502 if (!r->parent) { 503 pci_err(dev, "%s %pR: not claimed; can't enable device\n", 504 r_name, r); 505 return -EINVAL; 506 } 507 } 508 509 if (r->parent) { 510 if (r->flags & IORESOURCE_IO) 511 cmd |= PCI_COMMAND_IO; 512 if (r->flags & IORESOURCE_MEM) 513 cmd |= PCI_COMMAND_MEMORY; 514 } 515 } 516 517 if (cmd != old_cmd) { 518 pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd); 519 pci_write_config_word(dev, PCI_COMMAND, cmd); 520 } 521 return 0; 522 } 523