1 /* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * Init/reset quirks for USB host controllers should be in the 11 * USB quirks file, where their drivers can access reuse it. 12 */ 13 14 #include <linux/types.h> 15 #include <linux/kernel.h> 16 #include <linux/export.h> 17 #include <linux/pci.h> 18 #include <linux/init.h> 19 #include <linux/delay.h> 20 #include <linux/acpi.h> 21 #include <linux/kallsyms.h> 22 #include <linux/dmi.h> 23 #include <linux/pci-aspm.h> 24 #include <linux/ioport.h> 25 #include <linux/sched.h> 26 #include <linux/ktime.h> 27 #include <linux/mm.h> 28 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 29 #include "pci.h" 30 31 /* 32 * Decoding should be disabled for a PCI device during BAR sizing to avoid 33 * conflict. But doing so may cause problems on host bridge and perhaps other 34 * key system devices. For devices that need to have mmio decoding always-on, 35 * we need to set the dev->mmio_always_on bit. 36 */ 37 static void quirk_mmio_always_on(struct pci_dev *dev) 38 { 39 dev->mmio_always_on = 1; 40 } 41 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 42 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 43 44 /* The Mellanox Tavor device gives false positive parity errors 45 * Mark this device with a broken_parity_status, to allow 46 * PCI scanning code to "skip" this now blacklisted device. 47 */ 48 static void quirk_mellanox_tavor(struct pci_dev *dev) 49 { 50 dev->broken_parity_status = 1; /* This device gives false positives */ 51 } 52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor); 53 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor); 54 55 /* Deal with broken BIOSes that neglect to enable passive release, 56 which can cause problems in combination with the 82441FX/PPro MTRRs */ 57 static void quirk_passive_release(struct pci_dev *dev) 58 { 59 struct pci_dev *d = NULL; 60 unsigned char dlc; 61 62 /* We have to make sure a particular bit is set in the PIIX3 63 ISA bridge, so we have to go out and find it. */ 64 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 65 pci_read_config_byte(d, 0x82, &dlc); 66 if (!(dlc & 1<<1)) { 67 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); 68 dlc |= 1<<1; 69 pci_write_config_byte(d, 0x82, dlc); 70 } 71 } 72 } 73 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 74 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 75 76 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 77 but VIA don't answer queries. If you happen to have good contacts at VIA 78 ask them for me please -- Alan 79 80 This appears to be BIOS not version dependent. So presumably there is a 81 chipset level fix */ 82 83 static void quirk_isa_dma_hangs(struct pci_dev *dev) 84 { 85 if (!isa_dma_bridge_buggy) { 86 isa_dma_bridge_buggy = 1; 87 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); 88 } 89 } 90 /* 91 * Its not totally clear which chipsets are the problematic ones 92 * We know 82C586 and 82C596 variants are affected. 93 */ 94 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 95 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 101 102 /* 103 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear 104 * for some HT machines to use C4 w/o hanging. 105 */ 106 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 107 { 108 u32 pmbase; 109 u16 pm1a; 110 111 pci_read_config_dword(dev, 0x40, &pmbase); 112 pmbase = pmbase & 0xff80; 113 pm1a = inw(pmbase); 114 115 if (pm1a & 0x10) { 116 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); 117 outw(0x10, pmbase); 118 } 119 } 120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 121 122 /* 123 * Chipsets where PCI->PCI transfers vanish or hang 124 */ 125 static void quirk_nopcipci(struct pci_dev *dev) 126 { 127 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 128 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); 129 pci_pci_problems |= PCIPCI_FAIL; 130 } 131 } 132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 134 135 static void quirk_nopciamd(struct pci_dev *dev) 136 { 137 u8 rev; 138 pci_read_config_byte(dev, 0x08, &rev); 139 if (rev == 0x13) { 140 /* Erratum 24 */ 141 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 142 pci_pci_problems |= PCIAGP_FAIL; 143 } 144 } 145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 146 147 /* 148 * Triton requires workarounds to be used by the drivers 149 */ 150 static void quirk_triton(struct pci_dev *dev) 151 { 152 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 153 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 154 pci_pci_problems |= PCIPCI_TRITON; 155 } 156 } 157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 161 162 /* 163 * VIA Apollo KT133 needs PCI latency patch 164 * Made according to a windows driver based patch by George E. Breese 165 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 166 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 167 * the info on which Mr Breese based his work. 168 * 169 * Updated based on further information from the site and also on 170 * information provided by VIA 171 */ 172 static void quirk_vialatency(struct pci_dev *dev) 173 { 174 struct pci_dev *p; 175 u8 busarb; 176 /* Ok we have a potential problem chipset here. Now see if we have 177 a buggy southbridge */ 178 179 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 180 if (p != NULL) { 181 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 182 /* Check for buggy part revisions */ 183 if (p->revision < 0x40 || p->revision > 0x42) 184 goto exit; 185 } else { 186 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 187 if (p == NULL) /* No problem parts */ 188 goto exit; 189 /* Check for buggy part revisions */ 190 if (p->revision < 0x10 || p->revision > 0x12) 191 goto exit; 192 } 193 194 /* 195 * Ok we have the problem. Now set the PCI master grant to 196 * occur every master grant. The apparent bug is that under high 197 * PCI load (quite common in Linux of course) you can get data 198 * loss when the CPU is held off the bus for 3 bus master requests 199 * This happens to include the IDE controllers.... 200 * 201 * VIA only apply this fix when an SB Live! is present but under 202 * both Linux and Windows this isn't enough, and we have seen 203 * corruption without SB Live! but with things like 3 UDMA IDE 204 * controllers. So we ignore that bit of the VIA recommendation.. 205 */ 206 207 pci_read_config_byte(dev, 0x76, &busarb); 208 /* Set bit 4 and bi 5 of byte 76 to 0x01 209 "Master priority rotation on every PCI master grant */ 210 busarb &= ~(1<<5); 211 busarb |= (1<<4); 212 pci_write_config_byte(dev, 0x76, busarb); 213 dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); 214 exit: 215 pci_dev_put(p); 216 } 217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 220 /* Must restore this on a resume from RAM */ 221 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 222 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 223 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 224 225 /* 226 * VIA Apollo VP3 needs ETBF on BT848/878 227 */ 228 static void quirk_viaetbf(struct pci_dev *dev) 229 { 230 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 231 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 232 pci_pci_problems |= PCIPCI_VIAETBF; 233 } 234 } 235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 236 237 static void quirk_vsfx(struct pci_dev *dev) 238 { 239 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 240 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 241 pci_pci_problems |= PCIPCI_VSFX; 242 } 243 } 244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 245 246 /* 247 * Ali Magik requires workarounds to be used by the drivers 248 * that DMA to AGP space. Latency must be set to 0xA and triton 249 * workaround applied too 250 * [Info kindly provided by ALi] 251 */ 252 static void quirk_alimagik(struct pci_dev *dev) 253 { 254 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 255 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 256 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 257 } 258 } 259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 261 262 /* 263 * Natoma has some interesting boundary conditions with Zoran stuff 264 * at least 265 */ 266 static void quirk_natoma(struct pci_dev *dev) 267 { 268 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 269 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 270 pci_pci_problems |= PCIPCI_NATOMA; 271 } 272 } 273 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 279 280 /* 281 * This chip can cause PCI parity errors if config register 0xA0 is read 282 * while DMAs are occurring. 283 */ 284 static void quirk_citrine(struct pci_dev *dev) 285 { 286 dev->cfg_size = 0xA0; 287 } 288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 289 290 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 291 static void quirk_extend_bar_to_page(struct pci_dev *dev) 292 { 293 int i; 294 295 for (i = 0; i < PCI_STD_RESOURCE_END; i++) { 296 struct resource *r = &dev->resource[i]; 297 298 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 299 r->end = PAGE_SIZE - 1; 300 r->start = 0; 301 r->flags |= IORESOURCE_UNSET; 302 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n", 303 i, r); 304 } 305 } 306 } 307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 308 309 /* 310 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 311 * If it's needed, re-allocate the region. 312 */ 313 static void quirk_s3_64M(struct pci_dev *dev) 314 { 315 struct resource *r = &dev->resource[0]; 316 317 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 318 r->flags |= IORESOURCE_UNSET; 319 r->start = 0; 320 r->end = 0x3ffffff; 321 } 322 } 323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 325 326 static void quirk_io(struct pci_dev *dev, int pos, unsigned size, 327 const char *name) 328 { 329 u32 region; 330 struct pci_bus_region bus_region; 331 struct resource *res = dev->resource + pos; 332 333 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 334 335 if (!region) 336 return; 337 338 res->name = pci_name(dev); 339 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 340 res->flags |= 341 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 342 region &= ~(size - 1); 343 344 /* Convert from PCI bus to resource space */ 345 bus_region.start = region; 346 bus_region.end = region + size - 1; 347 pcibios_bus_to_resource(dev->bus, res, &bus_region); 348 349 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", 350 name, PCI_BASE_ADDRESS_0 + (pos << 2), res); 351 } 352 353 /* 354 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 355 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 356 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 357 * (which conflicts w/ BAR1's memory range). 358 * 359 * CS553x's ISA PCI BARs may also be read-only (ref: 360 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 361 */ 362 static void quirk_cs5536_vsa(struct pci_dev *dev) 363 { 364 static char *name = "CS5536 ISA bridge"; 365 366 if (pci_resource_len(dev, 0) != 8) { 367 quirk_io(dev, 0, 8, name); /* SMB */ 368 quirk_io(dev, 1, 256, name); /* GPIO */ 369 quirk_io(dev, 2, 64, name); /* MFGPT */ 370 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n", 371 name); 372 } 373 } 374 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 375 376 static void quirk_io_region(struct pci_dev *dev, int port, 377 unsigned size, int nr, const char *name) 378 { 379 u16 region; 380 struct pci_bus_region bus_region; 381 struct resource *res = dev->resource + nr; 382 383 pci_read_config_word(dev, port, ®ion); 384 region &= ~(size - 1); 385 386 if (!region) 387 return; 388 389 res->name = pci_name(dev); 390 res->flags = IORESOURCE_IO; 391 392 /* Convert from PCI bus to resource space */ 393 bus_region.start = region; 394 bus_region.end = region + size - 1; 395 pcibios_bus_to_resource(dev->bus, res, &bus_region); 396 397 if (!pci_claim_resource(dev, nr)) 398 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name); 399 } 400 401 /* 402 * ATI Northbridge setups MCE the processor if you even 403 * read somewhere between 0x3b0->0x3bb or read 0x3d3 404 */ 405 static void quirk_ati_exploding_mce(struct pci_dev *dev) 406 { 407 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 408 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 409 request_region(0x3b0, 0x0C, "RadeonIGP"); 410 request_region(0x3d3, 0x01, "RadeonIGP"); 411 } 412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 413 414 /* 415 * In the AMD NL platform, this device ([1022:7912]) has a class code of 416 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 417 * claim it. 418 * But the dwc3 driver is a more specific driver for this device, and we'd 419 * prefer to use it instead of xhci. To prevent xhci from claiming the 420 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 421 * defines as "USB device (not host controller)". The dwc3 driver can then 422 * claim it based on its Vendor and Device ID. 423 */ 424 static void quirk_amd_nl_class(struct pci_dev *pdev) 425 { 426 u32 class = pdev->class; 427 428 /* Use "USB Device (not host controller)" class */ 429 pdev->class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe; 430 dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 431 class, pdev->class); 432 } 433 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 434 quirk_amd_nl_class); 435 436 /* 437 * Let's make the southbridge information explicit instead 438 * of having to worry about people probing the ACPI areas, 439 * for example.. (Yes, it happens, and if you read the wrong 440 * ACPI register it will put the machine to sleep with no 441 * way of waking it up again. Bummer). 442 * 443 * ALI M7101: Two IO regions pointed to by words at 444 * 0xE0 (64 bytes of ACPI registers) 445 * 0xE2 (32 bytes of SMB registers) 446 */ 447 static void quirk_ali7101_acpi(struct pci_dev *dev) 448 { 449 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 450 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 451 } 452 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 453 454 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 455 { 456 u32 devres; 457 u32 mask, size, base; 458 459 pci_read_config_dword(dev, port, &devres); 460 if ((devres & enable) != enable) 461 return; 462 mask = (devres >> 16) & 15; 463 base = devres & 0xffff; 464 size = 16; 465 for (;;) { 466 unsigned bit = size >> 1; 467 if ((bit & mask) == bit) 468 break; 469 size = bit; 470 } 471 /* 472 * For now we only print it out. Eventually we'll want to 473 * reserve it (at least if it's in the 0x1000+ range), but 474 * let's get enough confirmation reports first. 475 */ 476 base &= -size; 477 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, 478 base + size - 1); 479 } 480 481 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 482 { 483 u32 devres; 484 u32 mask, size, base; 485 486 pci_read_config_dword(dev, port, &devres); 487 if ((devres & enable) != enable) 488 return; 489 base = devres & 0xffff0000; 490 mask = (devres & 0x3f) << 16; 491 size = 128 << 16; 492 for (;;) { 493 unsigned bit = size >> 1; 494 if ((bit & mask) == bit) 495 break; 496 size = bit; 497 } 498 /* 499 * For now we only print it out. Eventually we'll want to 500 * reserve it, but let's get enough confirmation reports first. 501 */ 502 base &= -size; 503 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, 504 base + size - 1); 505 } 506 507 /* 508 * PIIX4 ACPI: Two IO regions pointed to by longwords at 509 * 0x40 (64 bytes of ACPI registers) 510 * 0x90 (16 bytes of SMB registers) 511 * and a few strange programmable PIIX4 device resources. 512 */ 513 static void quirk_piix4_acpi(struct pci_dev *dev) 514 { 515 u32 res_a; 516 517 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 518 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 519 520 /* Device resource A has enables for some of the other ones */ 521 pci_read_config_dword(dev, 0x5c, &res_a); 522 523 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 524 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 525 526 /* Device resource D is just bitfields for static resources */ 527 528 /* Device 12 enabled? */ 529 if (res_a & (1 << 29)) { 530 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 531 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 532 } 533 /* Device 13 enabled? */ 534 if (res_a & (1 << 30)) { 535 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 536 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 537 } 538 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 539 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 540 } 541 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 542 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 543 544 #define ICH_PMBASE 0x40 545 #define ICH_ACPI_CNTL 0x44 546 #define ICH4_ACPI_EN 0x10 547 #define ICH6_ACPI_EN 0x80 548 #define ICH4_GPIOBASE 0x58 549 #define ICH4_GPIO_CNTL 0x5c 550 #define ICH4_GPIO_EN 0x10 551 #define ICH6_GPIOBASE 0x48 552 #define ICH6_GPIO_CNTL 0x4c 553 #define ICH6_GPIO_EN 0x10 554 555 /* 556 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 557 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 558 * 0x58 (64 bytes of GPIO I/O space) 559 */ 560 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 561 { 562 u8 enable; 563 564 /* 565 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 566 * with low legacy (and fixed) ports. We don't know the decoding 567 * priority and can't tell whether the legacy device or the one created 568 * here is really at that address. This happens on boards with broken 569 * BIOSes. 570 */ 571 572 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 573 if (enable & ICH4_ACPI_EN) 574 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 575 "ICH4 ACPI/GPIO/TCO"); 576 577 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 578 if (enable & ICH4_GPIO_EN) 579 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 580 "ICH4 GPIO"); 581 } 582 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 583 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 584 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 585 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 586 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 587 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 588 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 589 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 590 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 591 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 592 593 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 594 { 595 u8 enable; 596 597 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 598 if (enable & ICH6_ACPI_EN) 599 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 600 "ICH6 ACPI/GPIO/TCO"); 601 602 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 603 if (enable & ICH6_GPIO_EN) 604 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 605 "ICH6 GPIO"); 606 } 607 608 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) 609 { 610 u32 val; 611 u32 size, base; 612 613 pci_read_config_dword(dev, reg, &val); 614 615 /* Enabled? */ 616 if (!(val & 1)) 617 return; 618 base = val & 0xfffc; 619 if (dynsize) { 620 /* 621 * This is not correct. It is 16, 32 or 64 bytes depending on 622 * register D31:F0:ADh bits 5:4. 623 * 624 * But this gets us at least _part_ of it. 625 */ 626 size = 16; 627 } else { 628 size = 128; 629 } 630 base &= ~(size-1); 631 632 /* Just print it out for now. We should reserve it after more debugging */ 633 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 634 } 635 636 static void quirk_ich6_lpc(struct pci_dev *dev) 637 { 638 /* Shared ACPI/GPIO decode with all ICH6+ */ 639 ich6_lpc_acpi_gpio(dev); 640 641 /* ICH6-specific generic IO decode */ 642 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 643 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 644 } 645 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 646 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 647 648 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) 649 { 650 u32 val; 651 u32 mask, base; 652 653 pci_read_config_dword(dev, reg, &val); 654 655 /* Enabled? */ 656 if (!(val & 1)) 657 return; 658 659 /* 660 * IO base in bits 15:2, mask in bits 23:18, both 661 * are dword-based 662 */ 663 base = val & 0xfffc; 664 mask = (val >> 16) & 0xfc; 665 mask |= 3; 666 667 /* Just print it out for now. We should reserve it after more debugging */ 668 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 669 } 670 671 /* ICH7-10 has the same common LPC generic IO decode registers */ 672 static void quirk_ich7_lpc(struct pci_dev *dev) 673 { 674 /* We share the common ACPI/GPIO decode with ICH6 */ 675 ich6_lpc_acpi_gpio(dev); 676 677 /* And have 4 ICH7+ generic decodes */ 678 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 679 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 680 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 681 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 682 } 683 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 684 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 685 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 686 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 687 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 688 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 689 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 690 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 691 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 692 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 693 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 694 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 695 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 696 697 /* 698 * VIA ACPI: One IO region pointed to by longword at 699 * 0x48 or 0x20 (256 bytes of ACPI registers) 700 */ 701 static void quirk_vt82c586_acpi(struct pci_dev *dev) 702 { 703 if (dev->revision & 0x10) 704 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 705 "vt82c586 ACPI"); 706 } 707 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 708 709 /* 710 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 711 * 0x48 (256 bytes of ACPI registers) 712 * 0x70 (128 bytes of hardware monitoring register) 713 * 0x90 (16 bytes of SMB registers) 714 */ 715 static void quirk_vt82c686_acpi(struct pci_dev *dev) 716 { 717 quirk_vt82c586_acpi(dev); 718 719 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 720 "vt82c686 HW-mon"); 721 722 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 723 } 724 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 725 726 /* 727 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 728 * 0x88 (128 bytes of power management registers) 729 * 0xd0 (16 bytes of SMB registers) 730 */ 731 static void quirk_vt8235_acpi(struct pci_dev *dev) 732 { 733 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 734 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 735 } 736 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 737 738 /* 739 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: 740 * Disable fast back-to-back on the secondary bus segment 741 */ 742 static void quirk_xio2000a(struct pci_dev *dev) 743 { 744 struct pci_dev *pdev; 745 u16 command; 746 747 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 748 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 749 pci_read_config_word(pdev, PCI_COMMAND, &command); 750 if (command & PCI_COMMAND_FAST_BACK) 751 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 752 } 753 } 754 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 755 quirk_xio2000a); 756 757 #ifdef CONFIG_X86_IO_APIC 758 759 #include <asm/io_apic.h> 760 761 /* 762 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 763 * devices to the external APIC. 764 * 765 * TODO: When we have device-specific interrupt routers, 766 * this code will go away from quirks. 767 */ 768 static void quirk_via_ioapic(struct pci_dev *dev) 769 { 770 u8 tmp; 771 772 if (nr_ioapics < 1) 773 tmp = 0; /* nothing routed to external APIC */ 774 else 775 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 776 777 dev_info(&dev->dev, "%sbling VIA external APIC routing\n", 778 tmp == 0 ? "Disa" : "Ena"); 779 780 /* Offset 0x58: External APIC IRQ output control */ 781 pci_write_config_byte(dev, 0x58, tmp); 782 } 783 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 784 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 785 786 /* 787 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 788 * This leads to doubled level interrupt rates. 789 * Set this bit to get rid of cycle wastage. 790 * Otherwise uncritical. 791 */ 792 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 793 { 794 u8 misc_control2; 795 #define BYPASS_APIC_DEASSERT 8 796 797 pci_read_config_byte(dev, 0x5B, &misc_control2); 798 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 799 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 800 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 801 } 802 } 803 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 804 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 805 806 /* 807 * The AMD io apic can hang the box when an apic irq is masked. 808 * We check all revs >= B0 (yet not in the pre production!) as the bug 809 * is currently marked NoFix 810 * 811 * We have multiple reports of hangs with this chipset that went away with 812 * noapic specified. For the moment we assume it's the erratum. We may be wrong 813 * of course. However the advice is demonstrably good even if so.. 814 */ 815 static void quirk_amd_ioapic(struct pci_dev *dev) 816 { 817 if (dev->revision >= 0x02) { 818 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 819 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); 820 } 821 } 822 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 823 #endif /* CONFIG_X86_IO_APIC */ 824 825 /* 826 * Some settings of MMRBC can lead to data corruption so block changes. 827 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 828 */ 829 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 830 { 831 if (dev->subordinate && dev->revision <= 0x12) { 832 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 833 dev->revision); 834 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 835 } 836 } 837 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 838 839 /* 840 * FIXME: it is questionable that quirk_via_acpi 841 * is needed. It shows up as an ISA bridge, and does not 842 * support the PCI_INTERRUPT_LINE register at all. Therefore 843 * it seems like setting the pci_dev's 'irq' to the 844 * value of the ACPI SCI interrupt is only done for convenience. 845 * -jgarzik 846 */ 847 static void quirk_via_acpi(struct pci_dev *d) 848 { 849 /* 850 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 851 */ 852 u8 irq; 853 pci_read_config_byte(d, 0x42, &irq); 854 irq &= 0xf; 855 if (irq && (irq != 2)) 856 d->irq = irq; 857 } 858 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 859 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 860 861 862 /* 863 * VIA bridges which have VLink 864 */ 865 866 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 867 868 static void quirk_via_bridge(struct pci_dev *dev) 869 { 870 /* See what bridge we have and find the device ranges */ 871 switch (dev->device) { 872 case PCI_DEVICE_ID_VIA_82C686: 873 /* The VT82C686 is special, it attaches to PCI and can have 874 any device number. All its subdevices are functions of 875 that single device. */ 876 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 877 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 878 break; 879 case PCI_DEVICE_ID_VIA_8237: 880 case PCI_DEVICE_ID_VIA_8237A: 881 via_vlink_dev_lo = 15; 882 break; 883 case PCI_DEVICE_ID_VIA_8235: 884 via_vlink_dev_lo = 16; 885 break; 886 case PCI_DEVICE_ID_VIA_8231: 887 case PCI_DEVICE_ID_VIA_8233_0: 888 case PCI_DEVICE_ID_VIA_8233A: 889 case PCI_DEVICE_ID_VIA_8233C_0: 890 via_vlink_dev_lo = 17; 891 break; 892 } 893 } 894 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 896 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 897 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 898 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 902 903 /** 904 * quirk_via_vlink - VIA VLink IRQ number update 905 * @dev: PCI device 906 * 907 * If the device we are dealing with is on a PIC IRQ we need to 908 * ensure that the IRQ line register which usually is not relevant 909 * for PCI cards, is actually written so that interrupts get sent 910 * to the right place. 911 * We only do this on systems where a VIA south bridge was detected, 912 * and only for VIA devices on the motherboard (see quirk_via_bridge 913 * above). 914 */ 915 916 static void quirk_via_vlink(struct pci_dev *dev) 917 { 918 u8 irq, new_irq; 919 920 /* Check if we have VLink at all */ 921 if (via_vlink_dev_lo == -1) 922 return; 923 924 new_irq = dev->irq; 925 926 /* Don't quirk interrupts outside the legacy IRQ range */ 927 if (!new_irq || new_irq > 15) 928 return; 929 930 /* Internal device ? */ 931 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 932 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 933 return; 934 935 /* This is an internal VLink device on a PIC interrupt. The BIOS 936 ought to have set this but may not have, so we redo it */ 937 938 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 939 if (new_irq != irq) { 940 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", 941 irq, new_irq); 942 udelay(15); /* unknown if delay really needed */ 943 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 944 } 945 } 946 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 947 948 /* 949 * VIA VT82C598 has its device ID settable and many BIOSes 950 * set it to the ID of VT82C597 for backward compatibility. 951 * We need to switch it off to be able to recognize the real 952 * type of the chip. 953 */ 954 static void quirk_vt82c598_id(struct pci_dev *dev) 955 { 956 pci_write_config_byte(dev, 0xfc, 0); 957 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 958 } 959 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 960 961 /* 962 * CardBus controllers have a legacy base address that enables them 963 * to respond as i82365 pcmcia controllers. We don't want them to 964 * do this even if the Linux CardBus driver is not loaded, because 965 * the Linux i82365 driver does not (and should not) handle CardBus. 966 */ 967 static void quirk_cardbus_legacy(struct pci_dev *dev) 968 { 969 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 970 } 971 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 972 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 973 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 974 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 975 976 /* 977 * Following the PCI ordering rules is optional on the AMD762. I'm not 978 * sure what the designers were smoking but let's not inhale... 979 * 980 * To be fair to AMD, it follows the spec by default, its BIOS people 981 * who turn it off! 982 */ 983 static void quirk_amd_ordering(struct pci_dev *dev) 984 { 985 u32 pcic; 986 pci_read_config_dword(dev, 0x4C, &pcic); 987 if ((pcic & 6) != 6) { 988 pcic |= 6; 989 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 990 pci_write_config_dword(dev, 0x4C, pcic); 991 pci_read_config_dword(dev, 0x84, &pcic); 992 pcic |= (1 << 23); /* Required in this mode */ 993 pci_write_config_dword(dev, 0x84, pcic); 994 } 995 } 996 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 997 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 998 999 /* 1000 * DreamWorks provided workaround for Dunord I-3000 problem 1001 * 1002 * This card decodes and responds to addresses not apparently 1003 * assigned to it. We force a larger allocation to ensure that 1004 * nothing gets put too close to it. 1005 */ 1006 static void quirk_dunord(struct pci_dev *dev) 1007 { 1008 struct resource *r = &dev->resource[1]; 1009 1010 r->flags |= IORESOURCE_UNSET; 1011 r->start = 0; 1012 r->end = 0xffffff; 1013 } 1014 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1015 1016 /* 1017 * i82380FB mobile docking controller: its PCI-to-PCI bridge 1018 * is subtractive decoding (transparent), and does indicate this 1019 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 1020 * instead of 0x01. 1021 */ 1022 static void quirk_transparent_bridge(struct pci_dev *dev) 1023 { 1024 dev->transparent = 1; 1025 } 1026 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1027 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1028 1029 /* 1030 * Common misconfiguration of the MediaGX/Geode PCI master that will 1031 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 1032 * datasheets found at http://www.national.com/analog for info on what 1033 * these bits do. <christer@weinigel.se> 1034 */ 1035 static void quirk_mediagx_master(struct pci_dev *dev) 1036 { 1037 u8 reg; 1038 1039 pci_read_config_byte(dev, 0x41, ®); 1040 if (reg & 2) { 1041 reg &= ~2; 1042 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1043 reg); 1044 pci_write_config_byte(dev, 0x41, reg); 1045 } 1046 } 1047 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1048 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1049 1050 /* 1051 * Ensure C0 rev restreaming is off. This is normally done by 1052 * the BIOS but in the odd case it is not the results are corruption 1053 * hence the presence of a Linux check 1054 */ 1055 static void quirk_disable_pxb(struct pci_dev *pdev) 1056 { 1057 u16 config; 1058 1059 if (pdev->revision != 0x04) /* Only C0 requires this */ 1060 return; 1061 pci_read_config_word(pdev, 0x40, &config); 1062 if (config & (1<<6)) { 1063 config &= ~(1<<6); 1064 pci_write_config_word(pdev, 0x40, config); 1065 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1066 } 1067 } 1068 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1069 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1070 1071 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1072 { 1073 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1074 u8 tmp; 1075 1076 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1077 if (tmp == 0x01) { 1078 pci_read_config_byte(pdev, 0x40, &tmp); 1079 pci_write_config_byte(pdev, 0x40, tmp|1); 1080 pci_write_config_byte(pdev, 0x9, 1); 1081 pci_write_config_byte(pdev, 0xa, 6); 1082 pci_write_config_byte(pdev, 0x40, tmp); 1083 1084 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1085 dev_info(&pdev->dev, "set SATA to AHCI mode\n"); 1086 } 1087 } 1088 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1089 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1090 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1091 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1093 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1094 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1095 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1096 1097 /* 1098 * Serverworks CSB5 IDE does not fully support native mode 1099 */ 1100 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1101 { 1102 u8 prog; 1103 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1104 if (prog & 5) { 1105 prog &= ~5; 1106 pdev->class &= ~5; 1107 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1108 /* PCI layer will sort out resources */ 1109 } 1110 } 1111 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1112 1113 /* 1114 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 1115 */ 1116 static void quirk_ide_samemode(struct pci_dev *pdev) 1117 { 1118 u8 prog; 1119 1120 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1121 1122 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1123 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); 1124 prog &= ~5; 1125 pdev->class &= ~5; 1126 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1127 } 1128 } 1129 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1130 1131 /* 1132 * Some ATA devices break if put into D3 1133 */ 1134 1135 static void quirk_no_ata_d3(struct pci_dev *pdev) 1136 { 1137 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1138 } 1139 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1140 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1141 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1142 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1143 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1144 /* ALi loses some register settings that we cannot then restore */ 1145 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1146 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1147 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1148 occur when mode detecting */ 1149 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1150 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1151 1152 /* This was originally an Alpha specific thing, but it really fits here. 1153 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1154 */ 1155 static void quirk_eisa_bridge(struct pci_dev *dev) 1156 { 1157 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1158 } 1159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1160 1161 1162 /* 1163 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1164 * is not activated. The myth is that Asus said that they do not want the 1165 * users to be irritated by just another PCI Device in the Win98 device 1166 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1167 * package 2.7.0 for details) 1168 * 1169 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1170 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1171 * becomes necessary to do this tweak in two steps -- the chosen trigger 1172 * is either the Host bridge (preferred) or on-board VGA controller. 1173 * 1174 * Note that we used to unhide the SMBus that way on Toshiba laptops 1175 * (Satellite A40 and Tecra M2) but then found that the thermal management 1176 * was done by SMM code, which could cause unsynchronized concurrent 1177 * accesses to the SMBus registers, with potentially bad effects. Thus you 1178 * should be very careful when adding new entries: if SMM is accessing the 1179 * Intel SMBus, this is a very good reason to leave it hidden. 1180 * 1181 * Likewise, many recent laptops use ACPI for thermal management. If the 1182 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1183 * natively, and keeping the SMBus hidden is the right thing to do. If you 1184 * are about to add an entry in the table below, please first disassemble 1185 * the DSDT and double-check that there is no code accessing the SMBus. 1186 */ 1187 static int asus_hides_smbus; 1188 1189 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1190 { 1191 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1192 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1193 switch (dev->subsystem_device) { 1194 case 0x8025: /* P4B-LX */ 1195 case 0x8070: /* P4B */ 1196 case 0x8088: /* P4B533 */ 1197 case 0x1626: /* L3C notebook */ 1198 asus_hides_smbus = 1; 1199 } 1200 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1201 switch (dev->subsystem_device) { 1202 case 0x80b1: /* P4GE-V */ 1203 case 0x80b2: /* P4PE */ 1204 case 0x8093: /* P4B533-V */ 1205 asus_hides_smbus = 1; 1206 } 1207 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1208 switch (dev->subsystem_device) { 1209 case 0x8030: /* P4T533 */ 1210 asus_hides_smbus = 1; 1211 } 1212 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1213 switch (dev->subsystem_device) { 1214 case 0x8070: /* P4G8X Deluxe */ 1215 asus_hides_smbus = 1; 1216 } 1217 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1218 switch (dev->subsystem_device) { 1219 case 0x80c9: /* PU-DLS */ 1220 asus_hides_smbus = 1; 1221 } 1222 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1223 switch (dev->subsystem_device) { 1224 case 0x1751: /* M2N notebook */ 1225 case 0x1821: /* M5N notebook */ 1226 case 0x1897: /* A6L notebook */ 1227 asus_hides_smbus = 1; 1228 } 1229 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1230 switch (dev->subsystem_device) { 1231 case 0x184b: /* W1N notebook */ 1232 case 0x186a: /* M6Ne notebook */ 1233 asus_hides_smbus = 1; 1234 } 1235 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1236 switch (dev->subsystem_device) { 1237 case 0x80f2: /* P4P800-X */ 1238 asus_hides_smbus = 1; 1239 } 1240 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1241 switch (dev->subsystem_device) { 1242 case 0x1882: /* M6V notebook */ 1243 case 0x1977: /* A6VA notebook */ 1244 asus_hides_smbus = 1; 1245 } 1246 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1247 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1248 switch (dev->subsystem_device) { 1249 case 0x088C: /* HP Compaq nc8000 */ 1250 case 0x0890: /* HP Compaq nc6000 */ 1251 asus_hides_smbus = 1; 1252 } 1253 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1254 switch (dev->subsystem_device) { 1255 case 0x12bc: /* HP D330L */ 1256 case 0x12bd: /* HP D530 */ 1257 case 0x006a: /* HP Compaq nx9500 */ 1258 asus_hides_smbus = 1; 1259 } 1260 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1261 switch (dev->subsystem_device) { 1262 case 0x12bf: /* HP xw4100 */ 1263 asus_hides_smbus = 1; 1264 } 1265 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1266 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1267 switch (dev->subsystem_device) { 1268 case 0xC00C: /* Samsung P35 notebook */ 1269 asus_hides_smbus = 1; 1270 } 1271 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1272 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1273 switch (dev->subsystem_device) { 1274 case 0x0058: /* Compaq Evo N620c */ 1275 asus_hides_smbus = 1; 1276 } 1277 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1278 switch (dev->subsystem_device) { 1279 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1280 /* Motherboard doesn't have Host bridge 1281 * subvendor/subdevice IDs, therefore checking 1282 * its on-board VGA controller */ 1283 asus_hides_smbus = 1; 1284 } 1285 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1286 switch (dev->subsystem_device) { 1287 case 0x00b8: /* Compaq Evo D510 CMT */ 1288 case 0x00b9: /* Compaq Evo D510 SFF */ 1289 case 0x00ba: /* Compaq Evo D510 USDT */ 1290 /* Motherboard doesn't have Host bridge 1291 * subvendor/subdevice IDs and on-board VGA 1292 * controller is disabled if an AGP card is 1293 * inserted, therefore checking USB UHCI 1294 * Controller #1 */ 1295 asus_hides_smbus = 1; 1296 } 1297 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1298 switch (dev->subsystem_device) { 1299 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1300 /* Motherboard doesn't have host bridge 1301 * subvendor/subdevice IDs, therefore checking 1302 * its on-board VGA controller */ 1303 asus_hides_smbus = 1; 1304 } 1305 } 1306 } 1307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1309 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1310 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1311 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1312 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1316 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1317 1318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1321 1322 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1323 { 1324 u16 val; 1325 1326 if (likely(!asus_hides_smbus)) 1327 return; 1328 1329 pci_read_config_word(dev, 0xF2, &val); 1330 if (val & 0x8) { 1331 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1332 pci_read_config_word(dev, 0xF2, &val); 1333 if (val & 0x8) 1334 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1335 val); 1336 else 1337 dev_info(&dev->dev, "Enabled i801 SMBus device\n"); 1338 } 1339 } 1340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1342 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1343 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1345 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1347 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1348 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1349 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1350 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1351 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1352 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1353 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1354 1355 /* It appears we just have one such device. If not, we have a warning */ 1356 static void __iomem *asus_rcba_base; 1357 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1358 { 1359 u32 rcba; 1360 1361 if (likely(!asus_hides_smbus)) 1362 return; 1363 WARN_ON(asus_rcba_base); 1364 1365 pci_read_config_dword(dev, 0xF0, &rcba); 1366 /* use bits 31:14, 16 kB aligned */ 1367 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); 1368 if (asus_rcba_base == NULL) 1369 return; 1370 } 1371 1372 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1373 { 1374 u32 val; 1375 1376 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1377 return; 1378 /* read the Function Disable register, dword mode only */ 1379 val = readl(asus_rcba_base + 0x3418); 1380 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ 1381 } 1382 1383 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1384 { 1385 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1386 return; 1387 iounmap(asus_rcba_base); 1388 asus_rcba_base = NULL; 1389 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); 1390 } 1391 1392 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1393 { 1394 asus_hides_smbus_lpc_ich6_suspend(dev); 1395 asus_hides_smbus_lpc_ich6_resume_early(dev); 1396 asus_hides_smbus_lpc_ich6_resume(dev); 1397 } 1398 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1399 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1400 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1401 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1402 1403 /* 1404 * SiS 96x south bridge: BIOS typically hides SMBus device... 1405 */ 1406 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1407 { 1408 u8 val = 0; 1409 pci_read_config_byte(dev, 0x77, &val); 1410 if (val & 0x10) { 1411 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); 1412 pci_write_config_byte(dev, 0x77, val & ~0x10); 1413 } 1414 } 1415 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1416 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1417 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1418 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1419 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1420 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1421 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1422 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1423 1424 /* 1425 * ... This is further complicated by the fact that some SiS96x south 1426 * bridges pretend to be 85C503/5513 instead. In that case see if we 1427 * spotted a compatible north bridge to make sure. 1428 * (pci_find_device doesn't work yet) 1429 * 1430 * We can also enable the sis96x bit in the discovery register.. 1431 */ 1432 #define SIS_DETECT_REGISTER 0x40 1433 1434 static void quirk_sis_503(struct pci_dev *dev) 1435 { 1436 u8 reg; 1437 u16 devid; 1438 1439 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1440 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1441 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1442 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1443 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1444 return; 1445 } 1446 1447 /* 1448 * Ok, it now shows up as a 96x.. run the 96x quirk by 1449 * hand in case it has already been processed. 1450 * (depends on link order, which is apparently not guaranteed) 1451 */ 1452 dev->device = devid; 1453 quirk_sis_96x_smbus(dev); 1454 } 1455 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1456 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1457 1458 1459 /* 1460 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1461 * and MC97 modem controller are disabled when a second PCI soundcard is 1462 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1463 * -- bjd 1464 */ 1465 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1466 { 1467 u8 val; 1468 int asus_hides_ac97 = 0; 1469 1470 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1471 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1472 asus_hides_ac97 = 1; 1473 } 1474 1475 if (!asus_hides_ac97) 1476 return; 1477 1478 pci_read_config_byte(dev, 0x50, &val); 1479 if (val & 0xc0) { 1480 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1481 pci_read_config_byte(dev, 0x50, &val); 1482 if (val & 0xc0) 1483 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1484 val); 1485 else 1486 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); 1487 } 1488 } 1489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1490 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1491 1492 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1493 1494 /* 1495 * If we are using libata we can drive this chip properly but must 1496 * do this early on to make the additional device appear during 1497 * the PCI scanning. 1498 */ 1499 static void quirk_jmicron_ata(struct pci_dev *pdev) 1500 { 1501 u32 conf1, conf5, class; 1502 u8 hdr; 1503 1504 /* Only poke fn 0 */ 1505 if (PCI_FUNC(pdev->devfn)) 1506 return; 1507 1508 pci_read_config_dword(pdev, 0x40, &conf1); 1509 pci_read_config_dword(pdev, 0x80, &conf5); 1510 1511 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1512 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1513 1514 switch (pdev->device) { 1515 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1516 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1517 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1518 /* The controller should be in single function ahci mode */ 1519 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1520 break; 1521 1522 case PCI_DEVICE_ID_JMICRON_JMB365: 1523 case PCI_DEVICE_ID_JMICRON_JMB366: 1524 /* Redirect IDE second PATA port to the right spot */ 1525 conf5 |= (1 << 24); 1526 /* Fall through */ 1527 case PCI_DEVICE_ID_JMICRON_JMB361: 1528 case PCI_DEVICE_ID_JMICRON_JMB363: 1529 case PCI_DEVICE_ID_JMICRON_JMB369: 1530 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1531 /* Set the class codes correctly and then direct IDE 0 */ 1532 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1533 break; 1534 1535 case PCI_DEVICE_ID_JMICRON_JMB368: 1536 /* The controller should be in single function IDE mode */ 1537 conf1 |= 0x00C00000; /* Set 22, 23 */ 1538 break; 1539 } 1540 1541 pci_write_config_dword(pdev, 0x40, conf1); 1542 pci_write_config_dword(pdev, 0x80, conf5); 1543 1544 /* Update pdev accordingly */ 1545 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1546 pdev->hdr_type = hdr & 0x7f; 1547 pdev->multifunction = !!(hdr & 0x80); 1548 1549 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1550 pdev->class = class >> 8; 1551 } 1552 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1553 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1554 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1555 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1556 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1557 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1558 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1559 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1560 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1561 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1562 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1563 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1564 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1565 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1566 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1567 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1568 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1569 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1570 1571 #endif 1572 1573 static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1574 { 1575 if (dev->multifunction) { 1576 device_disable_async_suspend(&dev->dev); 1577 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1578 } 1579 } 1580 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1581 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1582 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1583 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1584 1585 #ifdef CONFIG_X86_IO_APIC 1586 static void quirk_alder_ioapic(struct pci_dev *pdev) 1587 { 1588 int i; 1589 1590 if ((pdev->class >> 8) != 0xff00) 1591 return; 1592 1593 /* the first BAR is the location of the IO APIC...we must 1594 * not touch this (and it's already covered by the fixmap), so 1595 * forcibly insert it into the resource tree */ 1596 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1597 insert_resource(&iomem_resource, &pdev->resource[0]); 1598 1599 /* The next five BARs all seem to be rubbish, so just clean 1600 * them out */ 1601 for (i = 1; i < 6; i++) 1602 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1603 } 1604 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1605 #endif 1606 1607 static void quirk_pcie_mch(struct pci_dev *pdev) 1608 { 1609 pdev->no_msi = 1; 1610 } 1611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1612 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1613 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1614 1615 1616 /* 1617 * It's possible for the MSI to get corrupted if shpc and acpi 1618 * are used together on certain PXH-based systems. 1619 */ 1620 static void quirk_pcie_pxh(struct pci_dev *dev) 1621 { 1622 dev->no_msi = 1; 1623 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1624 } 1625 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1626 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1627 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1628 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1629 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1630 1631 /* 1632 * Some Intel PCI Express chipsets have trouble with downstream 1633 * device power management. 1634 */ 1635 static void quirk_intel_pcie_pm(struct pci_dev *dev) 1636 { 1637 pci_pm_d3_delay = 120; 1638 dev->no_d1d2 = 1; 1639 } 1640 1641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1644 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1645 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1646 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1647 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1648 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1651 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1653 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1655 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1656 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1657 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1658 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1659 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1660 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1661 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1662 1663 #ifdef CONFIG_X86_IO_APIC 1664 /* 1665 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1666 * remap the original interrupt in the linux kernel to the boot interrupt, so 1667 * that a PCI device's interrupt handler is installed on the boot interrupt 1668 * line instead. 1669 */ 1670 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 1671 { 1672 if (noioapicquirk || noioapicreroute) 1673 return; 1674 1675 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 1676 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n", 1677 dev->vendor, dev->device); 1678 } 1679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1686 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1687 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1688 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1689 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1690 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1691 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1692 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1693 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1694 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1695 1696 /* 1697 * On some chipsets we can disable the generation of legacy INTx boot 1698 * interrupts. 1699 */ 1700 1701 /* 1702 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no 1703 * 300641-004US, section 5.7.3. 1704 */ 1705 #define INTEL_6300_IOAPIC_ABAR 0x40 1706 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 1707 1708 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 1709 { 1710 u16 pci_config_word; 1711 1712 if (noioapicquirk) 1713 return; 1714 1715 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); 1716 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 1717 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); 1718 1719 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1720 dev->vendor, dev->device); 1721 } 1722 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1723 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1724 1725 /* 1726 * disable boot interrupts on HT-1000 1727 */ 1728 #define BC_HT1000_FEATURE_REG 0x64 1729 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 1730 #define BC_HT1000_MAP_IDX 0xC00 1731 #define BC_HT1000_MAP_DATA 0xC01 1732 1733 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 1734 { 1735 u32 pci_config_dword; 1736 u8 irq; 1737 1738 if (noioapicquirk) 1739 return; 1740 1741 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 1742 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 1743 BC_HT1000_PIC_REGS_ENABLE); 1744 1745 for (irq = 0x10; irq < 0x10 + 32; irq++) { 1746 outb(irq, BC_HT1000_MAP_IDX); 1747 outb(0x00, BC_HT1000_MAP_DATA); 1748 } 1749 1750 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 1751 1752 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1753 dev->vendor, dev->device); 1754 } 1755 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1756 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1757 1758 /* 1759 * disable boot interrupts on AMD and ATI chipsets 1760 */ 1761 /* 1762 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 1763 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 1764 * (due to an erratum). 1765 */ 1766 #define AMD_813X_MISC 0x40 1767 #define AMD_813X_NOIOAMODE (1<<0) 1768 #define AMD_813X_REV_B1 0x12 1769 #define AMD_813X_REV_B2 0x13 1770 1771 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 1772 { 1773 u32 pci_config_dword; 1774 1775 if (noioapicquirk) 1776 return; 1777 if ((dev->revision == AMD_813X_REV_B1) || 1778 (dev->revision == AMD_813X_REV_B2)) 1779 return; 1780 1781 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 1782 pci_config_dword &= ~AMD_813X_NOIOAMODE; 1783 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 1784 1785 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1786 dev->vendor, dev->device); 1787 } 1788 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1789 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1790 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1791 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1792 1793 #define AMD_8111_PCI_IRQ_ROUTING 0x56 1794 1795 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 1796 { 1797 u16 pci_config_word; 1798 1799 if (noioapicquirk) 1800 return; 1801 1802 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 1803 if (!pci_config_word) { 1804 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n", 1805 dev->vendor, dev->device); 1806 return; 1807 } 1808 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 1809 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1810 dev->vendor, dev->device); 1811 } 1812 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1813 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1814 #endif /* CONFIG_X86_IO_APIC */ 1815 1816 /* 1817 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 1818 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 1819 * Re-allocate the region if needed... 1820 */ 1821 static void quirk_tc86c001_ide(struct pci_dev *dev) 1822 { 1823 struct resource *r = &dev->resource[0]; 1824 1825 if (r->start & 0x8) { 1826 r->flags |= IORESOURCE_UNSET; 1827 r->start = 0; 1828 r->end = 0xf; 1829 } 1830 } 1831 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 1832 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 1833 quirk_tc86c001_ide); 1834 1835 /* 1836 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the 1837 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 1838 * being read correctly if bit 7 of the base address is set. 1839 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 1840 * Re-allocate the regions to a 256-byte boundary if necessary. 1841 */ 1842 static void quirk_plx_pci9050(struct pci_dev *dev) 1843 { 1844 unsigned int bar; 1845 1846 /* Fixed in revision 2 (PCI 9052). */ 1847 if (dev->revision >= 2) 1848 return; 1849 for (bar = 0; bar <= 1; bar++) 1850 if (pci_resource_len(dev, bar) == 0x80 && 1851 (pci_resource_start(dev, bar) & 0x80)) { 1852 struct resource *r = &dev->resource[bar]; 1853 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 1854 bar); 1855 r->flags |= IORESOURCE_UNSET; 1856 r->start = 0; 1857 r->end = 0xff; 1858 } 1859 } 1860 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 1861 quirk_plx_pci9050); 1862 /* 1863 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 1864 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 1865 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 1866 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 1867 * 1868 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 1869 * driver. 1870 */ 1871 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 1872 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 1873 1874 static void quirk_netmos(struct pci_dev *dev) 1875 { 1876 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1877 unsigned int num_serial = dev->subsystem_device & 0xf; 1878 1879 /* 1880 * These Netmos parts are multiport serial devices with optional 1881 * parallel ports. Even when parallel ports are present, they 1882 * are identified as class SERIAL, which means the serial driver 1883 * will claim them. To prevent this, mark them as class OTHER. 1884 * These combo devices should be claimed by parport_serial. 1885 * 1886 * The subdevice ID is of the form 0x00PS, where <P> is the number 1887 * of parallel ports and <S> is the number of serial ports. 1888 */ 1889 switch (dev->device) { 1890 case PCI_DEVICE_ID_NETMOS_9835: 1891 /* Well, this rule doesn't hold for the following 9835 device */ 1892 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 1893 dev->subsystem_device == 0x0299) 1894 return; 1895 case PCI_DEVICE_ID_NETMOS_9735: 1896 case PCI_DEVICE_ID_NETMOS_9745: 1897 case PCI_DEVICE_ID_NETMOS_9845: 1898 case PCI_DEVICE_ID_NETMOS_9855: 1899 if (num_parallel) { 1900 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 1901 dev->device, num_parallel, num_serial); 1902 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1903 (dev->class & 0xff); 1904 } 1905 } 1906 } 1907 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 1908 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 1909 1910 static void quirk_f0_vpd_link(struct pci_dev *dev) 1911 { 1912 if (!dev->multifunction || !PCI_FUNC(dev->devfn)) 1913 return; 1914 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0; 1915 } 1916 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 1917 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link); 1918 1919 static void quirk_e100_interrupt(struct pci_dev *dev) 1920 { 1921 u16 command, pmcsr; 1922 u8 __iomem *csr; 1923 u8 cmd_hi; 1924 1925 switch (dev->device) { 1926 /* PCI IDs taken from drivers/net/e100.c */ 1927 case 0x1029: 1928 case 0x1030 ... 0x1034: 1929 case 0x1038 ... 0x103E: 1930 case 0x1050 ... 0x1057: 1931 case 0x1059: 1932 case 0x1064 ... 0x106B: 1933 case 0x1091 ... 0x1095: 1934 case 0x1209: 1935 case 0x1229: 1936 case 0x2449: 1937 case 0x2459: 1938 case 0x245D: 1939 case 0x27DC: 1940 break; 1941 default: 1942 return; 1943 } 1944 1945 /* 1946 * Some firmware hands off the e100 with interrupts enabled, 1947 * which can cause a flood of interrupts if packets are 1948 * received before the driver attaches to the device. So 1949 * disable all e100 interrupts here. The driver will 1950 * re-enable them when it's ready. 1951 */ 1952 pci_read_config_word(dev, PCI_COMMAND, &command); 1953 1954 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 1955 return; 1956 1957 /* 1958 * Check that the device is in the D0 power state. If it's not, 1959 * there is no point to look any further. 1960 */ 1961 if (dev->pm_cap) { 1962 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1963 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 1964 return; 1965 } 1966 1967 /* Convert from PCI bus to resource space. */ 1968 csr = ioremap(pci_resource_start(dev, 0), 8); 1969 if (!csr) { 1970 dev_warn(&dev->dev, "Can't map e100 registers\n"); 1971 return; 1972 } 1973 1974 cmd_hi = readb(csr + 3); 1975 if (cmd_hi == 0) { 1976 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n"); 1977 writeb(1, csr + 3); 1978 } 1979 1980 iounmap(csr); 1981 } 1982 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 1983 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 1984 1985 /* 1986 * The 82575 and 82598 may experience data corruption issues when transitioning 1987 * out of L0S. To prevent this we need to disable L0S on the pci-e link 1988 */ 1989 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 1990 { 1991 dev_info(&dev->dev, "Disabling L0s\n"); 1992 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 1993 } 1994 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 1995 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 1996 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 1997 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 1998 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 1999 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2000 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2001 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2002 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2003 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2004 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2005 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2006 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2007 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2008 2009 static void fixup_rev1_53c810(struct pci_dev *dev) 2010 { 2011 u32 class = dev->class; 2012 2013 /* 2014 * rev 1 ncr53c810 chips don't set the class at all which means 2015 * they don't get their resources remapped. Fix that here. 2016 */ 2017 if (class) 2018 return; 2019 2020 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2021 dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2022 class, dev->class); 2023 } 2024 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2025 2026 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2027 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2028 { 2029 u16 en1k; 2030 2031 pci_read_config_word(dev, 0x40, &en1k); 2032 2033 if (en1k & 0x200) { 2034 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); 2035 dev->io_window_1k = 1; 2036 } 2037 } 2038 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2039 2040 /* Under some circumstances, AER is not linked with extended capabilities. 2041 * Force it to be linked by setting the corresponding control bit in the 2042 * config space. 2043 */ 2044 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2045 { 2046 uint8_t b; 2047 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2048 if (!(b & 0x20)) { 2049 pci_write_config_byte(dev, 0xf41, b | 0x20); 2050 dev_info(&dev->dev, "Linking AER extended capability\n"); 2051 } 2052 } 2053 } 2054 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2055 quirk_nvidia_ck804_pcie_aer_ext_cap); 2056 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2057 quirk_nvidia_ck804_pcie_aer_ext_cap); 2058 2059 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2060 { 2061 /* 2062 * Disable PCI Bus Parking and PCI Master read caching on CX700 2063 * which causes unspecified timing errors with a VT6212L on the PCI 2064 * bus leading to USB2.0 packet loss. 2065 * 2066 * This quirk is only enabled if a second (on the external PCI bus) 2067 * VT6212L is found -- the CX700 core itself also contains a USB 2068 * host controller with the same PCI ID as the VT6212L. 2069 */ 2070 2071 /* Count VT6212L instances */ 2072 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2073 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2074 uint8_t b; 2075 2076 /* p should contain the first (internal) VT6212L -- see if we have 2077 an external one by searching again */ 2078 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2079 if (!p) 2080 return; 2081 pci_dev_put(p); 2082 2083 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2084 if (b & 0x40) { 2085 /* Turn off PCI Bus Parking */ 2086 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2087 2088 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n"); 2089 } 2090 } 2091 2092 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2093 if (b != 0) { 2094 /* Turn off PCI Master read caching */ 2095 pci_write_config_byte(dev, 0x72, 0x0); 2096 2097 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2098 pci_write_config_byte(dev, 0x75, 0x1); 2099 2100 /* Disable "Read FIFO Timer" */ 2101 pci_write_config_byte(dev, 0x77, 0x0); 2102 2103 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n"); 2104 } 2105 } 2106 } 2107 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2108 2109 /* 2110 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the 2111 * VPD end tag will hang the device. This problem was initially 2112 * observed when a vpd entry was created in sysfs 2113 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry 2114 * will dump 32k of data. Reading a full 32k will cause an access 2115 * beyond the VPD end tag causing the device to hang. Once the device 2116 * is hung, the bnx2 driver will not be able to reset the device. 2117 * We believe that it is legal to read beyond the end tag and 2118 * therefore the solution is to limit the read/write length. 2119 */ 2120 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev) 2121 { 2122 /* 2123 * Only disable the VPD capability for 5706, 5706S, 5708, 2124 * 5708S and 5709 rev. A 2125 */ 2126 if ((dev->device == PCI_DEVICE_ID_NX2_5706) || 2127 (dev->device == PCI_DEVICE_ID_NX2_5706S) || 2128 (dev->device == PCI_DEVICE_ID_NX2_5708) || 2129 (dev->device == PCI_DEVICE_ID_NX2_5708S) || 2130 ((dev->device == PCI_DEVICE_ID_NX2_5709) && 2131 (dev->revision & 0xf0) == 0x0)) { 2132 if (dev->vpd) 2133 dev->vpd->len = 0x80; 2134 } 2135 } 2136 2137 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2138 PCI_DEVICE_ID_NX2_5706, 2139 quirk_brcm_570x_limit_vpd); 2140 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2141 PCI_DEVICE_ID_NX2_5706S, 2142 quirk_brcm_570x_limit_vpd); 2143 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2144 PCI_DEVICE_ID_NX2_5708, 2145 quirk_brcm_570x_limit_vpd); 2146 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2147 PCI_DEVICE_ID_NX2_5708S, 2148 quirk_brcm_570x_limit_vpd); 2149 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2150 PCI_DEVICE_ID_NX2_5709, 2151 quirk_brcm_570x_limit_vpd); 2152 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2153 PCI_DEVICE_ID_NX2_5709S, 2154 quirk_brcm_570x_limit_vpd); 2155 2156 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2157 { 2158 u32 rev; 2159 2160 pci_read_config_dword(dev, 0xf4, &rev); 2161 2162 /* Only CAP the MRRS if the device is a 5719 A0 */ 2163 if (rev == 0x05719000) { 2164 int readrq = pcie_get_readrq(dev); 2165 if (readrq > 2048) 2166 pcie_set_readrq(dev, 2048); 2167 } 2168 } 2169 2170 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2171 PCI_DEVICE_ID_TIGON3_5719, 2172 quirk_brcm_5719_limit_mrrs); 2173 2174 /* Originally in EDAC sources for i82875P: 2175 * Intel tells BIOS developers to hide device 6 which 2176 * configures the overflow device access containing 2177 * the DRBs - this is where we expose device 6. 2178 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2179 */ 2180 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2181 { 2182 u8 reg; 2183 2184 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2185 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); 2186 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2187 } 2188 } 2189 2190 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2191 quirk_unhide_mch_dev6); 2192 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2193 quirk_unhide_mch_dev6); 2194 2195 #ifdef CONFIG_TILEPRO 2196 /* 2197 * The Tilera TILEmpower tilepro platform needs to set the link speed 2198 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed 2199 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe 2200 * capability register of the PEX8624 PCIe switch. The switch 2201 * supports link speed auto negotiation, but falsely sets 2202 * the link speed to 5GT/s. 2203 */ 2204 static void quirk_tile_plx_gen1(struct pci_dev *dev) 2205 { 2206 if (tile_plx_gen1) { 2207 pci_write_config_dword(dev, 0x98, 0x1); 2208 mdelay(50); 2209 } 2210 } 2211 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); 2212 #endif /* CONFIG_TILEPRO */ 2213 2214 #ifdef CONFIG_PCI_MSI 2215 /* Some chipsets do not support MSI. We cannot easily rely on setting 2216 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 2217 * some other buses controlled by the chipset even if Linux is not 2218 * aware of it. Instead of setting the flag on all buses in the 2219 * machine, simply disable MSI globally. 2220 */ 2221 static void quirk_disable_all_msi(struct pci_dev *dev) 2222 { 2223 pci_no_msi(); 2224 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); 2225 } 2226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2233 2234 /* Disable MSI on chipsets that are known to not support it */ 2235 static void quirk_disable_msi(struct pci_dev *dev) 2236 { 2237 if (dev->subordinate) { 2238 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2239 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2240 } 2241 } 2242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2245 2246 /* 2247 * The APC bridge device in AMD 780 family northbridges has some random 2248 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2249 * we use the possible vendor/device IDs of the host bridge for the 2250 * declared quirk, and search for the APC bridge by slot number. 2251 */ 2252 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2253 { 2254 struct pci_dev *apc_bridge; 2255 2256 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2257 if (apc_bridge) { 2258 if (apc_bridge->device == 0x9602) 2259 quirk_disable_msi(apc_bridge); 2260 pci_dev_put(apc_bridge); 2261 } 2262 } 2263 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2264 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2265 2266 /* Go through the list of Hypertransport capabilities and 2267 * return 1 if a HT MSI capability is found and enabled */ 2268 static int msi_ht_cap_enabled(struct pci_dev *dev) 2269 { 2270 int pos, ttl = PCI_FIND_CAP_TTL; 2271 2272 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2273 while (pos && ttl--) { 2274 u8 flags; 2275 2276 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2277 &flags) == 0) { 2278 dev_info(&dev->dev, "Found %s HT MSI Mapping\n", 2279 flags & HT_MSI_FLAGS_ENABLE ? 2280 "enabled" : "disabled"); 2281 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2282 } 2283 2284 pos = pci_find_next_ht_capability(dev, pos, 2285 HT_CAPTYPE_MSI_MAPPING); 2286 } 2287 return 0; 2288 } 2289 2290 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ 2291 static void quirk_msi_ht_cap(struct pci_dev *dev) 2292 { 2293 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2294 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2295 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2296 } 2297 } 2298 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2299 quirk_msi_ht_cap); 2300 2301 /* The nVidia CK804 chipset may have 2 HT MSI mappings. 2302 * MSI are supported if the MSI capability set in any of these mappings. 2303 */ 2304 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2305 { 2306 struct pci_dev *pdev; 2307 2308 if (!dev->subordinate) 2309 return; 2310 2311 /* check HT MSI cap on this chipset and the root one. 2312 * a single one having MSI is enough to be sure that MSI are supported. 2313 */ 2314 pdev = pci_get_slot(dev->bus, 0); 2315 if (!pdev) 2316 return; 2317 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2318 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2319 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2320 } 2321 pci_dev_put(pdev); 2322 } 2323 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2324 quirk_nvidia_ck804_msi_ht_cap); 2325 2326 /* Force enable MSI mapping capability on HT bridges */ 2327 static void ht_enable_msi_mapping(struct pci_dev *dev) 2328 { 2329 int pos, ttl = PCI_FIND_CAP_TTL; 2330 2331 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2332 while (pos && ttl--) { 2333 u8 flags; 2334 2335 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2336 &flags) == 0) { 2337 dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); 2338 2339 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2340 flags | HT_MSI_FLAGS_ENABLE); 2341 } 2342 pos = pci_find_next_ht_capability(dev, pos, 2343 HT_CAPTYPE_MSI_MAPPING); 2344 } 2345 } 2346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2347 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2348 ht_enable_msi_mapping); 2349 2350 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2351 ht_enable_msi_mapping); 2352 2353 /* The P5N32-SLI motherboards from Asus have a problem with msi 2354 * for the MCP55 NIC. It is not yet determined whether the msi problem 2355 * also affects other devices. As for now, turn off msi for this device. 2356 */ 2357 static void nvenet_msi_disable(struct pci_dev *dev) 2358 { 2359 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2360 2361 if (board_name && 2362 (strstr(board_name, "P5N32-SLI PREMIUM") || 2363 strstr(board_name, "P5N32-E SLI"))) { 2364 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n"); 2365 dev->no_msi = 1; 2366 } 2367 } 2368 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2369 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2370 nvenet_msi_disable); 2371 2372 /* 2373 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2374 * config register. This register controls the routing of legacy 2375 * interrupts from devices that route through the MCP55. If this register 2376 * is misprogrammed, interrupts are only sent to the BSP, unlike 2377 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2378 * having this register set properly prevents kdump from booting up 2379 * properly, so let's make sure that we have it set correctly. 2380 * Note that this is an undocumented register. 2381 */ 2382 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2383 { 2384 u32 cfg; 2385 2386 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2387 return; 2388 2389 pci_read_config_dword(dev, 0x74, &cfg); 2390 2391 if (cfg & ((1 << 2) | (1 << 15))) { 2392 printk(KERN_INFO "Rewriting irq routing register on MCP55\n"); 2393 cfg &= ~((1 << 2) | (1 << 15)); 2394 pci_write_config_dword(dev, 0x74, cfg); 2395 } 2396 } 2397 2398 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2399 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2400 nvbridge_check_legacy_irq_routing); 2401 2402 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2403 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2404 nvbridge_check_legacy_irq_routing); 2405 2406 static int ht_check_msi_mapping(struct pci_dev *dev) 2407 { 2408 int pos, ttl = PCI_FIND_CAP_TTL; 2409 int found = 0; 2410 2411 /* check if there is HT MSI cap or enabled on this device */ 2412 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2413 while (pos && ttl--) { 2414 u8 flags; 2415 2416 if (found < 1) 2417 found = 1; 2418 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2419 &flags) == 0) { 2420 if (flags & HT_MSI_FLAGS_ENABLE) { 2421 if (found < 2) { 2422 found = 2; 2423 break; 2424 } 2425 } 2426 } 2427 pos = pci_find_next_ht_capability(dev, pos, 2428 HT_CAPTYPE_MSI_MAPPING); 2429 } 2430 2431 return found; 2432 } 2433 2434 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2435 { 2436 struct pci_dev *dev; 2437 int pos; 2438 int i, dev_no; 2439 int found = 0; 2440 2441 dev_no = host_bridge->devfn >> 3; 2442 for (i = dev_no + 1; i < 0x20; i++) { 2443 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2444 if (!dev) 2445 continue; 2446 2447 /* found next host bridge ?*/ 2448 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2449 if (pos != 0) { 2450 pci_dev_put(dev); 2451 break; 2452 } 2453 2454 if (ht_check_msi_mapping(dev)) { 2455 found = 1; 2456 pci_dev_put(dev); 2457 break; 2458 } 2459 pci_dev_put(dev); 2460 } 2461 2462 return found; 2463 } 2464 2465 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2466 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2467 2468 static int is_end_of_ht_chain(struct pci_dev *dev) 2469 { 2470 int pos, ctrl_off; 2471 int end = 0; 2472 u16 flags, ctrl; 2473 2474 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2475 2476 if (!pos) 2477 goto out; 2478 2479 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2480 2481 ctrl_off = ((flags >> 10) & 1) ? 2482 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2483 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2484 2485 if (ctrl & (1 << 6)) 2486 end = 1; 2487 2488 out: 2489 return end; 2490 } 2491 2492 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 2493 { 2494 struct pci_dev *host_bridge; 2495 int pos; 2496 int i, dev_no; 2497 int found = 0; 2498 2499 dev_no = dev->devfn >> 3; 2500 for (i = dev_no; i >= 0; i--) { 2501 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 2502 if (!host_bridge) 2503 continue; 2504 2505 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2506 if (pos != 0) { 2507 found = 1; 2508 break; 2509 } 2510 pci_dev_put(host_bridge); 2511 } 2512 2513 if (!found) 2514 return; 2515 2516 /* don't enable end_device/host_bridge with leaf directly here */ 2517 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 2518 host_bridge_with_leaf(host_bridge)) 2519 goto out; 2520 2521 /* root did that ! */ 2522 if (msi_ht_cap_enabled(host_bridge)) 2523 goto out; 2524 2525 ht_enable_msi_mapping(dev); 2526 2527 out: 2528 pci_dev_put(host_bridge); 2529 } 2530 2531 static void ht_disable_msi_mapping(struct pci_dev *dev) 2532 { 2533 int pos, ttl = PCI_FIND_CAP_TTL; 2534 2535 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2536 while (pos && ttl--) { 2537 u8 flags; 2538 2539 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2540 &flags) == 0) { 2541 dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); 2542 2543 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2544 flags & ~HT_MSI_FLAGS_ENABLE); 2545 } 2546 pos = pci_find_next_ht_capability(dev, pos, 2547 HT_CAPTYPE_MSI_MAPPING); 2548 } 2549 } 2550 2551 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2552 { 2553 struct pci_dev *host_bridge; 2554 int pos; 2555 int found; 2556 2557 if (!pci_msi_enabled()) 2558 return; 2559 2560 /* check if there is HT MSI cap or enabled on this device */ 2561 found = ht_check_msi_mapping(dev); 2562 2563 /* no HT MSI CAP */ 2564 if (found == 0) 2565 return; 2566 2567 /* 2568 * HT MSI mapping should be disabled on devices that are below 2569 * a non-Hypertransport host bridge. Locate the host bridge... 2570 */ 2571 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); 2572 if (host_bridge == NULL) { 2573 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2574 return; 2575 } 2576 2577 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2578 if (pos != 0) { 2579 /* Host bridge is to HT */ 2580 if (found == 1) { 2581 /* it is not enabled, try to enable it */ 2582 if (all) 2583 ht_enable_msi_mapping(dev); 2584 else 2585 nv_ht_enable_msi_mapping(dev); 2586 } 2587 goto out; 2588 } 2589 2590 /* HT MSI is not enabled */ 2591 if (found == 1) 2592 goto out; 2593 2594 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2595 ht_disable_msi_mapping(dev); 2596 2597 out: 2598 pci_dev_put(host_bridge); 2599 } 2600 2601 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2602 { 2603 return __nv_msi_ht_cap_quirk(dev, 1); 2604 } 2605 2606 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2607 { 2608 return __nv_msi_ht_cap_quirk(dev, 0); 2609 } 2610 2611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2612 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2613 2614 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2615 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2616 2617 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 2618 { 2619 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2620 } 2621 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2622 { 2623 struct pci_dev *p; 2624 2625 /* SB700 MSI issue will be fixed at HW level from revision A21, 2626 * we need check PCI REVISION ID of SMBus controller to get SB700 2627 * revision. 2628 */ 2629 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2630 NULL); 2631 if (!p) 2632 return; 2633 2634 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 2635 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2636 pci_dev_put(p); 2637 } 2638 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 2639 { 2640 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 2641 if (dev->revision < 0x18) { 2642 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n"); 2643 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2644 } 2645 } 2646 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2647 PCI_DEVICE_ID_TIGON3_5780, 2648 quirk_msi_intx_disable_bug); 2649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2650 PCI_DEVICE_ID_TIGON3_5780S, 2651 quirk_msi_intx_disable_bug); 2652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2653 PCI_DEVICE_ID_TIGON3_5714, 2654 quirk_msi_intx_disable_bug); 2655 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2656 PCI_DEVICE_ID_TIGON3_5714S, 2657 quirk_msi_intx_disable_bug); 2658 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2659 PCI_DEVICE_ID_TIGON3_5715, 2660 quirk_msi_intx_disable_bug); 2661 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2662 PCI_DEVICE_ID_TIGON3_5715S, 2663 quirk_msi_intx_disable_bug); 2664 2665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 2666 quirk_msi_intx_disable_ati_bug); 2667 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 2668 quirk_msi_intx_disable_ati_bug); 2669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 2670 quirk_msi_intx_disable_ati_bug); 2671 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 2672 quirk_msi_intx_disable_ati_bug); 2673 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 2674 quirk_msi_intx_disable_ati_bug); 2675 2676 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 2677 quirk_msi_intx_disable_bug); 2678 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 2679 quirk_msi_intx_disable_bug); 2680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 2681 quirk_msi_intx_disable_bug); 2682 2683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 2684 quirk_msi_intx_disable_bug); 2685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 2686 quirk_msi_intx_disable_bug); 2687 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 2688 quirk_msi_intx_disable_bug); 2689 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 2690 quirk_msi_intx_disable_bug); 2691 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 2692 quirk_msi_intx_disable_bug); 2693 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 2694 quirk_msi_intx_disable_bug); 2695 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 2696 quirk_msi_intx_disable_qca_bug); 2697 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 2698 quirk_msi_intx_disable_qca_bug); 2699 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 2700 quirk_msi_intx_disable_qca_bug); 2701 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 2702 quirk_msi_intx_disable_qca_bug); 2703 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 2704 quirk_msi_intx_disable_qca_bug); 2705 #endif /* CONFIG_PCI_MSI */ 2706 2707 /* Allow manual resource allocation for PCI hotplug bridges 2708 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For 2709 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), 2710 * kernel fails to allocate resources when hotplug device is 2711 * inserted and PCI bus is rescanned. 2712 */ 2713 static void quirk_hotplug_bridge(struct pci_dev *dev) 2714 { 2715 dev->is_hotplug_bridge = 1; 2716 } 2717 2718 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 2719 2720 /* 2721 * This is a quirk for the Ricoh MMC controller found as a part of 2722 * some mulifunction chips. 2723 2724 * This is very similar and based on the ricoh_mmc driver written by 2725 * Philip Langdale. Thank you for these magic sequences. 2726 * 2727 * These chips implement the four main memory card controllers (SD, MMC, MS, xD) 2728 * and one or both of cardbus or firewire. 2729 * 2730 * It happens that they implement SD and MMC 2731 * support as separate controllers (and PCI functions). The linux SDHCI 2732 * driver supports MMC cards but the chip detects MMC cards in hardware 2733 * and directs them to the MMC controller - so the SDHCI driver never sees 2734 * them. 2735 * 2736 * To get around this, we must disable the useless MMC controller. 2737 * At that point, the SDHCI controller will start seeing them 2738 * It seems to be the case that the relevant PCI registers to deactivate the 2739 * MMC controller live on PCI function 0, which might be the cardbus controller 2740 * or the firewire controller, depending on the particular chip in question 2741 * 2742 * This has to be done early, because as soon as we disable the MMC controller 2743 * other pci functions shift up one level, e.g. function #2 becomes function 2744 * #1, and this will confuse the pci core. 2745 */ 2746 2747 #ifdef CONFIG_MMC_RICOH_MMC 2748 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 2749 { 2750 /* disable via cardbus interface */ 2751 u8 write_enable; 2752 u8 write_target; 2753 u8 disable; 2754 2755 /* disable must be done via function #0 */ 2756 if (PCI_FUNC(dev->devfn)) 2757 return; 2758 2759 pci_read_config_byte(dev, 0xB7, &disable); 2760 if (disable & 0x02) 2761 return; 2762 2763 pci_read_config_byte(dev, 0x8E, &write_enable); 2764 pci_write_config_byte(dev, 0x8E, 0xAA); 2765 pci_read_config_byte(dev, 0x8D, &write_target); 2766 pci_write_config_byte(dev, 0x8D, 0xB7); 2767 pci_write_config_byte(dev, 0xB7, disable | 0x02); 2768 pci_write_config_byte(dev, 0x8E, write_enable); 2769 pci_write_config_byte(dev, 0x8D, write_target); 2770 2771 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); 2772 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2773 } 2774 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2775 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2776 2777 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 2778 { 2779 /* disable via firewire interface */ 2780 u8 write_enable; 2781 u8 disable; 2782 2783 /* disable must be done via function #0 */ 2784 if (PCI_FUNC(dev->devfn)) 2785 return; 2786 /* 2787 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 2788 * certain types of SD/MMC cards. Lowering the SD base 2789 * clock frequency from 200Mhz to 50Mhz fixes this issue. 2790 * 2791 * 0x150 - SD2.0 mode enable for changing base clock 2792 * frequency to 50Mhz 2793 * 0xe1 - Base clock frequency 2794 * 0x32 - 50Mhz new clock frequency 2795 * 0xf9 - Key register for 0x150 2796 * 0xfc - key register for 0xe1 2797 */ 2798 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 2799 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 2800 pci_write_config_byte(dev, 0xf9, 0xfc); 2801 pci_write_config_byte(dev, 0x150, 0x10); 2802 pci_write_config_byte(dev, 0xf9, 0x00); 2803 pci_write_config_byte(dev, 0xfc, 0x01); 2804 pci_write_config_byte(dev, 0xe1, 0x32); 2805 pci_write_config_byte(dev, 0xfc, 0x00); 2806 2807 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n"); 2808 } 2809 2810 pci_read_config_byte(dev, 0xCB, &disable); 2811 2812 if (disable & 0x02) 2813 return; 2814 2815 pci_read_config_byte(dev, 0xCA, &write_enable); 2816 pci_write_config_byte(dev, 0xCA, 0x57); 2817 pci_write_config_byte(dev, 0xCB, disable | 0x02); 2818 pci_write_config_byte(dev, 0xCA, write_enable); 2819 2820 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); 2821 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2822 2823 } 2824 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2825 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2826 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 2827 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 2828 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2829 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2830 #endif /*CONFIG_MMC_RICOH_MMC*/ 2831 2832 #ifdef CONFIG_DMAR_TABLE 2833 #define VTUNCERRMSK_REG 0x1ac 2834 #define VTD_MSK_SPEC_ERRORS (1 << 31) 2835 /* 2836 * This is a quirk for masking vt-d spec defined errors to platform error 2837 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets 2838 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 2839 * on the RAS config settings of the platform) when a vt-d fault happens. 2840 * The resulting SMI caused the system to hang. 2841 * 2842 * VT-d spec related errors are already handled by the VT-d OS code, so no 2843 * need to report the same error through other channels. 2844 */ 2845 static void vtd_mask_spec_errors(struct pci_dev *dev) 2846 { 2847 u32 word; 2848 2849 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 2850 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 2851 } 2852 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 2853 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 2854 #endif 2855 2856 static void fixup_ti816x_class(struct pci_dev *dev) 2857 { 2858 u32 class = dev->class; 2859 2860 /* TI 816x devices do not have class code set when in PCIe boot mode */ 2861 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 2862 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n", 2863 class, dev->class); 2864 } 2865 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 2866 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 2867 2868 /* Some PCIe devices do not work reliably with the claimed maximum 2869 * payload size supported. 2870 */ 2871 static void fixup_mpss_256(struct pci_dev *dev) 2872 { 2873 dev->pcie_mpss = 1; /* 256 bytes */ 2874 } 2875 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2876 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 2877 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2878 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 2879 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2880 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 2881 2882 /* Intel 5000 and 5100 Memory controllers have an errata with read completion 2883 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 2884 * Since there is no way of knowing what the PCIE MPS on each fabric will be 2885 * until all of the devices are discovered and buses walked, read completion 2886 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 2887 * it is possible to hotplug a device with MPS of 256B. 2888 */ 2889 static void quirk_intel_mc_errata(struct pci_dev *dev) 2890 { 2891 int err; 2892 u16 rcc; 2893 2894 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 2895 pcie_bus_config == PCIE_BUS_DEFAULT) 2896 return; 2897 2898 /* Intel errata specifies bits to change but does not say what they are. 2899 * Keeping them magical until such time as the registers and values can 2900 * be explained. 2901 */ 2902 err = pci_read_config_word(dev, 0x48, &rcc); 2903 if (err) { 2904 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n"); 2905 return; 2906 } 2907 2908 if (!(rcc & (1 << 10))) 2909 return; 2910 2911 rcc &= ~(1 << 10); 2912 2913 err = pci_write_config_word(dev, 0x48, rcc); 2914 if (err) { 2915 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n"); 2916 return; 2917 } 2918 2919 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n"); 2920 } 2921 /* Intel 5000 series memory controllers and ports 2-7 */ 2922 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 2923 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 2924 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 2925 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 2926 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 2927 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 2928 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 2929 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 2930 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 2931 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 2932 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 2933 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 2934 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 2935 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 2936 /* Intel 5100 series memory controllers and ports 2-7 */ 2937 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 2938 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 2939 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 2940 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 2941 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 2942 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 2943 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 2944 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 2945 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 2946 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 2947 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 2948 2949 2950 /* 2951 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To 2952 * work around this, query the size it should be configured to by the device and 2953 * modify the resource end to correspond to this new size. 2954 */ 2955 static void quirk_intel_ntb(struct pci_dev *dev) 2956 { 2957 int rc; 2958 u8 val; 2959 2960 rc = pci_read_config_byte(dev, 0x00D0, &val); 2961 if (rc) 2962 return; 2963 2964 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; 2965 2966 rc = pci_read_config_byte(dev, 0x00D1, &val); 2967 if (rc) 2968 return; 2969 2970 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; 2971 } 2972 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 2973 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 2974 2975 static ktime_t fixup_debug_start(struct pci_dev *dev, 2976 void (*fn)(struct pci_dev *dev)) 2977 { 2978 ktime_t calltime = ktime_set(0, 0); 2979 2980 dev_dbg(&dev->dev, "calling %pF\n", fn); 2981 if (initcall_debug) { 2982 pr_debug("calling %pF @ %i for %s\n", 2983 fn, task_pid_nr(current), dev_name(&dev->dev)); 2984 calltime = ktime_get(); 2985 } 2986 2987 return calltime; 2988 } 2989 2990 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 2991 void (*fn)(struct pci_dev *dev)) 2992 { 2993 ktime_t delta, rettime; 2994 unsigned long long duration; 2995 2996 if (initcall_debug) { 2997 rettime = ktime_get(); 2998 delta = ktime_sub(rettime, calltime); 2999 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 3000 pr_debug("pci fixup %pF returned after %lld usecs for %s\n", 3001 fn, duration, dev_name(&dev->dev)); 3002 } 3003 } 3004 3005 /* 3006 * Some BIOS implementations leave the Intel GPU interrupts enabled, 3007 * even though no one is handling them (f.e. i915 driver is never loaded). 3008 * Additionally the interrupt destination is not set up properly 3009 * and the interrupt ends up -somewhere-. 3010 * 3011 * These spurious interrupts are "sticky" and the kernel disables 3012 * the (shared) interrupt line after 100.000+ generated interrupts. 3013 * 3014 * Fix it by disabling the still enabled interrupts. 3015 * This resolves crashes often seen on monitor unplug. 3016 */ 3017 #define I915_DEIER_REG 0x4400c 3018 static void disable_igfx_irq(struct pci_dev *dev) 3019 { 3020 void __iomem *regs = pci_iomap(dev, 0, 0); 3021 if (regs == NULL) { 3022 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n"); 3023 return; 3024 } 3025 3026 /* Check if any interrupt line is still enabled */ 3027 if (readl(regs + I915_DEIER_REG) != 0) { 3028 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3029 3030 writel(0, regs + I915_DEIER_REG); 3031 } 3032 3033 pci_iounmap(dev, regs); 3034 } 3035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3038 3039 /* 3040 * PCI devices which are on Intel chips can skip the 10ms delay 3041 * before entering D3 mode. 3042 */ 3043 static void quirk_remove_d3_delay(struct pci_dev *dev) 3044 { 3045 dev->d3_delay = 0; 3046 } 3047 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay); 3048 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay); 3049 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay); 3050 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay); 3051 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay); 3052 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay); 3053 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay); 3054 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay); 3055 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay); 3056 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay); 3057 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay); 3058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay); 3059 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay); 3060 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay); 3061 /* Intel Cherrytrail devices do not need 10ms d3_delay */ 3062 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay); 3063 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay); 3064 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay); 3065 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay); 3066 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay); 3067 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay); 3068 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay); 3069 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay); 3070 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay); 3071 /* 3072 * Some devices may pass our check in pci_intx_mask_supported if 3073 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3074 * support this feature. 3075 */ 3076 static void quirk_broken_intx_masking(struct pci_dev *dev) 3077 { 3078 dev->broken_intx_masking = 1; 3079 } 3080 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030, 3081 quirk_broken_intx_masking); 3082 DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3083 quirk_broken_intx_masking); 3084 /* 3085 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3086 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3087 * 3088 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3089 */ 3090 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_REALTEK, 0x8169, 3091 quirk_broken_intx_masking); 3092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3093 quirk_broken_intx_masking); 3094 3095 static void quirk_no_bus_reset(struct pci_dev *dev) 3096 { 3097 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3098 } 3099 3100 /* 3101 * Atheros AR93xx chips do not behave after a bus reset. The device will 3102 * throw a Link Down error on AER-capable systems and regardless of AER, 3103 * config space of the device is never accessible again and typically 3104 * causes the system to hang or reset when access is attempted. 3105 * http://www.spinics.net/lists/linux-pci/msg34797.html 3106 */ 3107 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3108 3109 static void quirk_no_pm_reset(struct pci_dev *dev) 3110 { 3111 /* 3112 * We can't do a bus reset on root bus devices, but an ineffective 3113 * PM reset may be better than nothing. 3114 */ 3115 if (!pci_is_root_bus(dev->bus)) 3116 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3117 } 3118 3119 /* 3120 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3121 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3122 * to have no effect on the device: it retains the framebuffer contents and 3123 * monitor sync. Advertising this support makes other layers, like VFIO, 3124 * assume pci_reset_function() is viable for this device. Mark it as 3125 * unavailable to skip it when testing reset methods. 3126 */ 3127 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3128 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3129 3130 #ifdef CONFIG_ACPI 3131 /* 3132 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3133 * 3134 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3135 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3136 * be present after resume if a device was plugged in before suspend. 3137 * 3138 * The thunderbolt controller consists of a pcie switch with downstream 3139 * bridges leading to the NHI and to the tunnel pci bridges. 3140 * 3141 * This quirk cuts power to the whole chip. Therefore we have to apply it 3142 * during suspend_noirq of the upstream bridge. 3143 * 3144 * Power is automagically restored before resume. No action is needed. 3145 */ 3146 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3147 { 3148 acpi_handle bridge, SXIO, SXFP, SXLV; 3149 3150 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc.")) 3151 return; 3152 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3153 return; 3154 bridge = ACPI_HANDLE(&dev->dev); 3155 if (!bridge) 3156 return; 3157 /* 3158 * SXIO and SXLV are present only on machines requiring this quirk. 3159 * TB bridges in external devices might have the same device id as those 3160 * on the host, but they will not have the associated ACPI methods. This 3161 * implicitly checks that we are at the right bridge. 3162 */ 3163 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3164 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3165 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3166 return; 3167 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n"); 3168 3169 /* magic sequence */ 3170 acpi_execute_simple_method(SXIO, NULL, 1); 3171 acpi_execute_simple_method(SXFP, NULL, 0); 3172 msleep(300); 3173 acpi_execute_simple_method(SXLV, NULL, 0); 3174 acpi_execute_simple_method(SXIO, NULL, 0); 3175 acpi_execute_simple_method(SXLV, NULL, 0); 3176 } 3177 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 0x1547, 3178 quirk_apple_poweroff_thunderbolt); 3179 3180 /* 3181 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels. 3182 * 3183 * During suspend the thunderbolt controller is reset and all pci 3184 * tunnels are lost. The NHI driver will try to reestablish all tunnels 3185 * during resume. We have to manually wait for the NHI since there is 3186 * no parent child relationship between the NHI and the tunneled 3187 * bridges. 3188 */ 3189 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev) 3190 { 3191 struct pci_dev *sibling = NULL; 3192 struct pci_dev *nhi = NULL; 3193 3194 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc.")) 3195 return; 3196 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM) 3197 return; 3198 /* 3199 * Find the NHI and confirm that we are a bridge on the tb host 3200 * controller and not on a tb endpoint. 3201 */ 3202 sibling = pci_get_slot(dev->bus, 0x0); 3203 if (sibling == dev) 3204 goto out; /* we are the downstream bridge to the NHI */ 3205 if (!sibling || !sibling->subordinate) 3206 goto out; 3207 nhi = pci_get_slot(sibling->subordinate, 0x0); 3208 if (!nhi) 3209 goto out; 3210 if (nhi->vendor != PCI_VENDOR_ID_INTEL 3211 || (nhi->device != 0x1547 && nhi->device != 0x156c) 3212 || nhi->subsystem_vendor != 0x2222 3213 || nhi->subsystem_device != 0x1111) 3214 goto out; 3215 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n"); 3216 device_pm_wait_for_dev(&dev->dev, &nhi->dev); 3217 out: 3218 pci_dev_put(nhi); 3219 pci_dev_put(sibling); 3220 } 3221 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x1547, 3222 quirk_apple_wait_for_thunderbolt); 3223 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x156d, 3224 quirk_apple_wait_for_thunderbolt); 3225 #endif 3226 3227 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 3228 struct pci_fixup *end) 3229 { 3230 ktime_t calltime; 3231 3232 for (; f < end; f++) 3233 if ((f->class == (u32) (dev->class >> f->class_shift) || 3234 f->class == (u32) PCI_ANY_ID) && 3235 (f->vendor == dev->vendor || 3236 f->vendor == (u16) PCI_ANY_ID) && 3237 (f->device == dev->device || 3238 f->device == (u16) PCI_ANY_ID)) { 3239 calltime = fixup_debug_start(dev, f->hook); 3240 f->hook(dev); 3241 fixup_debug_report(dev, calltime, f->hook); 3242 } 3243 } 3244 3245 extern struct pci_fixup __start_pci_fixups_early[]; 3246 extern struct pci_fixup __end_pci_fixups_early[]; 3247 extern struct pci_fixup __start_pci_fixups_header[]; 3248 extern struct pci_fixup __end_pci_fixups_header[]; 3249 extern struct pci_fixup __start_pci_fixups_final[]; 3250 extern struct pci_fixup __end_pci_fixups_final[]; 3251 extern struct pci_fixup __start_pci_fixups_enable[]; 3252 extern struct pci_fixup __end_pci_fixups_enable[]; 3253 extern struct pci_fixup __start_pci_fixups_resume[]; 3254 extern struct pci_fixup __end_pci_fixups_resume[]; 3255 extern struct pci_fixup __start_pci_fixups_resume_early[]; 3256 extern struct pci_fixup __end_pci_fixups_resume_early[]; 3257 extern struct pci_fixup __start_pci_fixups_suspend[]; 3258 extern struct pci_fixup __end_pci_fixups_suspend[]; 3259 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 3260 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 3261 3262 static bool pci_apply_fixup_final_quirks; 3263 3264 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 3265 { 3266 struct pci_fixup *start, *end; 3267 3268 switch (pass) { 3269 case pci_fixup_early: 3270 start = __start_pci_fixups_early; 3271 end = __end_pci_fixups_early; 3272 break; 3273 3274 case pci_fixup_header: 3275 start = __start_pci_fixups_header; 3276 end = __end_pci_fixups_header; 3277 break; 3278 3279 case pci_fixup_final: 3280 if (!pci_apply_fixup_final_quirks) 3281 return; 3282 start = __start_pci_fixups_final; 3283 end = __end_pci_fixups_final; 3284 break; 3285 3286 case pci_fixup_enable: 3287 start = __start_pci_fixups_enable; 3288 end = __end_pci_fixups_enable; 3289 break; 3290 3291 case pci_fixup_resume: 3292 start = __start_pci_fixups_resume; 3293 end = __end_pci_fixups_resume; 3294 break; 3295 3296 case pci_fixup_resume_early: 3297 start = __start_pci_fixups_resume_early; 3298 end = __end_pci_fixups_resume_early; 3299 break; 3300 3301 case pci_fixup_suspend: 3302 start = __start_pci_fixups_suspend; 3303 end = __end_pci_fixups_suspend; 3304 break; 3305 3306 case pci_fixup_suspend_late: 3307 start = __start_pci_fixups_suspend_late; 3308 end = __end_pci_fixups_suspend_late; 3309 break; 3310 3311 default: 3312 /* stupid compiler warning, you would think with an enum... */ 3313 return; 3314 } 3315 pci_do_fixups(dev, start, end); 3316 } 3317 EXPORT_SYMBOL(pci_fixup_device); 3318 3319 3320 static int __init pci_apply_final_quirks(void) 3321 { 3322 struct pci_dev *dev = NULL; 3323 u8 cls = 0; 3324 u8 tmp; 3325 3326 if (pci_cache_line_size) 3327 printk(KERN_DEBUG "PCI: CLS %u bytes\n", 3328 pci_cache_line_size << 2); 3329 3330 pci_apply_fixup_final_quirks = true; 3331 for_each_pci_dev(dev) { 3332 pci_fixup_device(pci_fixup_final, dev); 3333 /* 3334 * If arch hasn't set it explicitly yet, use the CLS 3335 * value shared by all PCI devices. If there's a 3336 * mismatch, fall back to the default value. 3337 */ 3338 if (!pci_cache_line_size) { 3339 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 3340 if (!cls) 3341 cls = tmp; 3342 if (!tmp || cls == tmp) 3343 continue; 3344 3345 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n", 3346 cls << 2, tmp << 2, 3347 pci_dfl_cache_line_size << 2); 3348 pci_cache_line_size = pci_dfl_cache_line_size; 3349 } 3350 } 3351 3352 if (!pci_cache_line_size) { 3353 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", 3354 cls << 2, pci_dfl_cache_line_size << 2); 3355 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 3356 } 3357 3358 return 0; 3359 } 3360 3361 fs_initcall_sync(pci_apply_final_quirks); 3362 3363 /* 3364 * Followings are device-specific reset methods which can be used to 3365 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3366 * not available. 3367 */ 3368 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 3369 { 3370 /* 3371 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3372 * 3373 * The 82599 supports FLR on VFs, but FLR support is reported only 3374 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3375 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP. 3376 */ 3377 3378 if (probe) 3379 return 0; 3380 3381 if (!pci_wait_for_pending_transaction(dev)) 3382 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); 3383 3384 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 3385 3386 msleep(100); 3387 3388 return 0; 3389 } 3390 3391 #include "../gpu/drm/i915/i915_reg.h" 3392 #define MSG_CTL 0x45010 3393 #define NSDE_PWR_STATE 0xd0100 3394 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3395 3396 static int reset_ivb_igd(struct pci_dev *dev, int probe) 3397 { 3398 void __iomem *mmio_base; 3399 unsigned long timeout; 3400 u32 val; 3401 3402 if (probe) 3403 return 0; 3404 3405 mmio_base = pci_iomap(dev, 0, 0); 3406 if (!mmio_base) 3407 return -ENOMEM; 3408 3409 iowrite32(0x00000002, mmio_base + MSG_CTL); 3410 3411 /* 3412 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3413 * driver loaded sets the right bits. However, this's a reset and 3414 * the bits have been set by i915 previously, so we clobber 3415 * SOUTH_CHICKEN2 register directly here. 3416 */ 3417 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3418 3419 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3420 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3421 3422 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3423 do { 3424 val = ioread32(mmio_base + PCH_PP_STATUS); 3425 if ((val & 0xb0000000) == 0) 3426 goto reset_complete; 3427 msleep(10); 3428 } while (time_before(jiffies, timeout)); 3429 dev_warn(&dev->dev, "timeout during reset\n"); 3430 3431 reset_complete: 3432 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3433 3434 pci_iounmap(dev, mmio_base); 3435 return 0; 3436 } 3437 3438 /* 3439 * Device-specific reset method for Chelsio T4-based adapters. 3440 */ 3441 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) 3442 { 3443 u16 old_command; 3444 u16 msix_flags; 3445 3446 /* 3447 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3448 * that we have no device-specific reset method. 3449 */ 3450 if ((dev->device & 0xf000) != 0x4000) 3451 return -ENOTTY; 3452 3453 /* 3454 * If this is the "probe" phase, return 0 indicating that we can 3455 * reset this device. 3456 */ 3457 if (probe) 3458 return 0; 3459 3460 /* 3461 * T4 can wedge if there are DMAs in flight within the chip and Bus 3462 * Master has been disabled. We need to have it on till the Function 3463 * Level Reset completes. (BUS_MASTER is disabled in 3464 * pci_reset_function()). 3465 */ 3466 pci_read_config_word(dev, PCI_COMMAND, &old_command); 3467 pci_write_config_word(dev, PCI_COMMAND, 3468 old_command | PCI_COMMAND_MASTER); 3469 3470 /* 3471 * Perform the actual device function reset, saving and restoring 3472 * configuration information around the reset. 3473 */ 3474 pci_save_state(dev); 3475 3476 /* 3477 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 3478 * are disabled when an MSI-X interrupt message needs to be delivered. 3479 * So we briefly re-enable MSI-X interrupts for the duration of the 3480 * FLR. The pci_restore_state() below will restore the original 3481 * MSI-X state. 3482 */ 3483 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 3484 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 3485 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 3486 msix_flags | 3487 PCI_MSIX_FLAGS_ENABLE | 3488 PCI_MSIX_FLAGS_MASKALL); 3489 3490 /* 3491 * Start of pcie_flr() code sequence. This reset code is a copy of 3492 * the guts of pcie_flr() because that's not an exported function. 3493 */ 3494 3495 if (!pci_wait_for_pending_transaction(dev)) 3496 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); 3497 3498 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 3499 msleep(100); 3500 3501 /* 3502 * End of pcie_flr() code sequence. 3503 */ 3504 3505 /* 3506 * Restore the configuration information (BAR values, etc.) including 3507 * the original PCI Configuration Space Command word, and return 3508 * success. 3509 */ 3510 pci_restore_state(dev); 3511 pci_write_config_word(dev, PCI_COMMAND, old_command); 3512 return 0; 3513 } 3514 3515 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 3516 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 3517 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 3518 3519 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 3520 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 3521 reset_intel_82599_sfp_virtfn }, 3522 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 3523 reset_ivb_igd }, 3524 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 3525 reset_ivb_igd }, 3526 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 3527 reset_chelsio_generic_dev }, 3528 { 0 } 3529 }; 3530 3531 /* 3532 * These device-specific reset methods are here rather than in a driver 3533 * because when a host assigns a device to a guest VM, the host may need 3534 * to reset the device but probably doesn't have a driver for it. 3535 */ 3536 int pci_dev_specific_reset(struct pci_dev *dev, int probe) 3537 { 3538 const struct pci_dev_reset_methods *i; 3539 3540 for (i = pci_dev_reset_methods; i->reset; i++) { 3541 if ((i->vendor == dev->vendor || 3542 i->vendor == (u16)PCI_ANY_ID) && 3543 (i->device == dev->device || 3544 i->device == (u16)PCI_ANY_ID)) 3545 return i->reset(dev, probe); 3546 } 3547 3548 return -ENOTTY; 3549 } 3550 3551 static void quirk_dma_func0_alias(struct pci_dev *dev) 3552 { 3553 if (PCI_FUNC(dev->devfn) != 0) { 3554 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0); 3555 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; 3556 } 3557 } 3558 3559 /* 3560 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 3561 * 3562 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 3563 */ 3564 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 3565 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 3566 3567 static void quirk_dma_func1_alias(struct pci_dev *dev) 3568 { 3569 if (PCI_FUNC(dev->devfn) != 1) { 3570 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 1); 3571 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; 3572 } 3573 } 3574 3575 /* 3576 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 3577 * SKUs function 1 is present and is a legacy IDE controller, in other 3578 * SKUs this function is not present, making this a ghost requester. 3579 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 3580 */ 3581 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 3582 quirk_dma_func1_alias); 3583 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 3584 quirk_dma_func1_alias); 3585 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 3586 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 3587 quirk_dma_func1_alias); 3588 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 3589 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 3590 quirk_dma_func1_alias); 3591 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 3592 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 3593 quirk_dma_func1_alias); 3594 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 3595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 3596 quirk_dma_func1_alias); 3597 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 3598 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 3599 quirk_dma_func1_alias); 3600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 3601 quirk_dma_func1_alias); 3602 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 3603 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 3604 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 3605 quirk_dma_func1_alias); 3606 3607 /* 3608 * Some devices DMA with the wrong devfn, not just the wrong function. 3609 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 3610 * the alias is "fixed" and independent of the device devfn. 3611 * 3612 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 3613 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 3614 * single device on the secondary bus. In reality, the single exposed 3615 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 3616 * that provides a bridge to the internal bus of the I/O processor. The 3617 * controller supports private devices, which can be hidden from PCI config 3618 * space. In the case of the Adaptec 3405, a private device at 01.0 3619 * appears to be the DMA engine, which therefore needs to become a DMA 3620 * alias for the device. 3621 */ 3622 static const struct pci_device_id fixed_dma_alias_tbl[] = { 3623 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 3624 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 3625 .driver_data = PCI_DEVFN(1, 0) }, 3626 { 0 } 3627 }; 3628 3629 static void quirk_fixed_dma_alias(struct pci_dev *dev) 3630 { 3631 const struct pci_device_id *id; 3632 3633 id = pci_match_id(fixed_dma_alias_tbl, dev); 3634 if (id) { 3635 dev->dma_alias_devfn = id->driver_data; 3636 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; 3637 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n", 3638 PCI_SLOT(dev->dma_alias_devfn), 3639 PCI_FUNC(dev->dma_alias_devfn)); 3640 } 3641 } 3642 3643 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 3644 3645 /* 3646 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 3647 * using the wrong DMA alias for the device. Some of these devices can be 3648 * used as either forward or reverse bridges, so we need to test whether the 3649 * device is operating in the correct mode. We could probably apply this 3650 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 3651 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 3652 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 3653 */ 3654 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 3655 { 3656 if (!pci_is_root_bus(pdev->bus) && 3657 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 3658 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 3659 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 3660 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 3661 } 3662 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 3663 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 3664 quirk_use_pcie_bridge_dma_alias); 3665 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 3666 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 3667 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 3668 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 3669 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 3670 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 3671 3672 /* 3673 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 3674 * class code. Fix it. 3675 */ 3676 static void quirk_tw686x_class(struct pci_dev *pdev) 3677 { 3678 u32 class = pdev->class; 3679 3680 /* Use "Multimedia controller" class */ 3681 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 3682 dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 3683 class, pdev->class); 3684 } 3685 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 3686 quirk_tw686x_class); 3687 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 3688 quirk_tw686x_class); 3689 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 3690 quirk_tw686x_class); 3691 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 3692 quirk_tw686x_class); 3693 3694 /* 3695 * AMD has indicated that the devices below do not support peer-to-peer 3696 * in any system where they are found in the southbridge with an AMD 3697 * IOMMU in the system. Multifunction devices that do not support 3698 * peer-to-peer between functions can claim to support a subset of ACS. 3699 * Such devices effectively enable request redirect (RR) and completion 3700 * redirect (CR) since all transactions are redirected to the upstream 3701 * root complex. 3702 * 3703 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086 3704 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102 3705 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402 3706 * 3707 * 1002:4385 SBx00 SMBus Controller 3708 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 3709 * 1002:4383 SBx00 Azalia (Intel HDA) 3710 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 3711 * 1002:4384 SBx00 PCI to PCI Bridge 3712 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 3713 * 3714 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 3715 * 3716 * 1022:780f [AMD] FCH PCI Bridge 3717 * 1022:7809 [AMD] FCH USB OHCI Controller 3718 */ 3719 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 3720 { 3721 #ifdef CONFIG_ACPI 3722 struct acpi_table_header *header = NULL; 3723 acpi_status status; 3724 3725 /* Targeting multifunction devices on the SB (appears on root bus) */ 3726 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 3727 return -ENODEV; 3728 3729 /* The IVRS table describes the AMD IOMMU */ 3730 status = acpi_get_table("IVRS", 0, &header); 3731 if (ACPI_FAILURE(status)) 3732 return -ENODEV; 3733 3734 /* Filter out flags not applicable to multifunction */ 3735 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 3736 3737 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1; 3738 #else 3739 return -ENODEV; 3740 #endif 3741 } 3742 3743 /* 3744 * Many Intel PCH root ports do provide ACS-like features to disable peer 3745 * transactions and validate bus numbers in requests, but do not provide an 3746 * actual PCIe ACS capability. This is the list of device IDs known to fall 3747 * into that category as provided by Intel in Red Hat bugzilla 1037684. 3748 */ 3749 static const u16 pci_quirk_intel_pch_acs_ids[] = { 3750 /* Ibexpeak PCH */ 3751 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 3752 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 3753 /* Cougarpoint PCH */ 3754 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 3755 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 3756 /* Pantherpoint PCH */ 3757 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 3758 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 3759 /* Lynxpoint-H PCH */ 3760 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 3761 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 3762 /* Lynxpoint-LP PCH */ 3763 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 3764 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 3765 /* Wildcat PCH */ 3766 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 3767 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 3768 /* Patsburg (X79) PCH */ 3769 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 3770 /* Wellsburg (X99) PCH */ 3771 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 3772 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 3773 /* Lynx Point (9 series) PCH */ 3774 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 3775 }; 3776 3777 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 3778 { 3779 int i; 3780 3781 /* Filter out a few obvious non-matches first */ 3782 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 3783 return false; 3784 3785 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 3786 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 3787 return true; 3788 3789 return false; 3790 } 3791 3792 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV) 3793 3794 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 3795 { 3796 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ? 3797 INTEL_PCH_ACS_FLAGS : 0; 3798 3799 if (!pci_quirk_intel_pch_acs_match(dev)) 3800 return -ENOTTY; 3801 3802 return acs_flags & ~flags ? 0 : 1; 3803 } 3804 3805 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 3806 { 3807 /* 3808 * SV, TB, and UF are not relevant to multifunction endpoints. 3809 * 3810 * Multifunction devices are only required to implement RR, CR, and DT 3811 * in their ACS capability if they support peer-to-peer transactions. 3812 * Devices matching this quirk have been verified by the vendor to not 3813 * perform peer-to-peer with other functions, allowing us to mask out 3814 * these bits as if they were unimplemented in the ACS capability. 3815 */ 3816 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 3817 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 3818 3819 return acs_flags ? 0 : 1; 3820 } 3821 3822 static const struct pci_dev_acs_enabled { 3823 u16 vendor; 3824 u16 device; 3825 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 3826 } pci_dev_acs_enabled[] = { 3827 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 3828 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 3829 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 3830 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 3831 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 3832 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 3833 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 3834 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 3835 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 3836 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 3837 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 3838 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 3839 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 3840 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 3841 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 3842 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 3843 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 3844 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 3845 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 3846 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 3847 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 3848 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 3849 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 3850 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 3851 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 3852 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 3853 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 3854 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 3855 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 3856 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 3857 /* 82580 */ 3858 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 3859 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 3860 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 3861 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 3862 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 3863 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 3864 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 3865 /* 82576 */ 3866 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 3867 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 3868 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 3869 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 3870 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 3871 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 3872 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 3873 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 3874 /* 82575 */ 3875 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 3876 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 3877 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 3878 /* I350 */ 3879 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 3880 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 3881 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 3882 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 3883 /* 82571 (Quads omitted due to non-ACS switch) */ 3884 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 3885 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 3886 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 3887 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 3888 /* I219 */ 3889 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 3890 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 3891 /* Intel PCH root ports */ 3892 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 3893 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 3894 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 3895 { 0 } 3896 }; 3897 3898 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 3899 { 3900 const struct pci_dev_acs_enabled *i; 3901 int ret; 3902 3903 /* 3904 * Allow devices that do not expose standard PCIe ACS capabilities 3905 * or control to indicate their support here. Multi-function express 3906 * devices which do not allow internal peer-to-peer between functions, 3907 * but do not implement PCIe ACS may wish to return true here. 3908 */ 3909 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 3910 if ((i->vendor == dev->vendor || 3911 i->vendor == (u16)PCI_ANY_ID) && 3912 (i->device == dev->device || 3913 i->device == (u16)PCI_ANY_ID)) { 3914 ret = i->acs_enabled(dev, acs_flags); 3915 if (ret >= 0) 3916 return ret; 3917 } 3918 } 3919 3920 return -ENOTTY; 3921 } 3922 3923 /* Config space offset of Root Complex Base Address register */ 3924 #define INTEL_LPC_RCBA_REG 0xf0 3925 /* 31:14 RCBA address */ 3926 #define INTEL_LPC_RCBA_MASK 0xffffc000 3927 /* RCBA Enable */ 3928 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 3929 3930 /* Backbone Scratch Pad Register */ 3931 #define INTEL_BSPR_REG 0x1104 3932 /* Backbone Peer Non-Posted Disable */ 3933 #define INTEL_BSPR_REG_BPNPD (1 << 8) 3934 /* Backbone Peer Posted Disable */ 3935 #define INTEL_BSPR_REG_BPPD (1 << 9) 3936 3937 /* Upstream Peer Decode Configuration Register */ 3938 #define INTEL_UPDCR_REG 0x1114 3939 /* 5:0 Peer Decode Enable bits */ 3940 #define INTEL_UPDCR_REG_MASK 0x3f 3941 3942 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 3943 { 3944 u32 rcba, bspr, updcr; 3945 void __iomem *rcba_mem; 3946 3947 /* 3948 * Read the RCBA register from the LPC (D31:F0). PCH root ports 3949 * are D28:F* and therefore get probed before LPC, thus we can't 3950 * use pci_get_slot/pci_read_config_dword here. 3951 */ 3952 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 3953 INTEL_LPC_RCBA_REG, &rcba); 3954 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 3955 return -EINVAL; 3956 3957 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK, 3958 PAGE_ALIGN(INTEL_UPDCR_REG)); 3959 if (!rcba_mem) 3960 return -ENOMEM; 3961 3962 /* 3963 * The BSPR can disallow peer cycles, but it's set by soft strap and 3964 * therefore read-only. If both posted and non-posted peer cycles are 3965 * disallowed, we're ok. If either are allowed, then we need to use 3966 * the UPDCR to disable peer decodes for each port. This provides the 3967 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 3968 */ 3969 bspr = readl(rcba_mem + INTEL_BSPR_REG); 3970 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 3971 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 3972 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 3973 if (updcr & INTEL_UPDCR_REG_MASK) { 3974 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n"); 3975 updcr &= ~INTEL_UPDCR_REG_MASK; 3976 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 3977 } 3978 } 3979 3980 iounmap(rcba_mem); 3981 return 0; 3982 } 3983 3984 /* Miscellaneous Port Configuration register */ 3985 #define INTEL_MPC_REG 0xd8 3986 /* MPC: Invalid Receive Bus Number Check Enable */ 3987 #define INTEL_MPC_REG_IRBNCE (1 << 26) 3988 3989 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 3990 { 3991 u32 mpc; 3992 3993 /* 3994 * When enabled, the IRBNCE bit of the MPC register enables the 3995 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 3996 * ensures that requester IDs fall within the bus number range 3997 * of the bridge. Enable if not already. 3998 */ 3999 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 4000 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 4001 dev_info(&dev->dev, "Enabling MPC IRBNCE\n"); 4002 mpc |= INTEL_MPC_REG_IRBNCE; 4003 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 4004 } 4005 } 4006 4007 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 4008 { 4009 if (!pci_quirk_intel_pch_acs_match(dev)) 4010 return -ENOTTY; 4011 4012 if (pci_quirk_enable_intel_lpc_acs(dev)) { 4013 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n"); 4014 return 0; 4015 } 4016 4017 pci_quirk_enable_intel_rp_mpc_acs(dev); 4018 4019 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 4020 4021 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n"); 4022 4023 return 0; 4024 } 4025 4026 static const struct pci_dev_enable_acs { 4027 u16 vendor; 4028 u16 device; 4029 int (*enable_acs)(struct pci_dev *dev); 4030 } pci_dev_enable_acs[] = { 4031 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs }, 4032 { 0 } 4033 }; 4034 4035 void pci_dev_specific_enable_acs(struct pci_dev *dev) 4036 { 4037 const struct pci_dev_enable_acs *i; 4038 int ret; 4039 4040 for (i = pci_dev_enable_acs; i->enable_acs; i++) { 4041 if ((i->vendor == dev->vendor || 4042 i->vendor == (u16)PCI_ANY_ID) && 4043 (i->device == dev->device || 4044 i->device == (u16)PCI_ANY_ID)) { 4045 ret = i->enable_acs(dev); 4046 if (ret >= 0) 4047 return; 4048 } 4049 } 4050 } 4051 4052 /* 4053 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with 4054 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 4055 * Next Capability pointer in the MSI Capability Structure should point to 4056 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 4057 * the list. 4058 */ 4059 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 4060 { 4061 int pos, i = 0; 4062 u8 next_cap; 4063 u16 reg16, *cap; 4064 struct pci_cap_saved_state *state; 4065 4066 /* Bail if the hardware bug is fixed */ 4067 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 4068 return; 4069 4070 /* Bail if MSI Capability Structure is not found for some reason */ 4071 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 4072 if (!pos) 4073 return; 4074 4075 /* 4076 * Bail if Next Capability pointer in the MSI Capability Structure 4077 * is not the expected incorrect 0x00. 4078 */ 4079 pci_read_config_byte(pdev, pos + 1, &next_cap); 4080 if (next_cap) 4081 return; 4082 4083 /* 4084 * PCIe Capability Structure is expected to be at 0x50 and should 4085 * terminate the list (Next Capability pointer is 0x00). Verify 4086 * Capability Id and Next Capability pointer is as expected. 4087 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 4088 * to correctly set kernel data structures which have already been 4089 * set incorrectly due to the hardware bug. 4090 */ 4091 pos = 0x50; 4092 pci_read_config_word(pdev, pos, ®16); 4093 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 4094 u32 status; 4095 #ifndef PCI_EXP_SAVE_REGS 4096 #define PCI_EXP_SAVE_REGS 7 4097 #endif 4098 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 4099 4100 pdev->pcie_cap = pos; 4101 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 4102 pdev->pcie_flags_reg = reg16; 4103 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 4104 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 4105 4106 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 4107 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) != 4108 PCIBIOS_SUCCESSFUL || (status == 0xffffffff)) 4109 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 4110 4111 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 4112 return; 4113 4114 /* 4115 * Save PCIE cap 4116 */ 4117 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 4118 if (!state) 4119 return; 4120 4121 state->cap.cap_nr = PCI_CAP_ID_EXP; 4122 state->cap.cap_extended = 0; 4123 state->cap.size = size; 4124 cap = (u16 *)&state->cap.data[0]; 4125 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 4126 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 4127 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 4128 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 4129 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 4130 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 4131 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 4132 hlist_add_head(&state->next, &pdev->saved_cap_space); 4133 } 4134 } 4135 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 4136