1 /* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * The bridge optimization stuff has been removed. If you really 11 * have a silly BIOS which is unable to set your host bridge right, 12 * use the PowerTweak utility (see http://powertweak.sourceforge.net). 13 */ 14 15 #include <linux/config.h> 16 #include <linux/types.h> 17 #include <linux/kernel.h> 18 #include <linux/pci.h> 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/acpi.h> 22 #include "pci.h" 23 24 /* Deal with broken BIOS'es that neglect to enable passive release, 25 which can cause problems in combination with the 82441FX/PPro MTRRs */ 26 static void __devinit quirk_passive_release(struct pci_dev *dev) 27 { 28 struct pci_dev *d = NULL; 29 unsigned char dlc; 30 31 /* We have to make sure a particular bit is set in the PIIX3 32 ISA bridge, so we have to go out and find it. */ 33 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 34 pci_read_config_byte(d, 0x82, &dlc); 35 if (!(dlc & 1<<1)) { 36 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d)); 37 dlc |= 1<<1; 38 pci_write_config_byte(d, 0x82, dlc); 39 } 40 } 41 } 42 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release ); 43 44 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 45 but VIA don't answer queries. If you happen to have good contacts at VIA 46 ask them for me please -- Alan 47 48 This appears to be BIOS not version dependent. So presumably there is a 49 chipset level fix */ 50 int isa_dma_bridge_buggy; /* Exported */ 51 52 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) 53 { 54 if (!isa_dma_bridge_buggy) { 55 isa_dma_bridge_buggy=1; 56 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n"); 57 } 58 } 59 /* 60 * Its not totally clear which chipsets are the problematic ones 61 * We know 82C586 and 82C596 variants are affected. 62 */ 63 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs ); 64 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs ); 65 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs ); 66 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs ); 67 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs ); 68 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs ); 69 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs ); 70 71 int pci_pci_problems; 72 73 /* 74 * Chipsets where PCI->PCI transfers vanish or hang 75 */ 76 static void __devinit quirk_nopcipci(struct pci_dev *dev) 77 { 78 if ((pci_pci_problems & PCIPCI_FAIL)==0) { 79 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n"); 80 pci_pci_problems |= PCIPCI_FAIL; 81 } 82 } 83 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci ); 84 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci ); 85 86 /* 87 * Triton requires workarounds to be used by the drivers 88 */ 89 static void __devinit quirk_triton(struct pci_dev *dev) 90 { 91 if ((pci_pci_problems&PCIPCI_TRITON)==0) { 92 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 93 pci_pci_problems |= PCIPCI_TRITON; 94 } 95 } 96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton ); 97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton ); 98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton ); 99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton ); 100 101 /* 102 * VIA Apollo KT133 needs PCI latency patch 103 * Made according to a windows driver based patch by George E. Breese 104 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 105 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 106 * the info on which Mr Breese based his work. 107 * 108 * Updated based on further information from the site and also on 109 * information provided by VIA 110 */ 111 static void __devinit quirk_vialatency(struct pci_dev *dev) 112 { 113 struct pci_dev *p; 114 u8 rev; 115 u8 busarb; 116 /* Ok we have a potential problem chipset here. Now see if we have 117 a buggy southbridge */ 118 119 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 120 if (p!=NULL) { 121 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); 122 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 123 /* Check for buggy part revisions */ 124 if (rev < 0x40 || rev > 0x42) 125 goto exit; 126 } else { 127 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 128 if (p==NULL) /* No problem parts */ 129 goto exit; 130 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); 131 /* Check for buggy part revisions */ 132 if (rev < 0x10 || rev > 0x12) 133 goto exit; 134 } 135 136 /* 137 * Ok we have the problem. Now set the PCI master grant to 138 * occur every master grant. The apparent bug is that under high 139 * PCI load (quite common in Linux of course) you can get data 140 * loss when the CPU is held off the bus for 3 bus master requests 141 * This happens to include the IDE controllers.... 142 * 143 * VIA only apply this fix when an SB Live! is present but under 144 * both Linux and Windows this isnt enough, and we have seen 145 * corruption without SB Live! but with things like 3 UDMA IDE 146 * controllers. So we ignore that bit of the VIA recommendation.. 147 */ 148 149 pci_read_config_byte(dev, 0x76, &busarb); 150 /* Set bit 4 and bi 5 of byte 76 to 0x01 151 "Master priority rotation on every PCI master grant */ 152 busarb &= ~(1<<5); 153 busarb |= (1<<4); 154 pci_write_config_byte(dev, 0x76, busarb); 155 printk(KERN_INFO "Applying VIA southbridge workaround.\n"); 156 exit: 157 pci_dev_put(p); 158 } 159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency ); 160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency ); 161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency ); 162 163 /* 164 * VIA Apollo VP3 needs ETBF on BT848/878 165 */ 166 static void __devinit quirk_viaetbf(struct pci_dev *dev) 167 { 168 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { 169 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 170 pci_pci_problems |= PCIPCI_VIAETBF; 171 } 172 } 173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf ); 174 175 static void __devinit quirk_vsfx(struct pci_dev *dev) 176 { 177 if ((pci_pci_problems&PCIPCI_VSFX)==0) { 178 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 179 pci_pci_problems |= PCIPCI_VSFX; 180 } 181 } 182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx ); 183 184 /* 185 * Ali Magik requires workarounds to be used by the drivers 186 * that DMA to AGP space. Latency must be set to 0xA and triton 187 * workaround applied too 188 * [Info kindly provided by ALi] 189 */ 190 static void __init quirk_alimagik(struct pci_dev *dev) 191 { 192 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { 193 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 194 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 195 } 196 } 197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik ); 198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik ); 199 200 /* 201 * Natoma has some interesting boundary conditions with Zoran stuff 202 * at least 203 */ 204 static void __devinit quirk_natoma(struct pci_dev *dev) 205 { 206 if ((pci_pci_problems&PCIPCI_NATOMA)==0) { 207 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 208 pci_pci_problems |= PCIPCI_NATOMA; 209 } 210 } 211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma ); 212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma ); 213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma ); 214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma ); 215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma ); 216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma ); 217 218 /* 219 * This chip can cause PCI parity errors if config register 0xA0 is read 220 * while DMAs are occurring. 221 */ 222 static void __devinit quirk_citrine(struct pci_dev *dev) 223 { 224 dev->cfg_size = 0xA0; 225 } 226 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine ); 227 228 /* 229 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 230 * If it's needed, re-allocate the region. 231 */ 232 static void __devinit quirk_s3_64M(struct pci_dev *dev) 233 { 234 struct resource *r = &dev->resource[0]; 235 236 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 237 r->start = 0; 238 r->end = 0x3ffffff; 239 } 240 } 241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M ); 242 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M ); 243 244 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr) 245 { 246 region &= ~(size-1); 247 if (region) { 248 struct resource *res = dev->resource + nr; 249 250 res->name = pci_name(dev); 251 res->start = region; 252 res->end = region + size - 1; 253 res->flags = IORESOURCE_IO; 254 pci_claim_resource(dev, nr); 255 } 256 } 257 258 /* 259 * ATI Northbridge setups MCE the processor if you even 260 * read somewhere between 0x3b0->0x3bb or read 0x3d3 261 */ 262 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) 263 { 264 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n"); 265 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 266 request_region(0x3b0, 0x0C, "RadeonIGP"); 267 request_region(0x3d3, 0x01, "RadeonIGP"); 268 } 269 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce ); 270 271 /* 272 * Let's make the southbridge information explicit instead 273 * of having to worry about people probing the ACPI areas, 274 * for example.. (Yes, it happens, and if you read the wrong 275 * ACPI register it will put the machine to sleep with no 276 * way of waking it up again. Bummer). 277 * 278 * ALI M7101: Two IO regions pointed to by words at 279 * 0xE0 (64 bytes of ACPI registers) 280 * 0xE2 (32 bytes of SMB registers) 281 */ 282 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) 283 { 284 u16 region; 285 286 pci_read_config_word(dev, 0xE0, ®ion); 287 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES); 288 pci_read_config_word(dev, 0xE2, ®ion); 289 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1); 290 } 291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi ); 292 293 /* 294 * PIIX4 ACPI: Two IO regions pointed to by longwords at 295 * 0x40 (64 bytes of ACPI registers) 296 * 0x90 (32 bytes of SMB registers) 297 */ 298 static void __devinit quirk_piix4_acpi(struct pci_dev *dev) 299 { 300 u32 region; 301 302 pci_read_config_dword(dev, 0x40, ®ion); 303 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES); 304 pci_read_config_dword(dev, 0x90, ®ion); 305 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1); 306 } 307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi ); 308 309 /* 310 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 311 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 312 * 0x58 (64 bytes of GPIO I/O space) 313 */ 314 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) 315 { 316 u32 region; 317 318 pci_read_config_dword(dev, 0x40, ®ion); 319 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES); 320 321 pci_read_config_dword(dev, 0x58, ®ion); 322 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1); 323 } 324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi ); 325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi ); 326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi ); 327 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi ); 328 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi ); 329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi ); 330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi ); 331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi ); 332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi ); 333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi ); 334 335 /* 336 * VIA ACPI: One IO region pointed to by longword at 337 * 0x48 or 0x20 (256 bytes of ACPI registers) 338 */ 339 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) 340 { 341 u8 rev; 342 u32 region; 343 344 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); 345 if (rev & 0x10) { 346 pci_read_config_dword(dev, 0x48, ®ion); 347 region &= PCI_BASE_ADDRESS_IO_MASK; 348 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES); 349 } 350 } 351 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi ); 352 353 /* 354 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 355 * 0x48 (256 bytes of ACPI registers) 356 * 0x70 (128 bytes of hardware monitoring register) 357 * 0x90 (16 bytes of SMB registers) 358 */ 359 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) 360 { 361 u16 hm; 362 u32 smb; 363 364 quirk_vt82c586_acpi(dev); 365 366 pci_read_config_word(dev, 0x70, &hm); 367 hm &= PCI_BASE_ADDRESS_IO_MASK; 368 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1); 369 370 pci_read_config_dword(dev, 0x90, &smb); 371 smb &= PCI_BASE_ADDRESS_IO_MASK; 372 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2); 373 } 374 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi ); 375 376 377 #ifdef CONFIG_X86_IO_APIC 378 379 #include <asm/io_apic.h> 380 381 /* 382 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 383 * devices to the external APIC. 384 * 385 * TODO: When we have device-specific interrupt routers, 386 * this code will go away from quirks. 387 */ 388 static void __devinit quirk_via_ioapic(struct pci_dev *dev) 389 { 390 u8 tmp; 391 392 if (nr_ioapics < 1) 393 tmp = 0; /* nothing routed to external APIC */ 394 else 395 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 396 397 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n", 398 tmp == 0 ? "Disa" : "Ena"); 399 400 /* Offset 0x58: External APIC IRQ output control */ 401 pci_write_config_byte (dev, 0x58, tmp); 402 } 403 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); 404 405 /* 406 * The AMD io apic can hang the box when an apic irq is masked. 407 * We check all revs >= B0 (yet not in the pre production!) as the bug 408 * is currently marked NoFix 409 * 410 * We have multiple reports of hangs with this chipset that went away with 411 * noapic specified. For the moment we assume its the errata. We may be wrong 412 * of course. However the advice is demonstrably good even if so.. 413 */ 414 static void __devinit quirk_amd_ioapic(struct pci_dev *dev) 415 { 416 u8 rev; 417 418 pci_read_config_byte(dev, PCI_REVISION_ID, &rev); 419 if (rev >= 0x02) { 420 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n"); 421 printk(KERN_WARNING " : booting with the \"noapic\" option.\n"); 422 } 423 } 424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic ); 425 426 static void __init quirk_ioapic_rmw(struct pci_dev *dev) 427 { 428 if (dev->devfn == 0 && dev->bus->number == 0) 429 sis_apic_bug = 1; 430 } 431 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw ); 432 433 int pci_msi_quirk; 434 435 #define AMD8131_revA0 0x01 436 #define AMD8131_revB0 0x11 437 #define AMD8131_MISC 0x40 438 #define AMD8131_NIOAMODE_BIT 0 439 static void __init quirk_amd_8131_ioapic(struct pci_dev *dev) 440 { 441 unsigned char revid, tmp; 442 443 pci_msi_quirk = 1; 444 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n"); 445 446 if (nr_ioapics == 0) 447 return; 448 449 pci_read_config_byte(dev, PCI_REVISION_ID, &revid); 450 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) { 451 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n"); 452 pci_read_config_byte( dev, AMD8131_MISC, &tmp); 453 tmp &= ~(1 << AMD8131_NIOAMODE_BIT); 454 pci_write_config_byte( dev, AMD8131_MISC, tmp); 455 } 456 } 457 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC, quirk_amd_8131_ioapic ); 458 459 static void __init quirk_svw_msi(struct pci_dev *dev) 460 { 461 pci_msi_quirk = 1; 462 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n"); 463 } 464 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi ); 465 #endif /* CONFIG_X86_IO_APIC */ 466 467 468 /* 469 * FIXME: it is questionable that quirk_via_acpi 470 * is needed. It shows up as an ISA bridge, and does not 471 * support the PCI_INTERRUPT_LINE register at all. Therefore 472 * it seems like setting the pci_dev's 'irq' to the 473 * value of the ACPI SCI interrupt is only done for convenience. 474 * -jgarzik 475 */ 476 static void __devinit quirk_via_acpi(struct pci_dev *d) 477 { 478 /* 479 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 480 */ 481 u8 irq; 482 pci_read_config_byte(d, 0x42, &irq); 483 irq &= 0xf; 484 if (irq && (irq != 2)) 485 d->irq = irq; 486 } 487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi ); 488 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi ); 489 490 /* 491 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip 492 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature: 493 * when written, it makes an internal connection to the PIC. 494 * For these devices, this register is defined to be 4 bits wide. 495 * Normally this is fine. However for IO-APIC motherboards, or 496 * non-x86 architectures (yes Via exists on PPC among other places), 497 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get 498 * interrupts delivered properly. 499 */ 500 static void quirk_via_irq(struct pci_dev *dev) 501 { 502 u8 irq, new_irq; 503 504 new_irq = dev->irq & 0xf; 505 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 506 if (new_irq != irq) { 507 printk(KERN_INFO "PCI: Via IRQ fixup for %s, from %d to %d\n", 508 pci_name(dev), irq, new_irq); 509 udelay(15); /* unknown if delay really needed */ 510 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 511 } 512 } 513 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_irq); 514 515 /* 516 * PIIX3 USB: We have to disable USB interrupts that are 517 * hardwired to PIRQD# and may be shared with an 518 * external device. 519 * 520 * Legacy Support Register (LEGSUP): 521 * bit13: USB PIRQ Enable (USBPIRQDEN), 522 * bit4: Trap/SMI On IRQ Enable (USBSMIEN). 523 * 524 * We mask out all r/wc bits, too. 525 */ 526 static void __devinit quirk_piix3_usb(struct pci_dev *dev) 527 { 528 u16 legsup; 529 530 pci_read_config_word(dev, 0xc0, &legsup); 531 legsup &= 0x50ef; 532 pci_write_config_word(dev, 0xc0, legsup); 533 } 534 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb ); 535 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb ); 536 537 /* 538 * VIA VT82C598 has its device ID settable and many BIOSes 539 * set it to the ID of VT82C597 for backward compatibility. 540 * We need to switch it off to be able to recognize the real 541 * type of the chip. 542 */ 543 static void __devinit quirk_vt82c598_id(struct pci_dev *dev) 544 { 545 pci_write_config_byte(dev, 0xfc, 0); 546 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 547 } 548 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id ); 549 550 /* 551 * CardBus controllers have a legacy base address that enables them 552 * to respond as i82365 pcmcia controllers. We don't want them to 553 * do this even if the Linux CardBus driver is not loaded, because 554 * the Linux i82365 driver does not (and should not) handle CardBus. 555 */ 556 static void __devinit quirk_cardbus_legacy(struct pci_dev *dev) 557 { 558 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) 559 return; 560 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 561 } 562 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); 563 564 /* 565 * Following the PCI ordering rules is optional on the AMD762. I'm not 566 * sure what the designers were smoking but let's not inhale... 567 * 568 * To be fair to AMD, it follows the spec by default, its BIOS people 569 * who turn it off! 570 */ 571 static void __devinit quirk_amd_ordering(struct pci_dev *dev) 572 { 573 u32 pcic; 574 pci_read_config_dword(dev, 0x4C, &pcic); 575 if ((pcic&6)!=6) { 576 pcic |= 6; 577 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n"); 578 pci_write_config_dword(dev, 0x4C, pcic); 579 pci_read_config_dword(dev, 0x84, &pcic); 580 pcic |= (1<<23); /* Required in this mode */ 581 pci_write_config_dword(dev, 0x84, pcic); 582 } 583 } 584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering ); 585 586 /* 587 * DreamWorks provided workaround for Dunord I-3000 problem 588 * 589 * This card decodes and responds to addresses not apparently 590 * assigned to it. We force a larger allocation to ensure that 591 * nothing gets put too close to it. 592 */ 593 static void __devinit quirk_dunord ( struct pci_dev * dev ) 594 { 595 struct resource *r = &dev->resource [1]; 596 r->start = 0; 597 r->end = 0xffffff; 598 } 599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord ); 600 601 /* 602 * i82380FB mobile docking controller: its PCI-to-PCI bridge 603 * is subtractive decoding (transparent), and does indicate this 604 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 605 * instead of 0x01. 606 */ 607 static void __devinit quirk_transparent_bridge(struct pci_dev *dev) 608 { 609 dev->transparent = 1; 610 } 611 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge ); 612 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge ); 613 614 /* 615 * Common misconfiguration of the MediaGX/Geode PCI master that will 616 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 617 * datasheets found at http://www.national.com/ds/GX for info on what 618 * these bits do. <christer@weinigel.se> 619 */ 620 static void __init quirk_mediagx_master(struct pci_dev *dev) 621 { 622 u8 reg; 623 pci_read_config_byte(dev, 0x41, ®); 624 if (reg & 2) { 625 reg &= ~2; 626 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); 627 pci_write_config_byte(dev, 0x41, reg); 628 } 629 } 630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); 631 632 /* 633 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers 634 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and 635 * secondary channels respectively). If the device reports Compatible mode 636 * but does use BAR0-3 for address decoding, we assume that firmware has 637 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374). 638 * Exceptions (if they exist) must be handled in chip/architecture specific 639 * fixups. 640 * 641 * Note: for non x86 people. You may need an arch specific quirk to handle 642 * moving IDE devices to native mode as well. Some plug in card devices power 643 * up in compatible mode and assume the BIOS will adjust them. 644 * 645 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as 646 * we do now ? We don't want is pci_enable_device to come along 647 * and assign new resources. Both approaches work for that. 648 */ 649 static void __devinit quirk_ide_bases(struct pci_dev *dev) 650 { 651 struct resource *res; 652 int first_bar = 2, last_bar = 0; 653 654 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) 655 return; 656 657 res = &dev->resource[0]; 658 659 /* primary channel: ProgIf bit 0, BAR0, BAR1 */ 660 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) { 661 res[0].start = res[0].end = res[0].flags = 0; 662 res[1].start = res[1].end = res[1].flags = 0; 663 first_bar = 0; 664 last_bar = 1; 665 } 666 667 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */ 668 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) { 669 res[2].start = res[2].end = res[2].flags = 0; 670 res[3].start = res[3].end = res[3].flags = 0; 671 last_bar = 3; 672 } 673 674 if (!last_bar) 675 return; 676 677 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n", 678 first_bar, last_bar, pci_name(dev)); 679 } 680 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases); 681 682 /* 683 * Ensure C0 rev restreaming is off. This is normally done by 684 * the BIOS but in the odd case it is not the results are corruption 685 * hence the presence of a Linux check 686 */ 687 static void __init quirk_disable_pxb(struct pci_dev *pdev) 688 { 689 u16 config; 690 u8 rev; 691 692 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); 693 if (rev != 0x04) /* Only C0 requires this */ 694 return; 695 pci_read_config_word(pdev, 0x40, &config); 696 if (config & (1<<6)) { 697 config &= ~(1<<6); 698 pci_write_config_word(pdev, 0x40, config); 699 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n"); 700 } 701 } 702 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb ); 703 704 705 /* 706 * Serverworks CSB5 IDE does not fully support native mode 707 */ 708 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) 709 { 710 u8 prog; 711 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 712 if (prog & 5) { 713 prog &= ~5; 714 pdev->class &= ~5; 715 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 716 /* need to re-assign BARs for compat mode */ 717 quirk_ide_bases(pdev); 718 } 719 } 720 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide ); 721 722 /* 723 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 724 */ 725 static void __init quirk_ide_samemode(struct pci_dev *pdev) 726 { 727 u8 prog; 728 729 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 730 731 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 732 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n"); 733 prog &= ~5; 734 pdev->class &= ~5; 735 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 736 /* need to re-assign BARs for compat mode */ 737 quirk_ide_bases(pdev); 738 } 739 } 740 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 741 742 /* This was originally an Alpha specific thing, but it really fits here. 743 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 744 */ 745 static void __init quirk_eisa_bridge(struct pci_dev *dev) 746 { 747 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 748 } 749 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge ); 750 751 /* 752 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 753 * is not activated. The myth is that Asus said that they do not want the 754 * users to be irritated by just another PCI Device in the Win98 device 755 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 756 * package 2.7.0 for details) 757 * 758 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 759 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 760 * becomes necessary to do this tweak in two steps -- I've chosen the Host 761 * bridge as trigger. 762 */ 763 static int __initdata asus_hides_smbus = 0; 764 765 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) 766 { 767 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 768 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 769 switch(dev->subsystem_device) { 770 case 0x8070: /* P4B */ 771 case 0x8088: /* P4B533 */ 772 case 0x1626: /* L3C notebook */ 773 asus_hides_smbus = 1; 774 } 775 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 776 switch(dev->subsystem_device) { 777 case 0x80b1: /* P4GE-V */ 778 case 0x80b2: /* P4PE */ 779 case 0x8093: /* P4B533-V */ 780 asus_hides_smbus = 1; 781 } 782 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 783 switch(dev->subsystem_device) { 784 case 0x8030: /* P4T533 */ 785 asus_hides_smbus = 1; 786 } 787 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 788 switch (dev->subsystem_device) { 789 case 0x8070: /* P4G8X Deluxe */ 790 asus_hides_smbus = 1; 791 } 792 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 793 switch (dev->subsystem_device) { 794 case 0x1751: /* M2N notebook */ 795 case 0x1821: /* M5N notebook */ 796 asus_hides_smbus = 1; 797 } 798 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 799 switch (dev->subsystem_device) { 800 case 0x184b: /* W1N notebook */ 801 case 0x186a: /* M6Ne notebook */ 802 asus_hides_smbus = 1; 803 } 804 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 805 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 806 switch(dev->subsystem_device) { 807 case 0x088C: /* HP Compaq nc8000 */ 808 case 0x0890: /* HP Compaq nc6000 */ 809 asus_hides_smbus = 1; 810 } 811 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 812 switch (dev->subsystem_device) { 813 case 0x12bc: /* HP D330L */ 814 asus_hides_smbus = 1; 815 } 816 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) { 817 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 818 switch(dev->subsystem_device) { 819 case 0x0001: /* Toshiba Satellite A40 */ 820 asus_hides_smbus = 1; 821 } 822 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 823 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 824 switch(dev->subsystem_device) { 825 case 0xC00C: /* Samsung P35 notebook */ 826 asus_hides_smbus = 1; 827 } 828 } 829 } 830 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge ); 831 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge ); 832 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge ); 833 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge ); 834 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge ); 835 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge ); 836 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge ); 837 838 static void __init asus_hides_smbus_lpc(struct pci_dev *dev) 839 { 840 u16 val; 841 842 if (likely(!asus_hides_smbus)) 843 return; 844 845 pci_read_config_word(dev, 0xF2, &val); 846 if (val & 0x8) { 847 pci_write_config_word(dev, 0xF2, val & (~0x8)); 848 pci_read_config_word(dev, 0xF2, &val); 849 if (val & 0x8) 850 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); 851 else 852 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n"); 853 } 854 } 855 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); 856 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); 857 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); 858 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); 859 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); 860 861 /* 862 * SiS 96x south bridge: BIOS typically hides SMBus device... 863 */ 864 static void __init quirk_sis_96x_smbus(struct pci_dev *dev) 865 { 866 u8 val = 0; 867 printk(KERN_INFO "Enabling SiS 96x SMBus.\n"); 868 pci_read_config_byte(dev, 0x77, &val); 869 pci_write_config_byte(dev, 0x77, val & ~0x10); 870 pci_read_config_byte(dev, 0x77, &val); 871 } 872 873 874 #define UHCI_USBLEGSUP 0xc0 /* legacy support */ 875 #define UHCI_USBCMD 0 /* command register */ 876 #define UHCI_USBSTS 2 /* status register */ 877 #define UHCI_USBINTR 4 /* interrupt register */ 878 #define UHCI_USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ 879 #define UHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */ 880 #define UHCI_USBCMD_GRESET (1 << 2) /* Global reset */ 881 #define UHCI_USBCMD_CONFIGURE (1 << 6) /* config semaphore */ 882 #define UHCI_USBSTS_HALTED (1 << 5) /* HCHalted bit */ 883 884 #define OHCI_CONTROL 0x04 885 #define OHCI_CMDSTATUS 0x08 886 #define OHCI_INTRSTATUS 0x0c 887 #define OHCI_INTRENABLE 0x10 888 #define OHCI_INTRDISABLE 0x14 889 #define OHCI_OCR (1 << 3) /* ownership change request */ 890 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ 891 #define OHCI_INTR_OC (1 << 30) /* ownership change */ 892 893 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */ 894 #define EHCI_USBCMD 0 /* command register */ 895 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */ 896 #define EHCI_USBSTS 4 /* status register */ 897 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */ 898 #define EHCI_USBINTR 8 /* interrupt register */ 899 #define EHCI_USBLEGSUP 0 /* legacy support register */ 900 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */ 901 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */ 902 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */ 903 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */ 904 905 int usb_early_handoff __devinitdata = 0; 906 static int __init usb_handoff_early(char *str) 907 { 908 usb_early_handoff = 1; 909 return 0; 910 } 911 __setup("usb-handoff", usb_handoff_early); 912 913 static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev) 914 { 915 unsigned long base = 0; 916 int wait_time, delta; 917 u16 val, sts; 918 int i; 919 920 for (i = 0; i < PCI_ROM_RESOURCE; i++) 921 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) { 922 base = pci_resource_start(pdev, i); 923 break; 924 } 925 926 if (!base) 927 return; 928 929 /* 930 * stop controller 931 */ 932 sts = inw(base + UHCI_USBSTS); 933 val = inw(base + UHCI_USBCMD); 934 val &= ~(u16)(UHCI_USBCMD_RUN | UHCI_USBCMD_CONFIGURE); 935 outw(val, base + UHCI_USBCMD); 936 937 /* 938 * wait while it stops if it was running 939 */ 940 if ((sts & UHCI_USBSTS_HALTED) == 0) 941 { 942 wait_time = 1000; 943 delta = 100; 944 945 do { 946 outw(0x1f, base + UHCI_USBSTS); 947 udelay(delta); 948 wait_time -= delta; 949 val = inw(base + UHCI_USBSTS); 950 if (val & UHCI_USBSTS_HALTED) 951 break; 952 } while (wait_time > 0); 953 } 954 955 /* 956 * disable interrupts & legacy support 957 */ 958 outw(0, base + UHCI_USBINTR); 959 outw(0x1f, base + UHCI_USBSTS); 960 pci_read_config_word(pdev, UHCI_USBLEGSUP, &val); 961 if (val & 0xbf) 962 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_DEFAULT); 963 964 } 965 966 static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev) 967 { 968 void __iomem *base; 969 int wait_time; 970 971 base = ioremap_nocache(pci_resource_start(pdev, 0), 972 pci_resource_len(pdev, 0)); 973 if (base == NULL) return; 974 975 if (readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) { 976 wait_time = 500; /* 0.5 seconds */ 977 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE); 978 writel(OHCI_OCR, base + OHCI_CMDSTATUS); 979 while (wait_time > 0 && 980 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) { 981 wait_time -= 10; 982 msleep(10); 983 } 984 } 985 986 /* 987 * disable interrupts 988 */ 989 writel(~(u32)0, base + OHCI_INTRDISABLE); 990 writel(~(u32)0, base + OHCI_INTRSTATUS); 991 992 iounmap(base); 993 } 994 995 static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev) 996 { 997 int wait_time, delta; 998 void __iomem *base, *op_reg_base; 999 u32 hcc_params, val, temp; 1000 u8 cap_length; 1001 1002 base = ioremap_nocache(pci_resource_start(pdev, 0), 1003 pci_resource_len(pdev, 0)); 1004 if (base == NULL) return; 1005 1006 cap_length = readb(base); 1007 op_reg_base = base + cap_length; 1008 hcc_params = readl(base + EHCI_HCC_PARAMS); 1009 hcc_params = (hcc_params >> 8) & 0xff; 1010 if (hcc_params) { 1011 pci_read_config_dword(pdev, 1012 hcc_params + EHCI_USBLEGSUP, 1013 &val); 1014 if (((val & 0xff) == 1) && (val & EHCI_USBLEGSUP_BIOS)) { 1015 /* 1016 * Ok, BIOS is in smm mode, try to hand off... 1017 */ 1018 pci_read_config_dword(pdev, 1019 hcc_params + EHCI_USBLEGCTLSTS, 1020 &temp); 1021 pci_write_config_dword(pdev, 1022 hcc_params + EHCI_USBLEGCTLSTS, 1023 temp | EHCI_USBLEGCTLSTS_SOOE); 1024 val |= EHCI_USBLEGSUP_OS; 1025 pci_write_config_dword(pdev, 1026 hcc_params + EHCI_USBLEGSUP, 1027 val); 1028 1029 wait_time = 500; 1030 do { 1031 msleep(10); 1032 wait_time -= 10; 1033 pci_read_config_dword(pdev, 1034 hcc_params + EHCI_USBLEGSUP, 1035 &val); 1036 } while (wait_time && (val & EHCI_USBLEGSUP_BIOS)); 1037 if (!wait_time) { 1038 /* 1039 * well, possibly buggy BIOS... 1040 */ 1041 printk(KERN_WARNING "EHCI early BIOS handoff " 1042 "failed (BIOS bug ?)\n"); 1043 pci_write_config_dword(pdev, 1044 hcc_params + EHCI_USBLEGSUP, 1045 EHCI_USBLEGSUP_OS); 1046 pci_write_config_dword(pdev, 1047 hcc_params + EHCI_USBLEGCTLSTS, 1048 0); 1049 } 1050 } 1051 } 1052 1053 /* 1054 * halt EHCI & disable its interrupts in any case 1055 */ 1056 val = readl(op_reg_base + EHCI_USBSTS); 1057 if ((val & EHCI_USBSTS_HALTED) == 0) { 1058 val = readl(op_reg_base + EHCI_USBCMD); 1059 val &= ~EHCI_USBCMD_RUN; 1060 writel(val, op_reg_base + EHCI_USBCMD); 1061 1062 wait_time = 2000; 1063 delta = 100; 1064 do { 1065 writel(0x3f, op_reg_base + EHCI_USBSTS); 1066 udelay(delta); 1067 wait_time -= delta; 1068 val = readl(op_reg_base + EHCI_USBSTS); 1069 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) { 1070 break; 1071 } 1072 } while (wait_time > 0); 1073 } 1074 writel(0, op_reg_base + EHCI_USBINTR); 1075 writel(0x3f, op_reg_base + EHCI_USBSTS); 1076 1077 iounmap(base); 1078 1079 return; 1080 } 1081 1082 1083 1084 static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev) 1085 { 1086 if (!usb_early_handoff) 1087 return; 1088 1089 if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x00)) { /* UHCI */ 1090 quirk_usb_handoff_uhci(pdev); 1091 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) { /* OHCI */ 1092 quirk_usb_handoff_ohci(pdev); 1093 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x20)) { /* EHCI */ 1094 quirk_usb_disable_ehci(pdev); 1095 } 1096 1097 return; 1098 } 1099 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff); 1100 1101 /* 1102 * ... This is further complicated by the fact that some SiS96x south 1103 * bridges pretend to be 85C503/5513 instead. In that case see if we 1104 * spotted a compatible north bridge to make sure. 1105 * (pci_find_device doesn't work yet) 1106 * 1107 * We can also enable the sis96x bit in the discovery register.. 1108 */ 1109 static int __devinitdata sis_96x_compatible = 0; 1110 1111 #define SIS_DETECT_REGISTER 0x40 1112 1113 static void __init quirk_sis_503(struct pci_dev *dev) 1114 { 1115 u8 reg; 1116 u16 devid; 1117 1118 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1119 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1120 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1121 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1122 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1123 return; 1124 } 1125 1126 /* Make people aware that we changed the config.. */ 1127 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible); 1128 1129 /* 1130 * Ok, it now shows up as a 96x.. The 96x quirks are after 1131 * the 503 quirk in the quirk table, so they'll automatically 1132 * run and enable things like the SMBus device 1133 */ 1134 dev->device = devid; 1135 } 1136 1137 static void __init quirk_sis_96x_compatible(struct pci_dev *dev) 1138 { 1139 sis_96x_compatible = 1; 1140 } 1141 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible ); 1142 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible ); 1143 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible ); 1144 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible ); 1145 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible ); 1146 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible ); 1147 1148 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 ); 1149 1150 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus ); 1151 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus ); 1152 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus ); 1153 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus ); 1154 1155 #ifdef CONFIG_X86_IO_APIC 1156 static void __init quirk_alder_ioapic(struct pci_dev *pdev) 1157 { 1158 int i; 1159 1160 if ((pdev->class >> 8) != 0xff00) 1161 return; 1162 1163 /* the first BAR is the location of the IO APIC...we must 1164 * not touch this (and it's already covered by the fixmap), so 1165 * forcibly insert it into the resource tree */ 1166 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1167 insert_resource(&iomem_resource, &pdev->resource[0]); 1168 1169 /* The next five BARs all seem to be rubbish, so just clean 1170 * them out */ 1171 for (i=1; i < 6; i++) { 1172 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1173 } 1174 1175 } 1176 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic ); 1177 #endif 1178 1179 #ifdef CONFIG_SCSI_SATA 1180 static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev) 1181 { 1182 u8 prog, comb, tmp; 1183 int ich = 0; 1184 1185 /* 1186 * Narrow down to Intel SATA PCI devices. 1187 */ 1188 switch (pdev->device) { 1189 /* PCI ids taken from drivers/scsi/ata_piix.c */ 1190 case 0x24d1: 1191 case 0x24df: 1192 case 0x25a3: 1193 case 0x25b0: 1194 ich = 5; 1195 break; 1196 case 0x2651: 1197 case 0x2652: 1198 case 0x2653: 1199 case 0x2680: /* ESB2 */ 1200 ich = 6; 1201 break; 1202 case 0x27c0: 1203 case 0x27c4: 1204 ich = 7; 1205 break; 1206 default: 1207 /* we do not handle this PCI device */ 1208 return; 1209 } 1210 1211 /* 1212 * Read combined mode register. 1213 */ 1214 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */ 1215 1216 if (ich == 5) { 1217 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */ 1218 if (tmp == 0x4) /* bits 10x */ 1219 comb = (1 << 0); /* SATA port 0, PATA port 1 */ 1220 else if (tmp == 0x6) /* bits 11x */ 1221 comb = (1 << 2); /* PATA port 0, SATA port 1 */ 1222 else 1223 return; /* not in combined mode */ 1224 } else { 1225 WARN_ON((ich != 6) && (ich != 7)); 1226 tmp &= 0x3; /* interesting bits 1:0 */ 1227 if (tmp & (1 << 0)) 1228 comb = (1 << 2); /* PATA port 0, SATA port 1 */ 1229 else if (tmp & (1 << 1)) 1230 comb = (1 << 0); /* SATA port 0, PATA port 1 */ 1231 else 1232 return; /* not in combined mode */ 1233 } 1234 1235 /* 1236 * Read programming interface register. 1237 * (Tells us if it's legacy or native mode) 1238 */ 1239 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1240 1241 /* if SATA port is in native mode, we're ok. */ 1242 if (prog & comb) 1243 return; 1244 1245 /* SATA port is in legacy mode. Reserve port so that 1246 * IDE driver does not attempt to use it. If request_region 1247 * fails, it will be obvious at boot time, so we don't bother 1248 * checking return values. 1249 */ 1250 if (comb == (1 << 0)) 1251 request_region(0x1f0, 8, "libata"); /* port 0 */ 1252 else 1253 request_region(0x170, 8, "libata"); /* port 1 */ 1254 } 1255 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined ); 1256 #endif /* CONFIG_SCSI_SATA */ 1257 1258 1259 int pcie_mch_quirk; 1260 1261 static void __devinit quirk_pcie_mch(struct pci_dev *pdev) 1262 { 1263 pcie_mch_quirk = 1; 1264 } 1265 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch ); 1266 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch ); 1267 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch ); 1268 1269 static void __devinit quirk_netmos(struct pci_dev *dev) 1270 { 1271 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1272 unsigned int num_serial = dev->subsystem_device & 0xf; 1273 1274 /* 1275 * These Netmos parts are multiport serial devices with optional 1276 * parallel ports. Even when parallel ports are present, they 1277 * are identified as class SERIAL, which means the serial driver 1278 * will claim them. To prevent this, mark them as class OTHER. 1279 * These combo devices should be claimed by parport_serial. 1280 * 1281 * The subdevice ID is of the form 0x00PS, where <P> is the number 1282 * of parallel ports and <S> is the number of serial ports. 1283 */ 1284 switch (dev->device) { 1285 case PCI_DEVICE_ID_NETMOS_9735: 1286 case PCI_DEVICE_ID_NETMOS_9745: 1287 case PCI_DEVICE_ID_NETMOS_9835: 1288 case PCI_DEVICE_ID_NETMOS_9845: 1289 case PCI_DEVICE_ID_NETMOS_9855: 1290 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && 1291 num_parallel) { 1292 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, " 1293 "%u serial); changing class SERIAL to OTHER " 1294 "(use parport_serial)\n", 1295 dev->device, num_parallel, num_serial); 1296 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1297 (dev->class & 0xff); 1298 } 1299 } 1300 } 1301 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); 1302 1303 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end) 1304 { 1305 while (f < end) { 1306 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && 1307 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { 1308 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev)); 1309 f->hook(dev); 1310 } 1311 f++; 1312 } 1313 } 1314 1315 extern struct pci_fixup __start_pci_fixups_early[]; 1316 extern struct pci_fixup __end_pci_fixups_early[]; 1317 extern struct pci_fixup __start_pci_fixups_header[]; 1318 extern struct pci_fixup __end_pci_fixups_header[]; 1319 extern struct pci_fixup __start_pci_fixups_final[]; 1320 extern struct pci_fixup __end_pci_fixups_final[]; 1321 extern struct pci_fixup __start_pci_fixups_enable[]; 1322 extern struct pci_fixup __end_pci_fixups_enable[]; 1323 1324 1325 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 1326 { 1327 struct pci_fixup *start, *end; 1328 1329 switch(pass) { 1330 case pci_fixup_early: 1331 start = __start_pci_fixups_early; 1332 end = __end_pci_fixups_early; 1333 break; 1334 1335 case pci_fixup_header: 1336 start = __start_pci_fixups_header; 1337 end = __end_pci_fixups_header; 1338 break; 1339 1340 case pci_fixup_final: 1341 start = __start_pci_fixups_final; 1342 end = __end_pci_fixups_final; 1343 break; 1344 1345 case pci_fixup_enable: 1346 start = __start_pci_fixups_enable; 1347 end = __end_pci_fixups_enable; 1348 break; 1349 1350 default: 1351 /* stupid compiler warning, you would think with an enum... */ 1352 return; 1353 } 1354 pci_do_fixups(dev, start, end); 1355 } 1356 1357 EXPORT_SYMBOL(pcie_mch_quirk); 1358 #ifdef CONFIG_HOTPLUG 1359 EXPORT_SYMBOL(pci_fixup_device); 1360 #endif 1361