1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/pci.h> 6 7 struct pcie_tlp_log; 8 9 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 10 #define MAX_NR_DEVFNS 256 11 12 #define MAX_NR_LANES 16 13 14 #define PCI_FIND_CAP_TTL 48 15 16 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 17 18 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 19 20 /* 21 * Power stable to PERST# inactive. 22 * 23 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 24 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 25 * "T_PVPERL". 26 */ 27 #define PCIE_T_PVPERL_MS 100 28 29 /* 30 * REFCLK stable before PERST# inactive. 31 * 32 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 33 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 34 * "T_PERST-CLK". 35 */ 36 #define PCIE_T_PERST_CLK_US 100 37 38 /* 39 * End of conventional reset (PERST# de-asserted) to first configuration 40 * request (device able to respond with a "Request Retry Status" completion), 41 * from PCIe r6.0, sec 6.6.1. 42 */ 43 #define PCIE_T_RRS_READY_MS 100 44 45 /* 46 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization> 47 * Recommends 1ms to 10ms timeout to check L2 ready. 48 */ 49 #define PCIE_PME_TO_L2_TIMEOUT_US 10000 50 51 /* 52 * PCIe r6.0, sec 6.6.1 <Conventional Reset> 53 * 54 * - "With a Downstream Port that does not support Link speeds greater 55 * than 5.0 GT/s, software must wait a minimum of 100 ms following exit 56 * from a Conventional Reset before sending a Configuration Request to 57 * the device immediately below that Port." 58 * 59 * - "With a Downstream Port that supports Link speeds greater than 60 * 5.0 GT/s, software must wait a minimum of 100 ms after Link training 61 * completes before sending a Configuration Request to the device 62 * immediately below that Port." 63 */ 64 #define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 65 66 /* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */ 67 #define PCIE_MSG_TYPE_R_RC 0 68 #define PCIE_MSG_TYPE_R_ADDR 1 69 #define PCIE_MSG_TYPE_R_ID 2 70 #define PCIE_MSG_TYPE_R_BC 3 71 #define PCIE_MSG_TYPE_R_LOCAL 4 72 #define PCIE_MSG_TYPE_R_GATHER 5 73 74 /* Power Management Messages; PCIe r6.0, sec 2.2.8.2 */ 75 #define PCIE_MSG_CODE_PME_TURN_OFF 0x19 76 77 /* INTx Mechanism Messages; PCIe r6.0, sec 2.2.8.1 */ 78 #define PCIE_MSG_CODE_ASSERT_INTA 0x20 79 #define PCIE_MSG_CODE_ASSERT_INTB 0x21 80 #define PCIE_MSG_CODE_ASSERT_INTC 0x22 81 #define PCIE_MSG_CODE_ASSERT_INTD 0x23 82 #define PCIE_MSG_CODE_DEASSERT_INTA 0x24 83 #define PCIE_MSG_CODE_DEASSERT_INTB 0x25 84 #define PCIE_MSG_CODE_DEASSERT_INTC 0x26 85 #define PCIE_MSG_CODE_DEASSERT_INTD 0x27 86 87 extern const unsigned char pcie_link_speed[]; 88 extern bool pci_early_dump; 89 90 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 91 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); 92 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 93 94 /* Functions internal to the PCI core code */ 95 96 #ifdef CONFIG_DMI 97 extern const struct attribute_group pci_dev_smbios_attr_group; 98 #endif 99 100 enum pci_mmap_api { 101 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 102 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 103 }; 104 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 105 enum pci_mmap_api mmap_api); 106 107 bool pci_reset_supported(struct pci_dev *dev); 108 void pci_init_reset_methods(struct pci_dev *dev); 109 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 110 int pci_bus_error_reset(struct pci_dev *dev); 111 int __pci_reset_bus(struct pci_bus *bus); 112 113 struct pci_cap_saved_data { 114 u16 cap_nr; 115 bool cap_extended; 116 unsigned int size; 117 u32 data[]; 118 }; 119 120 struct pci_cap_saved_state { 121 struct hlist_node next; 122 struct pci_cap_saved_data cap; 123 }; 124 125 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 126 void pci_free_cap_save_buffers(struct pci_dev *dev); 127 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 128 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 129 u16 cap, unsigned int size); 130 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 131 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 132 u16 cap); 133 134 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 135 #define PCI_PM_D3HOT_WAIT 10 /* msec */ 136 #define PCI_PM_D3COLD_WAIT 100 /* msec */ 137 138 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 139 void pci_refresh_power_state(struct pci_dev *dev); 140 int pci_power_up(struct pci_dev *dev); 141 void pci_disable_enabled_device(struct pci_dev *dev); 142 int pci_finish_runtime_suspend(struct pci_dev *dev); 143 void pcie_clear_device_status(struct pci_dev *dev); 144 void pcie_clear_root_pme_status(struct pci_dev *dev); 145 bool pci_check_pme_status(struct pci_dev *dev); 146 void pci_pme_wakeup_bus(struct pci_bus *bus); 147 void pci_pme_restore(struct pci_dev *dev); 148 bool pci_dev_need_resume(struct pci_dev *dev); 149 void pci_dev_adjust_pme(struct pci_dev *dev); 150 void pci_dev_complete_resume(struct pci_dev *pci_dev); 151 void pci_config_pm_runtime_get(struct pci_dev *dev); 152 void pci_config_pm_runtime_put(struct pci_dev *dev); 153 void pci_pm_power_up_and_verify_state(struct pci_dev *pci_dev); 154 void pci_pm_init(struct pci_dev *dev); 155 void pci_ea_init(struct pci_dev *dev); 156 void pci_msi_init(struct pci_dev *dev); 157 void pci_msix_init(struct pci_dev *dev); 158 bool pci_bridge_d3_possible(struct pci_dev *dev); 159 void pci_bridge_d3_update(struct pci_dev *dev); 160 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); 161 162 static inline bool pci_bus_rrs_vendor_id(u32 l) 163 { 164 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG; 165 } 166 167 static inline void pci_wakeup_event(struct pci_dev *dev) 168 { 169 /* Wait 100 ms before the system can be put into a sleep state. */ 170 pm_wakeup_event(&dev->dev, 100); 171 } 172 173 /** 174 * pci_bar_index_is_valid - Check whether a BAR index is within valid range 175 * @bar: BAR index 176 * 177 * Protects against overflowing &struct pci_dev.resource array. 178 * 179 * Return: true for valid index, false otherwise. 180 */ 181 static inline bool pci_bar_index_is_valid(int bar) 182 { 183 if (bar >= 0 && bar < PCI_NUM_RESOURCES) 184 return true; 185 186 return false; 187 } 188 189 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 190 { 191 return !!(pci_dev->subordinate); 192 } 193 194 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 195 { 196 /* 197 * Currently we allow normal PCI devices and PCI bridges transition 198 * into D3 if their bridge_d3 is set. 199 */ 200 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 201 } 202 203 static inline bool pcie_downstream_port(const struct pci_dev *dev) 204 { 205 int type = pci_pcie_type(dev); 206 207 return type == PCI_EXP_TYPE_ROOT_PORT || 208 type == PCI_EXP_TYPE_DOWNSTREAM || 209 type == PCI_EXP_TYPE_PCIE_BRIDGE; 210 } 211 212 void pci_vpd_init(struct pci_dev *dev); 213 extern const struct attribute_group pci_dev_vpd_attr_group; 214 215 /* PCI Virtual Channel */ 216 int pci_save_vc_state(struct pci_dev *dev); 217 void pci_restore_vc_state(struct pci_dev *dev); 218 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 219 220 /* PCI /proc functions */ 221 #ifdef CONFIG_PROC_FS 222 int pci_proc_attach_device(struct pci_dev *dev); 223 int pci_proc_detach_device(struct pci_dev *dev); 224 int pci_proc_detach_bus(struct pci_bus *bus); 225 #else 226 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 227 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 228 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 229 #endif 230 231 /* Functions for PCI Hotplug drivers to use */ 232 int pci_hp_add_bridge(struct pci_dev *dev); 233 bool pci_hp_spurious_link_change(struct pci_dev *pdev); 234 235 #if defined(CONFIG_SYSFS) && defined(HAVE_PCI_LEGACY) 236 void pci_create_legacy_files(struct pci_bus *bus); 237 void pci_remove_legacy_files(struct pci_bus *bus); 238 #else 239 static inline void pci_create_legacy_files(struct pci_bus *bus) { } 240 static inline void pci_remove_legacy_files(struct pci_bus *bus) { } 241 #endif 242 243 /* Lock for read/write access to pci device and bus lists */ 244 extern struct rw_semaphore pci_bus_sem; 245 extern struct mutex pci_slot_mutex; 246 247 extern raw_spinlock_t pci_lock; 248 249 extern unsigned int pci_pm_d3hot_delay; 250 251 #ifdef CONFIG_PCI_MSI 252 void pci_no_msi(void); 253 #else 254 static inline void pci_no_msi(void) { } 255 #endif 256 257 void pci_realloc_get_opt(char *); 258 259 static inline int pci_no_d1d2(struct pci_dev *dev) 260 { 261 unsigned int parent_dstates = 0; 262 263 if (dev->bus->self) 264 parent_dstates = dev->bus->self->no_d1d2; 265 return (dev->no_d1d2 || parent_dstates); 266 267 } 268 269 #ifdef CONFIG_SYSFS 270 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 271 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 272 extern const struct attribute_group *pci_dev_groups[]; 273 extern const struct attribute_group *pci_dev_attr_groups[]; 274 extern const struct attribute_group *pcibus_groups[]; 275 extern const struct attribute_group *pci_bus_groups[]; 276 extern const struct attribute_group pci_doe_sysfs_group; 277 #else 278 static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; } 279 static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { } 280 #define pci_dev_groups NULL 281 #define pci_dev_attr_groups NULL 282 #define pcibus_groups NULL 283 #define pci_bus_groups NULL 284 #endif 285 286 extern unsigned long pci_hotplug_io_size; 287 extern unsigned long pci_hotplug_mmio_size; 288 extern unsigned long pci_hotplug_mmio_pref_size; 289 extern unsigned long pci_hotplug_bus_size; 290 extern unsigned long pci_cardbus_io_size; 291 extern unsigned long pci_cardbus_mem_size; 292 293 /** 294 * pci_match_one_device - Tell if a PCI device structure has a matching 295 * PCI device id structure 296 * @id: single PCI device id structure to match 297 * @dev: the PCI device structure to match against 298 * 299 * Returns the matching pci_device_id structure or %NULL if there is no match. 300 */ 301 static inline const struct pci_device_id * 302 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 303 { 304 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 305 (id->device == PCI_ANY_ID || id->device == dev->device) && 306 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 307 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 308 !((id->class ^ dev->class) & id->class_mask)) 309 return id; 310 return NULL; 311 } 312 313 /* PCI slot sysfs helper code */ 314 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 315 316 extern struct kset *pci_slots_kset; 317 318 struct pci_slot_attribute { 319 struct attribute attr; 320 ssize_t (*show)(struct pci_slot *, char *); 321 ssize_t (*store)(struct pci_slot *, const char *, size_t); 322 }; 323 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 324 325 enum pci_bar_type { 326 pci_bar_unknown, /* Standard PCI BAR probe */ 327 pci_bar_io, /* An I/O port BAR */ 328 pci_bar_mem32, /* A 32-bit memory BAR */ 329 pci_bar_mem64, /* A 64-bit memory BAR */ 330 }; 331 332 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 333 void pci_put_host_bridge_device(struct device *dev); 334 335 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 336 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 337 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 338 339 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 340 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 341 int rrs_timeout); 342 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 343 int rrs_timeout); 344 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int rrs_timeout); 345 346 int pci_setup_device(struct pci_dev *dev); 347 void __pci_size_stdbars(struct pci_dev *dev, int count, 348 unsigned int pos, u32 *sizes); 349 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 350 struct resource *res, unsigned int reg, u32 *sizes); 351 void pci_configure_ari(struct pci_dev *dev); 352 void __pci_bus_size_bridges(struct pci_bus *bus, 353 struct list_head *realloc_head); 354 void __pci_bus_assign_resources(const struct pci_bus *bus, 355 struct list_head *realloc_head, 356 struct list_head *fail_head); 357 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 358 void pci_walk_bus_locked(struct pci_bus *top, 359 int (*cb)(struct pci_dev *, void *), 360 void *userdata); 361 362 const char *pci_resource_name(struct pci_dev *dev, unsigned int i); 363 bool pci_resource_is_optional(const struct pci_dev *dev, int resno); 364 365 /** 366 * pci_resource_num - Reverse lookup resource number from device resources 367 * @dev: PCI device 368 * @res: Resource to lookup index for (MUST be a @dev's resource) 369 * 370 * Perform reverse lookup to determine the resource number for @res within 371 * @dev resource array. NOTE: The caller is responsible for ensuring @res is 372 * among @dev's resources! 373 * 374 * Returns: resource number. 375 */ 376 static inline int pci_resource_num(const struct pci_dev *dev, 377 const struct resource *res) 378 { 379 int resno = res - &dev->resource[0]; 380 381 /* Passing a resource that is not among dev's resources? */ 382 WARN_ON_ONCE(resno >= PCI_NUM_RESOURCES); 383 384 return resno; 385 } 386 387 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 388 void pci_disable_bridge_window(struct pci_dev *dev); 389 struct pci_bus *pci_bus_get(struct pci_bus *bus); 390 void pci_bus_put(struct pci_bus *bus); 391 392 #define PCIE_LNKCAP_SLS2SPEED(lnkcap) \ 393 ({ \ 394 u32 lnkcap_sls = (lnkcap) & PCI_EXP_LNKCAP_SLS; \ 395 \ 396 (lnkcap_sls == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 397 lnkcap_sls == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 398 lnkcap_sls == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 399 lnkcap_sls == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 400 lnkcap_sls == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 401 lnkcap_sls == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 402 PCI_SPEED_UNKNOWN); \ 403 }) 404 405 /* PCIe link information from Link Capabilities 2 */ 406 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 407 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 408 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 409 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 410 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 411 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 412 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 413 PCI_SPEED_UNKNOWN) 414 415 #define PCIE_LNKCTL2_TLS2SPEED(lnkctl2) \ 416 ({ \ 417 u16 lnkctl2_tls = (lnkctl2) & PCI_EXP_LNKCTL2_TLS; \ 418 \ 419 (lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \ 420 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \ 421 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \ 422 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \ 423 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \ 424 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \ 425 PCI_SPEED_UNKNOWN); \ 426 }) 427 428 /* PCIe speed to Mb/s reduced by encoding overhead */ 429 #define PCIE_SPEED2MBS_ENC(speed) \ 430 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \ 431 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 432 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 433 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 434 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 435 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 436 0) 437 438 static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed) 439 { 440 switch (speed) { 441 case PCIE_SPEED_2_5GT: 442 return 2500; 443 case PCIE_SPEED_5_0GT: 444 return 5000; 445 case PCIE_SPEED_8_0GT: 446 return 8000; 447 case PCIE_SPEED_16_0GT: 448 return 16000; 449 case PCIE_SPEED_32_0GT: 450 return 32000; 451 case PCIE_SPEED_64_0GT: 452 return 64000; 453 default: 454 break; 455 } 456 457 return -EINVAL; 458 } 459 460 u8 pcie_get_supported_speeds(struct pci_dev *dev); 461 const char *pci_speed_string(enum pci_bus_speed speed); 462 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 463 void pcie_report_downtraining(struct pci_dev *dev); 464 465 static inline void __pcie_update_link_speed(struct pci_bus *bus, u16 linksta, u16 linksta2) 466 { 467 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 468 bus->flit_mode = (linksta2 & PCI_EXP_LNKSTA2_FLIT) ? 1 : 0; 469 } 470 void pcie_update_link_speed(struct pci_bus *bus); 471 472 /* Single Root I/O Virtualization */ 473 struct pci_sriov { 474 int pos; /* Capability position */ 475 int nres; /* Number of resources */ 476 u32 cap; /* SR-IOV Capabilities */ 477 u16 ctrl; /* SR-IOV Control */ 478 u16 total_VFs; /* Total VFs associated with the PF */ 479 u16 initial_VFs; /* Initial VFs associated with the PF */ 480 u16 num_VFs; /* Number of VFs available */ 481 u16 offset; /* First VF Routing ID offset */ 482 u16 stride; /* Following VF stride */ 483 u16 vf_device; /* VF device ID */ 484 u32 pgsz; /* Page size for BAR alignment */ 485 u8 link; /* Function Dependency Link */ 486 u8 max_VF_buses; /* Max buses consumed by VFs */ 487 u16 driver_max_VFs; /* Max num VFs driver supports */ 488 struct pci_dev *dev; /* Lowest numbered PF */ 489 struct pci_dev *self; /* This PF */ 490 u32 class; /* VF device */ 491 u8 hdr_type; /* VF header type */ 492 u16 subsystem_vendor; /* VF subsystem vendor */ 493 u16 subsystem_device; /* VF subsystem device */ 494 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 495 u16 vf_rebar_cap; /* VF Resizable BAR capability offset */ 496 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 497 }; 498 499 #ifdef CONFIG_PCI_DOE 500 void pci_doe_init(struct pci_dev *pdev); 501 void pci_doe_destroy(struct pci_dev *pdev); 502 void pci_doe_disconnected(struct pci_dev *pdev); 503 #else 504 static inline void pci_doe_init(struct pci_dev *pdev) { } 505 static inline void pci_doe_destroy(struct pci_dev *pdev) { } 506 static inline void pci_doe_disconnected(struct pci_dev *pdev) { } 507 #endif 508 509 #ifdef CONFIG_PCI_NPEM 510 void pci_npem_create(struct pci_dev *dev); 511 void pci_npem_remove(struct pci_dev *dev); 512 #else 513 static inline void pci_npem_create(struct pci_dev *dev) { } 514 static inline void pci_npem_remove(struct pci_dev *dev) { } 515 #endif 516 517 #if defined(CONFIG_PCI_DOE) && defined(CONFIG_SYSFS) 518 void pci_doe_sysfs_init(struct pci_dev *pci_dev); 519 void pci_doe_sysfs_teardown(struct pci_dev *pdev); 520 #else 521 static inline void pci_doe_sysfs_init(struct pci_dev *pdev) { } 522 static inline void pci_doe_sysfs_teardown(struct pci_dev *pdev) { } 523 #endif 524 525 /** 526 * pci_dev_set_io_state - Set the new error state if possible. 527 * 528 * @dev: PCI device to set new error_state 529 * @new: the state we want dev to be in 530 * 531 * If the device is experiencing perm_failure, it has to remain in that state. 532 * Any other transition is allowed. 533 * 534 * Returns true if state has been changed to the requested state. 535 */ 536 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 537 pci_channel_state_t new) 538 { 539 pci_channel_state_t old; 540 541 switch (new) { 542 case pci_channel_io_perm_failure: 543 xchg(&dev->error_state, pci_channel_io_perm_failure); 544 return true; 545 case pci_channel_io_frozen: 546 old = cmpxchg(&dev->error_state, pci_channel_io_normal, 547 pci_channel_io_frozen); 548 return old != pci_channel_io_perm_failure; 549 case pci_channel_io_normal: 550 old = cmpxchg(&dev->error_state, pci_channel_io_frozen, 551 pci_channel_io_normal); 552 return old != pci_channel_io_perm_failure; 553 default: 554 return false; 555 } 556 } 557 558 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 559 { 560 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 561 pci_doe_disconnected(dev); 562 563 return 0; 564 } 565 566 /* pci_dev priv_flags */ 567 #define PCI_DEV_ADDED 0 568 #define PCI_DPC_RECOVERED 1 569 #define PCI_DPC_RECOVERING 2 570 #define PCI_DEV_REMOVED 3 571 #define PCI_LINK_CHANGED 4 572 #define PCI_LINK_CHANGING 5 573 #define PCI_LINK_LBMS_SEEN 6 574 #define PCI_DEV_ALLOW_BINDING 7 575 576 static inline void pci_dev_assign_added(struct pci_dev *dev) 577 { 578 smp_mb__before_atomic(); 579 set_bit(PCI_DEV_ADDED, &dev->priv_flags); 580 smp_mb__after_atomic(); 581 } 582 583 static inline bool pci_dev_test_and_clear_added(struct pci_dev *dev) 584 { 585 return test_and_clear_bit(PCI_DEV_ADDED, &dev->priv_flags); 586 } 587 588 static inline bool pci_dev_is_added(const struct pci_dev *dev) 589 { 590 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 591 } 592 593 static inline bool pci_dev_test_and_set_removed(struct pci_dev *dev) 594 { 595 return test_and_set_bit(PCI_DEV_REMOVED, &dev->priv_flags); 596 } 597 598 static inline void pci_dev_allow_binding(struct pci_dev *dev) 599 { 600 set_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags); 601 } 602 603 static inline bool pci_dev_binding_disallowed(struct pci_dev *dev) 604 { 605 return !test_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags); 606 } 607 608 #ifdef CONFIG_PCIEAER 609 #include <linux/aer.h> 610 611 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 612 613 struct aer_err_info { 614 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 615 int ratelimit_print[AER_MAX_MULTI_ERR_DEVICES]; 616 int error_dev_num; 617 const char *level; /* printk level */ 618 619 unsigned int id:16; 620 621 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 622 unsigned int root_ratelimit_print:1; /* 0=skip, 1=print */ 623 unsigned int __pad1:4; 624 unsigned int multi_error_valid:1; 625 626 unsigned int first_error:5; 627 unsigned int __pad2:2; 628 unsigned int tlp_header_valid:1; 629 630 unsigned int status; /* COR/UNCOR Error Status */ 631 unsigned int mask; /* COR/UNCOR Error Mask */ 632 struct pcie_tlp_log tlp; /* TLP Header */ 633 }; 634 635 int aer_get_device_error_info(struct aer_err_info *info, int i); 636 void aer_print_error(struct aer_err_info *info, int i); 637 638 int pcie_read_tlp_log(struct pci_dev *dev, int where, int where2, 639 unsigned int tlp_len, bool flit, 640 struct pcie_tlp_log *log); 641 unsigned int aer_tlp_log_len(struct pci_dev *dev, u32 aercc); 642 void pcie_print_tlp_log(const struct pci_dev *dev, 643 const struct pcie_tlp_log *log, const char *level, 644 const char *pfx); 645 #endif /* CONFIG_PCIEAER */ 646 647 #ifdef CONFIG_PCIEPORTBUS 648 /* Cached RCEC Endpoint Association */ 649 struct rcec_ea { 650 u8 nextbusn; 651 u8 lastbusn; 652 u32 bitmap; 653 }; 654 #endif 655 656 #ifdef CONFIG_PCIE_DPC 657 void pci_save_dpc_state(struct pci_dev *dev); 658 void pci_restore_dpc_state(struct pci_dev *dev); 659 void pci_dpc_init(struct pci_dev *pdev); 660 void dpc_process_error(struct pci_dev *pdev); 661 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 662 bool pci_dpc_recovered(struct pci_dev *pdev); 663 unsigned int dpc_tlp_log_len(struct pci_dev *dev); 664 #else 665 static inline void pci_save_dpc_state(struct pci_dev *dev) { } 666 static inline void pci_restore_dpc_state(struct pci_dev *dev) { } 667 static inline void pci_dpc_init(struct pci_dev *pdev) { } 668 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 669 #endif 670 671 #ifdef CONFIG_PCIEPORTBUS 672 void pci_rcec_init(struct pci_dev *dev); 673 void pci_rcec_exit(struct pci_dev *dev); 674 void pcie_link_rcec(struct pci_dev *rcec); 675 void pcie_walk_rcec(struct pci_dev *rcec, 676 int (*cb)(struct pci_dev *, void *), 677 void *userdata); 678 #else 679 static inline void pci_rcec_init(struct pci_dev *dev) { } 680 static inline void pci_rcec_exit(struct pci_dev *dev) { } 681 static inline void pcie_link_rcec(struct pci_dev *rcec) { } 682 static inline void pcie_walk_rcec(struct pci_dev *rcec, 683 int (*cb)(struct pci_dev *, void *), 684 void *userdata) { } 685 #endif 686 687 #ifdef CONFIG_PCI_ATS 688 /* Address Translation Service */ 689 void pci_ats_init(struct pci_dev *dev); 690 void pci_restore_ats_state(struct pci_dev *dev); 691 #else 692 static inline void pci_ats_init(struct pci_dev *d) { } 693 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 694 #endif /* CONFIG_PCI_ATS */ 695 696 #ifdef CONFIG_PCI_PRI 697 void pci_pri_init(struct pci_dev *dev); 698 void pci_restore_pri_state(struct pci_dev *pdev); 699 #else 700 static inline void pci_pri_init(struct pci_dev *dev) { } 701 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 702 #endif 703 704 #ifdef CONFIG_PCI_PASID 705 void pci_pasid_init(struct pci_dev *dev); 706 void pci_restore_pasid_state(struct pci_dev *pdev); 707 #else 708 static inline void pci_pasid_init(struct pci_dev *dev) { } 709 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 710 #endif 711 712 #ifdef CONFIG_PCI_IOV 713 int pci_iov_init(struct pci_dev *dev); 714 void pci_iov_release(struct pci_dev *dev); 715 void pci_iov_remove(struct pci_dev *dev); 716 void pci_iov_update_resource(struct pci_dev *dev, int resno); 717 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 718 void pci_restore_iov_state(struct pci_dev *dev); 719 int pci_iov_bus_range(struct pci_bus *bus); 720 void pci_iov_resource_set_size(struct pci_dev *dev, int resno, 721 resource_size_t size); 722 bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev); 723 static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev) 724 { 725 if (!dev->is_physfn) 726 return 0; 727 728 return dev->sriov->vf_rebar_cap; 729 } 730 static inline bool pci_resource_is_iov(int resno) 731 { 732 return resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END; 733 } 734 static inline int pci_resource_num_from_vf_bar(int resno) 735 { 736 return resno + PCI_IOV_RESOURCES; 737 } 738 static inline int pci_resource_num_to_vf_bar(int resno) 739 { 740 return resno - PCI_IOV_RESOURCES; 741 } 742 extern const struct attribute_group sriov_pf_dev_attr_group; 743 extern const struct attribute_group sriov_vf_dev_attr_group; 744 #else 745 static inline int pci_iov_init(struct pci_dev *dev) 746 { 747 return -ENODEV; 748 } 749 static inline void pci_iov_release(struct pci_dev *dev) { } 750 static inline void pci_iov_remove(struct pci_dev *dev) { } 751 static inline void pci_iov_update_resource(struct pci_dev *dev, int resno) { } 752 static inline resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, 753 int resno) 754 { 755 return 0; 756 } 757 static inline void pci_restore_iov_state(struct pci_dev *dev) { } 758 static inline int pci_iov_bus_range(struct pci_bus *bus) 759 { 760 return 0; 761 } 762 static inline void pci_iov_resource_set_size(struct pci_dev *dev, int resno, 763 resource_size_t size) { } 764 static inline bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev) 765 { 766 return false; 767 } 768 static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev) 769 { 770 return 0; 771 } 772 static inline bool pci_resource_is_iov(int resno) 773 { 774 return false; 775 } 776 static inline int pci_resource_num_from_vf_bar(int resno) 777 { 778 WARN_ON_ONCE(1); 779 return -ENODEV; 780 } 781 static inline int pci_resource_num_to_vf_bar(int resno) 782 { 783 WARN_ON_ONCE(1); 784 return -ENODEV; 785 } 786 #endif /* CONFIG_PCI_IOV */ 787 788 #ifdef CONFIG_PCIE_TPH 789 void pci_restore_tph_state(struct pci_dev *dev); 790 void pci_save_tph_state(struct pci_dev *dev); 791 void pci_no_tph(void); 792 void pci_tph_init(struct pci_dev *dev); 793 #else 794 static inline void pci_restore_tph_state(struct pci_dev *dev) { } 795 static inline void pci_save_tph_state(struct pci_dev *dev) { } 796 static inline void pci_no_tph(void) { } 797 static inline void pci_tph_init(struct pci_dev *dev) { } 798 #endif 799 800 #ifdef CONFIG_PCIE_PTM 801 void pci_ptm_init(struct pci_dev *dev); 802 void pci_save_ptm_state(struct pci_dev *dev); 803 void pci_restore_ptm_state(struct pci_dev *dev); 804 void pci_suspend_ptm(struct pci_dev *dev); 805 void pci_resume_ptm(struct pci_dev *dev); 806 #else 807 static inline void pci_ptm_init(struct pci_dev *dev) { } 808 static inline void pci_save_ptm_state(struct pci_dev *dev) { } 809 static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 810 static inline void pci_suspend_ptm(struct pci_dev *dev) { } 811 static inline void pci_resume_ptm(struct pci_dev *dev) { } 812 #endif 813 814 unsigned long pci_cardbus_resource_alignment(struct resource *); 815 816 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 817 struct resource *res) 818 { 819 int resno = pci_resource_num(dev, res); 820 821 if (pci_resource_is_iov(resno)) 822 return pci_sriov_resource_alignment(dev, resno); 823 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 824 return pci_cardbus_resource_alignment(res); 825 return resource_alignment(res); 826 } 827 828 void pci_acs_init(struct pci_dev *dev); 829 #ifdef CONFIG_PCI_QUIRKS 830 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 831 int pci_dev_specific_enable_acs(struct pci_dev *dev); 832 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 833 int pcie_failed_link_retrain(struct pci_dev *dev); 834 #else 835 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 836 u16 acs_flags) 837 { 838 return -ENOTTY; 839 } 840 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 841 { 842 return -ENOTTY; 843 } 844 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 845 { 846 return -ENOTTY; 847 } 848 static inline int pcie_failed_link_retrain(struct pci_dev *dev) 849 { 850 return -ENOTTY; 851 } 852 #endif 853 854 /* PCI error reporting and recovery */ 855 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 856 pci_channel_state_t state, 857 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 858 859 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 860 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); 861 862 /* ASPM-related functionality we need even without CONFIG_PCIEASPM */ 863 void pci_save_ltr_state(struct pci_dev *dev); 864 void pci_restore_ltr_state(struct pci_dev *dev); 865 void pci_configure_aspm_l1ss(struct pci_dev *dev); 866 void pci_save_aspm_l1ss_state(struct pci_dev *dev); 867 void pci_restore_aspm_l1ss_state(struct pci_dev *dev); 868 869 #ifdef CONFIG_PCIEASPM 870 void pcie_aspm_init_link_state(struct pci_dev *pdev); 871 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 872 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked); 873 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 874 void pci_configure_ltr(struct pci_dev *pdev); 875 void pci_bridge_reconfigure_ltr(struct pci_dev *pdev); 876 #else 877 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 878 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 879 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { } 880 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 881 static inline void pci_configure_ltr(struct pci_dev *pdev) { } 882 static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { } 883 #endif 884 885 #ifdef CONFIG_PCIE_ECRC 886 void pcie_set_ecrc_checking(struct pci_dev *dev); 887 void pcie_ecrc_get_policy(char *str); 888 #else 889 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 890 static inline void pcie_ecrc_get_policy(char *str) { } 891 #endif 892 893 #ifdef CONFIG_PCIEPORTBUS 894 void pcie_reset_lbms(struct pci_dev *port); 895 #else 896 static inline void pcie_reset_lbms(struct pci_dev *port) {} 897 #endif 898 899 struct pci_dev_reset_methods { 900 u16 vendor; 901 u16 device; 902 int (*reset)(struct pci_dev *dev, bool probe); 903 }; 904 905 struct pci_reset_fn_method { 906 int (*reset_fn)(struct pci_dev *pdev, bool probe); 907 char *name; 908 }; 909 extern const struct pci_reset_fn_method pci_reset_fn_methods[]; 910 911 #ifdef CONFIG_PCI_QUIRKS 912 int pci_dev_specific_reset(struct pci_dev *dev, bool probe); 913 #else 914 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 915 { 916 return -ENOTTY; 917 } 918 #endif 919 920 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 921 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 922 struct resource *res); 923 #else 924 static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 925 u16 segment, struct resource *res) 926 { 927 return -ENODEV; 928 } 929 #endif 930 931 void pci_rebar_init(struct pci_dev *pdev); 932 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 933 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 934 static inline u64 pci_rebar_size_to_bytes(int size) 935 { 936 return 1ULL << (size + 20); 937 } 938 939 struct device_node; 940 941 #define PCI_EQ_RESV 0xff 942 943 enum equalization_preset_type { 944 EQ_PRESET_TYPE_8GTS, 945 EQ_PRESET_TYPE_16GTS, 946 EQ_PRESET_TYPE_32GTS, 947 EQ_PRESET_TYPE_64GTS, 948 EQ_PRESET_TYPE_MAX 949 }; 950 951 struct pci_eq_presets { 952 u16 eq_presets_8gts[MAX_NR_LANES]; 953 u8 eq_presets_Ngts[EQ_PRESET_TYPE_MAX - 1][MAX_NR_LANES]; 954 }; 955 956 #ifdef CONFIG_OF 957 int of_get_pci_domain_nr(struct device_node *node); 958 int of_pci_get_max_link_speed(struct device_node *node); 959 u32 of_pci_get_slot_power_limit(struct device_node *node, 960 u8 *slot_power_limit_value, 961 u8 *slot_power_limit_scale); 962 bool of_pci_preserve_config(struct device_node *node); 963 int pci_set_of_node(struct pci_dev *dev); 964 void pci_release_of_node(struct pci_dev *dev); 965 void pci_set_bus_of_node(struct pci_bus *bus); 966 void pci_release_bus_of_node(struct pci_bus *bus); 967 968 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 969 bool of_pci_supply_present(struct device_node *np); 970 int of_pci_get_equalization_presets(struct device *dev, 971 struct pci_eq_presets *presets, 972 int num_lanes); 973 #else 974 static inline int 975 of_get_pci_domain_nr(struct device_node *node) 976 { 977 return -1; 978 } 979 980 static inline int 981 of_pci_get_max_link_speed(struct device_node *node) 982 { 983 return -EINVAL; 984 } 985 986 static inline u32 987 of_pci_get_slot_power_limit(struct device_node *node, 988 u8 *slot_power_limit_value, 989 u8 *slot_power_limit_scale) 990 { 991 if (slot_power_limit_value) 992 *slot_power_limit_value = 0; 993 if (slot_power_limit_scale) 994 *slot_power_limit_scale = 0; 995 return 0; 996 } 997 998 static inline bool of_pci_preserve_config(struct device_node *node) 999 { 1000 return false; 1001 } 1002 1003 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; } 1004 static inline void pci_release_of_node(struct pci_dev *dev) { } 1005 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 1006 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 1007 1008 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 1009 { 1010 return 0; 1011 } 1012 1013 static inline bool of_pci_supply_present(struct device_node *np) 1014 { 1015 return false; 1016 } 1017 1018 static inline int of_pci_get_equalization_presets(struct device *dev, 1019 struct pci_eq_presets *presets, 1020 int num_lanes) 1021 { 1022 presets->eq_presets_8gts[0] = PCI_EQ_RESV; 1023 for (int i = 0; i < EQ_PRESET_TYPE_MAX - 1; i++) 1024 presets->eq_presets_Ngts[i][0] = PCI_EQ_RESV; 1025 1026 return 0; 1027 } 1028 #endif /* CONFIG_OF */ 1029 1030 struct of_changeset; 1031 1032 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES 1033 void of_pci_make_dev_node(struct pci_dev *pdev); 1034 void of_pci_remove_node(struct pci_dev *pdev); 1035 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, 1036 struct device_node *np); 1037 void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge); 1038 void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge); 1039 int of_pci_add_host_bridge_properties(struct pci_host_bridge *bridge, 1040 struct of_changeset *ocs, 1041 struct device_node *np); 1042 #else 1043 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { } 1044 static inline void of_pci_remove_node(struct pci_dev *pdev) { } 1045 static inline void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge) { } 1046 static inline void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge) { } 1047 #endif 1048 1049 #ifdef CONFIG_PCIEAER 1050 void pci_no_aer(void); 1051 void pci_aer_init(struct pci_dev *dev); 1052 void pci_aer_exit(struct pci_dev *dev); 1053 extern const struct attribute_group aer_stats_attr_group; 1054 extern const struct attribute_group aer_attr_group; 1055 void pci_aer_clear_fatal_status(struct pci_dev *dev); 1056 int pci_aer_clear_status(struct pci_dev *dev); 1057 int pci_aer_raw_clear_status(struct pci_dev *dev); 1058 void pci_save_aer_state(struct pci_dev *dev); 1059 void pci_restore_aer_state(struct pci_dev *dev); 1060 #else 1061 static inline void pci_no_aer(void) { } 1062 static inline void pci_aer_init(struct pci_dev *d) { } 1063 static inline void pci_aer_exit(struct pci_dev *d) { } 1064 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 1065 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 1066 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 1067 static inline void pci_save_aer_state(struct pci_dev *dev) { } 1068 static inline void pci_restore_aer_state(struct pci_dev *dev) { } 1069 #endif 1070 1071 #ifdef CONFIG_ACPI 1072 bool pci_acpi_preserve_config(struct pci_host_bridge *bridge); 1073 int pci_acpi_program_hp_params(struct pci_dev *dev); 1074 extern const struct attribute_group pci_dev_acpi_attr_group; 1075 void pci_set_acpi_fwnode(struct pci_dev *dev); 1076 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); 1077 bool acpi_pci_power_manageable(struct pci_dev *dev); 1078 bool acpi_pci_bridge_d3(struct pci_dev *dev); 1079 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1080 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev); 1081 void acpi_pci_refresh_power_state(struct pci_dev *dev); 1082 int acpi_pci_wakeup(struct pci_dev *dev, bool enable); 1083 bool acpi_pci_need_resume(struct pci_dev *dev); 1084 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); 1085 #else 1086 static inline bool pci_acpi_preserve_config(struct pci_host_bridge *bridge) 1087 { 1088 return false; 1089 } 1090 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 1091 { 1092 return -ENOTTY; 1093 } 1094 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { } 1095 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 1096 { 1097 return -ENODEV; 1098 } 1099 static inline bool acpi_pci_power_manageable(struct pci_dev *dev) 1100 { 1101 return false; 1102 } 1103 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev) 1104 { 1105 return false; 1106 } 1107 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1108 { 1109 return -ENODEV; 1110 } 1111 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 1112 { 1113 return PCI_UNKNOWN; 1114 } 1115 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { } 1116 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 1117 { 1118 return -ENODEV; 1119 } 1120 static inline bool acpi_pci_need_resume(struct pci_dev *dev) 1121 { 1122 return false; 1123 } 1124 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 1125 { 1126 return PCI_POWER_ERROR; 1127 } 1128 #endif 1129 1130 #ifdef CONFIG_PCIEASPM 1131 extern const struct attribute_group aspm_ctrl_attr_group; 1132 #endif 1133 1134 #ifdef CONFIG_X86_INTEL_MID 1135 bool pci_use_mid_pm(void); 1136 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 1137 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev); 1138 #else 1139 static inline bool pci_use_mid_pm(void) 1140 { 1141 return false; 1142 } 1143 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) 1144 { 1145 return -ENODEV; 1146 } 1147 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) 1148 { 1149 return PCI_UNKNOWN; 1150 } 1151 #endif 1152 1153 #ifdef CONFIG_PCI_MSI 1154 int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag); 1155 #else 1156 static inline int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag) 1157 { 1158 return -ENODEV; 1159 } 1160 #endif 1161 1162 /* 1163 * Config Address for PCI Configuration Mechanism #1 1164 * 1165 * See PCI Local Bus Specification, Revision 3.0, 1166 * Section 3.2.2.3.2, Figure 3-2, p. 50. 1167 */ 1168 1169 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ 1170 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */ 1171 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ 1172 1173 #define PCI_CONF1_BUS_MASK 0xff 1174 #define PCI_CONF1_DEV_MASK 0x1f 1175 #define PCI_CONF1_FUNC_MASK 0x7 1176 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ 1177 1178 #define PCI_CONF1_ENABLE BIT(31) 1179 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) 1180 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) 1181 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) 1182 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) 1183 1184 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ 1185 (PCI_CONF1_ENABLE | \ 1186 PCI_CONF1_BUS(bus) | \ 1187 PCI_CONF1_DEV(dev) | \ 1188 PCI_CONF1_FUNC(func) | \ 1189 PCI_CONF1_REG(reg)) 1190 1191 /* 1192 * Extension of PCI Config Address for accessing extended PCIe registers 1193 * 1194 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs 1195 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address 1196 * are used for specifying additional 4 high bits of PCI Express register. 1197 */ 1198 1199 #define PCI_CONF1_EXT_REG_SHIFT 16 1200 #define PCI_CONF1_EXT_REG_MASK 0xf00 1201 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) 1202 1203 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ 1204 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ 1205 PCI_CONF1_EXT_REG(reg)) 1206 1207 #endif /* DRIVERS_PCI_H */ 1208