1 /* 2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $ 3 * 4 * PCI Bus Services, see include/linux/pci.h for further explanation. 5 * 6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, 7 * David Mosberger-Tang 8 * 9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/delay.h> 14 #include <linux/init.h> 15 #include <linux/pci.h> 16 #include <linux/module.h> 17 #include <linux/spinlock.h> 18 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 19 #include "pci.h" 20 21 22 /** 23 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children 24 * @bus: pointer to PCI bus structure to search 25 * 26 * Given a PCI bus, returns the highest PCI bus number present in the set 27 * including the given PCI bus and its list of child PCI buses. 28 */ 29 unsigned char __devinit 30 pci_bus_max_busnr(struct pci_bus* bus) 31 { 32 struct list_head *tmp; 33 unsigned char max, n; 34 35 max = bus->number; 36 list_for_each(tmp, &bus->children) { 37 n = pci_bus_max_busnr(pci_bus_b(tmp)); 38 if(n > max) 39 max = n; 40 } 41 return max; 42 } 43 44 /** 45 * pci_max_busnr - returns maximum PCI bus number 46 * 47 * Returns the highest PCI bus number present in the system global list of 48 * PCI buses. 49 */ 50 unsigned char __devinit 51 pci_max_busnr(void) 52 { 53 struct pci_bus *bus = NULL; 54 unsigned char max, n; 55 56 max = 0; 57 while ((bus = pci_find_next_bus(bus)) != NULL) { 58 n = pci_bus_max_busnr(bus); 59 if(n > max) 60 max = n; 61 } 62 return max; 63 } 64 65 static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap) 66 { 67 u16 status; 68 u8 pos, id; 69 int ttl = 48; 70 71 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); 72 if (!(status & PCI_STATUS_CAP_LIST)) 73 return 0; 74 75 switch (hdr_type) { 76 case PCI_HEADER_TYPE_NORMAL: 77 case PCI_HEADER_TYPE_BRIDGE: 78 pci_bus_read_config_byte(bus, devfn, PCI_CAPABILITY_LIST, &pos); 79 break; 80 case PCI_HEADER_TYPE_CARDBUS: 81 pci_bus_read_config_byte(bus, devfn, PCI_CB_CAPABILITY_LIST, &pos); 82 break; 83 default: 84 return 0; 85 } 86 while (ttl-- && pos >= 0x40) { 87 pos &= ~3; 88 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, &id); 89 if (id == 0xff) 90 break; 91 if (id == cap) 92 return pos; 93 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_NEXT, &pos); 94 } 95 return 0; 96 } 97 98 /** 99 * pci_find_capability - query for devices' capabilities 100 * @dev: PCI device to query 101 * @cap: capability code 102 * 103 * Tell if a device supports a given PCI capability. 104 * Returns the address of the requested capability structure within the 105 * device's PCI configuration space or 0 in case the device does not 106 * support it. Possible values for @cap: 107 * 108 * %PCI_CAP_ID_PM Power Management 109 * %PCI_CAP_ID_AGP Accelerated Graphics Port 110 * %PCI_CAP_ID_VPD Vital Product Data 111 * %PCI_CAP_ID_SLOTID Slot Identification 112 * %PCI_CAP_ID_MSI Message Signalled Interrupts 113 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap 114 * %PCI_CAP_ID_PCIX PCI-X 115 * %PCI_CAP_ID_EXP PCI Express 116 */ 117 int pci_find_capability(struct pci_dev *dev, int cap) 118 { 119 return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap); 120 } 121 122 /** 123 * pci_bus_find_capability - query for devices' capabilities 124 * @bus: the PCI bus to query 125 * @devfn: PCI device to query 126 * @cap: capability code 127 * 128 * Like pci_find_capability() but works for pci devices that do not have a 129 * pci_dev structure set up yet. 130 * 131 * Returns the address of the requested capability structure within the 132 * device's PCI configuration space or 0 in case the device does not 133 * support it. 134 */ 135 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) 136 { 137 u8 hdr_type; 138 139 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); 140 141 return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap); 142 } 143 144 /** 145 * pci_find_ext_capability - Find an extended capability 146 * @dev: PCI device to query 147 * @cap: capability code 148 * 149 * Returns the address of the requested extended capability structure 150 * within the device's PCI configuration space or 0 if the device does 151 * not support it. Possible values for @cap: 152 * 153 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 154 * %PCI_EXT_CAP_ID_VC Virtual Channel 155 * %PCI_EXT_CAP_ID_DSN Device Serial Number 156 * %PCI_EXT_CAP_ID_PWR Power Budgeting 157 */ 158 int pci_find_ext_capability(struct pci_dev *dev, int cap) 159 { 160 u32 header; 161 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ 162 int pos = 0x100; 163 164 if (dev->cfg_size <= 256) 165 return 0; 166 167 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 168 return 0; 169 170 /* 171 * If we have no capabilities, this is indicated by cap ID, 172 * cap version and next pointer all being 0. 173 */ 174 if (header == 0) 175 return 0; 176 177 while (ttl-- > 0) { 178 if (PCI_EXT_CAP_ID(header) == cap) 179 return pos; 180 181 pos = PCI_EXT_CAP_NEXT(header); 182 if (pos < 0x100) 183 break; 184 185 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 186 break; 187 } 188 189 return 0; 190 } 191 192 /** 193 * pci_find_parent_resource - return resource region of parent bus of given region 194 * @dev: PCI device structure contains resources to be searched 195 * @res: child resource record for which parent is sought 196 * 197 * For given resource region of given device, return the resource 198 * region of parent bus the given region is contained in or where 199 * it should be allocated from. 200 */ 201 struct resource * 202 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) 203 { 204 const struct pci_bus *bus = dev->bus; 205 int i; 206 struct resource *best = NULL; 207 208 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { 209 struct resource *r = bus->resource[i]; 210 if (!r) 211 continue; 212 if (res->start && !(res->start >= r->start && res->end <= r->end)) 213 continue; /* Not contained */ 214 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) 215 continue; /* Wrong type */ 216 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) 217 return r; /* Exact match */ 218 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) 219 best = r; /* Approximating prefetchable by non-prefetchable */ 220 } 221 return best; 222 } 223 224 /** 225 * pci_set_power_state - Set the power state of a PCI device 226 * @dev: PCI device to be suspended 227 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering 228 * 229 * Transition a device to a new power state, using the Power Management 230 * Capabilities in the device's config space. 231 * 232 * RETURN VALUE: 233 * -EINVAL if trying to enter a lower state than we're already in. 234 * 0 if we're already in the requested state. 235 * -EIO if device does not support PCI PM. 236 * 0 if we can successfully change the power state. 237 */ 238 239 int 240 pci_set_power_state(struct pci_dev *dev, pci_power_t state) 241 { 242 int pm; 243 u16 pmcsr, pmc; 244 245 /* bound the state we're entering */ 246 if (state > PCI_D3hot) 247 state = PCI_D3hot; 248 249 /* Validate current state: 250 * Can enter D0 from any state, but if we can only go deeper 251 * to sleep if we're already in a low power state 252 */ 253 if (state != PCI_D0 && dev->current_state > state) 254 return -EINVAL; 255 else if (dev->current_state == state) 256 return 0; /* we're already there */ 257 258 /* find PCI PM capability in list */ 259 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 260 261 /* abort if the device doesn't support PM capabilities */ 262 if (!pm) 263 return -EIO; 264 265 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc); 266 if ((pmc & PCI_PM_CAP_VER_MASK) > 2) { 267 printk(KERN_DEBUG 268 "PCI: %s has unsupported PM cap regs version (%u)\n", 269 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK); 270 return -EIO; 271 } 272 273 /* check if this device supports the desired state */ 274 if (state == PCI_D1 || state == PCI_D2) { 275 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) 276 return -EIO; 277 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)) 278 return -EIO; 279 } 280 281 /* If we're in D3, force entire word to 0. 282 * This doesn't affect PME_Status, disables PME_En, and 283 * sets PowerState to 0. 284 */ 285 if (dev->current_state >= PCI_D3hot) 286 pmcsr = 0; 287 else { 288 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); 289 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 290 pmcsr |= state; 291 } 292 293 /* enter specified state */ 294 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); 295 296 /* Mandatory power management transition delays */ 297 /* see PCI PM 1.1 5.6.1 table 18 */ 298 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) 299 msleep(10); 300 else if (state == PCI_D2 || dev->current_state == PCI_D2) 301 udelay(200); 302 dev->current_state = state; 303 304 return 0; 305 } 306 307 /** 308 * pci_choose_state - Choose the power state of a PCI device 309 * @dev: PCI device to be suspended 310 * @state: target sleep state for the whole system. This is the value 311 * that is passed to suspend() function. 312 * 313 * Returns PCI power state suitable for given device and given system 314 * message. 315 */ 316 317 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) 318 { 319 if (!pci_find_capability(dev, PCI_CAP_ID_PM)) 320 return PCI_D0; 321 322 switch (state) { 323 case 0: return PCI_D0; 324 case 3: return PCI_D3hot; 325 default: 326 printk("They asked me for state %d\n", state); 327 BUG(); 328 } 329 return PCI_D0; 330 } 331 332 EXPORT_SYMBOL(pci_choose_state); 333 334 /** 335 * pci_save_state - save the PCI configuration space of a device before suspending 336 * @dev: - PCI device that we're dealing with 337 */ 338 int 339 pci_save_state(struct pci_dev *dev) 340 { 341 int i; 342 /* XXX: 100% dword access ok here? */ 343 for (i = 0; i < 16; i++) 344 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); 345 return 0; 346 } 347 348 /** 349 * pci_restore_state - Restore the saved state of a PCI device 350 * @dev: - PCI device that we're dealing with 351 */ 352 int 353 pci_restore_state(struct pci_dev *dev) 354 { 355 int i; 356 357 for (i = 0; i < 16; i++) 358 pci_write_config_dword(dev,i * 4, dev->saved_config_space[i]); 359 return 0; 360 } 361 362 /** 363 * pci_enable_device_bars - Initialize some of a device for use 364 * @dev: PCI device to be initialized 365 * @bars: bitmask of BAR's that must be configured 366 * 367 * Initialize device before it's used by a driver. Ask low-level code 368 * to enable selected I/O and memory resources. Wake up the device if it 369 * was suspended. Beware, this function can fail. 370 */ 371 372 int 373 pci_enable_device_bars(struct pci_dev *dev, int bars) 374 { 375 int err; 376 377 pci_set_power_state(dev, PCI_D0); 378 if ((err = pcibios_enable_device(dev, bars)) < 0) 379 return err; 380 return 0; 381 } 382 383 /** 384 * pci_enable_device - Initialize device before it's used by a driver. 385 * @dev: PCI device to be initialized 386 * 387 * Initialize device before it's used by a driver. Ask low-level code 388 * to enable I/O and memory. Wake up the device if it was suspended. 389 * Beware, this function can fail. 390 */ 391 int 392 pci_enable_device(struct pci_dev *dev) 393 { 394 int err; 395 396 if ((err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1))) 397 return err; 398 pci_fixup_device(pci_fixup_enable, dev); 399 dev->is_enabled = 1; 400 return 0; 401 } 402 403 /** 404 * pcibios_disable_device - disable arch specific PCI resources for device dev 405 * @dev: the PCI device to disable 406 * 407 * Disables architecture specific PCI resources for the device. This 408 * is the default implementation. Architecture implementations can 409 * override this. 410 */ 411 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} 412 413 /** 414 * pci_disable_device - Disable PCI device after use 415 * @dev: PCI device to be disabled 416 * 417 * Signal to the system that the PCI device is not in use by the system 418 * anymore. This only involves disabling PCI bus-mastering, if active. 419 */ 420 void 421 pci_disable_device(struct pci_dev *dev) 422 { 423 u16 pci_command; 424 425 pci_read_config_word(dev, PCI_COMMAND, &pci_command); 426 if (pci_command & PCI_COMMAND_MASTER) { 427 pci_command &= ~PCI_COMMAND_MASTER; 428 pci_write_config_word(dev, PCI_COMMAND, pci_command); 429 } 430 dev->is_busmaster = 0; 431 432 pcibios_disable_device(dev); 433 dev->is_enabled = 0; 434 } 435 436 /** 437 * pci_enable_wake - enable device to generate PME# when suspended 438 * @dev: - PCI device to operate on 439 * @state: - Current state of device. 440 * @enable: - Flag to enable or disable generation 441 * 442 * Set the bits in the device's PM Capabilities to generate PME# when 443 * the system is suspended. 444 * 445 * -EIO is returned if device doesn't have PM Capabilities. 446 * -EINVAL is returned if device supports it, but can't generate wake events. 447 * 0 if operation is successful. 448 * 449 */ 450 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) 451 { 452 int pm; 453 u16 value; 454 455 /* find PCI PM capability in list */ 456 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 457 458 /* If device doesn't support PM Capabilities, but request is to disable 459 * wake events, it's a nop; otherwise fail */ 460 if (!pm) 461 return enable ? -EIO : 0; 462 463 /* Check device's ability to generate PME# */ 464 pci_read_config_word(dev,pm+PCI_PM_PMC,&value); 465 466 value &= PCI_PM_CAP_PME_MASK; 467 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ 468 469 /* Check if it can generate PME# from requested state. */ 470 if (!value || !(value & (1 << state))) 471 return enable ? -EINVAL : 0; 472 473 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value); 474 475 /* Clear PME_Status by writing 1 to it and enable PME# */ 476 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; 477 478 if (!enable) 479 value &= ~PCI_PM_CTRL_PME_ENABLE; 480 481 pci_write_config_word(dev, pm + PCI_PM_CTRL, value); 482 483 return 0; 484 } 485 486 int 487 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) 488 { 489 u8 pin; 490 491 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 492 if (!pin) 493 return -1; 494 pin--; 495 while (dev->bus->self) { 496 pin = (pin + PCI_SLOT(dev->devfn)) % 4; 497 dev = dev->bus->self; 498 } 499 *bridge = dev; 500 return pin; 501 } 502 503 /** 504 * pci_release_region - Release a PCI bar 505 * @pdev: PCI device whose resources were previously reserved by pci_request_region 506 * @bar: BAR to release 507 * 508 * Releases the PCI I/O and memory resources previously reserved by a 509 * successful call to pci_request_region. Call this function only 510 * after all use of the PCI regions has ceased. 511 */ 512 void pci_release_region(struct pci_dev *pdev, int bar) 513 { 514 if (pci_resource_len(pdev, bar) == 0) 515 return; 516 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) 517 release_region(pci_resource_start(pdev, bar), 518 pci_resource_len(pdev, bar)); 519 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) 520 release_mem_region(pci_resource_start(pdev, bar), 521 pci_resource_len(pdev, bar)); 522 } 523 524 /** 525 * pci_request_region - Reserved PCI I/O and memory resource 526 * @pdev: PCI device whose resources are to be reserved 527 * @bar: BAR to be reserved 528 * @res_name: Name to be associated with resource. 529 * 530 * Mark the PCI region associated with PCI device @pdev BR @bar as 531 * being reserved by owner @res_name. Do not access any 532 * address inside the PCI regions unless this call returns 533 * successfully. 534 * 535 * Returns 0 on success, or %EBUSY on error. A warning 536 * message is also printed on failure. 537 */ 538 int pci_request_region(struct pci_dev *pdev, int bar, char *res_name) 539 { 540 if (pci_resource_len(pdev, bar) == 0) 541 return 0; 542 543 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { 544 if (!request_region(pci_resource_start(pdev, bar), 545 pci_resource_len(pdev, bar), res_name)) 546 goto err_out; 547 } 548 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 549 if (!request_mem_region(pci_resource_start(pdev, bar), 550 pci_resource_len(pdev, bar), res_name)) 551 goto err_out; 552 } 553 554 return 0; 555 556 err_out: 557 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n", 558 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", 559 bar + 1, /* PCI BAR # */ 560 pci_resource_len(pdev, bar), pci_resource_start(pdev, bar), 561 pci_name(pdev)); 562 return -EBUSY; 563 } 564 565 566 /** 567 * pci_release_regions - Release reserved PCI I/O and memory resources 568 * @pdev: PCI device whose resources were previously reserved by pci_request_regions 569 * 570 * Releases all PCI I/O and memory resources previously reserved by a 571 * successful call to pci_request_regions. Call this function only 572 * after all use of the PCI regions has ceased. 573 */ 574 575 void pci_release_regions(struct pci_dev *pdev) 576 { 577 int i; 578 579 for (i = 0; i < 6; i++) 580 pci_release_region(pdev, i); 581 } 582 583 /** 584 * pci_request_regions - Reserved PCI I/O and memory resources 585 * @pdev: PCI device whose resources are to be reserved 586 * @res_name: Name to be associated with resource. 587 * 588 * Mark all PCI regions associated with PCI device @pdev as 589 * being reserved by owner @res_name. Do not access any 590 * address inside the PCI regions unless this call returns 591 * successfully. 592 * 593 * Returns 0 on success, or %EBUSY on error. A warning 594 * message is also printed on failure. 595 */ 596 int pci_request_regions(struct pci_dev *pdev, char *res_name) 597 { 598 int i; 599 600 for (i = 0; i < 6; i++) 601 if(pci_request_region(pdev, i, res_name)) 602 goto err_out; 603 return 0; 604 605 err_out: 606 while(--i >= 0) 607 pci_release_region(pdev, i); 608 609 return -EBUSY; 610 } 611 612 /** 613 * pci_set_master - enables bus-mastering for device dev 614 * @dev: the PCI device to enable 615 * 616 * Enables bus-mastering on the device and calls pcibios_set_master() 617 * to do the needed arch specific settings. 618 */ 619 void 620 pci_set_master(struct pci_dev *dev) 621 { 622 u16 cmd; 623 624 pci_read_config_word(dev, PCI_COMMAND, &cmd); 625 if (! (cmd & PCI_COMMAND_MASTER)) { 626 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev)); 627 cmd |= PCI_COMMAND_MASTER; 628 pci_write_config_word(dev, PCI_COMMAND, cmd); 629 } 630 dev->is_busmaster = 1; 631 pcibios_set_master(dev); 632 } 633 634 #ifndef HAVE_ARCH_PCI_MWI 635 /* This can be overridden by arch code. */ 636 u8 pci_cache_line_size = L1_CACHE_BYTES >> 2; 637 638 /** 639 * pci_generic_prep_mwi - helper function for pci_set_mwi 640 * @dev: the PCI device for which MWI is enabled 641 * 642 * Helper function for generic implementation of pcibios_prep_mwi 643 * function. Originally copied from drivers/net/acenic.c. 644 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. 645 * 646 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 647 */ 648 static int 649 pci_generic_prep_mwi(struct pci_dev *dev) 650 { 651 u8 cacheline_size; 652 653 if (!pci_cache_line_size) 654 return -EINVAL; /* The system doesn't support MWI. */ 655 656 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be 657 equal to or multiple of the right value. */ 658 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 659 if (cacheline_size >= pci_cache_line_size && 660 (cacheline_size % pci_cache_line_size) == 0) 661 return 0; 662 663 /* Write the correct value. */ 664 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); 665 /* Read it back. */ 666 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 667 if (cacheline_size == pci_cache_line_size) 668 return 0; 669 670 printk(KERN_DEBUG "PCI: cache line size of %d is not supported " 671 "by device %s\n", pci_cache_line_size << 2, pci_name(dev)); 672 673 return -EINVAL; 674 } 675 #endif /* !HAVE_ARCH_PCI_MWI */ 676 677 /** 678 * pci_set_mwi - enables memory-write-invalidate PCI transaction 679 * @dev: the PCI device for which MWI is enabled 680 * 681 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND, 682 * and then calls @pcibios_set_mwi to do the needed arch specific 683 * operations or a generic mwi-prep function. 684 * 685 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 686 */ 687 int 688 pci_set_mwi(struct pci_dev *dev) 689 { 690 int rc; 691 u16 cmd; 692 693 #ifdef HAVE_ARCH_PCI_MWI 694 rc = pcibios_prep_mwi(dev); 695 #else 696 rc = pci_generic_prep_mwi(dev); 697 #endif 698 699 if (rc) 700 return rc; 701 702 pci_read_config_word(dev, PCI_COMMAND, &cmd); 703 if (! (cmd & PCI_COMMAND_INVALIDATE)) { 704 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev)); 705 cmd |= PCI_COMMAND_INVALIDATE; 706 pci_write_config_word(dev, PCI_COMMAND, cmd); 707 } 708 709 return 0; 710 } 711 712 /** 713 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev 714 * @dev: the PCI device to disable 715 * 716 * Disables PCI Memory-Write-Invalidate transaction on the device 717 */ 718 void 719 pci_clear_mwi(struct pci_dev *dev) 720 { 721 u16 cmd; 722 723 pci_read_config_word(dev, PCI_COMMAND, &cmd); 724 if (cmd & PCI_COMMAND_INVALIDATE) { 725 cmd &= ~PCI_COMMAND_INVALIDATE; 726 pci_write_config_word(dev, PCI_COMMAND, cmd); 727 } 728 } 729 730 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK 731 /* 732 * These can be overridden by arch-specific implementations 733 */ 734 int 735 pci_set_dma_mask(struct pci_dev *dev, u64 mask) 736 { 737 if (!pci_dma_supported(dev, mask)) 738 return -EIO; 739 740 dev->dma_mask = mask; 741 742 return 0; 743 } 744 745 int 746 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 747 { 748 if (!pci_dma_supported(dev, mask)) 749 return -EIO; 750 751 dev->dev.coherent_dma_mask = mask; 752 753 return 0; 754 } 755 #endif 756 757 static int __devinit pci_init(void) 758 { 759 struct pci_dev *dev = NULL; 760 761 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { 762 pci_fixup_device(pci_fixup_final, dev); 763 } 764 return 0; 765 } 766 767 static int __devinit pci_setup(char *str) 768 { 769 while (str) { 770 char *k = strchr(str, ','); 771 if (k) 772 *k++ = 0; 773 if (*str && (str = pcibios_setup(str)) && *str) { 774 /* PCI layer options should be handled here */ 775 printk(KERN_ERR "PCI: Unknown option `%s'\n", str); 776 } 777 str = k; 778 } 779 return 1; 780 } 781 782 device_initcall(pci_init); 783 784 __setup("pci=", pci_setup); 785 786 #if defined(CONFIG_ISA) || defined(CONFIG_EISA) 787 /* FIXME: Some boxes have multiple ISA bridges! */ 788 struct pci_dev *isa_bridge; 789 EXPORT_SYMBOL(isa_bridge); 790 #endif 791 792 EXPORT_SYMBOL(pci_enable_device_bars); 793 EXPORT_SYMBOL(pci_enable_device); 794 EXPORT_SYMBOL(pci_disable_device); 795 EXPORT_SYMBOL(pci_max_busnr); 796 EXPORT_SYMBOL(pci_bus_max_busnr); 797 EXPORT_SYMBOL(pci_find_capability); 798 EXPORT_SYMBOL(pci_bus_find_capability); 799 EXPORT_SYMBOL(pci_release_regions); 800 EXPORT_SYMBOL(pci_request_regions); 801 EXPORT_SYMBOL(pci_release_region); 802 EXPORT_SYMBOL(pci_request_region); 803 EXPORT_SYMBOL(pci_set_master); 804 EXPORT_SYMBOL(pci_set_mwi); 805 EXPORT_SYMBOL(pci_clear_mwi); 806 EXPORT_SYMBOL(pci_set_dma_mask); 807 EXPORT_SYMBOL(pci_set_consistent_dma_mask); 808 EXPORT_SYMBOL(pci_assign_resource); 809 EXPORT_SYMBOL(pci_find_parent_resource); 810 811 EXPORT_SYMBOL(pci_set_power_state); 812 EXPORT_SYMBOL(pci_save_state); 813 EXPORT_SYMBOL(pci_restore_state); 814 EXPORT_SYMBOL(pci_enable_wake); 815 816 /* Quirk info */ 817 818 EXPORT_SYMBOL(isa_dma_bridge_buggy); 819 EXPORT_SYMBOL(pci_pci_problems); 820