xref: /linux/drivers/pci/iov.c (revision 363c75db1d7bbda0aa90e680565f2673bab92ee4)
1d1b054daSYu Zhao /*
2d1b054daSYu Zhao  * drivers/pci/iov.c
3d1b054daSYu Zhao  *
4d1b054daSYu Zhao  * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
5d1b054daSYu Zhao  *
6d1b054daSYu Zhao  * PCI Express I/O Virtualization (IOV) support.
7d1b054daSYu Zhao  *   Single Root IOV 1.0
8302b4215SYu Zhao  *   Address Translation Service 1.0
9d1b054daSYu Zhao  */
10d1b054daSYu Zhao 
11d1b054daSYu Zhao #include <linux/pci.h>
125a0e3ad6STejun Heo #include <linux/slab.h>
13d1b054daSYu Zhao #include <linux/mutex.h>
14*363c75dbSPaul Gortmaker #include <linux/export.h>
15d1b054daSYu Zhao #include <linux/string.h>
16d1b054daSYu Zhao #include <linux/delay.h>
175cdede24SJoerg Roedel #include <linux/pci-ats.h>
18d1b054daSYu Zhao #include "pci.h"
19d1b054daSYu Zhao 
20dd7cc44dSYu Zhao #define VIRTFN_ID_LEN	16
21d1b054daSYu Zhao 
22a28724b0SYu Zhao static inline u8 virtfn_bus(struct pci_dev *dev, int id)
23a28724b0SYu Zhao {
24a28724b0SYu Zhao 	return dev->bus->number + ((dev->devfn + dev->sriov->offset +
25a28724b0SYu Zhao 				    dev->sriov->stride * id) >> 8);
26a28724b0SYu Zhao }
27a28724b0SYu Zhao 
28a28724b0SYu Zhao static inline u8 virtfn_devfn(struct pci_dev *dev, int id)
29a28724b0SYu Zhao {
30a28724b0SYu Zhao 	return (dev->devfn + dev->sriov->offset +
31a28724b0SYu Zhao 		dev->sriov->stride * id) & 0xff;
32a28724b0SYu Zhao }
33a28724b0SYu Zhao 
34dd7cc44dSYu Zhao static struct pci_bus *virtfn_add_bus(struct pci_bus *bus, int busnr)
35dd7cc44dSYu Zhao {
36dd7cc44dSYu Zhao 	int rc;
37dd7cc44dSYu Zhao 	struct pci_bus *child;
38dd7cc44dSYu Zhao 
39dd7cc44dSYu Zhao 	if (bus->number == busnr)
40dd7cc44dSYu Zhao 		return bus;
41dd7cc44dSYu Zhao 
42dd7cc44dSYu Zhao 	child = pci_find_bus(pci_domain_nr(bus), busnr);
43dd7cc44dSYu Zhao 	if (child)
44dd7cc44dSYu Zhao 		return child;
45dd7cc44dSYu Zhao 
46dd7cc44dSYu Zhao 	child = pci_add_new_bus(bus, NULL, busnr);
47dd7cc44dSYu Zhao 	if (!child)
48dd7cc44dSYu Zhao 		return NULL;
49dd7cc44dSYu Zhao 
50dd7cc44dSYu Zhao 	child->subordinate = busnr;
51dd7cc44dSYu Zhao 	child->dev.parent = bus->bridge;
52dd7cc44dSYu Zhao 	rc = pci_bus_add_child(child);
53dd7cc44dSYu Zhao 	if (rc) {
54dd7cc44dSYu Zhao 		pci_remove_bus(child);
55dd7cc44dSYu Zhao 		return NULL;
56dd7cc44dSYu Zhao 	}
57dd7cc44dSYu Zhao 
58dd7cc44dSYu Zhao 	return child;
59dd7cc44dSYu Zhao }
60dd7cc44dSYu Zhao 
61dd7cc44dSYu Zhao static void virtfn_remove_bus(struct pci_bus *bus, int busnr)
62dd7cc44dSYu Zhao {
63dd7cc44dSYu Zhao 	struct pci_bus *child;
64dd7cc44dSYu Zhao 
65dd7cc44dSYu Zhao 	if (bus->number == busnr)
66dd7cc44dSYu Zhao 		return;
67dd7cc44dSYu Zhao 
68dd7cc44dSYu Zhao 	child = pci_find_bus(pci_domain_nr(bus), busnr);
69dd7cc44dSYu Zhao 	BUG_ON(!child);
70dd7cc44dSYu Zhao 
71dd7cc44dSYu Zhao 	if (list_empty(&child->devices))
72dd7cc44dSYu Zhao 		pci_remove_bus(child);
73dd7cc44dSYu Zhao }
74dd7cc44dSYu Zhao 
75dd7cc44dSYu Zhao static int virtfn_add(struct pci_dev *dev, int id, int reset)
76dd7cc44dSYu Zhao {
77dd7cc44dSYu Zhao 	int i;
78dd7cc44dSYu Zhao 	int rc;
79dd7cc44dSYu Zhao 	u64 size;
80dd7cc44dSYu Zhao 	char buf[VIRTFN_ID_LEN];
81dd7cc44dSYu Zhao 	struct pci_dev *virtfn;
82dd7cc44dSYu Zhao 	struct resource *res;
83dd7cc44dSYu Zhao 	struct pci_sriov *iov = dev->sriov;
84dd7cc44dSYu Zhao 
85dd7cc44dSYu Zhao 	virtfn = alloc_pci_dev();
86dd7cc44dSYu Zhao 	if (!virtfn)
87dd7cc44dSYu Zhao 		return -ENOMEM;
88dd7cc44dSYu Zhao 
89dd7cc44dSYu Zhao 	mutex_lock(&iov->dev->sriov->lock);
90dd7cc44dSYu Zhao 	virtfn->bus = virtfn_add_bus(dev->bus, virtfn_bus(dev, id));
91dd7cc44dSYu Zhao 	if (!virtfn->bus) {
92dd7cc44dSYu Zhao 		kfree(virtfn);
93dd7cc44dSYu Zhao 		mutex_unlock(&iov->dev->sriov->lock);
94dd7cc44dSYu Zhao 		return -ENOMEM;
95dd7cc44dSYu Zhao 	}
96dd7cc44dSYu Zhao 	virtfn->devfn = virtfn_devfn(dev, id);
97dd7cc44dSYu Zhao 	virtfn->vendor = dev->vendor;
98dd7cc44dSYu Zhao 	pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_DID, &virtfn->device);
99dd7cc44dSYu Zhao 	pci_setup_device(virtfn);
100dd7cc44dSYu Zhao 	virtfn->dev.parent = dev->dev.parent;
101dd7cc44dSYu Zhao 
102dd7cc44dSYu Zhao 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
103dd7cc44dSYu Zhao 		res = dev->resource + PCI_IOV_RESOURCES + i;
104dd7cc44dSYu Zhao 		if (!res->parent)
105dd7cc44dSYu Zhao 			continue;
106dd7cc44dSYu Zhao 		virtfn->resource[i].name = pci_name(virtfn);
107dd7cc44dSYu Zhao 		virtfn->resource[i].flags = res->flags;
108dd7cc44dSYu Zhao 		size = resource_size(res);
109dd7cc44dSYu Zhao 		do_div(size, iov->total);
110dd7cc44dSYu Zhao 		virtfn->resource[i].start = res->start + size * id;
111dd7cc44dSYu Zhao 		virtfn->resource[i].end = virtfn->resource[i].start + size - 1;
112dd7cc44dSYu Zhao 		rc = request_resource(res, &virtfn->resource[i]);
113dd7cc44dSYu Zhao 		BUG_ON(rc);
114dd7cc44dSYu Zhao 	}
115dd7cc44dSYu Zhao 
116dd7cc44dSYu Zhao 	if (reset)
1178c1c699fSYu Zhao 		__pci_reset_function(virtfn);
118dd7cc44dSYu Zhao 
119dd7cc44dSYu Zhao 	pci_device_add(virtfn, virtfn->bus);
120dd7cc44dSYu Zhao 	mutex_unlock(&iov->dev->sriov->lock);
121dd7cc44dSYu Zhao 
122dd7cc44dSYu Zhao 	virtfn->physfn = pci_dev_get(dev);
123dd7cc44dSYu Zhao 	virtfn->is_virtfn = 1;
124dd7cc44dSYu Zhao 
125dd7cc44dSYu Zhao 	rc = pci_bus_add_device(virtfn);
126dd7cc44dSYu Zhao 	if (rc)
127dd7cc44dSYu Zhao 		goto failed1;
128dd7cc44dSYu Zhao 	sprintf(buf, "virtfn%u", id);
129dd7cc44dSYu Zhao 	rc = sysfs_create_link(&dev->dev.kobj, &virtfn->dev.kobj, buf);
130dd7cc44dSYu Zhao 	if (rc)
131dd7cc44dSYu Zhao 		goto failed1;
132dd7cc44dSYu Zhao 	rc = sysfs_create_link(&virtfn->dev.kobj, &dev->dev.kobj, "physfn");
133dd7cc44dSYu Zhao 	if (rc)
134dd7cc44dSYu Zhao 		goto failed2;
135dd7cc44dSYu Zhao 
136dd7cc44dSYu Zhao 	kobject_uevent(&virtfn->dev.kobj, KOBJ_CHANGE);
137dd7cc44dSYu Zhao 
138dd7cc44dSYu Zhao 	return 0;
139dd7cc44dSYu Zhao 
140dd7cc44dSYu Zhao failed2:
141dd7cc44dSYu Zhao 	sysfs_remove_link(&dev->dev.kobj, buf);
142dd7cc44dSYu Zhao failed1:
143dd7cc44dSYu Zhao 	pci_dev_put(dev);
144dd7cc44dSYu Zhao 	mutex_lock(&iov->dev->sriov->lock);
145dd7cc44dSYu Zhao 	pci_remove_bus_device(virtfn);
146dd7cc44dSYu Zhao 	virtfn_remove_bus(dev->bus, virtfn_bus(dev, id));
147dd7cc44dSYu Zhao 	mutex_unlock(&iov->dev->sriov->lock);
148dd7cc44dSYu Zhao 
149dd7cc44dSYu Zhao 	return rc;
150dd7cc44dSYu Zhao }
151dd7cc44dSYu Zhao 
152dd7cc44dSYu Zhao static void virtfn_remove(struct pci_dev *dev, int id, int reset)
153dd7cc44dSYu Zhao {
154dd7cc44dSYu Zhao 	char buf[VIRTFN_ID_LEN];
155dd7cc44dSYu Zhao 	struct pci_bus *bus;
156dd7cc44dSYu Zhao 	struct pci_dev *virtfn;
157dd7cc44dSYu Zhao 	struct pci_sriov *iov = dev->sriov;
158dd7cc44dSYu Zhao 
159dd7cc44dSYu Zhao 	bus = pci_find_bus(pci_domain_nr(dev->bus), virtfn_bus(dev, id));
160dd7cc44dSYu Zhao 	if (!bus)
161dd7cc44dSYu Zhao 		return;
162dd7cc44dSYu Zhao 
163dd7cc44dSYu Zhao 	virtfn = pci_get_slot(bus, virtfn_devfn(dev, id));
164dd7cc44dSYu Zhao 	if (!virtfn)
165dd7cc44dSYu Zhao 		return;
166dd7cc44dSYu Zhao 
167dd7cc44dSYu Zhao 	pci_dev_put(virtfn);
168dd7cc44dSYu Zhao 
169dd7cc44dSYu Zhao 	if (reset) {
170dd7cc44dSYu Zhao 		device_release_driver(&virtfn->dev);
1718c1c699fSYu Zhao 		__pci_reset_function(virtfn);
172dd7cc44dSYu Zhao 	}
173dd7cc44dSYu Zhao 
174dd7cc44dSYu Zhao 	sprintf(buf, "virtfn%u", id);
175dd7cc44dSYu Zhao 	sysfs_remove_link(&dev->dev.kobj, buf);
176dd7cc44dSYu Zhao 	sysfs_remove_link(&virtfn->dev.kobj, "physfn");
177dd7cc44dSYu Zhao 
178dd7cc44dSYu Zhao 	mutex_lock(&iov->dev->sriov->lock);
179dd7cc44dSYu Zhao 	pci_remove_bus_device(virtfn);
180dd7cc44dSYu Zhao 	virtfn_remove_bus(dev->bus, virtfn_bus(dev, id));
181dd7cc44dSYu Zhao 	mutex_unlock(&iov->dev->sriov->lock);
182dd7cc44dSYu Zhao 
183dd7cc44dSYu Zhao 	pci_dev_put(dev);
184dd7cc44dSYu Zhao }
185dd7cc44dSYu Zhao 
18674bb1bccSYu Zhao static int sriov_migration(struct pci_dev *dev)
18774bb1bccSYu Zhao {
18874bb1bccSYu Zhao 	u16 status;
18974bb1bccSYu Zhao 	struct pci_sriov *iov = dev->sriov;
19074bb1bccSYu Zhao 
19174bb1bccSYu Zhao 	if (!iov->nr_virtfn)
19274bb1bccSYu Zhao 		return 0;
19374bb1bccSYu Zhao 
19474bb1bccSYu Zhao 	if (!(iov->cap & PCI_SRIOV_CAP_VFM))
19574bb1bccSYu Zhao 		return 0;
19674bb1bccSYu Zhao 
19774bb1bccSYu Zhao 	pci_read_config_word(dev, iov->pos + PCI_SRIOV_STATUS, &status);
19874bb1bccSYu Zhao 	if (!(status & PCI_SRIOV_STATUS_VFM))
19974bb1bccSYu Zhao 		return 0;
20074bb1bccSYu Zhao 
20174bb1bccSYu Zhao 	schedule_work(&iov->mtask);
20274bb1bccSYu Zhao 
20374bb1bccSYu Zhao 	return 1;
20474bb1bccSYu Zhao }
20574bb1bccSYu Zhao 
20674bb1bccSYu Zhao static void sriov_migration_task(struct work_struct *work)
20774bb1bccSYu Zhao {
20874bb1bccSYu Zhao 	int i;
20974bb1bccSYu Zhao 	u8 state;
21074bb1bccSYu Zhao 	u16 status;
21174bb1bccSYu Zhao 	struct pci_sriov *iov = container_of(work, struct pci_sriov, mtask);
21274bb1bccSYu Zhao 
21374bb1bccSYu Zhao 	for (i = iov->initial; i < iov->nr_virtfn; i++) {
21474bb1bccSYu Zhao 		state = readb(iov->mstate + i);
21574bb1bccSYu Zhao 		if (state == PCI_SRIOV_VFM_MI) {
21674bb1bccSYu Zhao 			writeb(PCI_SRIOV_VFM_AV, iov->mstate + i);
21774bb1bccSYu Zhao 			state = readb(iov->mstate + i);
21874bb1bccSYu Zhao 			if (state == PCI_SRIOV_VFM_AV)
21974bb1bccSYu Zhao 				virtfn_add(iov->self, i, 1);
22074bb1bccSYu Zhao 		} else if (state == PCI_SRIOV_VFM_MO) {
22174bb1bccSYu Zhao 			virtfn_remove(iov->self, i, 1);
22274bb1bccSYu Zhao 			writeb(PCI_SRIOV_VFM_UA, iov->mstate + i);
22374bb1bccSYu Zhao 			state = readb(iov->mstate + i);
22474bb1bccSYu Zhao 			if (state == PCI_SRIOV_VFM_AV)
22574bb1bccSYu Zhao 				virtfn_add(iov->self, i, 0);
22674bb1bccSYu Zhao 		}
22774bb1bccSYu Zhao 	}
22874bb1bccSYu Zhao 
22974bb1bccSYu Zhao 	pci_read_config_word(iov->self, iov->pos + PCI_SRIOV_STATUS, &status);
23074bb1bccSYu Zhao 	status &= ~PCI_SRIOV_STATUS_VFM;
23174bb1bccSYu Zhao 	pci_write_config_word(iov->self, iov->pos + PCI_SRIOV_STATUS, status);
23274bb1bccSYu Zhao }
23374bb1bccSYu Zhao 
23474bb1bccSYu Zhao static int sriov_enable_migration(struct pci_dev *dev, int nr_virtfn)
23574bb1bccSYu Zhao {
23674bb1bccSYu Zhao 	int bir;
23774bb1bccSYu Zhao 	u32 table;
23874bb1bccSYu Zhao 	resource_size_t pa;
23974bb1bccSYu Zhao 	struct pci_sriov *iov = dev->sriov;
24074bb1bccSYu Zhao 
24174bb1bccSYu Zhao 	if (nr_virtfn <= iov->initial)
24274bb1bccSYu Zhao 		return 0;
24374bb1bccSYu Zhao 
24474bb1bccSYu Zhao 	pci_read_config_dword(dev, iov->pos + PCI_SRIOV_VFM, &table);
24574bb1bccSYu Zhao 	bir = PCI_SRIOV_VFM_BIR(table);
24674bb1bccSYu Zhao 	if (bir > PCI_STD_RESOURCE_END)
24774bb1bccSYu Zhao 		return -EIO;
24874bb1bccSYu Zhao 
24974bb1bccSYu Zhao 	table = PCI_SRIOV_VFM_OFFSET(table);
25074bb1bccSYu Zhao 	if (table + nr_virtfn > pci_resource_len(dev, bir))
25174bb1bccSYu Zhao 		return -EIO;
25274bb1bccSYu Zhao 
25374bb1bccSYu Zhao 	pa = pci_resource_start(dev, bir) + table;
25474bb1bccSYu Zhao 	iov->mstate = ioremap(pa, nr_virtfn);
25574bb1bccSYu Zhao 	if (!iov->mstate)
25674bb1bccSYu Zhao 		return -ENOMEM;
25774bb1bccSYu Zhao 
25874bb1bccSYu Zhao 	INIT_WORK(&iov->mtask, sriov_migration_task);
25974bb1bccSYu Zhao 
26074bb1bccSYu Zhao 	iov->ctrl |= PCI_SRIOV_CTRL_VFM | PCI_SRIOV_CTRL_INTR;
26174bb1bccSYu Zhao 	pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
26274bb1bccSYu Zhao 
26374bb1bccSYu Zhao 	return 0;
26474bb1bccSYu Zhao }
26574bb1bccSYu Zhao 
26674bb1bccSYu Zhao static void sriov_disable_migration(struct pci_dev *dev)
26774bb1bccSYu Zhao {
26874bb1bccSYu Zhao 	struct pci_sriov *iov = dev->sriov;
26974bb1bccSYu Zhao 
27074bb1bccSYu Zhao 	iov->ctrl &= ~(PCI_SRIOV_CTRL_VFM | PCI_SRIOV_CTRL_INTR);
27174bb1bccSYu Zhao 	pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
27274bb1bccSYu Zhao 
27374bb1bccSYu Zhao 	cancel_work_sync(&iov->mtask);
27474bb1bccSYu Zhao 	iounmap(iov->mstate);
27574bb1bccSYu Zhao }
27674bb1bccSYu Zhao 
277dd7cc44dSYu Zhao static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
278dd7cc44dSYu Zhao {
279dd7cc44dSYu Zhao 	int rc;
280dd7cc44dSYu Zhao 	int i, j;
281dd7cc44dSYu Zhao 	int nres;
282dd7cc44dSYu Zhao 	u16 offset, stride, initial;
283dd7cc44dSYu Zhao 	struct resource *res;
284dd7cc44dSYu Zhao 	struct pci_dev *pdev;
285dd7cc44dSYu Zhao 	struct pci_sriov *iov = dev->sriov;
286dd7cc44dSYu Zhao 
287dd7cc44dSYu Zhao 	if (!nr_virtfn)
288dd7cc44dSYu Zhao 		return 0;
289dd7cc44dSYu Zhao 
290dd7cc44dSYu Zhao 	if (iov->nr_virtfn)
291dd7cc44dSYu Zhao 		return -EINVAL;
292dd7cc44dSYu Zhao 
293dd7cc44dSYu Zhao 	pci_read_config_word(dev, iov->pos + PCI_SRIOV_INITIAL_VF, &initial);
294dd7cc44dSYu Zhao 	if (initial > iov->total ||
295dd7cc44dSYu Zhao 	    (!(iov->cap & PCI_SRIOV_CAP_VFM) && (initial != iov->total)))
296dd7cc44dSYu Zhao 		return -EIO;
297dd7cc44dSYu Zhao 
298dd7cc44dSYu Zhao 	if (nr_virtfn < 0 || nr_virtfn > iov->total ||
299dd7cc44dSYu Zhao 	    (!(iov->cap & PCI_SRIOV_CAP_VFM) && (nr_virtfn > initial)))
300dd7cc44dSYu Zhao 		return -EINVAL;
301dd7cc44dSYu Zhao 
302dd7cc44dSYu Zhao 	pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, nr_virtfn);
303dd7cc44dSYu Zhao 	pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_OFFSET, &offset);
304dd7cc44dSYu Zhao 	pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_STRIDE, &stride);
305dd7cc44dSYu Zhao 	if (!offset || (nr_virtfn > 1 && !stride))
306dd7cc44dSYu Zhao 		return -EIO;
307dd7cc44dSYu Zhao 
308dd7cc44dSYu Zhao 	nres = 0;
309dd7cc44dSYu Zhao 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
310dd7cc44dSYu Zhao 		res = dev->resource + PCI_IOV_RESOURCES + i;
311dd7cc44dSYu Zhao 		if (res->parent)
312dd7cc44dSYu Zhao 			nres++;
313dd7cc44dSYu Zhao 	}
314dd7cc44dSYu Zhao 	if (nres != iov->nres) {
315dd7cc44dSYu Zhao 		dev_err(&dev->dev, "not enough MMIO resources for SR-IOV\n");
316dd7cc44dSYu Zhao 		return -ENOMEM;
317dd7cc44dSYu Zhao 	}
318dd7cc44dSYu Zhao 
319dd7cc44dSYu Zhao 	iov->offset = offset;
320dd7cc44dSYu Zhao 	iov->stride = stride;
321dd7cc44dSYu Zhao 
322dd7cc44dSYu Zhao 	if (virtfn_bus(dev, nr_virtfn - 1) > dev->bus->subordinate) {
323dd7cc44dSYu Zhao 		dev_err(&dev->dev, "SR-IOV: bus number out of range\n");
324dd7cc44dSYu Zhao 		return -ENOMEM;
325dd7cc44dSYu Zhao 	}
326dd7cc44dSYu Zhao 
327dd7cc44dSYu Zhao 	if (iov->link != dev->devfn) {
328dd7cc44dSYu Zhao 		pdev = pci_get_slot(dev->bus, iov->link);
329dd7cc44dSYu Zhao 		if (!pdev)
330dd7cc44dSYu Zhao 			return -ENODEV;
331dd7cc44dSYu Zhao 
332dd7cc44dSYu Zhao 		pci_dev_put(pdev);
333dd7cc44dSYu Zhao 
334dd7cc44dSYu Zhao 		if (!pdev->is_physfn)
335dd7cc44dSYu Zhao 			return -ENODEV;
336dd7cc44dSYu Zhao 
337dd7cc44dSYu Zhao 		rc = sysfs_create_link(&dev->dev.kobj,
338dd7cc44dSYu Zhao 					&pdev->dev.kobj, "dep_link");
339dd7cc44dSYu Zhao 		if (rc)
340dd7cc44dSYu Zhao 			return rc;
341dd7cc44dSYu Zhao 	}
342dd7cc44dSYu Zhao 
343dd7cc44dSYu Zhao 	iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
344dd7cc44dSYu Zhao 	pci_block_user_cfg_access(dev);
345dd7cc44dSYu Zhao 	pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
346dd7cc44dSYu Zhao 	msleep(100);
347dd7cc44dSYu Zhao 	pci_unblock_user_cfg_access(dev);
348dd7cc44dSYu Zhao 
349dd7cc44dSYu Zhao 	iov->initial = initial;
350dd7cc44dSYu Zhao 	if (nr_virtfn < initial)
351dd7cc44dSYu Zhao 		initial = nr_virtfn;
352dd7cc44dSYu Zhao 
353dd7cc44dSYu Zhao 	for (i = 0; i < initial; i++) {
354dd7cc44dSYu Zhao 		rc = virtfn_add(dev, i, 0);
355dd7cc44dSYu Zhao 		if (rc)
356dd7cc44dSYu Zhao 			goto failed;
357dd7cc44dSYu Zhao 	}
358dd7cc44dSYu Zhao 
35974bb1bccSYu Zhao 	if (iov->cap & PCI_SRIOV_CAP_VFM) {
36074bb1bccSYu Zhao 		rc = sriov_enable_migration(dev, nr_virtfn);
36174bb1bccSYu Zhao 		if (rc)
36274bb1bccSYu Zhao 			goto failed;
36374bb1bccSYu Zhao 	}
36474bb1bccSYu Zhao 
365dd7cc44dSYu Zhao 	kobject_uevent(&dev->dev.kobj, KOBJ_CHANGE);
366dd7cc44dSYu Zhao 	iov->nr_virtfn = nr_virtfn;
367dd7cc44dSYu Zhao 
368dd7cc44dSYu Zhao 	return 0;
369dd7cc44dSYu Zhao 
370dd7cc44dSYu Zhao failed:
371dd7cc44dSYu Zhao 	for (j = 0; j < i; j++)
372dd7cc44dSYu Zhao 		virtfn_remove(dev, j, 0);
373dd7cc44dSYu Zhao 
374dd7cc44dSYu Zhao 	iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
375dd7cc44dSYu Zhao 	pci_block_user_cfg_access(dev);
376dd7cc44dSYu Zhao 	pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
377dd7cc44dSYu Zhao 	ssleep(1);
378dd7cc44dSYu Zhao 	pci_unblock_user_cfg_access(dev);
379dd7cc44dSYu Zhao 
380dd7cc44dSYu Zhao 	if (iov->link != dev->devfn)
381dd7cc44dSYu Zhao 		sysfs_remove_link(&dev->dev.kobj, "dep_link");
382dd7cc44dSYu Zhao 
383dd7cc44dSYu Zhao 	return rc;
384dd7cc44dSYu Zhao }
385dd7cc44dSYu Zhao 
386dd7cc44dSYu Zhao static void sriov_disable(struct pci_dev *dev)
387dd7cc44dSYu Zhao {
388dd7cc44dSYu Zhao 	int i;
389dd7cc44dSYu Zhao 	struct pci_sriov *iov = dev->sriov;
390dd7cc44dSYu Zhao 
391dd7cc44dSYu Zhao 	if (!iov->nr_virtfn)
392dd7cc44dSYu Zhao 		return;
393dd7cc44dSYu Zhao 
39474bb1bccSYu Zhao 	if (iov->cap & PCI_SRIOV_CAP_VFM)
39574bb1bccSYu Zhao 		sriov_disable_migration(dev);
39674bb1bccSYu Zhao 
397dd7cc44dSYu Zhao 	for (i = 0; i < iov->nr_virtfn; i++)
398dd7cc44dSYu Zhao 		virtfn_remove(dev, i, 0);
399dd7cc44dSYu Zhao 
400dd7cc44dSYu Zhao 	iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
401dd7cc44dSYu Zhao 	pci_block_user_cfg_access(dev);
402dd7cc44dSYu Zhao 	pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
403dd7cc44dSYu Zhao 	ssleep(1);
404dd7cc44dSYu Zhao 	pci_unblock_user_cfg_access(dev);
405dd7cc44dSYu Zhao 
406dd7cc44dSYu Zhao 	if (iov->link != dev->devfn)
407dd7cc44dSYu Zhao 		sysfs_remove_link(&dev->dev.kobj, "dep_link");
408dd7cc44dSYu Zhao 
409dd7cc44dSYu Zhao 	iov->nr_virtfn = 0;
410dd7cc44dSYu Zhao }
411dd7cc44dSYu Zhao 
412d1b054daSYu Zhao static int sriov_init(struct pci_dev *dev, int pos)
413d1b054daSYu Zhao {
414d1b054daSYu Zhao 	int i;
415d1b054daSYu Zhao 	int rc;
416d1b054daSYu Zhao 	int nres;
417d1b054daSYu Zhao 	u32 pgsz;
418d1b054daSYu Zhao 	u16 ctrl, total, offset, stride;
419d1b054daSYu Zhao 	struct pci_sriov *iov;
420d1b054daSYu Zhao 	struct resource *res;
421d1b054daSYu Zhao 	struct pci_dev *pdev;
422d1b054daSYu Zhao 
423d1b054daSYu Zhao 	if (dev->pcie_type != PCI_EXP_TYPE_RC_END &&
424d1b054daSYu Zhao 	    dev->pcie_type != PCI_EXP_TYPE_ENDPOINT)
425d1b054daSYu Zhao 		return -ENODEV;
426d1b054daSYu Zhao 
427d1b054daSYu Zhao 	pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &ctrl);
428d1b054daSYu Zhao 	if (ctrl & PCI_SRIOV_CTRL_VFE) {
429d1b054daSYu Zhao 		pci_write_config_word(dev, pos + PCI_SRIOV_CTRL, 0);
430d1b054daSYu Zhao 		ssleep(1);
431d1b054daSYu Zhao 	}
432d1b054daSYu Zhao 
433d1b054daSYu Zhao 	pci_read_config_word(dev, pos + PCI_SRIOV_TOTAL_VF, &total);
434d1b054daSYu Zhao 	if (!total)
435d1b054daSYu Zhao 		return 0;
436d1b054daSYu Zhao 
437d1b054daSYu Zhao 	ctrl = 0;
438d1b054daSYu Zhao 	list_for_each_entry(pdev, &dev->bus->devices, bus_list)
439d1b054daSYu Zhao 		if (pdev->is_physfn)
440d1b054daSYu Zhao 			goto found;
441d1b054daSYu Zhao 
442d1b054daSYu Zhao 	pdev = NULL;
443d1b054daSYu Zhao 	if (pci_ari_enabled(dev->bus))
444d1b054daSYu Zhao 		ctrl |= PCI_SRIOV_CTRL_ARI;
445d1b054daSYu Zhao 
446d1b054daSYu Zhao found:
447d1b054daSYu Zhao 	pci_write_config_word(dev, pos + PCI_SRIOV_CTRL, ctrl);
448d1b054daSYu Zhao 	pci_write_config_word(dev, pos + PCI_SRIOV_NUM_VF, total);
449d1b054daSYu Zhao 	pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &offset);
450d1b054daSYu Zhao 	pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &stride);
451d1b054daSYu Zhao 	if (!offset || (total > 1 && !stride))
452d1b054daSYu Zhao 		return -EIO;
453d1b054daSYu Zhao 
454d1b054daSYu Zhao 	pci_read_config_dword(dev, pos + PCI_SRIOV_SUP_PGSIZE, &pgsz);
455d1b054daSYu Zhao 	i = PAGE_SHIFT > 12 ? PAGE_SHIFT - 12 : 0;
456d1b054daSYu Zhao 	pgsz &= ~((1 << i) - 1);
457d1b054daSYu Zhao 	if (!pgsz)
458d1b054daSYu Zhao 		return -EIO;
459d1b054daSYu Zhao 
460d1b054daSYu Zhao 	pgsz &= ~(pgsz - 1);
461d1b054daSYu Zhao 	pci_write_config_dword(dev, pos + PCI_SRIOV_SYS_PGSIZE, pgsz);
462d1b054daSYu Zhao 
463d1b054daSYu Zhao 	nres = 0;
464d1b054daSYu Zhao 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
465d1b054daSYu Zhao 		res = dev->resource + PCI_IOV_RESOURCES + i;
466d1b054daSYu Zhao 		i += __pci_read_base(dev, pci_bar_unknown, res,
467d1b054daSYu Zhao 				     pos + PCI_SRIOV_BAR + i * 4);
468d1b054daSYu Zhao 		if (!res->flags)
469d1b054daSYu Zhao 			continue;
470d1b054daSYu Zhao 		if (resource_size(res) & (PAGE_SIZE - 1)) {
471d1b054daSYu Zhao 			rc = -EIO;
472d1b054daSYu Zhao 			goto failed;
473d1b054daSYu Zhao 		}
474d1b054daSYu Zhao 		res->end = res->start + resource_size(res) * total - 1;
475d1b054daSYu Zhao 		nres++;
476d1b054daSYu Zhao 	}
477d1b054daSYu Zhao 
478d1b054daSYu Zhao 	iov = kzalloc(sizeof(*iov), GFP_KERNEL);
479d1b054daSYu Zhao 	if (!iov) {
480d1b054daSYu Zhao 		rc = -ENOMEM;
481d1b054daSYu Zhao 		goto failed;
482d1b054daSYu Zhao 	}
483d1b054daSYu Zhao 
484d1b054daSYu Zhao 	iov->pos = pos;
485d1b054daSYu Zhao 	iov->nres = nres;
486d1b054daSYu Zhao 	iov->ctrl = ctrl;
487d1b054daSYu Zhao 	iov->total = total;
488d1b054daSYu Zhao 	iov->offset = offset;
489d1b054daSYu Zhao 	iov->stride = stride;
490d1b054daSYu Zhao 	iov->pgsz = pgsz;
491d1b054daSYu Zhao 	iov->self = dev;
492d1b054daSYu Zhao 	pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap);
493d1b054daSYu Zhao 	pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
4944d135dbeSYu Zhao 	if (dev->pcie_type == PCI_EXP_TYPE_RC_END)
4954d135dbeSYu Zhao 		iov->link = PCI_DEVFN(PCI_SLOT(dev->devfn), iov->link);
496d1b054daSYu Zhao 
497d1b054daSYu Zhao 	if (pdev)
498d1b054daSYu Zhao 		iov->dev = pci_dev_get(pdev);
499e277d2fcSYu Zhao 	else
500d1b054daSYu Zhao 		iov->dev = dev;
501e277d2fcSYu Zhao 
502d1b054daSYu Zhao 	mutex_init(&iov->lock);
503d1b054daSYu Zhao 
504d1b054daSYu Zhao 	dev->sriov = iov;
505d1b054daSYu Zhao 	dev->is_physfn = 1;
506d1b054daSYu Zhao 
507d1b054daSYu Zhao 	return 0;
508d1b054daSYu Zhao 
509d1b054daSYu Zhao failed:
510d1b054daSYu Zhao 	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
511d1b054daSYu Zhao 		res = dev->resource + PCI_IOV_RESOURCES + i;
512d1b054daSYu Zhao 		res->flags = 0;
513d1b054daSYu Zhao 	}
514d1b054daSYu Zhao 
515d1b054daSYu Zhao 	return rc;
516d1b054daSYu Zhao }
517d1b054daSYu Zhao 
518d1b054daSYu Zhao static void sriov_release(struct pci_dev *dev)
519d1b054daSYu Zhao {
520dd7cc44dSYu Zhao 	BUG_ON(dev->sriov->nr_virtfn);
521dd7cc44dSYu Zhao 
522e277d2fcSYu Zhao 	if (dev != dev->sriov->dev)
523d1b054daSYu Zhao 		pci_dev_put(dev->sriov->dev);
524d1b054daSYu Zhao 
525e277d2fcSYu Zhao 	mutex_destroy(&dev->sriov->lock);
526e277d2fcSYu Zhao 
527d1b054daSYu Zhao 	kfree(dev->sriov);
528d1b054daSYu Zhao 	dev->sriov = NULL;
529d1b054daSYu Zhao }
530d1b054daSYu Zhao 
5318c5cdb6aSYu Zhao static void sriov_restore_state(struct pci_dev *dev)
5328c5cdb6aSYu Zhao {
5338c5cdb6aSYu Zhao 	int i;
5348c5cdb6aSYu Zhao 	u16 ctrl;
5358c5cdb6aSYu Zhao 	struct pci_sriov *iov = dev->sriov;
5368c5cdb6aSYu Zhao 
5378c5cdb6aSYu Zhao 	pci_read_config_word(dev, iov->pos + PCI_SRIOV_CTRL, &ctrl);
5388c5cdb6aSYu Zhao 	if (ctrl & PCI_SRIOV_CTRL_VFE)
5398c5cdb6aSYu Zhao 		return;
5408c5cdb6aSYu Zhao 
5418c5cdb6aSYu Zhao 	for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++)
5428c5cdb6aSYu Zhao 		pci_update_resource(dev, i);
5438c5cdb6aSYu Zhao 
5448c5cdb6aSYu Zhao 	pci_write_config_dword(dev, iov->pos + PCI_SRIOV_SYS_PGSIZE, iov->pgsz);
545dd7cc44dSYu Zhao 	pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, iov->nr_virtfn);
5468c5cdb6aSYu Zhao 	pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
5478c5cdb6aSYu Zhao 	if (iov->ctrl & PCI_SRIOV_CTRL_VFE)
5488c5cdb6aSYu Zhao 		msleep(100);
5498c5cdb6aSYu Zhao }
5508c5cdb6aSYu Zhao 
551d1b054daSYu Zhao /**
552d1b054daSYu Zhao  * pci_iov_init - initialize the IOV capability
553d1b054daSYu Zhao  * @dev: the PCI device
554d1b054daSYu Zhao  *
555d1b054daSYu Zhao  * Returns 0 on success, or negative on failure.
556d1b054daSYu Zhao  */
557d1b054daSYu Zhao int pci_iov_init(struct pci_dev *dev)
558d1b054daSYu Zhao {
559d1b054daSYu Zhao 	int pos;
560d1b054daSYu Zhao 
5615f4d91a1SKenji Kaneshige 	if (!pci_is_pcie(dev))
562d1b054daSYu Zhao 		return -ENODEV;
563d1b054daSYu Zhao 
564d1b054daSYu Zhao 	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
565d1b054daSYu Zhao 	if (pos)
566d1b054daSYu Zhao 		return sriov_init(dev, pos);
567d1b054daSYu Zhao 
568d1b054daSYu Zhao 	return -ENODEV;
569d1b054daSYu Zhao }
570d1b054daSYu Zhao 
571d1b054daSYu Zhao /**
572d1b054daSYu Zhao  * pci_iov_release - release resources used by the IOV capability
573d1b054daSYu Zhao  * @dev: the PCI device
574d1b054daSYu Zhao  */
575d1b054daSYu Zhao void pci_iov_release(struct pci_dev *dev)
576d1b054daSYu Zhao {
577d1b054daSYu Zhao 	if (dev->is_physfn)
578d1b054daSYu Zhao 		sriov_release(dev);
579d1b054daSYu Zhao }
580d1b054daSYu Zhao 
581d1b054daSYu Zhao /**
582d1b054daSYu Zhao  * pci_iov_resource_bar - get position of the SR-IOV BAR
583d1b054daSYu Zhao  * @dev: the PCI device
584d1b054daSYu Zhao  * @resno: the resource number
585d1b054daSYu Zhao  * @type: the BAR type to be filled in
586d1b054daSYu Zhao  *
587d1b054daSYu Zhao  * Returns position of the BAR encapsulated in the SR-IOV capability.
588d1b054daSYu Zhao  */
589d1b054daSYu Zhao int pci_iov_resource_bar(struct pci_dev *dev, int resno,
590d1b054daSYu Zhao 			 enum pci_bar_type *type)
591d1b054daSYu Zhao {
592d1b054daSYu Zhao 	if (resno < PCI_IOV_RESOURCES || resno > PCI_IOV_RESOURCE_END)
593d1b054daSYu Zhao 		return 0;
594d1b054daSYu Zhao 
595d1b054daSYu Zhao 	BUG_ON(!dev->is_physfn);
596d1b054daSYu Zhao 
597d1b054daSYu Zhao 	*type = pci_bar_unknown;
598d1b054daSYu Zhao 
599d1b054daSYu Zhao 	return dev->sriov->pos + PCI_SRIOV_BAR +
600d1b054daSYu Zhao 		4 * (resno - PCI_IOV_RESOURCES);
601d1b054daSYu Zhao }
6028c5cdb6aSYu Zhao 
6038c5cdb6aSYu Zhao /**
6046faf17f6SChris Wright  * pci_sriov_resource_alignment - get resource alignment for VF BAR
6056faf17f6SChris Wright  * @dev: the PCI device
6066faf17f6SChris Wright  * @resno: the resource number
6076faf17f6SChris Wright  *
6086faf17f6SChris Wright  * Returns the alignment of the VF BAR found in the SR-IOV capability.
6096faf17f6SChris Wright  * This is not the same as the resource size which is defined as
6106faf17f6SChris Wright  * the VF BAR size multiplied by the number of VFs.  The alignment
6116faf17f6SChris Wright  * is just the VF BAR size.
6126faf17f6SChris Wright  */
6130e52247aSCam Macdonell resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno)
6146faf17f6SChris Wright {
6156faf17f6SChris Wright 	struct resource tmp;
6166faf17f6SChris Wright 	enum pci_bar_type type;
6176faf17f6SChris Wright 	int reg = pci_iov_resource_bar(dev, resno, &type);
6186faf17f6SChris Wright 
6196faf17f6SChris Wright 	if (!reg)
6206faf17f6SChris Wright 		return 0;
6216faf17f6SChris Wright 
6226faf17f6SChris Wright 	 __pci_read_base(dev, type, &tmp, reg);
6236faf17f6SChris Wright 	return resource_alignment(&tmp);
6246faf17f6SChris Wright }
6256faf17f6SChris Wright 
6266faf17f6SChris Wright /**
6278c5cdb6aSYu Zhao  * pci_restore_iov_state - restore the state of the IOV capability
6288c5cdb6aSYu Zhao  * @dev: the PCI device
6298c5cdb6aSYu Zhao  */
6308c5cdb6aSYu Zhao void pci_restore_iov_state(struct pci_dev *dev)
6318c5cdb6aSYu Zhao {
6328c5cdb6aSYu Zhao 	if (dev->is_physfn)
6338c5cdb6aSYu Zhao 		sriov_restore_state(dev);
6348c5cdb6aSYu Zhao }
635a28724b0SYu Zhao 
636a28724b0SYu Zhao /**
637a28724b0SYu Zhao  * pci_iov_bus_range - find bus range used by Virtual Function
638a28724b0SYu Zhao  * @bus: the PCI bus
639a28724b0SYu Zhao  *
640a28724b0SYu Zhao  * Returns max number of buses (exclude current one) used by Virtual
641a28724b0SYu Zhao  * Functions.
642a28724b0SYu Zhao  */
643a28724b0SYu Zhao int pci_iov_bus_range(struct pci_bus *bus)
644a28724b0SYu Zhao {
645a28724b0SYu Zhao 	int max = 0;
646a28724b0SYu Zhao 	u8 busnr;
647a28724b0SYu Zhao 	struct pci_dev *dev;
648a28724b0SYu Zhao 
649a28724b0SYu Zhao 	list_for_each_entry(dev, &bus->devices, bus_list) {
650a28724b0SYu Zhao 		if (!dev->is_physfn)
651a28724b0SYu Zhao 			continue;
652a28724b0SYu Zhao 		busnr = virtfn_bus(dev, dev->sriov->total - 1);
653a28724b0SYu Zhao 		if (busnr > max)
654a28724b0SYu Zhao 			max = busnr;
655a28724b0SYu Zhao 	}
656a28724b0SYu Zhao 
657a28724b0SYu Zhao 	return max ? max - bus->number : 0;
658a28724b0SYu Zhao }
659dd7cc44dSYu Zhao 
660dd7cc44dSYu Zhao /**
661dd7cc44dSYu Zhao  * pci_enable_sriov - enable the SR-IOV capability
662dd7cc44dSYu Zhao  * @dev: the PCI device
66352a8873bSRandy Dunlap  * @nr_virtfn: number of virtual functions to enable
664dd7cc44dSYu Zhao  *
665dd7cc44dSYu Zhao  * Returns 0 on success, or negative on failure.
666dd7cc44dSYu Zhao  */
667dd7cc44dSYu Zhao int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
668dd7cc44dSYu Zhao {
669dd7cc44dSYu Zhao 	might_sleep();
670dd7cc44dSYu Zhao 
671dd7cc44dSYu Zhao 	if (!dev->is_physfn)
672dd7cc44dSYu Zhao 		return -ENODEV;
673dd7cc44dSYu Zhao 
674dd7cc44dSYu Zhao 	return sriov_enable(dev, nr_virtfn);
675dd7cc44dSYu Zhao }
676dd7cc44dSYu Zhao EXPORT_SYMBOL_GPL(pci_enable_sriov);
677dd7cc44dSYu Zhao 
678dd7cc44dSYu Zhao /**
679dd7cc44dSYu Zhao  * pci_disable_sriov - disable the SR-IOV capability
680dd7cc44dSYu Zhao  * @dev: the PCI device
681dd7cc44dSYu Zhao  */
682dd7cc44dSYu Zhao void pci_disable_sriov(struct pci_dev *dev)
683dd7cc44dSYu Zhao {
684dd7cc44dSYu Zhao 	might_sleep();
685dd7cc44dSYu Zhao 
686dd7cc44dSYu Zhao 	if (!dev->is_physfn)
687dd7cc44dSYu Zhao 		return;
688dd7cc44dSYu Zhao 
689dd7cc44dSYu Zhao 	sriov_disable(dev);
690dd7cc44dSYu Zhao }
691dd7cc44dSYu Zhao EXPORT_SYMBOL_GPL(pci_disable_sriov);
69274bb1bccSYu Zhao 
69374bb1bccSYu Zhao /**
69474bb1bccSYu Zhao  * pci_sriov_migration - notify SR-IOV core of Virtual Function Migration
69574bb1bccSYu Zhao  * @dev: the PCI device
69674bb1bccSYu Zhao  *
69774bb1bccSYu Zhao  * Returns IRQ_HANDLED if the IRQ is handled, or IRQ_NONE if not.
69874bb1bccSYu Zhao  *
69974bb1bccSYu Zhao  * Physical Function driver is responsible to register IRQ handler using
70074bb1bccSYu Zhao  * VF Migration Interrupt Message Number, and call this function when the
70174bb1bccSYu Zhao  * interrupt is generated by the hardware.
70274bb1bccSYu Zhao  */
70374bb1bccSYu Zhao irqreturn_t pci_sriov_migration(struct pci_dev *dev)
70474bb1bccSYu Zhao {
70574bb1bccSYu Zhao 	if (!dev->is_physfn)
70674bb1bccSYu Zhao 		return IRQ_NONE;
70774bb1bccSYu Zhao 
70874bb1bccSYu Zhao 	return sriov_migration(dev) ? IRQ_HANDLED : IRQ_NONE;
70974bb1bccSYu Zhao }
71074bb1bccSYu Zhao EXPORT_SYMBOL_GPL(pci_sriov_migration);
711302b4215SYu Zhao 
712fb8a0d9dSWilliams, Mitch A /**
713fb8a0d9dSWilliams, Mitch A  * pci_num_vf - return number of VFs associated with a PF device_release_driver
714fb8a0d9dSWilliams, Mitch A  * @dev: the PCI device
715fb8a0d9dSWilliams, Mitch A  *
716fb8a0d9dSWilliams, Mitch A  * Returns number of VFs, or 0 if SR-IOV is not enabled.
717fb8a0d9dSWilliams, Mitch A  */
718fb8a0d9dSWilliams, Mitch A int pci_num_vf(struct pci_dev *dev)
719fb8a0d9dSWilliams, Mitch A {
720fb8a0d9dSWilliams, Mitch A 	if (!dev || !dev->is_physfn)
721fb8a0d9dSWilliams, Mitch A 		return 0;
722fb8a0d9dSWilliams, Mitch A 	else
723fb8a0d9dSWilliams, Mitch A 		return dev->sriov->nr_virtfn;
724fb8a0d9dSWilliams, Mitch A }
725fb8a0d9dSWilliams, Mitch A EXPORT_SYMBOL_GPL(pci_num_vf);
726