1 /* 2 * Standard PCI Hot Plug Driver 3 * 4 * Copyright (C) 1995,2001 Compaq Computer Corporation 5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 6 * Copyright (C) 2001 IBM Corp. 7 * Copyright (C) 2003-2004 Intel Corporation 8 * 9 * All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 19 * NON INFRINGEMENT. See the GNU General Public License for more 20 * details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 27 * 28 */ 29 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/types.h> 33 #include <linux/pci.h> 34 #include <linux/interrupt.h> 35 36 #include "shpchp.h" 37 38 #ifdef DEBUG 39 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */ 40 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */ 41 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */ 42 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */ 43 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT) 44 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE) 45 /* Redefine this flagword to set debug level */ 46 #define DEBUG_LEVEL DBG_K_STANDARD 47 48 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256]; 49 50 #define DBG_PRINT( dbg_flags, args... ) \ 51 do { \ 52 if ( DEBUG_LEVEL & ( dbg_flags ) ) \ 53 { \ 54 int len; \ 55 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \ 56 __FILE__, __LINE__, __FUNCTION__ ); \ 57 sprintf( __dbg_str_buf + len, args ); \ 58 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \ 59 } \ 60 } while (0) 61 62 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]"); 63 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]"); 64 #else 65 #define DEFINE_DBG_BUFFER 66 #define DBG_ENTER_ROUTINE 67 #define DBG_LEAVE_ROUTINE 68 #endif /* DEBUG */ 69 70 /* Slot Available Register I field definition */ 71 #define SLOT_33MHZ 0x0000001f 72 #define SLOT_66MHZ_PCIX 0x00001f00 73 #define SLOT_100MHZ_PCIX 0x001f0000 74 #define SLOT_133MHZ_PCIX 0x1f000000 75 76 /* Slot Available Register II field definition */ 77 #define SLOT_66MHZ 0x0000001f 78 #define SLOT_66MHZ_PCIX_266 0x00000f00 79 #define SLOT_100MHZ_PCIX_266 0x0000f000 80 #define SLOT_133MHZ_PCIX_266 0x000f0000 81 #define SLOT_66MHZ_PCIX_533 0x00f00000 82 #define SLOT_100MHZ_PCIX_533 0x0f000000 83 #define SLOT_133MHZ_PCIX_533 0xf0000000 84 85 /* Slot Configuration */ 86 #define SLOT_NUM 0x0000001F 87 #define FIRST_DEV_NUM 0x00001F00 88 #define PSN 0x07FF0000 89 #define UPDOWN 0x20000000 90 #define MRLSENSOR 0x40000000 91 #define ATTN_BUTTON 0x80000000 92 93 /* Slot Status Field Definitions */ 94 /* Slot State */ 95 #define PWR_ONLY 0x0001 96 #define ENABLED 0x0002 97 #define DISABLED 0x0003 98 99 /* Power Indicator State */ 100 #define PWR_LED_ON 0x0004 101 #define PWR_LED_BLINK 0x0008 102 #define PWR_LED_OFF 0x000c 103 104 /* Attention Indicator State */ 105 #define ATTEN_LED_ON 0x0010 106 #define ATTEN_LED_BLINK 0x0020 107 #define ATTEN_LED_OFF 0x0030 108 109 /* Power Fault */ 110 #define pwr_fault 0x0040 111 112 /* Attention Button */ 113 #define ATTEN_BUTTON 0x0080 114 115 /* MRL Sensor */ 116 #define MRL_SENSOR 0x0100 117 118 /* 66 MHz Capable */ 119 #define IS_66MHZ_CAP 0x0200 120 121 /* PRSNT1#/PRSNT2# */ 122 #define SLOT_EMP 0x0c00 123 124 /* PCI-X Capability */ 125 #define NON_PCIX 0x0000 126 #define PCIX_66 0x1000 127 #define PCIX_133 0x3000 128 #define PCIX_266 0x4000 /* For PI = 2 only */ 129 #define PCIX_533 0x5000 /* For PI = 2 only */ 130 131 /* SHPC 'write' operations/commands */ 132 133 /* Slot operation - 0x00h to 0x3Fh */ 134 135 #define NO_CHANGE 0x00 136 137 /* Slot state - Bits 0 & 1 of controller command register */ 138 #define SET_SLOT_PWR 0x01 139 #define SET_SLOT_ENABLE 0x02 140 #define SET_SLOT_DISABLE 0x03 141 142 /* Power indicator state - Bits 2 & 3 of controller command register*/ 143 #define SET_PWR_ON 0x04 144 #define SET_PWR_BLINK 0x08 145 #define SET_PWR_OFF 0x0C 146 147 /* Attention indicator state - Bits 4 & 5 of controller command register*/ 148 #define SET_ATTN_ON 0x010 149 #define SET_ATTN_BLINK 0x020 150 #define SET_ATTN_OFF 0x030 151 152 /* Set bus speed/mode A - 0x40h to 0x47h */ 153 #define SETA_PCI_33MHZ 0x40 154 #define SETA_PCI_66MHZ 0x41 155 #define SETA_PCIX_66MHZ 0x42 156 #define SETA_PCIX_100MHZ 0x43 157 #define SETA_PCIX_133MHZ 0x44 158 #define RESERV_1 0x45 159 #define RESERV_2 0x46 160 #define RESERV_3 0x47 161 162 /* Set bus speed/mode B - 0x50h to 0x5fh */ 163 #define SETB_PCI_33MHZ 0x50 164 #define SETB_PCI_66MHZ 0x51 165 #define SETB_PCIX_66MHZ_PM 0x52 166 #define SETB_PCIX_100MHZ_PM 0x53 167 #define SETB_PCIX_133MHZ_PM 0x54 168 #define SETB_PCIX_66MHZ_EM 0x55 169 #define SETB_PCIX_100MHZ_EM 0x56 170 #define SETB_PCIX_133MHZ_EM 0x57 171 #define SETB_PCIX_66MHZ_266 0x58 172 #define SETB_PCIX_100MHZ_266 0x59 173 #define SETB_PCIX_133MHZ_266 0x5a 174 #define SETB_PCIX_66MHZ_533 0x5b 175 #define SETB_PCIX_100MHZ_533 0x5c 176 #define SETB_PCIX_133MHZ_533 0x5d 177 178 179 /* Power-on all slots - 0x48h */ 180 #define SET_PWR_ON_ALL 0x48 181 182 /* Enable all slots - 0x49h */ 183 #define SET_ENABLE_ALL 0x49 184 185 /* SHPC controller command error code */ 186 #define SWITCH_OPEN 0x1 187 #define INVALID_CMD 0x2 188 #define INVALID_SPEED_MODE 0x4 189 190 /* For accessing SHPC Working Register Set */ 191 #define DWORD_SELECT 0x2 192 #define DWORD_DATA 0x4 193 #define BASE_OFFSET 0x0 194 195 /* Field Offset in Logical Slot Register - byte boundary */ 196 #define SLOT_EVENT_LATCH 0x2 197 #define SLOT_SERR_INT_MASK 0x3 198 199 static spinlock_t hpc_event_lock; 200 201 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */ 202 static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */ 203 static int ctlr_seq_num = 0; /* Controller sequenc # */ 204 static spinlock_t list_lock; 205 206 static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs); 207 208 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds); 209 static int hpc_check_cmd_status(struct controller *ctrl); 210 211 /* This is the interrupt polling timeout function. */ 212 static void int_poll_timeout(unsigned long lphp_ctlr) 213 { 214 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr; 215 216 DBG_ENTER_ROUTINE 217 218 if ( !php_ctlr ) { 219 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 220 return; 221 } 222 223 /* Poll for interrupt events. regs == NULL => polling */ 224 shpc_isr( 0, (void *)php_ctlr, NULL ); 225 226 init_timer(&php_ctlr->int_poll_timer); 227 if (!shpchp_poll_time) 228 shpchp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/ 229 230 start_int_poll_timer(php_ctlr, shpchp_poll_time); 231 232 return; 233 } 234 235 /* This function starts the interrupt polling timer. */ 236 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds) 237 { 238 if (!php_ctlr) { 239 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 240 return; 241 } 242 243 if ( ( seconds <= 0 ) || ( seconds > 60 ) ) 244 seconds = 2; /* Clamp to sane value */ 245 246 php_ctlr->int_poll_timer.function = &int_poll_timeout; 247 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */ 248 php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ; 249 add_timer(&php_ctlr->int_poll_timer); 250 251 return; 252 } 253 254 static inline int shpc_wait_cmd(struct controller *ctrl) 255 { 256 int retval = 0; 257 unsigned int timeout_msec = shpchp_poll_mode ? 2000 : 1000; 258 unsigned long timeout = msecs_to_jiffies(timeout_msec); 259 int rc = wait_event_interruptible_timeout(ctrl->queue, 260 !ctrl->cmd_busy, timeout); 261 if (!rc) { 262 retval = -EIO; 263 err("Command not completed in %d msec\n", timeout_msec); 264 } else if (rc < 0) { 265 retval = -EINTR; 266 info("Command was interrupted by a signal\n"); 267 } 268 ctrl->cmd_busy = 0; 269 270 return retval; 271 } 272 273 static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) 274 { 275 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 276 u16 cmd_status; 277 int retval = 0; 278 u16 temp_word; 279 int i; 280 281 DBG_ENTER_ROUTINE 282 283 mutex_lock(&slot->ctrl->cmd_lock); 284 285 if (!php_ctlr) { 286 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 287 retval = -EINVAL; 288 goto out; 289 } 290 291 for (i = 0; i < 10; i++) { 292 cmd_status = readw(php_ctlr->creg + CMD_STATUS); 293 294 if (!(cmd_status & 0x1)) 295 break; 296 /* Check every 0.1 sec for a total of 1 sec*/ 297 msleep(100); 298 } 299 300 cmd_status = readw(php_ctlr->creg + CMD_STATUS); 301 302 if (cmd_status & 0x1) { 303 /* After 1 sec and and the controller is still busy */ 304 err("%s : Controller is still busy after 1 sec.\n", __FUNCTION__); 305 retval = -EBUSY; 306 goto out; 307 } 308 309 ++t_slot; 310 temp_word = (t_slot << 8) | (cmd & 0xFF); 311 dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd); 312 313 /* To make sure the Controller Busy bit is 0 before we send out the 314 * command. 315 */ 316 slot->ctrl->cmd_busy = 1; 317 writew(temp_word, php_ctlr->creg + CMD); 318 319 /* 320 * Wait for command completion. 321 */ 322 retval = shpc_wait_cmd(slot->ctrl); 323 if (retval) 324 goto out; 325 326 cmd_status = hpc_check_cmd_status(slot->ctrl); 327 if (cmd_status) { 328 err("%s: Failed to issued command 0x%x (error code = %d)\n", 329 __FUNCTION__, cmd, cmd_status); 330 retval = -EIO; 331 } 332 out: 333 mutex_unlock(&slot->ctrl->cmd_lock); 334 335 DBG_LEAVE_ROUTINE 336 return retval; 337 } 338 339 static int hpc_check_cmd_status(struct controller *ctrl) 340 { 341 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; 342 u16 cmd_status; 343 int retval = 0; 344 345 DBG_ENTER_ROUTINE 346 347 if (!ctrl->hpc_ctlr_handle) { 348 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 349 return -1; 350 } 351 352 cmd_status = readw(php_ctlr->creg + CMD_STATUS) & 0x000F; 353 354 switch (cmd_status >> 1) { 355 case 0: 356 retval = 0; 357 break; 358 case 1: 359 retval = SWITCH_OPEN; 360 err("%s: Switch opened!\n", __FUNCTION__); 361 break; 362 case 2: 363 retval = INVALID_CMD; 364 err("%s: Invalid HPC command!\n", __FUNCTION__); 365 break; 366 case 4: 367 retval = INVALID_SPEED_MODE; 368 err("%s: Invalid bus speed/mode!\n", __FUNCTION__); 369 break; 370 default: 371 retval = cmd_status; 372 } 373 374 DBG_LEAVE_ROUTINE 375 return retval; 376 } 377 378 379 static int hpc_get_attention_status(struct slot *slot, u8 *status) 380 { 381 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 382 u32 slot_reg; 383 u16 slot_status; 384 u8 atten_led_state; 385 386 DBG_ENTER_ROUTINE 387 388 if (!slot->ctrl->hpc_ctlr_handle) { 389 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 390 return -1; 391 } 392 393 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot)); 394 slot_status = (u16) slot_reg; 395 atten_led_state = (slot_status & 0x0030) >> 4; 396 397 switch (atten_led_state) { 398 case 0: 399 *status = 0xFF; /* Reserved */ 400 break; 401 case 1: 402 *status = 1; /* On */ 403 break; 404 case 2: 405 *status = 2; /* Blink */ 406 break; 407 case 3: 408 *status = 0; /* Off */ 409 break; 410 default: 411 *status = 0xFF; 412 break; 413 } 414 415 DBG_LEAVE_ROUTINE 416 return 0; 417 } 418 419 static int hpc_get_power_status(struct slot * slot, u8 *status) 420 { 421 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 422 u32 slot_reg; 423 u16 slot_status; 424 u8 slot_state; 425 int retval = 0; 426 427 DBG_ENTER_ROUTINE 428 429 if (!slot->ctrl->hpc_ctlr_handle) { 430 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 431 return -1; 432 } 433 434 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot)); 435 slot_status = (u16) slot_reg; 436 slot_state = (slot_status & 0x0003); 437 438 switch (slot_state) { 439 case 0: 440 *status = 0xFF; 441 break; 442 case 1: 443 *status = 2; /* Powered only */ 444 break; 445 case 2: 446 *status = 1; /* Enabled */ 447 break; 448 case 3: 449 *status = 0; /* Disabled */ 450 break; 451 default: 452 *status = 0xFF; 453 break; 454 } 455 456 DBG_LEAVE_ROUTINE 457 return retval; 458 } 459 460 461 static int hpc_get_latch_status(struct slot *slot, u8 *status) 462 { 463 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 464 u32 slot_reg; 465 u16 slot_status; 466 467 DBG_ENTER_ROUTINE 468 469 if (!slot->ctrl->hpc_ctlr_handle) { 470 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 471 return -1; 472 } 473 474 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot)); 475 slot_status = (u16)slot_reg; 476 477 *status = ((slot_status & 0x0100) == 0) ? 0 : 1; /* 0 -> close; 1 -> open */ 478 479 480 DBG_LEAVE_ROUTINE 481 return 0; 482 } 483 484 static int hpc_get_adapter_status(struct slot *slot, u8 *status) 485 { 486 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 487 u32 slot_reg; 488 u16 slot_status; 489 u8 card_state; 490 491 DBG_ENTER_ROUTINE 492 493 if (!slot->ctrl->hpc_ctlr_handle) { 494 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 495 return -1; 496 } 497 498 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot)); 499 slot_status = (u16)slot_reg; 500 card_state = (u8)((slot_status & 0x0C00) >> 10); 501 *status = (card_state != 0x3) ? 1 : 0; 502 503 DBG_LEAVE_ROUTINE 504 return 0; 505 } 506 507 static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) 508 { 509 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 510 511 DBG_ENTER_ROUTINE 512 513 if (!slot->ctrl->hpc_ctlr_handle) { 514 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 515 return -1; 516 } 517 518 *prog_int = readb(php_ctlr->creg + PROG_INTERFACE); 519 520 DBG_LEAVE_ROUTINE 521 return 0; 522 } 523 524 static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) 525 { 526 int retval = 0; 527 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 528 u32 slot_reg = readl(php_ctlr->creg + SLOT1 + 4 * slot->hp_slot); 529 u8 pcix_cap = (slot_reg >> 12) & 7; 530 u8 m66_cap = (slot_reg >> 9) & 1; 531 532 DBG_ENTER_ROUTINE 533 534 dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n", 535 __FUNCTION__, slot_reg, pcix_cap, m66_cap); 536 537 switch (pcix_cap) { 538 case 0x0: 539 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz; 540 break; 541 case 0x1: 542 *value = PCI_SPEED_66MHz_PCIX; 543 break; 544 case 0x3: 545 *value = PCI_SPEED_133MHz_PCIX; 546 break; 547 case 0x4: 548 *value = PCI_SPEED_133MHz_PCIX_266; 549 break; 550 case 0x5: 551 *value = PCI_SPEED_133MHz_PCIX_533; 552 break; 553 case 0x2: 554 default: 555 *value = PCI_SPEED_UNKNOWN; 556 retval = -ENODEV; 557 break; 558 } 559 560 dbg("Adapter speed = %d\n", *value); 561 DBG_LEAVE_ROUTINE 562 return retval; 563 } 564 565 static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) 566 { 567 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 568 u16 sec_bus_status; 569 u8 pi; 570 int retval = 0; 571 572 DBG_ENTER_ROUTINE 573 574 if (!slot->ctrl->hpc_ctlr_handle) { 575 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 576 return -1; 577 } 578 579 pi = readb(php_ctlr->creg + PROG_INTERFACE); 580 sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG); 581 582 if (pi == 2) { 583 *mode = (sec_bus_status & 0x0100) >> 8; 584 } else { 585 retval = -1; 586 } 587 588 dbg("Mode 1 ECC cap = %d\n", *mode); 589 590 DBG_LEAVE_ROUTINE 591 return retval; 592 } 593 594 static int hpc_query_power_fault(struct slot * slot) 595 { 596 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 597 u32 slot_reg; 598 u16 slot_status; 599 u8 pwr_fault_state, status; 600 601 DBG_ENTER_ROUTINE 602 603 if (!slot->ctrl->hpc_ctlr_handle) { 604 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 605 return -1; 606 } 607 608 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot)); 609 slot_status = (u16) slot_reg; 610 pwr_fault_state = (slot_status & 0x0040) >> 7; 611 status = (pwr_fault_state == 1) ? 0 : 1; 612 613 DBG_LEAVE_ROUTINE 614 /* Note: Logic 0 => fault */ 615 return status; 616 } 617 618 static int hpc_set_attention_status(struct slot *slot, u8 value) 619 { 620 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 621 u8 slot_cmd = 0; 622 int rc = 0; 623 624 if (!slot->ctrl->hpc_ctlr_handle) { 625 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 626 return -1; 627 } 628 629 if (slot->hp_slot >= php_ctlr->num_slots) { 630 err("%s: Invalid HPC slot number!\n", __FUNCTION__); 631 return -1; 632 } 633 634 switch (value) { 635 case 0 : 636 slot_cmd = 0x30; /* OFF */ 637 break; 638 case 1: 639 slot_cmd = 0x10; /* ON */ 640 break; 641 case 2: 642 slot_cmd = 0x20; /* BLINK */ 643 break; 644 default: 645 return -1; 646 } 647 648 shpc_write_cmd(slot, slot->hp_slot, slot_cmd); 649 650 return rc; 651 } 652 653 654 static void hpc_set_green_led_on(struct slot *slot) 655 { 656 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 657 u8 slot_cmd; 658 659 if (!slot->ctrl->hpc_ctlr_handle) { 660 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 661 return ; 662 } 663 664 if (slot->hp_slot >= php_ctlr->num_slots) { 665 err("%s: Invalid HPC slot number!\n", __FUNCTION__); 666 return ; 667 } 668 669 slot_cmd = 0x04; 670 671 shpc_write_cmd(slot, slot->hp_slot, slot_cmd); 672 673 return; 674 } 675 676 static void hpc_set_green_led_off(struct slot *slot) 677 { 678 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 679 u8 slot_cmd; 680 681 if (!slot->ctrl->hpc_ctlr_handle) { 682 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 683 return ; 684 } 685 686 if (slot->hp_slot >= php_ctlr->num_slots) { 687 err("%s: Invalid HPC slot number!\n", __FUNCTION__); 688 return ; 689 } 690 691 slot_cmd = 0x0C; 692 693 shpc_write_cmd(slot, slot->hp_slot, slot_cmd); 694 695 return; 696 } 697 698 static void hpc_set_green_led_blink(struct slot *slot) 699 { 700 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 701 u8 slot_cmd; 702 703 if (!slot->ctrl->hpc_ctlr_handle) { 704 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 705 return ; 706 } 707 708 if (slot->hp_slot >= php_ctlr->num_slots) { 709 err("%s: Invalid HPC slot number!\n", __FUNCTION__); 710 return ; 711 } 712 713 slot_cmd = 0x08; 714 715 shpc_write_cmd(slot, slot->hp_slot, slot_cmd); 716 717 return; 718 } 719 720 int shpc_get_ctlr_slot_config(struct controller *ctrl, 721 int *num_ctlr_slots, /* number of slots in this HPC */ 722 int *first_device_num, /* PCI dev num of the first slot in this SHPC */ 723 int *physical_slot_num, /* phy slot num of the first slot in this SHPC */ 724 int *updown, /* physical_slot_num increament: 1 or -1 */ 725 int *flags) 726 { 727 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; 728 729 DBG_ENTER_ROUTINE 730 731 if (!ctrl->hpc_ctlr_handle) { 732 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 733 return -1; 734 } 735 736 *first_device_num = php_ctlr->slot_device_offset; /* Obtained in shpc_init() */ 737 *num_ctlr_slots = php_ctlr->num_slots; /* Obtained in shpc_init() */ 738 739 *physical_slot_num = (readl(php_ctlr->creg + SLOT_CONFIG) & PSN) >> 16; 740 dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num); 741 *updown = ((readl(php_ctlr->creg + SLOT_CONFIG) & UPDOWN ) >> 29) ? 1 : -1; 742 743 DBG_LEAVE_ROUTINE 744 return 0; 745 } 746 747 static void hpc_release_ctlr(struct controller *ctrl) 748 { 749 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; 750 struct php_ctlr_state_s *p, *p_prev; 751 int i; 752 753 DBG_ENTER_ROUTINE 754 755 if (!ctrl->hpc_ctlr_handle) { 756 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 757 return ; 758 } 759 760 /* 761 * Mask all slot event interrupts 762 */ 763 for (i = 0; i < ctrl->num_slots; i++) 764 writel(0xffff3fff, php_ctlr->creg + SLOT1 + (4 * i)); 765 766 cleanup_slots(ctrl); 767 768 if (shpchp_poll_mode) { 769 del_timer(&php_ctlr->int_poll_timer); 770 } else { 771 if (php_ctlr->irq) { 772 free_irq(php_ctlr->irq, ctrl); 773 php_ctlr->irq = 0; 774 pci_disable_msi(php_ctlr->pci_dev); 775 } 776 } 777 778 if (php_ctlr->pci_dev) { 779 iounmap(php_ctlr->creg); 780 release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 781 php_ctlr->pci_dev = NULL; 782 } 783 784 spin_lock(&list_lock); 785 p = php_ctlr_list_head; 786 p_prev = NULL; 787 while (p) { 788 if (p == php_ctlr) { 789 if (p_prev) 790 p_prev->pnext = p->pnext; 791 else 792 php_ctlr_list_head = p->pnext; 793 break; 794 } else { 795 p_prev = p; 796 p = p->pnext; 797 } 798 } 799 spin_unlock(&list_lock); 800 801 kfree(php_ctlr); 802 803 DBG_LEAVE_ROUTINE 804 805 } 806 807 static int hpc_power_on_slot(struct slot * slot) 808 { 809 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 810 u8 slot_cmd; 811 int retval = 0; 812 813 DBG_ENTER_ROUTINE 814 815 if (!slot->ctrl->hpc_ctlr_handle) { 816 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 817 return -1; 818 } 819 820 if (slot->hp_slot >= php_ctlr->num_slots) { 821 err("%s: Invalid HPC slot number!\n", __FUNCTION__); 822 return -1; 823 } 824 slot_cmd = 0x01; 825 826 retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd); 827 828 if (retval) { 829 err("%s: Write command failed!\n", __FUNCTION__); 830 return -1; 831 } 832 833 DBG_LEAVE_ROUTINE 834 835 return retval; 836 } 837 838 static int hpc_slot_enable(struct slot * slot) 839 { 840 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 841 u8 slot_cmd; 842 int retval = 0; 843 844 DBG_ENTER_ROUTINE 845 846 if (!slot->ctrl->hpc_ctlr_handle) { 847 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 848 return -1; 849 } 850 851 if (slot->hp_slot >= php_ctlr->num_slots) { 852 err("%s: Invalid HPC slot number!\n", __FUNCTION__); 853 return -1; 854 } 855 /* 3A => Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ 856 slot_cmd = 0x3A; 857 858 retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd); 859 860 if (retval) { 861 err("%s: Write command failed!\n", __FUNCTION__); 862 return -1; 863 } 864 865 DBG_LEAVE_ROUTINE 866 return retval; 867 } 868 869 static int hpc_slot_disable(struct slot * slot) 870 { 871 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 872 u8 slot_cmd; 873 int retval = 0; 874 875 DBG_ENTER_ROUTINE 876 877 if (!slot->ctrl->hpc_ctlr_handle) { 878 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 879 return -1; 880 } 881 882 if (slot->hp_slot >= php_ctlr->num_slots) { 883 err("%s: Invalid HPC slot number!\n", __FUNCTION__); 884 return -1; 885 } 886 887 /* 1F => Slot - Disable, Power Indicator - Off, Attention Indicator - On */ 888 slot_cmd = 0x1F; 889 890 retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd); 891 892 if (retval) { 893 err("%s: Write command failed!\n", __FUNCTION__); 894 return -1; 895 } 896 897 DBG_LEAVE_ROUTINE 898 return retval; 899 } 900 901 static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) 902 { 903 int retval; 904 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 905 u8 pi, cmd; 906 907 DBG_ENTER_ROUTINE 908 909 pi = readb(php_ctlr->creg + PROG_INTERFACE); 910 if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX)) 911 return -EINVAL; 912 913 switch (value) { 914 case PCI_SPEED_33MHz: 915 cmd = SETA_PCI_33MHZ; 916 break; 917 case PCI_SPEED_66MHz: 918 cmd = SETA_PCI_66MHZ; 919 break; 920 case PCI_SPEED_66MHz_PCIX: 921 cmd = SETA_PCIX_66MHZ; 922 break; 923 case PCI_SPEED_100MHz_PCIX: 924 cmd = SETA_PCIX_100MHZ; 925 break; 926 case PCI_SPEED_133MHz_PCIX: 927 cmd = SETA_PCIX_133MHZ; 928 break; 929 case PCI_SPEED_66MHz_PCIX_ECC: 930 cmd = SETB_PCIX_66MHZ_EM; 931 break; 932 case PCI_SPEED_100MHz_PCIX_ECC: 933 cmd = SETB_PCIX_100MHZ_EM; 934 break; 935 case PCI_SPEED_133MHz_PCIX_ECC: 936 cmd = SETB_PCIX_133MHZ_EM; 937 break; 938 case PCI_SPEED_66MHz_PCIX_266: 939 cmd = SETB_PCIX_66MHZ_266; 940 break; 941 case PCI_SPEED_100MHz_PCIX_266: 942 cmd = SETB_PCIX_100MHZ_266; 943 break; 944 case PCI_SPEED_133MHz_PCIX_266: 945 cmd = SETB_PCIX_133MHZ_266; 946 break; 947 case PCI_SPEED_66MHz_PCIX_533: 948 cmd = SETB_PCIX_66MHZ_533; 949 break; 950 case PCI_SPEED_100MHz_PCIX_533: 951 cmd = SETB_PCIX_100MHZ_533; 952 break; 953 case PCI_SPEED_133MHz_PCIX_533: 954 cmd = SETB_PCIX_133MHZ_533; 955 break; 956 default: 957 return -EINVAL; 958 } 959 960 retval = shpc_write_cmd(slot, 0, cmd); 961 if (retval) 962 err("%s: Write command failed!\n", __FUNCTION__); 963 964 DBG_LEAVE_ROUTINE 965 return retval; 966 } 967 968 static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs) 969 { 970 struct controller *ctrl = NULL; 971 struct php_ctlr_state_s *php_ctlr; 972 u8 schedule_flag = 0; 973 u8 temp_byte; 974 u32 temp_dword, intr_loc, intr_loc2; 975 int hp_slot; 976 977 if (!dev_id) 978 return IRQ_NONE; 979 980 if (!shpchp_poll_mode) { 981 ctrl = (struct controller *)dev_id; 982 php_ctlr = ctrl->hpc_ctlr_handle; 983 } else { 984 php_ctlr = (struct php_ctlr_state_s *) dev_id; 985 ctrl = (struct controller *)php_ctlr->callback_instance_id; 986 } 987 988 if (!ctrl) 989 return IRQ_NONE; 990 991 if (!php_ctlr || !php_ctlr->creg) 992 return IRQ_NONE; 993 994 /* Check to see if it was our interrupt */ 995 intr_loc = readl(php_ctlr->creg + INTR_LOC); 996 997 if (!intr_loc) 998 return IRQ_NONE; 999 dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc); 1000 1001 if(!shpchp_poll_mode) { 1002 /* Mask Global Interrupt Mask - see implementation note on p. 139 */ 1003 /* of SHPC spec rev 1.0*/ 1004 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE); 1005 temp_dword |= 0x00000001; 1006 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE); 1007 1008 intr_loc2 = readl(php_ctlr->creg + INTR_LOC); 1009 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2); 1010 } 1011 1012 if (intr_loc & 0x0001) { 1013 /* 1014 * Command Complete Interrupt Pending 1015 * RO only - clear by writing 1 to the Command Completion 1016 * Detect bit in Controller SERR-INT register 1017 */ 1018 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE); 1019 temp_dword &= 0xfffdffff; 1020 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE); 1021 ctrl->cmd_busy = 0; 1022 wake_up_interruptible(&ctrl->queue); 1023 } 1024 1025 if ((intr_loc = (intr_loc >> 1)) == 0) 1026 goto out; 1027 1028 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 1029 /* To find out which slot has interrupt pending */ 1030 if ((intr_loc >> hp_slot) & 0x01) { 1031 temp_dword = readl(php_ctlr->creg + SLOT1 + (4*hp_slot)); 1032 dbg("%s: Slot %x with intr, slot register = %x\n", 1033 __FUNCTION__, hp_slot, temp_dword); 1034 temp_byte = (temp_dword >> 16) & 0xFF; 1035 if ((php_ctlr->switch_change_callback) && (temp_byte & 0x08)) 1036 schedule_flag += php_ctlr->switch_change_callback( 1037 hp_slot, php_ctlr->callback_instance_id); 1038 if ((php_ctlr->attention_button_callback) && (temp_byte & 0x04)) 1039 schedule_flag += php_ctlr->attention_button_callback( 1040 hp_slot, php_ctlr->callback_instance_id); 1041 if ((php_ctlr->presence_change_callback) && (temp_byte & 0x01)) 1042 schedule_flag += php_ctlr->presence_change_callback( 1043 hp_slot , php_ctlr->callback_instance_id); 1044 if ((php_ctlr->power_fault_callback) && (temp_byte & 0x12)) 1045 schedule_flag += php_ctlr->power_fault_callback( 1046 hp_slot, php_ctlr->callback_instance_id); 1047 1048 /* Clear all slot events */ 1049 temp_dword = 0xe01f3fff; 1050 writel(temp_dword, php_ctlr->creg + SLOT1 + (4*hp_slot)); 1051 1052 intr_loc2 = readl(php_ctlr->creg + INTR_LOC); 1053 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2); 1054 } 1055 } 1056 out: 1057 if (!shpchp_poll_mode) { 1058 /* Unmask Global Interrupt Mask */ 1059 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE); 1060 temp_dword &= 0xfffffffe; 1061 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE); 1062 } 1063 1064 return IRQ_HANDLED; 1065 } 1066 1067 static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value) 1068 { 1069 int retval = 0; 1070 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 1071 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 1072 u8 pi = readb(php_ctlr->creg + PROG_INTERFACE); 1073 u32 slot_avail1 = readl(php_ctlr->creg + SLOT_AVAIL1); 1074 u32 slot_avail2 = readl(php_ctlr->creg + SLOT_AVAIL2); 1075 1076 DBG_ENTER_ROUTINE 1077 1078 if (pi == 2) { 1079 if (slot_avail2 & SLOT_133MHZ_PCIX_533) 1080 bus_speed = PCI_SPEED_133MHz_PCIX_533; 1081 else if (slot_avail2 & SLOT_100MHZ_PCIX_533) 1082 bus_speed = PCI_SPEED_100MHz_PCIX_533; 1083 else if (slot_avail2 & SLOT_66MHZ_PCIX_533) 1084 bus_speed = PCI_SPEED_66MHz_PCIX_533; 1085 else if (slot_avail2 & SLOT_133MHZ_PCIX_266) 1086 bus_speed = PCI_SPEED_133MHz_PCIX_266; 1087 else if (slot_avail2 & SLOT_100MHZ_PCIX_266) 1088 bus_speed = PCI_SPEED_100MHz_PCIX_266; 1089 else if (slot_avail2 & SLOT_66MHZ_PCIX_266) 1090 bus_speed = PCI_SPEED_66MHz_PCIX_266; 1091 } 1092 1093 if (bus_speed == PCI_SPEED_UNKNOWN) { 1094 if (slot_avail1 & SLOT_133MHZ_PCIX) 1095 bus_speed = PCI_SPEED_133MHz_PCIX; 1096 else if (slot_avail1 & SLOT_100MHZ_PCIX) 1097 bus_speed = PCI_SPEED_100MHz_PCIX; 1098 else if (slot_avail1 & SLOT_66MHZ_PCIX) 1099 bus_speed = PCI_SPEED_66MHz_PCIX; 1100 else if (slot_avail2 & SLOT_66MHZ) 1101 bus_speed = PCI_SPEED_66MHz; 1102 else if (slot_avail1 & SLOT_33MHZ) 1103 bus_speed = PCI_SPEED_33MHz; 1104 else 1105 retval = -ENODEV; 1106 } 1107 1108 *value = bus_speed; 1109 dbg("Max bus speed = %d\n", bus_speed); 1110 DBG_LEAVE_ROUTINE 1111 return retval; 1112 } 1113 1114 static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value) 1115 { 1116 int retval = 0; 1117 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 1118 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 1119 u16 sec_bus_reg = readw(php_ctlr->creg + SEC_BUS_CONFIG); 1120 u8 pi = readb(php_ctlr->creg + PROG_INTERFACE); 1121 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7); 1122 1123 DBG_ENTER_ROUTINE 1124 1125 if ((pi == 1) && (speed_mode > 4)) { 1126 *value = PCI_SPEED_UNKNOWN; 1127 return -ENODEV; 1128 } 1129 1130 switch (speed_mode) { 1131 case 0x0: 1132 *value = PCI_SPEED_33MHz; 1133 break; 1134 case 0x1: 1135 *value = PCI_SPEED_66MHz; 1136 break; 1137 case 0x2: 1138 *value = PCI_SPEED_66MHz_PCIX; 1139 break; 1140 case 0x3: 1141 *value = PCI_SPEED_100MHz_PCIX; 1142 break; 1143 case 0x4: 1144 *value = PCI_SPEED_133MHz_PCIX; 1145 break; 1146 case 0x5: 1147 *value = PCI_SPEED_66MHz_PCIX_ECC; 1148 break; 1149 case 0x6: 1150 *value = PCI_SPEED_100MHz_PCIX_ECC; 1151 break; 1152 case 0x7: 1153 *value = PCI_SPEED_133MHz_PCIX_ECC; 1154 break; 1155 case 0x8: 1156 *value = PCI_SPEED_66MHz_PCIX_266; 1157 break; 1158 case 0x9: 1159 *value = PCI_SPEED_100MHz_PCIX_266; 1160 break; 1161 case 0xa: 1162 *value = PCI_SPEED_133MHz_PCIX_266; 1163 break; 1164 case 0xb: 1165 *value = PCI_SPEED_66MHz_PCIX_533; 1166 break; 1167 case 0xc: 1168 *value = PCI_SPEED_100MHz_PCIX_533; 1169 break; 1170 case 0xd: 1171 *value = PCI_SPEED_133MHz_PCIX_533; 1172 break; 1173 default: 1174 *value = PCI_SPEED_UNKNOWN; 1175 retval = -ENODEV; 1176 break; 1177 } 1178 1179 dbg("Current bus speed = %d\n", bus_speed); 1180 DBG_LEAVE_ROUTINE 1181 return retval; 1182 } 1183 1184 static struct hpc_ops shpchp_hpc_ops = { 1185 .power_on_slot = hpc_power_on_slot, 1186 .slot_enable = hpc_slot_enable, 1187 .slot_disable = hpc_slot_disable, 1188 .set_bus_speed_mode = hpc_set_bus_speed_mode, 1189 .set_attention_status = hpc_set_attention_status, 1190 .get_power_status = hpc_get_power_status, 1191 .get_attention_status = hpc_get_attention_status, 1192 .get_latch_status = hpc_get_latch_status, 1193 .get_adapter_status = hpc_get_adapter_status, 1194 1195 .get_max_bus_speed = hpc_get_max_bus_speed, 1196 .get_cur_bus_speed = hpc_get_cur_bus_speed, 1197 .get_adapter_speed = hpc_get_adapter_speed, 1198 .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap, 1199 .get_prog_int = hpc_get_prog_int, 1200 1201 .query_power_fault = hpc_query_power_fault, 1202 .green_led_on = hpc_set_green_led_on, 1203 .green_led_off = hpc_set_green_led_off, 1204 .green_led_blink = hpc_set_green_led_blink, 1205 1206 .release_ctlr = hpc_release_ctlr, 1207 }; 1208 1209 inline static int shpc_indirect_creg_read(struct controller *ctrl, int index, 1210 u32 *value) 1211 { 1212 int rc; 1213 u32 cap_offset = ctrl->cap_offset; 1214 struct pci_dev *pdev = ctrl->pci_dev; 1215 1216 rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index); 1217 if (rc) 1218 return rc; 1219 return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value); 1220 } 1221 1222 int shpc_init(struct controller * ctrl, struct pci_dev * pdev) 1223 { 1224 struct php_ctlr_state_s *php_ctlr, *p; 1225 void *instance_id = ctrl; 1226 int rc, num_slots = 0; 1227 u8 hp_slot; 1228 static int first = 1; 1229 u32 shpc_base_offset; 1230 u32 tempdword, slot_reg; 1231 u8 i; 1232 1233 DBG_ENTER_ROUTINE 1234 1235 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ 1236 1237 spin_lock_init(&list_lock); 1238 php_ctlr = kzalloc(sizeof(*php_ctlr), GFP_KERNEL); 1239 1240 if (!php_ctlr) { /* allocate controller state data */ 1241 err("%s: HPC controller memory allocation error!\n", __FUNCTION__); 1242 goto abort; 1243 } 1244 1245 php_ctlr->pci_dev = pdev; /* save pci_dev in context */ 1246 1247 if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device == 1248 PCI_DEVICE_ID_AMD_GOLAM_7450)) { 1249 /* amd shpc driver doesn't use Base Offset; assume 0 */ 1250 ctrl->mmio_base = pci_resource_start(pdev, 0); 1251 ctrl->mmio_size = pci_resource_len(pdev, 0); 1252 } else { 1253 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); 1254 if (!ctrl->cap_offset) { 1255 err("%s : cap_offset == 0\n", __FUNCTION__); 1256 goto abort_free_ctlr; 1257 } 1258 dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset); 1259 1260 rc = shpc_indirect_creg_read(ctrl, 0, &shpc_base_offset); 1261 if (rc) { 1262 err("%s: cannot read base_offset\n", __FUNCTION__); 1263 goto abort_free_ctlr; 1264 } 1265 1266 rc = shpc_indirect_creg_read(ctrl, 3, &tempdword); 1267 if (rc) { 1268 err("%s: cannot read slot config\n", __FUNCTION__); 1269 goto abort_free_ctlr; 1270 } 1271 num_slots = tempdword & SLOT_NUM; 1272 dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots); 1273 1274 for (i = 0; i < 9 + num_slots; i++) { 1275 rc = shpc_indirect_creg_read(ctrl, i, &tempdword); 1276 if (rc) { 1277 err("%s: cannot read creg (index = %d)\n", 1278 __FUNCTION__, i); 1279 goto abort_free_ctlr; 1280 } 1281 dbg("%s: offset %d: value %x\n", __FUNCTION__,i, 1282 tempdword); 1283 } 1284 1285 ctrl->mmio_base = 1286 pci_resource_start(pdev, 0) + shpc_base_offset; 1287 ctrl->mmio_size = 0x24 + 0x4 * num_slots; 1288 } 1289 1290 if (first) { 1291 spin_lock_init(&hpc_event_lock); 1292 first = 0; 1293 } 1294 1295 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor, 1296 pdev->subsystem_device); 1297 1298 if (pci_enable_device(pdev)) 1299 goto abort_free_ctlr; 1300 1301 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { 1302 err("%s: cannot reserve MMIO region\n", __FUNCTION__); 1303 goto abort_free_ctlr; 1304 } 1305 1306 php_ctlr->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); 1307 if (!php_ctlr->creg) { 1308 err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__, 1309 ctrl->mmio_size, ctrl->mmio_base); 1310 release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 1311 goto abort_free_ctlr; 1312 } 1313 dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg); 1314 1315 mutex_init(&ctrl->crit_sect); 1316 mutex_init(&ctrl->cmd_lock); 1317 1318 /* Setup wait queue */ 1319 init_waitqueue_head(&ctrl->queue); 1320 1321 /* Find the IRQ */ 1322 php_ctlr->irq = pdev->irq; 1323 php_ctlr->attention_button_callback = shpchp_handle_attention_button, 1324 php_ctlr->switch_change_callback = shpchp_handle_switch_change; 1325 php_ctlr->presence_change_callback = shpchp_handle_presence_change; 1326 php_ctlr->power_fault_callback = shpchp_handle_power_fault; 1327 php_ctlr->callback_instance_id = instance_id; 1328 1329 /* Return PCI Controller Info */ 1330 php_ctlr->slot_device_offset = (readl(php_ctlr->creg + SLOT_CONFIG) & FIRST_DEV_NUM ) >> 8; 1331 php_ctlr->num_slots = readl(php_ctlr->creg + SLOT_CONFIG) & SLOT_NUM; 1332 dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset); 1333 dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots); 1334 1335 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ 1336 tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE); 1337 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); 1338 tempdword = 0x0003000f; 1339 writel(tempdword, php_ctlr->creg + SERR_INTR_ENABLE); 1340 tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE); 1341 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); 1342 1343 /* Mask the MRL sensor SERR Mask of individual slot in 1344 * Slot SERR-INT Mask & clear all the existing event if any 1345 */ 1346 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) { 1347 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*hp_slot ); 1348 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, 1349 hp_slot, slot_reg); 1350 tempdword = 0xffff3fff; 1351 writel(tempdword, php_ctlr->creg + SLOT1 + (4*hp_slot)); 1352 } 1353 1354 if (shpchp_poll_mode) {/* Install interrupt polling code */ 1355 /* Install and start the interrupt polling timer */ 1356 init_timer(&php_ctlr->int_poll_timer); 1357 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */ 1358 } else { 1359 /* Installs the interrupt handler */ 1360 rc = pci_enable_msi(pdev); 1361 if (rc) { 1362 info("Can't get msi for the hotplug controller\n"); 1363 info("Use INTx for the hotplug controller\n"); 1364 } else 1365 php_ctlr->irq = pdev->irq; 1366 1367 rc = request_irq(php_ctlr->irq, shpc_isr, SA_SHIRQ, MY_NAME, (void *) ctrl); 1368 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc); 1369 if (rc) { 1370 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq); 1371 goto abort_free_ctlr; 1372 } 1373 } 1374 dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__, 1375 pdev->bus->number, PCI_SLOT(pdev->devfn), 1376 PCI_FUNC(pdev->devfn), pdev->irq); 1377 get_hp_hw_control_from_firmware(pdev); 1378 1379 /* Add this HPC instance into the HPC list */ 1380 spin_lock(&list_lock); 1381 if (php_ctlr_list_head == 0) { 1382 php_ctlr_list_head = php_ctlr; 1383 p = php_ctlr_list_head; 1384 p->pnext = NULL; 1385 } else { 1386 p = php_ctlr_list_head; 1387 1388 while (p->pnext) 1389 p = p->pnext; 1390 1391 p->pnext = php_ctlr; 1392 } 1393 spin_unlock(&list_lock); 1394 1395 1396 ctlr_seq_num++; 1397 ctrl->hpc_ctlr_handle = php_ctlr; 1398 ctrl->hpc_ops = &shpchp_hpc_ops; 1399 1400 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) { 1401 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*hp_slot ); 1402 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, 1403 hp_slot, slot_reg); 1404 tempdword = 0xe01f3fff; 1405 writel(tempdword, php_ctlr->creg + SLOT1 + (4*hp_slot)); 1406 } 1407 if (!shpchp_poll_mode) { 1408 /* Unmask all general input interrupts and SERR */ 1409 tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE); 1410 tempdword = 0x0000000a; 1411 writel(tempdword, php_ctlr->creg + SERR_INTR_ENABLE); 1412 tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE); 1413 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); 1414 } 1415 1416 DBG_LEAVE_ROUTINE 1417 return 0; 1418 1419 /* We end up here for the many possible ways to fail this API. */ 1420 abort_free_ctlr: 1421 kfree(php_ctlr); 1422 abort: 1423 DBG_LEAVE_ROUTINE 1424 return -1; 1425 } 1426