178a0d7f2SLad Prabhakar /* SPDX-License-Identifier: GPL-2.0 */ 278a0d7f2SLad Prabhakar /* 378a0d7f2SLad Prabhakar * PCIe driver for Renesas R-Car SoCs 478a0d7f2SLad Prabhakar * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd 578a0d7f2SLad Prabhakar * 678a0d7f2SLad Prabhakar * Author: Phil Edworthy <phil.edworthy@renesas.com> 778a0d7f2SLad Prabhakar */ 878a0d7f2SLad Prabhakar 978a0d7f2SLad Prabhakar #ifndef _PCIE_RCAR_H 1078a0d7f2SLad Prabhakar #define _PCIE_RCAR_H 1178a0d7f2SLad Prabhakar 1278a0d7f2SLad Prabhakar #define PCIECAR 0x000010 1378a0d7f2SLad Prabhakar #define PCIECCTLR 0x000018 14*727de4c0SLukas Bulwahn #define PCIECCTLR_CCIE BIT(31) 1578a0d7f2SLad Prabhakar #define TYPE0 (0 << 8) 1678a0d7f2SLad Prabhakar #define TYPE1 BIT(8) 1778a0d7f2SLad Prabhakar #define PCIECDR 0x000020 1878a0d7f2SLad Prabhakar #define PCIEMSR 0x000028 1978a0d7f2SLad Prabhakar #define PCIEINTXR 0x000400 202a6d0d63SLad Prabhakar #define ASTINTX BIT(16) 2178a0d7f2SLad Prabhakar #define PCIEPHYSR 0x0007f0 2278a0d7f2SLad Prabhakar #define PHYRDY BIT(0) 2378a0d7f2SLad Prabhakar #define PCIEMSITXR 0x000840 2478a0d7f2SLad Prabhakar 2578a0d7f2SLad Prabhakar /* Transfer control */ 2678a0d7f2SLad Prabhakar #define PCIETCTLR 0x02000 2778a0d7f2SLad Prabhakar #define DL_DOWN BIT(3) 2878a0d7f2SLad Prabhakar #define CFINIT BIT(0) 2978a0d7f2SLad Prabhakar #define PCIETSTR 0x02004 3078a0d7f2SLad Prabhakar #define DATA_LINK_ACTIVE BIT(0) 3178a0d7f2SLad Prabhakar #define PCIEERRFR 0x02020 3278a0d7f2SLad Prabhakar #define UNSUPPORTED_REQUEST BIT(4) 3378a0d7f2SLad Prabhakar #define PCIEMSIFR 0x02044 3478a0d7f2SLad Prabhakar #define PCIEMSIALR 0x02048 3578a0d7f2SLad Prabhakar #define MSIFE BIT(0) 3678a0d7f2SLad Prabhakar #define PCIEMSIAUR 0x0204c 3778a0d7f2SLad Prabhakar #define PCIEMSIIER 0x02050 3878a0d7f2SLad Prabhakar 3978a0d7f2SLad Prabhakar /* root port address */ 4078a0d7f2SLad Prabhakar #define PCIEPRAR(x) (0x02080 + ((x) * 0x4)) 4178a0d7f2SLad Prabhakar 4278a0d7f2SLad Prabhakar /* local address reg & mask */ 4378a0d7f2SLad Prabhakar #define PCIELAR(x) (0x02200 + ((x) * 0x20)) 4478a0d7f2SLad Prabhakar #define PCIELAMR(x) (0x02208 + ((x) * 0x20)) 4578a0d7f2SLad Prabhakar #define LAM_PREFETCH BIT(3) 4678a0d7f2SLad Prabhakar #define LAM_64BIT BIT(2) 4778a0d7f2SLad Prabhakar #define LAR_ENABLE BIT(1) 4878a0d7f2SLad Prabhakar 4978a0d7f2SLad Prabhakar /* PCIe address reg & mask */ 5078a0d7f2SLad Prabhakar #define PCIEPALR(x) (0x03400 + ((x) * 0x20)) 5178a0d7f2SLad Prabhakar #define PCIEPAUR(x) (0x03404 + ((x) * 0x20)) 5278a0d7f2SLad Prabhakar #define PCIEPAMR(x) (0x03408 + ((x) * 0x20)) 5378a0d7f2SLad Prabhakar #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20)) 5478a0d7f2SLad Prabhakar #define PAR_ENABLE BIT(31) 5578a0d7f2SLad Prabhakar #define IO_SPACE BIT(8) 5678a0d7f2SLad Prabhakar 5778a0d7f2SLad Prabhakar /* Configuration */ 5878a0d7f2SLad Prabhakar #define PCICONF(x) (0x010000 + ((x) * 0x4)) 592a6d0d63SLad Prabhakar #define INTDIS BIT(10) 6078a0d7f2SLad Prabhakar #define PMCAP(x) (0x010040 + ((x) * 0x4)) 612a6d0d63SLad Prabhakar #define MSICAP(x) (0x010050 + ((x) * 0x4)) 622a6d0d63SLad Prabhakar #define MSICAP0_MSIE BIT(16) 632a6d0d63SLad Prabhakar #define MSICAP0_MMESCAP_OFFSET 17 642a6d0d63SLad Prabhakar #define MSICAP0_MMESE_OFFSET 20 652a6d0d63SLad Prabhakar #define MSICAP0_MMESE_MASK GENMASK(22, 20) 6678a0d7f2SLad Prabhakar #define EXPCAP(x) (0x010070 + ((x) * 0x4)) 6778a0d7f2SLad Prabhakar #define VCCAP(x) (0x010100 + ((x) * 0x4)) 6878a0d7f2SLad Prabhakar 6978a0d7f2SLad Prabhakar /* link layer */ 702a6d0d63SLad Prabhakar #define IDSETR0 0x011000 7178a0d7f2SLad Prabhakar #define IDSETR1 0x011004 722a6d0d63SLad Prabhakar #define SUBIDSETR 0x011024 7378a0d7f2SLad Prabhakar #define TLCTLR 0x011048 7478a0d7f2SLad Prabhakar #define MACSR 0x011054 7578a0d7f2SLad Prabhakar #define SPCHGFIN BIT(4) 7678a0d7f2SLad Prabhakar #define SPCHGFAIL BIT(6) 7778a0d7f2SLad Prabhakar #define SPCHGSUC BIT(7) 7878a0d7f2SLad Prabhakar #define LINK_SPEED (0xf << 16) 7978a0d7f2SLad Prabhakar #define LINK_SPEED_2_5GTS (1 << 16) 8078a0d7f2SLad Prabhakar #define LINK_SPEED_5_0GTS (2 << 16) 8178a0d7f2SLad Prabhakar #define MACCTLR 0x011058 8278a0d7f2SLad Prabhakar #define MACCTLR_NFTS_MASK GENMASK(23, 16) /* The name is from SH7786 */ 8378a0d7f2SLad Prabhakar #define SPEED_CHANGE BIT(24) 8478a0d7f2SLad Prabhakar #define SCRAMBLE_DISABLE BIT(27) 8578a0d7f2SLad Prabhakar #define LTSMDIS BIT(31) 8678a0d7f2SLad Prabhakar #define MACCTLR_INIT_VAL (LTSMDIS | MACCTLR_NFTS_MASK) 8778a0d7f2SLad Prabhakar #define PMSR 0x01105c 88a115b1bdSMarek Vasut #define L1FAEG BIT(31) 89a115b1bdSMarek Vasut #define PMEL1RX BIT(23) 90a115b1bdSMarek Vasut #define PMSTATE GENMASK(18, 16) 91a115b1bdSMarek Vasut #define PMSTATE_L1 (3 << 16) 92a115b1bdSMarek Vasut #define PMCTLR 0x011060 93a115b1bdSMarek Vasut #define L1IATN BIT(31) 94a115b1bdSMarek Vasut 9578a0d7f2SLad Prabhakar #define MACS2R 0x011078 9678a0d7f2SLad Prabhakar #define MACCGSPSETR 0x011084 9778a0d7f2SLad Prabhakar #define SPCNGRSN BIT(31) 9878a0d7f2SLad Prabhakar 9978a0d7f2SLad Prabhakar /* R-Car H1 PHY */ 10078a0d7f2SLad Prabhakar #define H1_PCIEPHYADRR 0x04000c 10178a0d7f2SLad Prabhakar #define WRITE_CMD BIT(16) 10278a0d7f2SLad Prabhakar #define PHY_ACK BIT(24) 10378a0d7f2SLad Prabhakar #define RATE_POS 12 10478a0d7f2SLad Prabhakar #define LANE_POS 8 10578a0d7f2SLad Prabhakar #define ADR_POS 0 10678a0d7f2SLad Prabhakar #define H1_PCIEPHYDOUTR 0x040014 10778a0d7f2SLad Prabhakar 10878a0d7f2SLad Prabhakar /* R-Car Gen2 PHY */ 10978a0d7f2SLad Prabhakar #define GEN2_PCIEPHYADDR 0x780 11078a0d7f2SLad Prabhakar #define GEN2_PCIEPHYDATA 0x784 11178a0d7f2SLad Prabhakar #define GEN2_PCIEPHYCTRL 0x78c 11278a0d7f2SLad Prabhakar 11378a0d7f2SLad Prabhakar #define INT_PCI_MSI_NR 32 11478a0d7f2SLad Prabhakar 11578a0d7f2SLad Prabhakar #define RCONF(x) (PCICONF(0) + (x)) 11678a0d7f2SLad Prabhakar #define RPMCAP(x) (PMCAP(0) + (x)) 11778a0d7f2SLad Prabhakar #define REXPCAP(x) (EXPCAP(0) + (x)) 11878a0d7f2SLad Prabhakar #define RVCCAP(x) (VCCAP(0) + (x)) 11978a0d7f2SLad Prabhakar 12078a0d7f2SLad Prabhakar #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24) 12178a0d7f2SLad Prabhakar #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19) 12278a0d7f2SLad Prabhakar #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16) 12378a0d7f2SLad Prabhakar 12478a0d7f2SLad Prabhakar #define RCAR_PCI_MAX_RESOURCES 4 12578a0d7f2SLad Prabhakar #define MAX_NR_INBOUND_MAPS 6 12678a0d7f2SLad Prabhakar 12778a0d7f2SLad Prabhakar struct rcar_pcie { 12878a0d7f2SLad Prabhakar struct device *dev; 12978a0d7f2SLad Prabhakar void __iomem *base; 13078a0d7f2SLad Prabhakar }; 13178a0d7f2SLad Prabhakar 13278a0d7f2SLad Prabhakar enum { 13378a0d7f2SLad Prabhakar RCAR_PCI_ACCESS_READ, 13478a0d7f2SLad Prabhakar RCAR_PCI_ACCESS_WRITE, 13578a0d7f2SLad Prabhakar }; 13678a0d7f2SLad Prabhakar 13778a0d7f2SLad Prabhakar void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg); 13878a0d7f2SLad Prabhakar u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg); 13978a0d7f2SLad Prabhakar void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data); 14078a0d7f2SLad Prabhakar int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie); 14178a0d7f2SLad Prabhakar int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie); 14278a0d7f2SLad Prabhakar void rcar_pcie_set_outbound(struct rcar_pcie *pcie, int win, 14378a0d7f2SLad Prabhakar struct resource_entry *window); 14478a0d7f2SLad Prabhakar void rcar_pcie_set_inbound(struct rcar_pcie *pcie, u64 cpu_addr, 14578a0d7f2SLad Prabhakar u64 pci_addr, u64 flags, int idx, bool host); 14678a0d7f2SLad Prabhakar 14778a0d7f2SLad Prabhakar #endif 148