1 #include <linux/delay.h> 2 #include <linux/pci.h> 3 #include <linux/module.h> 4 #include <linux/sched.h> 5 #include <linux/slab.h> 6 #include <linux/ioport.h> 7 #include <linux/wait.h> 8 9 #include "pci.h" 10 11 /* 12 * This interrupt-safe spinlock protects all accesses to PCI 13 * configuration space. 14 */ 15 16 DEFINE_RAW_SPINLOCK(pci_lock); 17 18 /* 19 * Wrappers for all PCI configuration access functions. They just check 20 * alignment, do locking and call the low-level functions pointed to 21 * by pci_dev->ops. 22 */ 23 24 #define PCI_byte_BAD 0 25 #define PCI_word_BAD (pos & 1) 26 #define PCI_dword_BAD (pos & 3) 27 28 #define PCI_OP_READ(size,type,len) \ 29 int pci_bus_read_config_##size \ 30 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \ 31 { \ 32 int res; \ 33 unsigned long flags; \ 34 u32 data = 0; \ 35 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ 36 raw_spin_lock_irqsave(&pci_lock, flags); \ 37 res = bus->ops->read(bus, devfn, pos, len, &data); \ 38 *value = (type)data; \ 39 raw_spin_unlock_irqrestore(&pci_lock, flags); \ 40 return res; \ 41 } 42 43 #define PCI_OP_WRITE(size,type,len) \ 44 int pci_bus_write_config_##size \ 45 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \ 46 { \ 47 int res; \ 48 unsigned long flags; \ 49 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ 50 raw_spin_lock_irqsave(&pci_lock, flags); \ 51 res = bus->ops->write(bus, devfn, pos, len, value); \ 52 raw_spin_unlock_irqrestore(&pci_lock, flags); \ 53 return res; \ 54 } 55 56 PCI_OP_READ(byte, u8, 1) 57 PCI_OP_READ(word, u16, 2) 58 PCI_OP_READ(dword, u32, 4) 59 PCI_OP_WRITE(byte, u8, 1) 60 PCI_OP_WRITE(word, u16, 2) 61 PCI_OP_WRITE(dword, u32, 4) 62 63 EXPORT_SYMBOL(pci_bus_read_config_byte); 64 EXPORT_SYMBOL(pci_bus_read_config_word); 65 EXPORT_SYMBOL(pci_bus_read_config_dword); 66 EXPORT_SYMBOL(pci_bus_write_config_byte); 67 EXPORT_SYMBOL(pci_bus_write_config_word); 68 EXPORT_SYMBOL(pci_bus_write_config_dword); 69 70 /** 71 * pci_bus_set_ops - Set raw operations of pci bus 72 * @bus: pci bus struct 73 * @ops: new raw operations 74 * 75 * Return previous raw operations 76 */ 77 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops) 78 { 79 struct pci_ops *old_ops; 80 unsigned long flags; 81 82 raw_spin_lock_irqsave(&pci_lock, flags); 83 old_ops = bus->ops; 84 bus->ops = ops; 85 raw_spin_unlock_irqrestore(&pci_lock, flags); 86 return old_ops; 87 } 88 EXPORT_SYMBOL(pci_bus_set_ops); 89 90 /** 91 * pci_read_vpd - Read one entry from Vital Product Data 92 * @dev: pci device struct 93 * @pos: offset in vpd space 94 * @count: number of bytes to read 95 * @buf: pointer to where to store result 96 * 97 */ 98 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf) 99 { 100 if (!dev->vpd || !dev->vpd->ops) 101 return -ENODEV; 102 return dev->vpd->ops->read(dev, pos, count, buf); 103 } 104 EXPORT_SYMBOL(pci_read_vpd); 105 106 /** 107 * pci_write_vpd - Write entry to Vital Product Data 108 * @dev: pci device struct 109 * @pos: offset in vpd space 110 * @count: number of bytes to write 111 * @buf: buffer containing write data 112 * 113 */ 114 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf) 115 { 116 if (!dev->vpd || !dev->vpd->ops) 117 return -ENODEV; 118 return dev->vpd->ops->write(dev, pos, count, buf); 119 } 120 EXPORT_SYMBOL(pci_write_vpd); 121 122 /* 123 * The following routines are to prevent the user from accessing PCI config 124 * space when it's unsafe to do so. Some devices require this during BIST and 125 * we're required to prevent it during D-state transitions. 126 * 127 * We have a bit per device to indicate it's blocked and a global wait queue 128 * for callers to sleep on until devices are unblocked. 129 */ 130 static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait); 131 132 static noinline void pci_wait_cfg(struct pci_dev *dev) 133 { 134 DECLARE_WAITQUEUE(wait, current); 135 136 __add_wait_queue(&pci_cfg_wait, &wait); 137 do { 138 set_current_state(TASK_UNINTERRUPTIBLE); 139 raw_spin_unlock_irq(&pci_lock); 140 schedule(); 141 raw_spin_lock_irq(&pci_lock); 142 } while (dev->block_cfg_access); 143 __remove_wait_queue(&pci_cfg_wait, &wait); 144 } 145 146 /* Returns 0 on success, negative values indicate error. */ 147 #define PCI_USER_READ_CONFIG(size,type) \ 148 int pci_user_read_config_##size \ 149 (struct pci_dev *dev, int pos, type *val) \ 150 { \ 151 int ret = PCIBIOS_SUCCESSFUL; \ 152 u32 data = -1; \ 153 if (PCI_##size##_BAD) \ 154 return -EINVAL; \ 155 raw_spin_lock_irq(&pci_lock); \ 156 if (unlikely(dev->block_cfg_access)) \ 157 pci_wait_cfg(dev); \ 158 ret = dev->bus->ops->read(dev->bus, dev->devfn, \ 159 pos, sizeof(type), &data); \ 160 raw_spin_unlock_irq(&pci_lock); \ 161 *val = (type)data; \ 162 return pcibios_err_to_errno(ret); \ 163 } \ 164 EXPORT_SYMBOL_GPL(pci_user_read_config_##size); 165 166 /* Returns 0 on success, negative values indicate error. */ 167 #define PCI_USER_WRITE_CONFIG(size,type) \ 168 int pci_user_write_config_##size \ 169 (struct pci_dev *dev, int pos, type val) \ 170 { \ 171 int ret = PCIBIOS_SUCCESSFUL; \ 172 if (PCI_##size##_BAD) \ 173 return -EINVAL; \ 174 raw_spin_lock_irq(&pci_lock); \ 175 if (unlikely(dev->block_cfg_access)) \ 176 pci_wait_cfg(dev); \ 177 ret = dev->bus->ops->write(dev->bus, dev->devfn, \ 178 pos, sizeof(type), val); \ 179 raw_spin_unlock_irq(&pci_lock); \ 180 return pcibios_err_to_errno(ret); \ 181 } \ 182 EXPORT_SYMBOL_GPL(pci_user_write_config_##size); 183 184 PCI_USER_READ_CONFIG(byte, u8) 185 PCI_USER_READ_CONFIG(word, u16) 186 PCI_USER_READ_CONFIG(dword, u32) 187 PCI_USER_WRITE_CONFIG(byte, u8) 188 PCI_USER_WRITE_CONFIG(word, u16) 189 PCI_USER_WRITE_CONFIG(dword, u32) 190 191 /* VPD access through PCI 2.2+ VPD capability */ 192 193 #define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1) 194 195 struct pci_vpd_pci22 { 196 struct pci_vpd base; 197 struct mutex lock; 198 u16 flag; 199 bool busy; 200 u8 cap; 201 }; 202 203 /* 204 * Wait for last operation to complete. 205 * This code has to spin since there is no other notification from the PCI 206 * hardware. Since the VPD is often implemented by serial attachment to an 207 * EEPROM, it may take many milliseconds to complete. 208 * 209 * Returns 0 on success, negative values indicate error. 210 */ 211 static int pci_vpd_pci22_wait(struct pci_dev *dev) 212 { 213 struct pci_vpd_pci22 *vpd = 214 container_of(dev->vpd, struct pci_vpd_pci22, base); 215 unsigned long timeout = jiffies + HZ/20 + 2; 216 u16 status; 217 int ret; 218 219 if (!vpd->busy) 220 return 0; 221 222 for (;;) { 223 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR, 224 &status); 225 if (ret < 0) 226 return ret; 227 228 if ((status & PCI_VPD_ADDR_F) == vpd->flag) { 229 vpd->busy = false; 230 return 0; 231 } 232 233 if (time_after(jiffies, timeout)) { 234 dev_printk(KERN_DEBUG, &dev->dev, "vpd r/w failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n"); 235 return -ETIMEDOUT; 236 } 237 if (fatal_signal_pending(current)) 238 return -EINTR; 239 if (!cond_resched()) 240 udelay(10); 241 } 242 } 243 244 static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count, 245 void *arg) 246 { 247 struct pci_vpd_pci22 *vpd = 248 container_of(dev->vpd, struct pci_vpd_pci22, base); 249 int ret; 250 loff_t end = pos + count; 251 u8 *buf = arg; 252 253 if (pos < 0 || pos > vpd->base.len || end > vpd->base.len) 254 return -EINVAL; 255 256 if (mutex_lock_killable(&vpd->lock)) 257 return -EINTR; 258 259 ret = pci_vpd_pci22_wait(dev); 260 if (ret < 0) 261 goto out; 262 263 while (pos < end) { 264 u32 val; 265 unsigned int i, skip; 266 267 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR, 268 pos & ~3); 269 if (ret < 0) 270 break; 271 vpd->busy = true; 272 vpd->flag = PCI_VPD_ADDR_F; 273 ret = pci_vpd_pci22_wait(dev); 274 if (ret < 0) 275 break; 276 277 ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val); 278 if (ret < 0) 279 break; 280 281 skip = pos & 3; 282 for (i = 0; i < sizeof(u32); i++) { 283 if (i >= skip) { 284 *buf++ = val; 285 if (++pos == end) 286 break; 287 } 288 val >>= 8; 289 } 290 } 291 out: 292 mutex_unlock(&vpd->lock); 293 return ret ? ret : count; 294 } 295 296 static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count, 297 const void *arg) 298 { 299 struct pci_vpd_pci22 *vpd = 300 container_of(dev->vpd, struct pci_vpd_pci22, base); 301 const u8 *buf = arg; 302 loff_t end = pos + count; 303 int ret = 0; 304 305 if (pos < 0 || (pos & 3) || (count & 3) || end > vpd->base.len) 306 return -EINVAL; 307 308 if (mutex_lock_killable(&vpd->lock)) 309 return -EINTR; 310 311 ret = pci_vpd_pci22_wait(dev); 312 if (ret < 0) 313 goto out; 314 315 while (pos < end) { 316 u32 val; 317 318 val = *buf++; 319 val |= *buf++ << 8; 320 val |= *buf++ << 16; 321 val |= *buf++ << 24; 322 323 ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val); 324 if (ret < 0) 325 break; 326 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR, 327 pos | PCI_VPD_ADDR_F); 328 if (ret < 0) 329 break; 330 331 vpd->busy = true; 332 vpd->flag = 0; 333 ret = pci_vpd_pci22_wait(dev); 334 if (ret < 0) 335 break; 336 337 pos += sizeof(u32); 338 } 339 out: 340 mutex_unlock(&vpd->lock); 341 return ret ? ret : count; 342 } 343 344 static void pci_vpd_pci22_release(struct pci_dev *dev) 345 { 346 kfree(container_of(dev->vpd, struct pci_vpd_pci22, base)); 347 } 348 349 static const struct pci_vpd_ops pci_vpd_pci22_ops = { 350 .read = pci_vpd_pci22_read, 351 .write = pci_vpd_pci22_write, 352 .release = pci_vpd_pci22_release, 353 }; 354 355 int pci_vpd_pci22_init(struct pci_dev *dev) 356 { 357 struct pci_vpd_pci22 *vpd; 358 u8 cap; 359 360 cap = pci_find_capability(dev, PCI_CAP_ID_VPD); 361 if (!cap) 362 return -ENODEV; 363 vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC); 364 if (!vpd) 365 return -ENOMEM; 366 367 vpd->base.len = PCI_VPD_PCI22_SIZE; 368 vpd->base.ops = &pci_vpd_pci22_ops; 369 mutex_init(&vpd->lock); 370 vpd->cap = cap; 371 vpd->busy = false; 372 dev->vpd = &vpd->base; 373 return 0; 374 } 375 376 /** 377 * pci_cfg_access_lock - Lock PCI config reads/writes 378 * @dev: pci device struct 379 * 380 * When access is locked, any userspace reads or writes to config 381 * space and concurrent lock requests will sleep until access is 382 * allowed via pci_cfg_access_unlocked again. 383 */ 384 void pci_cfg_access_lock(struct pci_dev *dev) 385 { 386 might_sleep(); 387 388 raw_spin_lock_irq(&pci_lock); 389 if (dev->block_cfg_access) 390 pci_wait_cfg(dev); 391 dev->block_cfg_access = 1; 392 raw_spin_unlock_irq(&pci_lock); 393 } 394 EXPORT_SYMBOL_GPL(pci_cfg_access_lock); 395 396 /** 397 * pci_cfg_access_trylock - try to lock PCI config reads/writes 398 * @dev: pci device struct 399 * 400 * Same as pci_cfg_access_lock, but will return 0 if access is 401 * already locked, 1 otherwise. This function can be used from 402 * atomic contexts. 403 */ 404 bool pci_cfg_access_trylock(struct pci_dev *dev) 405 { 406 unsigned long flags; 407 bool locked = true; 408 409 raw_spin_lock_irqsave(&pci_lock, flags); 410 if (dev->block_cfg_access) 411 locked = false; 412 else 413 dev->block_cfg_access = 1; 414 raw_spin_unlock_irqrestore(&pci_lock, flags); 415 416 return locked; 417 } 418 EXPORT_SYMBOL_GPL(pci_cfg_access_trylock); 419 420 /** 421 * pci_cfg_access_unlock - Unlock PCI config reads/writes 422 * @dev: pci device struct 423 * 424 * This function allows PCI config accesses to resume. 425 */ 426 void pci_cfg_access_unlock(struct pci_dev *dev) 427 { 428 unsigned long flags; 429 430 raw_spin_lock_irqsave(&pci_lock, flags); 431 432 /* This indicates a problem in the caller, but we don't need 433 * to kill them, unlike a double-block above. */ 434 WARN_ON(!dev->block_cfg_access); 435 436 dev->block_cfg_access = 0; 437 wake_up_all(&pci_cfg_wait); 438 raw_spin_unlock_irqrestore(&pci_lock, flags); 439 } 440 EXPORT_SYMBOL_GPL(pci_cfg_access_unlock); 441 442 static inline int pcie_cap_version(const struct pci_dev *dev) 443 { 444 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS; 445 } 446 447 static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev) 448 { 449 int type = pci_pcie_type(dev); 450 451 return type == PCI_EXP_TYPE_ENDPOINT || 452 type == PCI_EXP_TYPE_LEG_END || 453 type == PCI_EXP_TYPE_ROOT_PORT || 454 type == PCI_EXP_TYPE_UPSTREAM || 455 type == PCI_EXP_TYPE_DOWNSTREAM || 456 type == PCI_EXP_TYPE_PCI_BRIDGE || 457 type == PCI_EXP_TYPE_PCIE_BRIDGE; 458 } 459 460 static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev) 461 { 462 int type = pci_pcie_type(dev); 463 464 return (type == PCI_EXP_TYPE_ROOT_PORT || 465 type == PCI_EXP_TYPE_DOWNSTREAM) && 466 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT; 467 } 468 469 static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev) 470 { 471 int type = pci_pcie_type(dev); 472 473 return type == PCI_EXP_TYPE_ROOT_PORT || 474 type == PCI_EXP_TYPE_RC_EC; 475 } 476 477 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 478 { 479 if (!pci_is_pcie(dev)) 480 return false; 481 482 switch (pos) { 483 case PCI_EXP_FLAGS: 484 return true; 485 case PCI_EXP_DEVCAP: 486 case PCI_EXP_DEVCTL: 487 case PCI_EXP_DEVSTA: 488 return true; 489 case PCI_EXP_LNKCAP: 490 case PCI_EXP_LNKCTL: 491 case PCI_EXP_LNKSTA: 492 return pcie_cap_has_lnkctl(dev); 493 case PCI_EXP_SLTCAP: 494 case PCI_EXP_SLTCTL: 495 case PCI_EXP_SLTSTA: 496 return pcie_cap_has_sltctl(dev); 497 case PCI_EXP_RTCTL: 498 case PCI_EXP_RTCAP: 499 case PCI_EXP_RTSTA: 500 return pcie_cap_has_rtctl(dev); 501 case PCI_EXP_DEVCAP2: 502 case PCI_EXP_DEVCTL2: 503 case PCI_EXP_LNKCAP2: 504 case PCI_EXP_LNKCTL2: 505 case PCI_EXP_LNKSTA2: 506 return pcie_cap_version(dev) > 1; 507 default: 508 return false; 509 } 510 } 511 512 /* 513 * Note that these accessor functions are only for the "PCI Express 514 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the 515 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.) 516 */ 517 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val) 518 { 519 int ret; 520 521 *val = 0; 522 if (pos & 1) 523 return -EINVAL; 524 525 if (pcie_capability_reg_implemented(dev, pos)) { 526 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val); 527 /* 528 * Reset *val to 0 if pci_read_config_word() fails, it may 529 * have been written as 0xFFFF if hardware error happens 530 * during pci_read_config_word(). 531 */ 532 if (ret) 533 *val = 0; 534 return ret; 535 } 536 537 /* 538 * For Functions that do not implement the Slot Capabilities, 539 * Slot Status, and Slot Control registers, these spaces must 540 * be hardwired to 0b, with the exception of the Presence Detect 541 * State bit in the Slot Status register of Downstream Ports, 542 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8) 543 */ 544 if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA && 545 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) { 546 *val = PCI_EXP_SLTSTA_PDS; 547 } 548 549 return 0; 550 } 551 EXPORT_SYMBOL(pcie_capability_read_word); 552 553 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val) 554 { 555 int ret; 556 557 *val = 0; 558 if (pos & 3) 559 return -EINVAL; 560 561 if (pcie_capability_reg_implemented(dev, pos)) { 562 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val); 563 /* 564 * Reset *val to 0 if pci_read_config_dword() fails, it may 565 * have been written as 0xFFFFFFFF if hardware error happens 566 * during pci_read_config_dword(). 567 */ 568 if (ret) 569 *val = 0; 570 return ret; 571 } 572 573 if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL && 574 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) { 575 *val = PCI_EXP_SLTSTA_PDS; 576 } 577 578 return 0; 579 } 580 EXPORT_SYMBOL(pcie_capability_read_dword); 581 582 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 583 { 584 if (pos & 1) 585 return -EINVAL; 586 587 if (!pcie_capability_reg_implemented(dev, pos)) 588 return 0; 589 590 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 591 } 592 EXPORT_SYMBOL(pcie_capability_write_word); 593 594 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val) 595 { 596 if (pos & 3) 597 return -EINVAL; 598 599 if (!pcie_capability_reg_implemented(dev, pos)) 600 return 0; 601 602 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val); 603 } 604 EXPORT_SYMBOL(pcie_capability_write_dword); 605 606 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 607 u16 clear, u16 set) 608 { 609 int ret; 610 u16 val; 611 612 ret = pcie_capability_read_word(dev, pos, &val); 613 if (!ret) { 614 val &= ~clear; 615 val |= set; 616 ret = pcie_capability_write_word(dev, pos, val); 617 } 618 619 return ret; 620 } 621 EXPORT_SYMBOL(pcie_capability_clear_and_set_word); 622 623 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 624 u32 clear, u32 set) 625 { 626 int ret; 627 u32 val; 628 629 ret = pcie_capability_read_dword(dev, pos, &val); 630 if (!ret) { 631 val &= ~clear; 632 val |= set; 633 ret = pcie_capability_write_dword(dev, pos, val); 634 } 635 636 return ret; 637 } 638 EXPORT_SYMBOL(pcie_capability_clear_and_set_dword); 639