1# 2# PCI configuration 3# 4config PCI_MSI 5 bool "Message Signaled Interrupts (MSI and MSI-X)" 6 depends on PCI 7 depends on (X86_LOCAL_APIC && X86_IO_APIC) || IA64 || SPARC64 8 help 9 This allows device drivers to enable MSI (Message Signaled 10 Interrupts). Message Signaled Interrupts enable a device to 11 generate an interrupt using an inbound Memory Write on its 12 PCI bus instead of asserting a device IRQ pin. 13 14 Use of PCI MSI interrupts can be disabled at kernel boot time 15 by using the 'pci=nomsi' option. This disables MSI for the 16 entire system. 17 18 If you don't know what to do here, say N. 19 20config PCI_MULTITHREAD_PROBE 21 bool "PCI Multi-threaded probe (EXPERIMENTAL)" 22 depends on PCI && EXPERIMENTAL && BROKEN 23 help 24 Say Y here if you want the PCI core to spawn a new thread for 25 every PCI device that is probed. This can cause a huge 26 speedup in boot times on multiprocessor machines, and even a 27 smaller speedup on single processor machines. 28 29 But it can also cause lots of bad things to happen. A number 30 of PCI drivers cannot properly handle running in this way, 31 some will just not work properly at all, while others might 32 decide to blow up power supplies with a huge load all at once, 33 so use this option at your own risk. 34 35 It is very unwise to use this option if you are not using a 36 boot process that can handle devices being created in any 37 order. A program that can create persistent block and network 38 device names (like udev) is a good idea if you wish to use 39 this option. 40 41 Again, use this option at your own risk, you have been warned! 42 43 When in doubt, say N. 44 45config PCI_DEBUG 46 bool "PCI Debugging" 47 depends on PCI && DEBUG_KERNEL 48 help 49 Say Y here if you want the PCI core to produce a bunch of debug 50 messages to the system log. Select this if you are having a 51 problem with PCI support and want to see more of what is going on. 52 53 When in doubt, say N. 54 55config HT_IRQ 56 bool "Interrupts on hypertransport devices" 57 default y 58 depends on PCI && X86_LOCAL_APIC && X86_IO_APIC 59 help 60 This allows native hypertransport devices to use interrupts. 61 62 If unsure say Y. 63