1 /* 2 * NVM Express device driver 3 * Copyright (c) 2011-2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #include <linux/aer.h> 16 #include <linux/async.h> 17 #include <linux/blkdev.h> 18 #include <linux/blk-mq.h> 19 #include <linux/blk-mq-pci.h> 20 #include <linux/dmi.h> 21 #include <linux/init.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/mm.h> 25 #include <linux/module.h> 26 #include <linux/mutex.h> 27 #include <linux/once.h> 28 #include <linux/pci.h> 29 #include <linux/t10-pi.h> 30 #include <linux/types.h> 31 #include <linux/io-64-nonatomic-lo-hi.h> 32 #include <linux/sed-opal.h> 33 34 #include "nvme.h" 35 36 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 37 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 38 39 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 40 41 static int use_threaded_interrupts; 42 module_param(use_threaded_interrupts, int, 0); 43 44 static bool use_cmb_sqes = true; 45 module_param(use_cmb_sqes, bool, 0644); 46 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 47 48 static unsigned int max_host_mem_size_mb = 128; 49 module_param(max_host_mem_size_mb, uint, 0444); 50 MODULE_PARM_DESC(max_host_mem_size_mb, 51 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 52 53 static unsigned int sgl_threshold = SZ_32K; 54 module_param(sgl_threshold, uint, 0644); 55 MODULE_PARM_DESC(sgl_threshold, 56 "Use SGLs when average request segment size is larger or equal to " 57 "this size. Use 0 to disable SGLs."); 58 59 static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 60 static const struct kernel_param_ops io_queue_depth_ops = { 61 .set = io_queue_depth_set, 62 .get = param_get_int, 63 }; 64 65 static int io_queue_depth = 1024; 66 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 67 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 68 69 struct nvme_dev; 70 struct nvme_queue; 71 72 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 73 74 /* 75 * Represents an NVM Express device. Each nvme_dev is a PCI function. 76 */ 77 struct nvme_dev { 78 struct nvme_queue *queues; 79 struct blk_mq_tag_set tagset; 80 struct blk_mq_tag_set admin_tagset; 81 u32 __iomem *dbs; 82 struct device *dev; 83 struct dma_pool *prp_page_pool; 84 struct dma_pool *prp_small_pool; 85 unsigned online_queues; 86 unsigned max_qid; 87 unsigned int num_vecs; 88 int q_depth; 89 u32 db_stride; 90 void __iomem *bar; 91 unsigned long bar_mapped_size; 92 struct work_struct remove_work; 93 struct mutex shutdown_lock; 94 bool subsystem; 95 void __iomem *cmb; 96 pci_bus_addr_t cmb_bus_addr; 97 u64 cmb_size; 98 u32 cmbsz; 99 u32 cmbloc; 100 struct nvme_ctrl ctrl; 101 struct completion ioq_wait; 102 103 /* shadow doorbell buffer support: */ 104 u32 *dbbuf_dbs; 105 dma_addr_t dbbuf_dbs_dma_addr; 106 u32 *dbbuf_eis; 107 dma_addr_t dbbuf_eis_dma_addr; 108 109 /* host memory buffer support: */ 110 u64 host_mem_size; 111 u32 nr_host_mem_descs; 112 dma_addr_t host_mem_descs_dma; 113 struct nvme_host_mem_buf_desc *host_mem_descs; 114 void **host_mem_desc_bufs; 115 }; 116 117 static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 118 { 119 int n = 0, ret; 120 121 ret = kstrtoint(val, 10, &n); 122 if (ret != 0 || n < 2) 123 return -EINVAL; 124 125 return param_set_int(val, kp); 126 } 127 128 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 129 { 130 return qid * 2 * stride; 131 } 132 133 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 134 { 135 return (qid * 2 + 1) * stride; 136 } 137 138 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 139 { 140 return container_of(ctrl, struct nvme_dev, ctrl); 141 } 142 143 /* 144 * An NVM Express queue. Each device has at least two (one for admin 145 * commands and one for I/O commands). 146 */ 147 struct nvme_queue { 148 struct device *q_dmadev; 149 struct nvme_dev *dev; 150 spinlock_t sq_lock; 151 struct nvme_command *sq_cmds; 152 struct nvme_command __iomem *sq_cmds_io; 153 spinlock_t cq_lock ____cacheline_aligned_in_smp; 154 volatile struct nvme_completion *cqes; 155 struct blk_mq_tags **tags; 156 dma_addr_t sq_dma_addr; 157 dma_addr_t cq_dma_addr; 158 u32 __iomem *q_db; 159 u16 q_depth; 160 s16 cq_vector; 161 u16 sq_tail; 162 u16 cq_head; 163 u16 last_cq_head; 164 u16 qid; 165 u8 cq_phase; 166 u32 *dbbuf_sq_db; 167 u32 *dbbuf_cq_db; 168 u32 *dbbuf_sq_ei; 169 u32 *dbbuf_cq_ei; 170 }; 171 172 /* 173 * The nvme_iod describes the data in an I/O, including the list of PRP 174 * entries. You can't see it in this data structure because C doesn't let 175 * me express that. Use nvme_init_iod to ensure there's enough space 176 * allocated to store the PRP list. 177 */ 178 struct nvme_iod { 179 struct nvme_request req; 180 struct nvme_queue *nvmeq; 181 bool use_sgl; 182 int aborted; 183 int npages; /* In the PRP list. 0 means small pool in use */ 184 int nents; /* Used in scatterlist */ 185 int length; /* Of data, in bytes */ 186 dma_addr_t first_dma; 187 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 188 struct scatterlist *sg; 189 struct scatterlist inline_sg[0]; 190 }; 191 192 /* 193 * Check we didin't inadvertently grow the command struct 194 */ 195 static inline void _nvme_check_size(void) 196 { 197 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 198 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 199 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 200 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 201 BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 202 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 203 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 204 BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 205 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 206 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 207 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 208 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 209 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 210 } 211 212 static inline unsigned int nvme_dbbuf_size(u32 stride) 213 { 214 return ((num_possible_cpus() + 1) * 8 * stride); 215 } 216 217 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 218 { 219 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 220 221 if (dev->dbbuf_dbs) 222 return 0; 223 224 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 225 &dev->dbbuf_dbs_dma_addr, 226 GFP_KERNEL); 227 if (!dev->dbbuf_dbs) 228 return -ENOMEM; 229 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 230 &dev->dbbuf_eis_dma_addr, 231 GFP_KERNEL); 232 if (!dev->dbbuf_eis) { 233 dma_free_coherent(dev->dev, mem_size, 234 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 235 dev->dbbuf_dbs = NULL; 236 return -ENOMEM; 237 } 238 239 return 0; 240 } 241 242 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 243 { 244 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 245 246 if (dev->dbbuf_dbs) { 247 dma_free_coherent(dev->dev, mem_size, 248 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 249 dev->dbbuf_dbs = NULL; 250 } 251 if (dev->dbbuf_eis) { 252 dma_free_coherent(dev->dev, mem_size, 253 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 254 dev->dbbuf_eis = NULL; 255 } 256 } 257 258 static void nvme_dbbuf_init(struct nvme_dev *dev, 259 struct nvme_queue *nvmeq, int qid) 260 { 261 if (!dev->dbbuf_dbs || !qid) 262 return; 263 264 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 265 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 266 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 267 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 268 } 269 270 static void nvme_dbbuf_set(struct nvme_dev *dev) 271 { 272 struct nvme_command c; 273 274 if (!dev->dbbuf_dbs) 275 return; 276 277 memset(&c, 0, sizeof(c)); 278 c.dbbuf.opcode = nvme_admin_dbbuf; 279 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 280 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 281 282 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 283 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 284 /* Free memory and continue on */ 285 nvme_dbbuf_dma_free(dev); 286 } 287 } 288 289 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 290 { 291 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 292 } 293 294 /* Update dbbuf and return true if an MMIO is required */ 295 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 296 volatile u32 *dbbuf_ei) 297 { 298 if (dbbuf_db) { 299 u16 old_value; 300 301 /* 302 * Ensure that the queue is written before updating 303 * the doorbell in memory 304 */ 305 wmb(); 306 307 old_value = *dbbuf_db; 308 *dbbuf_db = value; 309 310 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 311 return false; 312 } 313 314 return true; 315 } 316 317 /* 318 * Max size of iod being embedded in the request payload 319 */ 320 #define NVME_INT_PAGES 2 321 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 322 323 /* 324 * Will slightly overestimate the number of pages needed. This is OK 325 * as it only leads to a small amount of wasted memory for the lifetime of 326 * the I/O. 327 */ 328 static int nvme_npages(unsigned size, struct nvme_dev *dev) 329 { 330 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 331 dev->ctrl.page_size); 332 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 333 } 334 335 /* 336 * Calculates the number of pages needed for the SGL segments. For example a 4k 337 * page can accommodate 256 SGL descriptors. 338 */ 339 static int nvme_pci_npages_sgl(unsigned int num_seg) 340 { 341 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 342 } 343 344 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 345 unsigned int size, unsigned int nseg, bool use_sgl) 346 { 347 size_t alloc_size; 348 349 if (use_sgl) 350 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 351 else 352 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 353 354 return alloc_size + sizeof(struct scatterlist) * nseg; 355 } 356 357 static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) 358 { 359 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, 360 NVME_INT_BYTES(dev), NVME_INT_PAGES, 361 use_sgl); 362 363 return sizeof(struct nvme_iod) + alloc_size; 364 } 365 366 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 367 unsigned int hctx_idx) 368 { 369 struct nvme_dev *dev = data; 370 struct nvme_queue *nvmeq = &dev->queues[0]; 371 372 WARN_ON(hctx_idx != 0); 373 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 374 WARN_ON(nvmeq->tags); 375 376 hctx->driver_data = nvmeq; 377 nvmeq->tags = &dev->admin_tagset.tags[0]; 378 return 0; 379 } 380 381 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 382 { 383 struct nvme_queue *nvmeq = hctx->driver_data; 384 385 nvmeq->tags = NULL; 386 } 387 388 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 389 unsigned int hctx_idx) 390 { 391 struct nvme_dev *dev = data; 392 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 393 394 if (!nvmeq->tags) 395 nvmeq->tags = &dev->tagset.tags[hctx_idx]; 396 397 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 398 hctx->driver_data = nvmeq; 399 return 0; 400 } 401 402 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 403 unsigned int hctx_idx, unsigned int numa_node) 404 { 405 struct nvme_dev *dev = set->driver_data; 406 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 407 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 408 struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 409 410 BUG_ON(!nvmeq); 411 iod->nvmeq = nvmeq; 412 return 0; 413 } 414 415 static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 416 { 417 struct nvme_dev *dev = set->driver_data; 418 419 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev), 420 dev->num_vecs > 1 ? 1 /* admin queue */ : 0); 421 } 422 423 /** 424 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 425 * @nvmeq: The queue to use 426 * @cmd: The command to send 427 */ 428 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) 429 { 430 spin_lock(&nvmeq->sq_lock); 431 if (nvmeq->sq_cmds_io) 432 memcpy_toio(&nvmeq->sq_cmds_io[nvmeq->sq_tail], cmd, 433 sizeof(*cmd)); 434 else 435 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 436 437 if (++nvmeq->sq_tail == nvmeq->q_depth) 438 nvmeq->sq_tail = 0; 439 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 440 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 441 writel(nvmeq->sq_tail, nvmeq->q_db); 442 spin_unlock(&nvmeq->sq_lock); 443 } 444 445 static void **nvme_pci_iod_list(struct request *req) 446 { 447 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 448 return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 449 } 450 451 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 452 { 453 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 454 int nseg = blk_rq_nr_phys_segments(req); 455 unsigned int avg_seg_size; 456 457 if (nseg == 0) 458 return false; 459 460 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 461 462 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 463 return false; 464 if (!iod->nvmeq->qid) 465 return false; 466 if (!sgl_threshold || avg_seg_size < sgl_threshold) 467 return false; 468 return true; 469 } 470 471 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 472 { 473 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 474 int nseg = blk_rq_nr_phys_segments(rq); 475 unsigned int size = blk_rq_payload_bytes(rq); 476 477 iod->use_sgl = nvme_pci_use_sgls(dev, rq); 478 479 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 480 size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg, 481 iod->use_sgl); 482 483 iod->sg = kmalloc(alloc_size, GFP_ATOMIC); 484 if (!iod->sg) 485 return BLK_STS_RESOURCE; 486 } else { 487 iod->sg = iod->inline_sg; 488 } 489 490 iod->aborted = 0; 491 iod->npages = -1; 492 iod->nents = 0; 493 iod->length = size; 494 495 return BLK_STS_OK; 496 } 497 498 static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 499 { 500 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 501 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 502 dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 503 504 int i; 505 506 if (iod->npages == 0) 507 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 508 dma_addr); 509 510 for (i = 0; i < iod->npages; i++) { 511 void *addr = nvme_pci_iod_list(req)[i]; 512 513 if (iod->use_sgl) { 514 struct nvme_sgl_desc *sg_list = addr; 515 516 next_dma_addr = 517 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 518 } else { 519 __le64 *prp_list = addr; 520 521 next_dma_addr = le64_to_cpu(prp_list[last_prp]); 522 } 523 524 dma_pool_free(dev->prp_page_pool, addr, dma_addr); 525 dma_addr = next_dma_addr; 526 } 527 528 if (iod->sg != iod->inline_sg) 529 kfree(iod->sg); 530 } 531 532 #ifdef CONFIG_BLK_DEV_INTEGRITY 533 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 534 { 535 if (be32_to_cpu(pi->ref_tag) == v) 536 pi->ref_tag = cpu_to_be32(p); 537 } 538 539 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 540 { 541 if (be32_to_cpu(pi->ref_tag) == p) 542 pi->ref_tag = cpu_to_be32(v); 543 } 544 545 /** 546 * nvme_dif_remap - remaps ref tags to bip seed and physical lba 547 * 548 * The virtual start sector is the one that was originally submitted by the 549 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical 550 * start sector may be different. Remap protection information to match the 551 * physical LBA on writes, and back to the original seed on reads. 552 * 553 * Type 0 and 3 do not have a ref tag, so no remapping required. 554 */ 555 static void nvme_dif_remap(struct request *req, 556 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 557 { 558 struct nvme_ns *ns = req->rq_disk->private_data; 559 struct bio_integrity_payload *bip; 560 struct t10_pi_tuple *pi; 561 void *p, *pmap; 562 u32 i, nlb, ts, phys, virt; 563 564 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) 565 return; 566 567 bip = bio_integrity(req->bio); 568 if (!bip) 569 return; 570 571 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; 572 573 p = pmap; 574 virt = bip_get_seed(bip); 575 phys = nvme_block_nr(ns, blk_rq_pos(req)); 576 nlb = (blk_rq_bytes(req) >> ns->lba_shift); 577 ts = ns->disk->queue->integrity.tuple_size; 578 579 for (i = 0; i < nlb; i++, virt++, phys++) { 580 pi = (struct t10_pi_tuple *)p; 581 dif_swap(phys, virt, pi); 582 p += ts; 583 } 584 kunmap_atomic(pmap); 585 } 586 #else /* CONFIG_BLK_DEV_INTEGRITY */ 587 static void nvme_dif_remap(struct request *req, 588 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 589 { 590 } 591 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 592 { 593 } 594 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 595 { 596 } 597 #endif 598 599 static void nvme_print_sgl(struct scatterlist *sgl, int nents) 600 { 601 int i; 602 struct scatterlist *sg; 603 604 for_each_sg(sgl, sg, nents, i) { 605 dma_addr_t phys = sg_phys(sg); 606 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 607 "dma_address:%pad dma_length:%d\n", 608 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 609 sg_dma_len(sg)); 610 } 611 } 612 613 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 614 struct request *req, struct nvme_rw_command *cmnd) 615 { 616 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 617 struct dma_pool *pool; 618 int length = blk_rq_payload_bytes(req); 619 struct scatterlist *sg = iod->sg; 620 int dma_len = sg_dma_len(sg); 621 u64 dma_addr = sg_dma_address(sg); 622 u32 page_size = dev->ctrl.page_size; 623 int offset = dma_addr & (page_size - 1); 624 __le64 *prp_list; 625 void **list = nvme_pci_iod_list(req); 626 dma_addr_t prp_dma; 627 int nprps, i; 628 629 length -= (page_size - offset); 630 if (length <= 0) { 631 iod->first_dma = 0; 632 goto done; 633 } 634 635 dma_len -= (page_size - offset); 636 if (dma_len) { 637 dma_addr += (page_size - offset); 638 } else { 639 sg = sg_next(sg); 640 dma_addr = sg_dma_address(sg); 641 dma_len = sg_dma_len(sg); 642 } 643 644 if (length <= page_size) { 645 iod->first_dma = dma_addr; 646 goto done; 647 } 648 649 nprps = DIV_ROUND_UP(length, page_size); 650 if (nprps <= (256 / 8)) { 651 pool = dev->prp_small_pool; 652 iod->npages = 0; 653 } else { 654 pool = dev->prp_page_pool; 655 iod->npages = 1; 656 } 657 658 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 659 if (!prp_list) { 660 iod->first_dma = dma_addr; 661 iod->npages = -1; 662 return BLK_STS_RESOURCE; 663 } 664 list[0] = prp_list; 665 iod->first_dma = prp_dma; 666 i = 0; 667 for (;;) { 668 if (i == page_size >> 3) { 669 __le64 *old_prp_list = prp_list; 670 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 671 if (!prp_list) 672 return BLK_STS_RESOURCE; 673 list[iod->npages++] = prp_list; 674 prp_list[0] = old_prp_list[i - 1]; 675 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 676 i = 1; 677 } 678 prp_list[i++] = cpu_to_le64(dma_addr); 679 dma_len -= page_size; 680 dma_addr += page_size; 681 length -= page_size; 682 if (length <= 0) 683 break; 684 if (dma_len > 0) 685 continue; 686 if (unlikely(dma_len < 0)) 687 goto bad_sgl; 688 sg = sg_next(sg); 689 dma_addr = sg_dma_address(sg); 690 dma_len = sg_dma_len(sg); 691 } 692 693 done: 694 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 695 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 696 697 return BLK_STS_OK; 698 699 bad_sgl: 700 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 701 "Invalid SGL for payload:%d nents:%d\n", 702 blk_rq_payload_bytes(req), iod->nents); 703 return BLK_STS_IOERR; 704 } 705 706 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 707 struct scatterlist *sg) 708 { 709 sge->addr = cpu_to_le64(sg_dma_address(sg)); 710 sge->length = cpu_to_le32(sg_dma_len(sg)); 711 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 712 } 713 714 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 715 dma_addr_t dma_addr, int entries) 716 { 717 sge->addr = cpu_to_le64(dma_addr); 718 if (entries < SGES_PER_PAGE) { 719 sge->length = cpu_to_le32(entries * sizeof(*sge)); 720 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 721 } else { 722 sge->length = cpu_to_le32(PAGE_SIZE); 723 sge->type = NVME_SGL_FMT_SEG_DESC << 4; 724 } 725 } 726 727 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 728 struct request *req, struct nvme_rw_command *cmd, int entries) 729 { 730 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 731 struct dma_pool *pool; 732 struct nvme_sgl_desc *sg_list; 733 struct scatterlist *sg = iod->sg; 734 dma_addr_t sgl_dma; 735 int i = 0; 736 737 /* setting the transfer type as SGL */ 738 cmd->flags = NVME_CMD_SGL_METABUF; 739 740 if (entries == 1) { 741 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 742 return BLK_STS_OK; 743 } 744 745 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 746 pool = dev->prp_small_pool; 747 iod->npages = 0; 748 } else { 749 pool = dev->prp_page_pool; 750 iod->npages = 1; 751 } 752 753 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 754 if (!sg_list) { 755 iod->npages = -1; 756 return BLK_STS_RESOURCE; 757 } 758 759 nvme_pci_iod_list(req)[0] = sg_list; 760 iod->first_dma = sgl_dma; 761 762 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 763 764 do { 765 if (i == SGES_PER_PAGE) { 766 struct nvme_sgl_desc *old_sg_desc = sg_list; 767 struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 768 769 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 770 if (!sg_list) 771 return BLK_STS_RESOURCE; 772 773 i = 0; 774 nvme_pci_iod_list(req)[iod->npages++] = sg_list; 775 sg_list[i++] = *link; 776 nvme_pci_sgl_set_seg(link, sgl_dma, entries); 777 } 778 779 nvme_pci_sgl_set_data(&sg_list[i++], sg); 780 sg = sg_next(sg); 781 } while (--entries > 0); 782 783 return BLK_STS_OK; 784 } 785 786 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 787 struct nvme_command *cmnd) 788 { 789 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 790 struct request_queue *q = req->q; 791 enum dma_data_direction dma_dir = rq_data_dir(req) ? 792 DMA_TO_DEVICE : DMA_FROM_DEVICE; 793 blk_status_t ret = BLK_STS_IOERR; 794 int nr_mapped; 795 796 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 797 iod->nents = blk_rq_map_sg(q, req, iod->sg); 798 if (!iod->nents) 799 goto out; 800 801 ret = BLK_STS_RESOURCE; 802 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, 803 DMA_ATTR_NO_WARN); 804 if (!nr_mapped) 805 goto out; 806 807 if (iod->use_sgl) 808 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 809 else 810 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 811 812 if (ret != BLK_STS_OK) 813 goto out_unmap; 814 815 ret = BLK_STS_IOERR; 816 if (blk_integrity_rq(req)) { 817 if (blk_rq_count_integrity_sg(q, req->bio) != 1) 818 goto out_unmap; 819 820 sg_init_table(&iod->meta_sg, 1); 821 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 822 goto out_unmap; 823 824 if (req_op(req) == REQ_OP_WRITE) 825 nvme_dif_remap(req, nvme_dif_prep); 826 827 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 828 goto out_unmap; 829 } 830 831 if (blk_integrity_rq(req)) 832 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 833 return BLK_STS_OK; 834 835 out_unmap: 836 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 837 out: 838 return ret; 839 } 840 841 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 842 { 843 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 844 enum dma_data_direction dma_dir = rq_data_dir(req) ? 845 DMA_TO_DEVICE : DMA_FROM_DEVICE; 846 847 if (iod->nents) { 848 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 849 if (blk_integrity_rq(req)) { 850 if (req_op(req) == REQ_OP_READ) 851 nvme_dif_remap(req, nvme_dif_complete); 852 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 853 } 854 } 855 856 nvme_cleanup_cmd(req); 857 nvme_free_iod(dev, req); 858 } 859 860 /* 861 * NOTE: ns is NULL when called on the admin queue. 862 */ 863 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 864 const struct blk_mq_queue_data *bd) 865 { 866 struct nvme_ns *ns = hctx->queue->queuedata; 867 struct nvme_queue *nvmeq = hctx->driver_data; 868 struct nvme_dev *dev = nvmeq->dev; 869 struct request *req = bd->rq; 870 struct nvme_command cmnd; 871 blk_status_t ret; 872 873 /* 874 * We should not need to do this, but we're still using this to 875 * ensure we can drain requests on a dying queue. 876 */ 877 if (unlikely(nvmeq->cq_vector < 0)) 878 return BLK_STS_IOERR; 879 880 ret = nvme_setup_cmd(ns, req, &cmnd); 881 if (ret) 882 return ret; 883 884 ret = nvme_init_iod(req, dev); 885 if (ret) 886 goto out_free_cmd; 887 888 if (blk_rq_nr_phys_segments(req)) { 889 ret = nvme_map_data(dev, req, &cmnd); 890 if (ret) 891 goto out_cleanup_iod; 892 } 893 894 blk_mq_start_request(req); 895 nvme_submit_cmd(nvmeq, &cmnd); 896 return BLK_STS_OK; 897 out_cleanup_iod: 898 nvme_free_iod(dev, req); 899 out_free_cmd: 900 nvme_cleanup_cmd(req); 901 return ret; 902 } 903 904 static void nvme_pci_complete_rq(struct request *req) 905 { 906 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 907 908 nvme_unmap_data(iod->nvmeq->dev, req); 909 nvme_complete_rq(req); 910 } 911 912 /* We read the CQE phase first to check if the rest of the entry is valid */ 913 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 914 { 915 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 916 nvmeq->cq_phase; 917 } 918 919 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 920 { 921 u16 head = nvmeq->cq_head; 922 923 if (likely(nvmeq->cq_vector >= 0)) { 924 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 925 nvmeq->dbbuf_cq_ei)) 926 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 927 } 928 } 929 930 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 931 { 932 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 933 struct request *req; 934 935 if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 936 dev_warn(nvmeq->dev->ctrl.device, 937 "invalid id %d completed on queue %d\n", 938 cqe->command_id, le16_to_cpu(cqe->sq_id)); 939 return; 940 } 941 942 /* 943 * AEN requests are special as they don't time out and can 944 * survive any kind of queue freeze and often don't respond to 945 * aborts. We don't even bother to allocate a struct request 946 * for them but rather special case them here. 947 */ 948 if (unlikely(nvmeq->qid == 0 && 949 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 950 nvme_complete_async_event(&nvmeq->dev->ctrl, 951 cqe->status, &cqe->result); 952 return; 953 } 954 955 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 956 nvme_end_request(req, cqe->status, cqe->result); 957 } 958 959 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 960 { 961 while (start != end) { 962 nvme_handle_cqe(nvmeq, start); 963 if (++start == nvmeq->q_depth) 964 start = 0; 965 } 966 } 967 968 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 969 { 970 if (++nvmeq->cq_head == nvmeq->q_depth) { 971 nvmeq->cq_head = 0; 972 nvmeq->cq_phase = !nvmeq->cq_phase; 973 } 974 } 975 976 static inline bool nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 977 u16 *end, int tag) 978 { 979 bool found = false; 980 981 *start = nvmeq->cq_head; 982 while (!found && nvme_cqe_pending(nvmeq)) { 983 if (nvmeq->cqes[nvmeq->cq_head].command_id == tag) 984 found = true; 985 nvme_update_cq_head(nvmeq); 986 } 987 *end = nvmeq->cq_head; 988 989 if (*start != *end) 990 nvme_ring_cq_doorbell(nvmeq); 991 return found; 992 } 993 994 static irqreturn_t nvme_irq(int irq, void *data) 995 { 996 struct nvme_queue *nvmeq = data; 997 irqreturn_t ret = IRQ_NONE; 998 u16 start, end; 999 1000 spin_lock(&nvmeq->cq_lock); 1001 if (nvmeq->cq_head != nvmeq->last_cq_head) 1002 ret = IRQ_HANDLED; 1003 nvme_process_cq(nvmeq, &start, &end, -1); 1004 nvmeq->last_cq_head = nvmeq->cq_head; 1005 spin_unlock(&nvmeq->cq_lock); 1006 1007 if (start != end) { 1008 nvme_complete_cqes(nvmeq, start, end); 1009 return IRQ_HANDLED; 1010 } 1011 1012 return ret; 1013 } 1014 1015 static irqreturn_t nvme_irq_check(int irq, void *data) 1016 { 1017 struct nvme_queue *nvmeq = data; 1018 if (nvme_cqe_pending(nvmeq)) 1019 return IRQ_WAKE_THREAD; 1020 return IRQ_NONE; 1021 } 1022 1023 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) 1024 { 1025 u16 start, end; 1026 bool found; 1027 1028 if (!nvme_cqe_pending(nvmeq)) 1029 return 0; 1030 1031 spin_lock_irq(&nvmeq->cq_lock); 1032 found = nvme_process_cq(nvmeq, &start, &end, tag); 1033 spin_unlock_irq(&nvmeq->cq_lock); 1034 1035 nvme_complete_cqes(nvmeq, start, end); 1036 return found; 1037 } 1038 1039 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 1040 { 1041 struct nvme_queue *nvmeq = hctx->driver_data; 1042 1043 return __nvme_poll(nvmeq, tag); 1044 } 1045 1046 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 1047 { 1048 struct nvme_dev *dev = to_nvme_dev(ctrl); 1049 struct nvme_queue *nvmeq = &dev->queues[0]; 1050 struct nvme_command c; 1051 1052 memset(&c, 0, sizeof(c)); 1053 c.common.opcode = nvme_admin_async_event; 1054 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1055 nvme_submit_cmd(nvmeq, &c); 1056 } 1057 1058 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1059 { 1060 struct nvme_command c; 1061 1062 memset(&c, 0, sizeof(c)); 1063 c.delete_queue.opcode = opcode; 1064 c.delete_queue.qid = cpu_to_le16(id); 1065 1066 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1067 } 1068 1069 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1070 struct nvme_queue *nvmeq, s16 vector) 1071 { 1072 struct nvme_command c; 1073 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; 1074 1075 /* 1076 * Note: we (ab)use the fact that the prp fields survive if no data 1077 * is attached to the request. 1078 */ 1079 memset(&c, 0, sizeof(c)); 1080 c.create_cq.opcode = nvme_admin_create_cq; 1081 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1082 c.create_cq.cqid = cpu_to_le16(qid); 1083 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1084 c.create_cq.cq_flags = cpu_to_le16(flags); 1085 c.create_cq.irq_vector = cpu_to_le16(vector); 1086 1087 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1088 } 1089 1090 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1091 struct nvme_queue *nvmeq) 1092 { 1093 struct nvme_ctrl *ctrl = &dev->ctrl; 1094 struct nvme_command c; 1095 int flags = NVME_QUEUE_PHYS_CONTIG; 1096 1097 /* 1098 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1099 * set. Since URGENT priority is zeroes, it makes all queues 1100 * URGENT. 1101 */ 1102 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1103 flags |= NVME_SQ_PRIO_MEDIUM; 1104 1105 /* 1106 * Note: we (ab)use the fact that the prp fields survive if no data 1107 * is attached to the request. 1108 */ 1109 memset(&c, 0, sizeof(c)); 1110 c.create_sq.opcode = nvme_admin_create_sq; 1111 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1112 c.create_sq.sqid = cpu_to_le16(qid); 1113 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1114 c.create_sq.sq_flags = cpu_to_le16(flags); 1115 c.create_sq.cqid = cpu_to_le16(qid); 1116 1117 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1118 } 1119 1120 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1121 { 1122 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1123 } 1124 1125 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1126 { 1127 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1128 } 1129 1130 static void abort_endio(struct request *req, blk_status_t error) 1131 { 1132 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1133 struct nvme_queue *nvmeq = iod->nvmeq; 1134 1135 dev_warn(nvmeq->dev->ctrl.device, 1136 "Abort status: 0x%x", nvme_req(req)->status); 1137 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1138 blk_mq_free_request(req); 1139 } 1140 1141 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1142 { 1143 1144 /* If true, indicates loss of adapter communication, possibly by a 1145 * NVMe Subsystem reset. 1146 */ 1147 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1148 1149 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1150 switch (dev->ctrl.state) { 1151 case NVME_CTRL_RESETTING: 1152 case NVME_CTRL_CONNECTING: 1153 return false; 1154 default: 1155 break; 1156 } 1157 1158 /* We shouldn't reset unless the controller is on fatal error state 1159 * _or_ if we lost the communication with it. 1160 */ 1161 if (!(csts & NVME_CSTS_CFS) && !nssro) 1162 return false; 1163 1164 return true; 1165 } 1166 1167 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1168 { 1169 /* Read a config register to help see what died. */ 1170 u16 pci_status; 1171 int result; 1172 1173 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1174 &pci_status); 1175 if (result == PCIBIOS_SUCCESSFUL) 1176 dev_warn(dev->ctrl.device, 1177 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1178 csts, pci_status); 1179 else 1180 dev_warn(dev->ctrl.device, 1181 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1182 csts, result); 1183 } 1184 1185 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 1186 { 1187 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1188 struct nvme_queue *nvmeq = iod->nvmeq; 1189 struct nvme_dev *dev = nvmeq->dev; 1190 struct request *abort_req; 1191 struct nvme_command cmd; 1192 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1193 1194 /* If PCI error recovery process is happening, we cannot reset or 1195 * the recovery mechanism will surely fail. 1196 */ 1197 mb(); 1198 if (pci_channel_offline(to_pci_dev(dev->dev))) 1199 return BLK_EH_RESET_TIMER; 1200 1201 /* 1202 * Reset immediately if the controller is failed 1203 */ 1204 if (nvme_should_reset(dev, csts)) { 1205 nvme_warn_reset(dev, csts); 1206 nvme_dev_disable(dev, false); 1207 nvme_reset_ctrl(&dev->ctrl); 1208 return BLK_EH_DONE; 1209 } 1210 1211 /* 1212 * Did we miss an interrupt? 1213 */ 1214 if (__nvme_poll(nvmeq, req->tag)) { 1215 dev_warn(dev->ctrl.device, 1216 "I/O %d QID %d timeout, completion polled\n", 1217 req->tag, nvmeq->qid); 1218 return BLK_EH_DONE; 1219 } 1220 1221 /* 1222 * Shutdown immediately if controller times out while starting. The 1223 * reset work will see the pci device disabled when it gets the forced 1224 * cancellation error. All outstanding requests are completed on 1225 * shutdown, so we return BLK_EH_DONE. 1226 */ 1227 switch (dev->ctrl.state) { 1228 case NVME_CTRL_CONNECTING: 1229 case NVME_CTRL_RESETTING: 1230 dev_warn_ratelimited(dev->ctrl.device, 1231 "I/O %d QID %d timeout, disable controller\n", 1232 req->tag, nvmeq->qid); 1233 nvme_dev_disable(dev, false); 1234 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1235 return BLK_EH_DONE; 1236 default: 1237 break; 1238 } 1239 1240 /* 1241 * Shutdown the controller immediately and schedule a reset if the 1242 * command was already aborted once before and still hasn't been 1243 * returned to the driver, or if this is the admin queue. 1244 */ 1245 if (!nvmeq->qid || iod->aborted) { 1246 dev_warn(dev->ctrl.device, 1247 "I/O %d QID %d timeout, reset controller\n", 1248 req->tag, nvmeq->qid); 1249 nvme_dev_disable(dev, false); 1250 nvme_reset_ctrl(&dev->ctrl); 1251 1252 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1253 return BLK_EH_DONE; 1254 } 1255 1256 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1257 atomic_inc(&dev->ctrl.abort_limit); 1258 return BLK_EH_RESET_TIMER; 1259 } 1260 iod->aborted = 1; 1261 1262 memset(&cmd, 0, sizeof(cmd)); 1263 cmd.abort.opcode = nvme_admin_abort_cmd; 1264 cmd.abort.cid = req->tag; 1265 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1266 1267 dev_warn(nvmeq->dev->ctrl.device, 1268 "I/O %d QID %d timeout, aborting\n", 1269 req->tag, nvmeq->qid); 1270 1271 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1272 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1273 if (IS_ERR(abort_req)) { 1274 atomic_inc(&dev->ctrl.abort_limit); 1275 return BLK_EH_RESET_TIMER; 1276 } 1277 1278 abort_req->timeout = ADMIN_TIMEOUT; 1279 abort_req->end_io_data = NULL; 1280 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 1281 1282 /* 1283 * The aborted req will be completed on receiving the abort req. 1284 * We enable the timer again. If hit twice, it'll cause a device reset, 1285 * as the device then is in a faulty state. 1286 */ 1287 return BLK_EH_RESET_TIMER; 1288 } 1289 1290 static void nvme_free_queue(struct nvme_queue *nvmeq) 1291 { 1292 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 1293 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1294 if (nvmeq->sq_cmds) 1295 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 1296 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1297 } 1298 1299 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1300 { 1301 int i; 1302 1303 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1304 dev->ctrl.queue_count--; 1305 nvme_free_queue(&dev->queues[i]); 1306 } 1307 } 1308 1309 /** 1310 * nvme_suspend_queue - put queue into suspended state 1311 * @nvmeq - queue to suspend 1312 */ 1313 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1314 { 1315 int vector; 1316 1317 spin_lock_irq(&nvmeq->cq_lock); 1318 if (nvmeq->cq_vector == -1) { 1319 spin_unlock_irq(&nvmeq->cq_lock); 1320 return 1; 1321 } 1322 vector = nvmeq->cq_vector; 1323 nvmeq->dev->online_queues--; 1324 nvmeq->cq_vector = -1; 1325 spin_unlock_irq(&nvmeq->cq_lock); 1326 1327 /* 1328 * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without 1329 * having to grab the lock. 1330 */ 1331 mb(); 1332 1333 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1334 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 1335 1336 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); 1337 1338 return 0; 1339 } 1340 1341 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 1342 { 1343 struct nvme_queue *nvmeq = &dev->queues[0]; 1344 u16 start, end; 1345 1346 if (shutdown) 1347 nvme_shutdown_ctrl(&dev->ctrl); 1348 else 1349 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 1350 1351 spin_lock_irq(&nvmeq->cq_lock); 1352 nvme_process_cq(nvmeq, &start, &end, -1); 1353 spin_unlock_irq(&nvmeq->cq_lock); 1354 1355 nvme_complete_cqes(nvmeq, start, end); 1356 } 1357 1358 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1359 int entry_size) 1360 { 1361 int q_depth = dev->q_depth; 1362 unsigned q_size_aligned = roundup(q_depth * entry_size, 1363 dev->ctrl.page_size); 1364 1365 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1366 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1367 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 1368 q_depth = div_u64(mem_per_q, entry_size); 1369 1370 /* 1371 * Ensure the reduced q_depth is above some threshold where it 1372 * would be better to map queues in system memory with the 1373 * original depth 1374 */ 1375 if (q_depth < 64) 1376 return -ENOMEM; 1377 } 1378 1379 return q_depth; 1380 } 1381 1382 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1383 int qid, int depth) 1384 { 1385 /* CMB SQEs will be mapped before creation */ 1386 if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) 1387 return 0; 1388 1389 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 1390 &nvmeq->sq_dma_addr, GFP_KERNEL); 1391 if (!nvmeq->sq_cmds) 1392 return -ENOMEM; 1393 return 0; 1394 } 1395 1396 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1397 { 1398 struct nvme_queue *nvmeq = &dev->queues[qid]; 1399 1400 if (dev->ctrl.queue_count > qid) 1401 return 0; 1402 1403 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 1404 &nvmeq->cq_dma_addr, GFP_KERNEL); 1405 if (!nvmeq->cqes) 1406 goto free_nvmeq; 1407 1408 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 1409 goto free_cqdma; 1410 1411 nvmeq->q_dmadev = dev->dev; 1412 nvmeq->dev = dev; 1413 spin_lock_init(&nvmeq->sq_lock); 1414 spin_lock_init(&nvmeq->cq_lock); 1415 nvmeq->cq_head = 0; 1416 nvmeq->cq_phase = 1; 1417 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1418 nvmeq->q_depth = depth; 1419 nvmeq->qid = qid; 1420 nvmeq->cq_vector = -1; 1421 dev->ctrl.queue_count++; 1422 1423 return 0; 1424 1425 free_cqdma: 1426 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 1427 nvmeq->cq_dma_addr); 1428 free_nvmeq: 1429 return -ENOMEM; 1430 } 1431 1432 static int queue_request_irq(struct nvme_queue *nvmeq) 1433 { 1434 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1435 int nr = nvmeq->dev->ctrl.instance; 1436 1437 if (use_threaded_interrupts) { 1438 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1439 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1440 } else { 1441 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1442 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1443 } 1444 } 1445 1446 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1447 { 1448 struct nvme_dev *dev = nvmeq->dev; 1449 1450 spin_lock_irq(&nvmeq->cq_lock); 1451 nvmeq->sq_tail = 0; 1452 nvmeq->cq_head = 0; 1453 nvmeq->cq_phase = 1; 1454 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1455 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1456 nvme_dbbuf_init(dev, nvmeq, qid); 1457 dev->online_queues++; 1458 spin_unlock_irq(&nvmeq->cq_lock); 1459 } 1460 1461 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) 1462 { 1463 struct nvme_dev *dev = nvmeq->dev; 1464 int result; 1465 s16 vector; 1466 1467 if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1468 unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth), 1469 dev->ctrl.page_size); 1470 nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset; 1471 nvmeq->sq_cmds_io = dev->cmb + offset; 1472 } 1473 1474 /* 1475 * A queue's vector matches the queue identifier unless the controller 1476 * has only one vector available. 1477 */ 1478 vector = dev->num_vecs == 1 ? 0 : qid; 1479 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1480 if (result < 0) 1481 goto out; 1482 1483 result = adapter_alloc_sq(dev, qid, nvmeq); 1484 if (result < 0) 1485 goto release_cq; 1486 1487 /* 1488 * Set cq_vector after alloc cq/sq, otherwise nvme_suspend_queue will 1489 * invoke free_irq for it and cause a 'Trying to free already-free IRQ 1490 * xxx' warning if the create CQ/SQ command times out. 1491 */ 1492 nvmeq->cq_vector = vector; 1493 nvme_init_queue(nvmeq, qid); 1494 result = queue_request_irq(nvmeq); 1495 if (result < 0) 1496 goto release_sq; 1497 1498 return result; 1499 1500 release_sq: 1501 nvmeq->cq_vector = -1; 1502 dev->online_queues--; 1503 adapter_delete_sq(dev, qid); 1504 release_cq: 1505 adapter_delete_cq(dev, qid); 1506 out: 1507 return result; 1508 } 1509 1510 static const struct blk_mq_ops nvme_mq_admin_ops = { 1511 .queue_rq = nvme_queue_rq, 1512 .complete = nvme_pci_complete_rq, 1513 .init_hctx = nvme_admin_init_hctx, 1514 .exit_hctx = nvme_admin_exit_hctx, 1515 .init_request = nvme_init_request, 1516 .timeout = nvme_timeout, 1517 }; 1518 1519 static const struct blk_mq_ops nvme_mq_ops = { 1520 .queue_rq = nvme_queue_rq, 1521 .complete = nvme_pci_complete_rq, 1522 .init_hctx = nvme_init_hctx, 1523 .init_request = nvme_init_request, 1524 .map_queues = nvme_pci_map_queues, 1525 .timeout = nvme_timeout, 1526 .poll = nvme_poll, 1527 }; 1528 1529 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1530 { 1531 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1532 /* 1533 * If the controller was reset during removal, it's possible 1534 * user requests may be waiting on a stopped queue. Start the 1535 * queue to flush these to completion. 1536 */ 1537 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1538 blk_cleanup_queue(dev->ctrl.admin_q); 1539 blk_mq_free_tag_set(&dev->admin_tagset); 1540 } 1541 } 1542 1543 static int nvme_alloc_admin_tags(struct nvme_dev *dev) 1544 { 1545 if (!dev->ctrl.admin_q) { 1546 dev->admin_tagset.ops = &nvme_mq_admin_ops; 1547 dev->admin_tagset.nr_hw_queues = 1; 1548 1549 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1550 dev->admin_tagset.timeout = ADMIN_TIMEOUT; 1551 dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1552 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); 1553 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 1554 dev->admin_tagset.driver_data = dev; 1555 1556 if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 1557 return -ENOMEM; 1558 dev->ctrl.admin_tagset = &dev->admin_tagset; 1559 1560 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 1561 if (IS_ERR(dev->ctrl.admin_q)) { 1562 blk_mq_free_tag_set(&dev->admin_tagset); 1563 return -ENOMEM; 1564 } 1565 if (!blk_get_queue(dev->ctrl.admin_q)) { 1566 nvme_dev_remove_admin(dev); 1567 dev->ctrl.admin_q = NULL; 1568 return -ENODEV; 1569 } 1570 } else 1571 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1572 1573 return 0; 1574 } 1575 1576 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1577 { 1578 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1579 } 1580 1581 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1582 { 1583 struct pci_dev *pdev = to_pci_dev(dev->dev); 1584 1585 if (size <= dev->bar_mapped_size) 1586 return 0; 1587 if (size > pci_resource_len(pdev, 0)) 1588 return -ENOMEM; 1589 if (dev->bar) 1590 iounmap(dev->bar); 1591 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1592 if (!dev->bar) { 1593 dev->bar_mapped_size = 0; 1594 return -ENOMEM; 1595 } 1596 dev->bar_mapped_size = size; 1597 dev->dbs = dev->bar + NVME_REG_DBS; 1598 1599 return 0; 1600 } 1601 1602 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1603 { 1604 int result; 1605 u32 aqa; 1606 struct nvme_queue *nvmeq; 1607 1608 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1609 if (result < 0) 1610 return result; 1611 1612 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1613 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1614 1615 if (dev->subsystem && 1616 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1617 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1618 1619 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 1620 if (result < 0) 1621 return result; 1622 1623 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1624 if (result) 1625 return result; 1626 1627 nvmeq = &dev->queues[0]; 1628 aqa = nvmeq->q_depth - 1; 1629 aqa |= aqa << 16; 1630 1631 writel(aqa, dev->bar + NVME_REG_AQA); 1632 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1633 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1634 1635 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 1636 if (result) 1637 return result; 1638 1639 nvmeq->cq_vector = 0; 1640 nvme_init_queue(nvmeq, 0); 1641 result = queue_request_irq(nvmeq); 1642 if (result) { 1643 nvmeq->cq_vector = -1; 1644 return result; 1645 } 1646 1647 return result; 1648 } 1649 1650 static int nvme_create_io_queues(struct nvme_dev *dev) 1651 { 1652 unsigned i, max; 1653 int ret = 0; 1654 1655 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1656 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1657 ret = -ENOMEM; 1658 break; 1659 } 1660 } 1661 1662 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1663 for (i = dev->online_queues; i <= max; i++) { 1664 ret = nvme_create_queue(&dev->queues[i], i); 1665 if (ret) 1666 break; 1667 } 1668 1669 /* 1670 * Ignore failing Create SQ/CQ commands, we can continue with less 1671 * than the desired amount of queues, and even a controller without 1672 * I/O queues can still be used to issue admin commands. This might 1673 * be useful to upgrade a buggy firmware for example. 1674 */ 1675 return ret >= 0 ? 0 : ret; 1676 } 1677 1678 static ssize_t nvme_cmb_show(struct device *dev, 1679 struct device_attribute *attr, 1680 char *buf) 1681 { 1682 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1683 1684 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1685 ndev->cmbloc, ndev->cmbsz); 1686 } 1687 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1688 1689 static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1690 { 1691 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1692 1693 return 1ULL << (12 + 4 * szu); 1694 } 1695 1696 static u32 nvme_cmb_size(struct nvme_dev *dev) 1697 { 1698 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1699 } 1700 1701 static void nvme_map_cmb(struct nvme_dev *dev) 1702 { 1703 u64 size, offset; 1704 resource_size_t bar_size; 1705 struct pci_dev *pdev = to_pci_dev(dev->dev); 1706 int bar; 1707 1708 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1709 if (!dev->cmbsz) 1710 return; 1711 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1712 1713 if (!use_cmb_sqes) 1714 return; 1715 1716 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1717 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1718 bar = NVME_CMB_BIR(dev->cmbloc); 1719 bar_size = pci_resource_len(pdev, bar); 1720 1721 if (offset > bar_size) 1722 return; 1723 1724 /* 1725 * Controllers may support a CMB size larger than their BAR, 1726 * for example, due to being behind a bridge. Reduce the CMB to 1727 * the reported size of the BAR 1728 */ 1729 if (size > bar_size - offset) 1730 size = bar_size - offset; 1731 1732 dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size); 1733 if (!dev->cmb) 1734 return; 1735 dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset; 1736 dev->cmb_size = size; 1737 1738 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1739 &dev_attr_cmb.attr, NULL)) 1740 dev_warn(dev->ctrl.device, 1741 "failed to add sysfs attribute for CMB\n"); 1742 } 1743 1744 static inline void nvme_release_cmb(struct nvme_dev *dev) 1745 { 1746 if (dev->cmb) { 1747 iounmap(dev->cmb); 1748 dev->cmb = NULL; 1749 sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1750 &dev_attr_cmb.attr, NULL); 1751 dev->cmbsz = 0; 1752 } 1753 } 1754 1755 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1756 { 1757 u64 dma_addr = dev->host_mem_descs_dma; 1758 struct nvme_command c; 1759 int ret; 1760 1761 memset(&c, 0, sizeof(c)); 1762 c.features.opcode = nvme_admin_set_features; 1763 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1764 c.features.dword11 = cpu_to_le32(bits); 1765 c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 1766 ilog2(dev->ctrl.page_size)); 1767 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1768 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1769 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1770 1771 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1772 if (ret) { 1773 dev_warn(dev->ctrl.device, 1774 "failed to set host mem (err %d, flags %#x).\n", 1775 ret, bits); 1776 } 1777 return ret; 1778 } 1779 1780 static void nvme_free_host_mem(struct nvme_dev *dev) 1781 { 1782 int i; 1783 1784 for (i = 0; i < dev->nr_host_mem_descs; i++) { 1785 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 1786 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 1787 1788 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], 1789 le64_to_cpu(desc->addr)); 1790 } 1791 1792 kfree(dev->host_mem_desc_bufs); 1793 dev->host_mem_desc_bufs = NULL; 1794 dma_free_coherent(dev->dev, 1795 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 1796 dev->host_mem_descs, dev->host_mem_descs_dma); 1797 dev->host_mem_descs = NULL; 1798 dev->nr_host_mem_descs = 0; 1799 } 1800 1801 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 1802 u32 chunk_size) 1803 { 1804 struct nvme_host_mem_buf_desc *descs; 1805 u32 max_entries, len; 1806 dma_addr_t descs_dma; 1807 int i = 0; 1808 void **bufs; 1809 u64 size, tmp; 1810 1811 tmp = (preferred + chunk_size - 1); 1812 do_div(tmp, chunk_size); 1813 max_entries = tmp; 1814 1815 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1816 max_entries = dev->ctrl.hmmaxd; 1817 1818 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs), 1819 &descs_dma, GFP_KERNEL); 1820 if (!descs) 1821 goto out; 1822 1823 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 1824 if (!bufs) 1825 goto out_free_descs; 1826 1827 for (size = 0; size < preferred && i < max_entries; size += len) { 1828 dma_addr_t dma_addr; 1829 1830 len = min_t(u64, chunk_size, preferred - size); 1831 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 1832 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1833 if (!bufs[i]) 1834 break; 1835 1836 descs[i].addr = cpu_to_le64(dma_addr); 1837 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 1838 i++; 1839 } 1840 1841 if (!size) 1842 goto out_free_bufs; 1843 1844 dev->nr_host_mem_descs = i; 1845 dev->host_mem_size = size; 1846 dev->host_mem_descs = descs; 1847 dev->host_mem_descs_dma = descs_dma; 1848 dev->host_mem_desc_bufs = bufs; 1849 return 0; 1850 1851 out_free_bufs: 1852 while (--i >= 0) { 1853 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 1854 1855 dma_free_coherent(dev->dev, size, bufs[i], 1856 le64_to_cpu(descs[i].addr)); 1857 } 1858 1859 kfree(bufs); 1860 out_free_descs: 1861 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 1862 descs_dma); 1863 out: 1864 dev->host_mem_descs = NULL; 1865 return -ENOMEM; 1866 } 1867 1868 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 1869 { 1870 u32 chunk_size; 1871 1872 /* start big and work our way down */ 1873 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1874 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 1875 chunk_size /= 2) { 1876 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 1877 if (!min || dev->host_mem_size >= min) 1878 return 0; 1879 nvme_free_host_mem(dev); 1880 } 1881 } 1882 1883 return -ENOMEM; 1884 } 1885 1886 static int nvme_setup_host_mem(struct nvme_dev *dev) 1887 { 1888 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 1889 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 1890 u64 min = (u64)dev->ctrl.hmmin * 4096; 1891 u32 enable_bits = NVME_HOST_MEM_ENABLE; 1892 int ret; 1893 1894 preferred = min(preferred, max); 1895 if (min > max) { 1896 dev_warn(dev->ctrl.device, 1897 "min host memory (%lld MiB) above limit (%d MiB).\n", 1898 min >> ilog2(SZ_1M), max_host_mem_size_mb); 1899 nvme_free_host_mem(dev); 1900 return 0; 1901 } 1902 1903 /* 1904 * If we already have a buffer allocated check if we can reuse it. 1905 */ 1906 if (dev->host_mem_descs) { 1907 if (dev->host_mem_size >= min) 1908 enable_bits |= NVME_HOST_MEM_RETURN; 1909 else 1910 nvme_free_host_mem(dev); 1911 } 1912 1913 if (!dev->host_mem_descs) { 1914 if (nvme_alloc_host_mem(dev, min, preferred)) { 1915 dev_warn(dev->ctrl.device, 1916 "failed to allocate host memory buffer.\n"); 1917 return 0; /* controller must work without HMB */ 1918 } 1919 1920 dev_info(dev->ctrl.device, 1921 "allocated %lld MiB host memory buffer.\n", 1922 dev->host_mem_size >> ilog2(SZ_1M)); 1923 } 1924 1925 ret = nvme_set_host_mem(dev, enable_bits); 1926 if (ret) 1927 nvme_free_host_mem(dev); 1928 return ret; 1929 } 1930 1931 static int nvme_setup_io_queues(struct nvme_dev *dev) 1932 { 1933 struct nvme_queue *adminq = &dev->queues[0]; 1934 struct pci_dev *pdev = to_pci_dev(dev->dev); 1935 int result, nr_io_queues; 1936 unsigned long size; 1937 1938 struct irq_affinity affd = { 1939 .pre_vectors = 1 1940 }; 1941 1942 nr_io_queues = num_possible_cpus(); 1943 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 1944 if (result < 0) 1945 return result; 1946 1947 if (nr_io_queues == 0) 1948 return 0; 1949 1950 if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1951 result = nvme_cmb_qdepth(dev, nr_io_queues, 1952 sizeof(struct nvme_command)); 1953 if (result > 0) 1954 dev->q_depth = result; 1955 else 1956 nvme_release_cmb(dev); 1957 } 1958 1959 do { 1960 size = db_bar_size(dev, nr_io_queues); 1961 result = nvme_remap_bar(dev, size); 1962 if (!result) 1963 break; 1964 if (!--nr_io_queues) 1965 return -ENOMEM; 1966 } while (1); 1967 adminq->q_db = dev->dbs; 1968 1969 /* Deregister the admin queue's interrupt */ 1970 pci_free_irq(pdev, 0, adminq); 1971 1972 /* 1973 * If we enable msix early due to not intx, disable it again before 1974 * setting up the full range we need. 1975 */ 1976 pci_free_irq_vectors(pdev); 1977 result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1, 1978 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 1979 if (result <= 0) 1980 return -EIO; 1981 dev->num_vecs = result; 1982 dev->max_qid = max(result - 1, 1); 1983 1984 /* 1985 * Should investigate if there's a performance win from allocating 1986 * more queues than interrupt vectors; it might allow the submission 1987 * path to scale better, even if the receive path is limited by the 1988 * number of interrupts. 1989 */ 1990 1991 result = queue_request_irq(adminq); 1992 if (result) { 1993 adminq->cq_vector = -1; 1994 return result; 1995 } 1996 return nvme_create_io_queues(dev); 1997 } 1998 1999 static void nvme_del_queue_end(struct request *req, blk_status_t error) 2000 { 2001 struct nvme_queue *nvmeq = req->end_io_data; 2002 2003 blk_mq_free_request(req); 2004 complete(&nvmeq->dev->ioq_wait); 2005 } 2006 2007 static void nvme_del_cq_end(struct request *req, blk_status_t error) 2008 { 2009 struct nvme_queue *nvmeq = req->end_io_data; 2010 u16 start, end; 2011 2012 if (!error) { 2013 unsigned long flags; 2014 2015 /* 2016 * We might be called with the AQ cq_lock held 2017 * and the I/O queue cq_lock should always 2018 * nest inside the AQ one. 2019 */ 2020 spin_lock_irqsave_nested(&nvmeq->cq_lock, flags, 2021 SINGLE_DEPTH_NESTING); 2022 nvme_process_cq(nvmeq, &start, &end, -1); 2023 spin_unlock_irqrestore(&nvmeq->cq_lock, flags); 2024 2025 nvme_complete_cqes(nvmeq, start, end); 2026 } 2027 2028 nvme_del_queue_end(req, error); 2029 } 2030 2031 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2032 { 2033 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2034 struct request *req; 2035 struct nvme_command cmd; 2036 2037 memset(&cmd, 0, sizeof(cmd)); 2038 cmd.delete_queue.opcode = opcode; 2039 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2040 2041 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2042 if (IS_ERR(req)) 2043 return PTR_ERR(req); 2044 2045 req->timeout = ADMIN_TIMEOUT; 2046 req->end_io_data = nvmeq; 2047 2048 blk_execute_rq_nowait(q, NULL, req, false, 2049 opcode == nvme_admin_delete_cq ? 2050 nvme_del_cq_end : nvme_del_queue_end); 2051 return 0; 2052 } 2053 2054 static void nvme_disable_io_queues(struct nvme_dev *dev) 2055 { 2056 int pass, queues = dev->online_queues - 1; 2057 unsigned long timeout; 2058 u8 opcode = nvme_admin_delete_sq; 2059 2060 for (pass = 0; pass < 2; pass++) { 2061 int sent = 0, i = queues; 2062 2063 reinit_completion(&dev->ioq_wait); 2064 retry: 2065 timeout = ADMIN_TIMEOUT; 2066 for (; i > 0; i--, sent++) 2067 if (nvme_delete_queue(&dev->queues[i], opcode)) 2068 break; 2069 2070 while (sent--) { 2071 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); 2072 if (timeout == 0) 2073 return; 2074 if (i) 2075 goto retry; 2076 } 2077 opcode = nvme_admin_delete_cq; 2078 } 2079 } 2080 2081 /* 2082 * return error value only when tagset allocation failed 2083 */ 2084 static int nvme_dev_add(struct nvme_dev *dev) 2085 { 2086 int ret; 2087 2088 if (!dev->ctrl.tagset) { 2089 dev->tagset.ops = &nvme_mq_ops; 2090 dev->tagset.nr_hw_queues = dev->online_queues - 1; 2091 dev->tagset.timeout = NVME_IO_TIMEOUT; 2092 dev->tagset.numa_node = dev_to_node(dev->dev); 2093 dev->tagset.queue_depth = 2094 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2095 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); 2096 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { 2097 dev->tagset.cmd_size = max(dev->tagset.cmd_size, 2098 nvme_pci_cmd_size(dev, true)); 2099 } 2100 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 2101 dev->tagset.driver_data = dev; 2102 2103 ret = blk_mq_alloc_tag_set(&dev->tagset); 2104 if (ret) { 2105 dev_warn(dev->ctrl.device, 2106 "IO queues tagset allocation failed %d\n", ret); 2107 return ret; 2108 } 2109 dev->ctrl.tagset = &dev->tagset; 2110 2111 nvme_dbbuf_set(dev); 2112 } else { 2113 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2114 2115 /* Free previously allocated queues that are no longer usable */ 2116 nvme_free_queues(dev, dev->online_queues); 2117 } 2118 2119 return 0; 2120 } 2121 2122 static int nvme_pci_enable(struct nvme_dev *dev) 2123 { 2124 int result = -ENOMEM; 2125 struct pci_dev *pdev = to_pci_dev(dev->dev); 2126 2127 if (pci_enable_device_mem(pdev)) 2128 return result; 2129 2130 pci_set_master(pdev); 2131 2132 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 2133 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 2134 goto disable; 2135 2136 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2137 result = -ENODEV; 2138 goto disable; 2139 } 2140 2141 /* 2142 * Some devices and/or platforms don't advertise or work with INTx 2143 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2144 * adjust this later. 2145 */ 2146 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2147 if (result < 0) 2148 return result; 2149 2150 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2151 2152 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2153 io_queue_depth); 2154 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2155 dev->dbs = dev->bar + 4096; 2156 2157 /* 2158 * Temporary fix for the Apple controller found in the MacBook8,1 and 2159 * some MacBook7,1 to avoid controller resets and data loss. 2160 */ 2161 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 2162 dev->q_depth = 2; 2163 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 2164 "set queue depth=%u to work around controller resets\n", 2165 dev->q_depth); 2166 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2167 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2168 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2169 dev->q_depth = 64; 2170 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2171 "set queue depth=%u\n", dev->q_depth); 2172 } 2173 2174 nvme_map_cmb(dev); 2175 2176 pci_enable_pcie_error_reporting(pdev); 2177 pci_save_state(pdev); 2178 return 0; 2179 2180 disable: 2181 pci_disable_device(pdev); 2182 return result; 2183 } 2184 2185 static void nvme_dev_unmap(struct nvme_dev *dev) 2186 { 2187 if (dev->bar) 2188 iounmap(dev->bar); 2189 pci_release_mem_regions(to_pci_dev(dev->dev)); 2190 } 2191 2192 static void nvme_pci_disable(struct nvme_dev *dev) 2193 { 2194 struct pci_dev *pdev = to_pci_dev(dev->dev); 2195 2196 nvme_release_cmb(dev); 2197 pci_free_irq_vectors(pdev); 2198 2199 if (pci_is_enabled(pdev)) { 2200 pci_disable_pcie_error_reporting(pdev); 2201 pci_disable_device(pdev); 2202 } 2203 } 2204 2205 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2206 { 2207 int i; 2208 bool dead = true; 2209 struct pci_dev *pdev = to_pci_dev(dev->dev); 2210 2211 mutex_lock(&dev->shutdown_lock); 2212 if (pci_is_enabled(pdev)) { 2213 u32 csts = readl(dev->bar + NVME_REG_CSTS); 2214 2215 if (dev->ctrl.state == NVME_CTRL_LIVE || 2216 dev->ctrl.state == NVME_CTRL_RESETTING) 2217 nvme_start_freeze(&dev->ctrl); 2218 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2219 pdev->error_state != pci_channel_io_normal); 2220 } 2221 2222 /* 2223 * Give the controller a chance to complete all entered requests if 2224 * doing a safe shutdown. 2225 */ 2226 if (!dead) { 2227 if (shutdown) 2228 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2229 } 2230 2231 nvme_stop_queues(&dev->ctrl); 2232 2233 if (!dead && dev->ctrl.queue_count > 0) { 2234 /* 2235 * If the controller is still alive tell it to stop using the 2236 * host memory buffer. In theory the shutdown / reset should 2237 * make sure that it doesn't access the host memoery anymore, 2238 * but I'd rather be safe than sorry.. 2239 */ 2240 if (dev->host_mem_descs) 2241 nvme_set_host_mem(dev, 0); 2242 nvme_disable_io_queues(dev); 2243 nvme_disable_admin_queue(dev, shutdown); 2244 } 2245 for (i = dev->ctrl.queue_count - 1; i >= 0; i--) 2246 nvme_suspend_queue(&dev->queues[i]); 2247 2248 nvme_pci_disable(dev); 2249 2250 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2251 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2252 2253 /* 2254 * The driver will not be starting up queues again if shutting down so 2255 * must flush all entered requests to their failed completion to avoid 2256 * deadlocking blk-mq hot-cpu notifier. 2257 */ 2258 if (shutdown) 2259 nvme_start_queues(&dev->ctrl); 2260 mutex_unlock(&dev->shutdown_lock); 2261 } 2262 2263 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2264 { 2265 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2266 PAGE_SIZE, PAGE_SIZE, 0); 2267 if (!dev->prp_page_pool) 2268 return -ENOMEM; 2269 2270 /* Optimisation for I/Os between 4k and 128k */ 2271 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2272 256, 256, 0); 2273 if (!dev->prp_small_pool) { 2274 dma_pool_destroy(dev->prp_page_pool); 2275 return -ENOMEM; 2276 } 2277 return 0; 2278 } 2279 2280 static void nvme_release_prp_pools(struct nvme_dev *dev) 2281 { 2282 dma_pool_destroy(dev->prp_page_pool); 2283 dma_pool_destroy(dev->prp_small_pool); 2284 } 2285 2286 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2287 { 2288 struct nvme_dev *dev = to_nvme_dev(ctrl); 2289 2290 nvme_dbbuf_dma_free(dev); 2291 put_device(dev->dev); 2292 if (dev->tagset.tags) 2293 blk_mq_free_tag_set(&dev->tagset); 2294 if (dev->ctrl.admin_q) 2295 blk_put_queue(dev->ctrl.admin_q); 2296 kfree(dev->queues); 2297 free_opal_dev(dev->ctrl.opal_dev); 2298 kfree(dev); 2299 } 2300 2301 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2302 { 2303 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2304 2305 nvme_get_ctrl(&dev->ctrl); 2306 nvme_dev_disable(dev, false); 2307 if (!queue_work(nvme_wq, &dev->remove_work)) 2308 nvme_put_ctrl(&dev->ctrl); 2309 } 2310 2311 static void nvme_reset_work(struct work_struct *work) 2312 { 2313 struct nvme_dev *dev = 2314 container_of(work, struct nvme_dev, ctrl.reset_work); 2315 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2316 int result = -ENODEV; 2317 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 2318 2319 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2320 goto out; 2321 2322 /* 2323 * If we're called to reset a live controller first shut it down before 2324 * moving on. 2325 */ 2326 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2327 nvme_dev_disable(dev, false); 2328 2329 /* 2330 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2331 * initializing procedure here. 2332 */ 2333 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2334 dev_warn(dev->ctrl.device, 2335 "failed to mark controller CONNECTING\n"); 2336 goto out; 2337 } 2338 2339 result = nvme_pci_enable(dev); 2340 if (result) 2341 goto out; 2342 2343 result = nvme_pci_configure_admin_queue(dev); 2344 if (result) 2345 goto out; 2346 2347 result = nvme_alloc_admin_tags(dev); 2348 if (result) 2349 goto out; 2350 2351 result = nvme_init_identify(&dev->ctrl); 2352 if (result) 2353 goto out; 2354 2355 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2356 if (!dev->ctrl.opal_dev) 2357 dev->ctrl.opal_dev = 2358 init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2359 else if (was_suspend) 2360 opal_unlock_from_suspend(dev->ctrl.opal_dev); 2361 } else { 2362 free_opal_dev(dev->ctrl.opal_dev); 2363 dev->ctrl.opal_dev = NULL; 2364 } 2365 2366 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2367 result = nvme_dbbuf_dma_alloc(dev); 2368 if (result) 2369 dev_warn(dev->dev, 2370 "unable to allocate dma for dbbuf\n"); 2371 } 2372 2373 if (dev->ctrl.hmpre) { 2374 result = nvme_setup_host_mem(dev); 2375 if (result < 0) 2376 goto out; 2377 } 2378 2379 result = nvme_setup_io_queues(dev); 2380 if (result) 2381 goto out; 2382 2383 /* 2384 * Keep the controller around but remove all namespaces if we don't have 2385 * any working I/O queue. 2386 */ 2387 if (dev->online_queues < 2) { 2388 dev_warn(dev->ctrl.device, "IO queues not created\n"); 2389 nvme_kill_queues(&dev->ctrl); 2390 nvme_remove_namespaces(&dev->ctrl); 2391 new_state = NVME_CTRL_ADMIN_ONLY; 2392 } else { 2393 nvme_start_queues(&dev->ctrl); 2394 nvme_wait_freeze(&dev->ctrl); 2395 /* hit this only when allocate tagset fails */ 2396 if (nvme_dev_add(dev)) 2397 new_state = NVME_CTRL_ADMIN_ONLY; 2398 nvme_unfreeze(&dev->ctrl); 2399 } 2400 2401 /* 2402 * If only admin queue live, keep it to do further investigation or 2403 * recovery. 2404 */ 2405 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 2406 dev_warn(dev->ctrl.device, 2407 "failed to mark controller state %d\n", new_state); 2408 goto out; 2409 } 2410 2411 nvme_start_ctrl(&dev->ctrl); 2412 return; 2413 2414 out: 2415 nvme_remove_dead_ctrl(dev, result); 2416 } 2417 2418 static void nvme_remove_dead_ctrl_work(struct work_struct *work) 2419 { 2420 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 2421 struct pci_dev *pdev = to_pci_dev(dev->dev); 2422 2423 nvme_kill_queues(&dev->ctrl); 2424 if (pci_get_drvdata(pdev)) 2425 device_release_driver(&pdev->dev); 2426 nvme_put_ctrl(&dev->ctrl); 2427 } 2428 2429 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2430 { 2431 *val = readl(to_nvme_dev(ctrl)->bar + off); 2432 return 0; 2433 } 2434 2435 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2436 { 2437 writel(val, to_nvme_dev(ctrl)->bar + off); 2438 return 0; 2439 } 2440 2441 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2442 { 2443 *val = readq(to_nvme_dev(ctrl)->bar + off); 2444 return 0; 2445 } 2446 2447 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2448 { 2449 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2450 2451 return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 2452 } 2453 2454 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2455 .name = "pcie", 2456 .module = THIS_MODULE, 2457 .flags = NVME_F_METADATA_SUPPORTED, 2458 .reg_read32 = nvme_pci_reg_read32, 2459 .reg_write32 = nvme_pci_reg_write32, 2460 .reg_read64 = nvme_pci_reg_read64, 2461 .free_ctrl = nvme_pci_free_ctrl, 2462 .submit_async_event = nvme_pci_submit_async_event, 2463 .get_address = nvme_pci_get_address, 2464 }; 2465 2466 static int nvme_dev_map(struct nvme_dev *dev) 2467 { 2468 struct pci_dev *pdev = to_pci_dev(dev->dev); 2469 2470 if (pci_request_mem_regions(pdev, "nvme")) 2471 return -ENODEV; 2472 2473 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2474 goto release; 2475 2476 return 0; 2477 release: 2478 pci_release_mem_regions(pdev); 2479 return -ENODEV; 2480 } 2481 2482 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2483 { 2484 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2485 /* 2486 * Several Samsung devices seem to drop off the PCIe bus 2487 * randomly when APST is on and uses the deepest sleep state. 2488 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2489 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2490 * 950 PRO 256GB", but it seems to be restricted to two Dell 2491 * laptops. 2492 */ 2493 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2494 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2495 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2496 return NVME_QUIRK_NO_DEEPEST_PS; 2497 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 2498 /* 2499 * Samsung SSD 960 EVO drops off the PCIe bus after system 2500 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2501 * within few minutes after bootup on a Coffee Lake board - 2502 * ASUS PRIME Z370-A 2503 */ 2504 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2505 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2506 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 2507 return NVME_QUIRK_NO_APST; 2508 } 2509 2510 return 0; 2511 } 2512 2513 static void nvme_async_probe(void *data, async_cookie_t cookie) 2514 { 2515 struct nvme_dev *dev = data; 2516 2517 nvme_reset_ctrl_sync(&dev->ctrl); 2518 flush_work(&dev->ctrl.scan_work); 2519 nvme_put_ctrl(&dev->ctrl); 2520 } 2521 2522 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2523 { 2524 int node, result = -ENOMEM; 2525 struct nvme_dev *dev; 2526 unsigned long quirks = id->driver_data; 2527 2528 node = dev_to_node(&pdev->dev); 2529 if (node == NUMA_NO_NODE) 2530 set_dev_node(&pdev->dev, first_memory_node); 2531 2532 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2533 if (!dev) 2534 return -ENOMEM; 2535 2536 dev->queues = kcalloc_node(num_possible_cpus() + 1, 2537 sizeof(struct nvme_queue), GFP_KERNEL, node); 2538 if (!dev->queues) 2539 goto free; 2540 2541 dev->dev = get_device(&pdev->dev); 2542 pci_set_drvdata(pdev, dev); 2543 2544 result = nvme_dev_map(dev); 2545 if (result) 2546 goto put_pci; 2547 2548 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 2549 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 2550 mutex_init(&dev->shutdown_lock); 2551 init_completion(&dev->ioq_wait); 2552 2553 result = nvme_setup_prp_pools(dev); 2554 if (result) 2555 goto unmap; 2556 2557 quirks |= check_vendor_combination_bug(pdev); 2558 2559 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2560 quirks); 2561 if (result) 2562 goto release_pools; 2563 2564 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 2565 2566 nvme_get_ctrl(&dev->ctrl); 2567 async_schedule(nvme_async_probe, dev); 2568 2569 return 0; 2570 2571 release_pools: 2572 nvme_release_prp_pools(dev); 2573 unmap: 2574 nvme_dev_unmap(dev); 2575 put_pci: 2576 put_device(dev->dev); 2577 free: 2578 kfree(dev->queues); 2579 kfree(dev); 2580 return result; 2581 } 2582 2583 static void nvme_reset_prepare(struct pci_dev *pdev) 2584 { 2585 struct nvme_dev *dev = pci_get_drvdata(pdev); 2586 nvme_dev_disable(dev, false); 2587 } 2588 2589 static void nvme_reset_done(struct pci_dev *pdev) 2590 { 2591 struct nvme_dev *dev = pci_get_drvdata(pdev); 2592 nvme_reset_ctrl_sync(&dev->ctrl); 2593 } 2594 2595 static void nvme_shutdown(struct pci_dev *pdev) 2596 { 2597 struct nvme_dev *dev = pci_get_drvdata(pdev); 2598 nvme_dev_disable(dev, true); 2599 } 2600 2601 /* 2602 * The driver's remove may be called on a device in a partially initialized 2603 * state. This function must not have any dependencies on the device state in 2604 * order to proceed. 2605 */ 2606 static void nvme_remove(struct pci_dev *pdev) 2607 { 2608 struct nvme_dev *dev = pci_get_drvdata(pdev); 2609 2610 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2611 2612 cancel_work_sync(&dev->ctrl.reset_work); 2613 pci_set_drvdata(pdev, NULL); 2614 2615 if (!pci_device_is_present(pdev)) { 2616 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 2617 nvme_dev_disable(dev, false); 2618 } 2619 2620 flush_work(&dev->ctrl.reset_work); 2621 nvme_stop_ctrl(&dev->ctrl); 2622 nvme_remove_namespaces(&dev->ctrl); 2623 nvme_dev_disable(dev, true); 2624 nvme_free_host_mem(dev); 2625 nvme_dev_remove_admin(dev); 2626 nvme_free_queues(dev, 0); 2627 nvme_uninit_ctrl(&dev->ctrl); 2628 nvme_release_prp_pools(dev); 2629 nvme_dev_unmap(dev); 2630 nvme_put_ctrl(&dev->ctrl); 2631 } 2632 2633 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) 2634 { 2635 int ret = 0; 2636 2637 if (numvfs == 0) { 2638 if (pci_vfs_assigned(pdev)) { 2639 dev_warn(&pdev->dev, 2640 "Cannot disable SR-IOV VFs while assigned\n"); 2641 return -EPERM; 2642 } 2643 pci_disable_sriov(pdev); 2644 return 0; 2645 } 2646 2647 ret = pci_enable_sriov(pdev, numvfs); 2648 return ret ? ret : numvfs; 2649 } 2650 2651 #ifdef CONFIG_PM_SLEEP 2652 static int nvme_suspend(struct device *dev) 2653 { 2654 struct pci_dev *pdev = to_pci_dev(dev); 2655 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2656 2657 nvme_dev_disable(ndev, true); 2658 return 0; 2659 } 2660 2661 static int nvme_resume(struct device *dev) 2662 { 2663 struct pci_dev *pdev = to_pci_dev(dev); 2664 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2665 2666 nvme_reset_ctrl(&ndev->ctrl); 2667 return 0; 2668 } 2669 #endif 2670 2671 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 2672 2673 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2674 pci_channel_state_t state) 2675 { 2676 struct nvme_dev *dev = pci_get_drvdata(pdev); 2677 2678 /* 2679 * A frozen channel requires a reset. When detected, this method will 2680 * shutdown the controller to quiesce. The controller will be restarted 2681 * after the slot reset through driver's slot_reset callback. 2682 */ 2683 switch (state) { 2684 case pci_channel_io_normal: 2685 return PCI_ERS_RESULT_CAN_RECOVER; 2686 case pci_channel_io_frozen: 2687 dev_warn(dev->ctrl.device, 2688 "frozen state error detected, reset controller\n"); 2689 nvme_dev_disable(dev, false); 2690 return PCI_ERS_RESULT_NEED_RESET; 2691 case pci_channel_io_perm_failure: 2692 dev_warn(dev->ctrl.device, 2693 "failure state error detected, request disconnect\n"); 2694 return PCI_ERS_RESULT_DISCONNECT; 2695 } 2696 return PCI_ERS_RESULT_NEED_RESET; 2697 } 2698 2699 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2700 { 2701 struct nvme_dev *dev = pci_get_drvdata(pdev); 2702 2703 dev_info(dev->ctrl.device, "restart after slot reset\n"); 2704 pci_restore_state(pdev); 2705 nvme_reset_ctrl(&dev->ctrl); 2706 return PCI_ERS_RESULT_RECOVERED; 2707 } 2708 2709 static void nvme_error_resume(struct pci_dev *pdev) 2710 { 2711 struct nvme_dev *dev = pci_get_drvdata(pdev); 2712 2713 flush_work(&dev->ctrl.reset_work); 2714 pci_cleanup_aer_uncorrect_error_status(pdev); 2715 } 2716 2717 static const struct pci_error_handlers nvme_err_handler = { 2718 .error_detected = nvme_error_detected, 2719 .slot_reset = nvme_slot_reset, 2720 .resume = nvme_error_resume, 2721 .reset_prepare = nvme_reset_prepare, 2722 .reset_done = nvme_reset_done, 2723 }; 2724 2725 static const struct pci_device_id nvme_id_table[] = { 2726 { PCI_VDEVICE(INTEL, 0x0953), 2727 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2728 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2729 { PCI_VDEVICE(INTEL, 0x0a53), 2730 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2731 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2732 { PCI_VDEVICE(INTEL, 0x0a54), 2733 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2734 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2735 { PCI_VDEVICE(INTEL, 0x0a55), 2736 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2737 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2738 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 2739 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 2740 NVME_QUIRK_MEDIUM_PRIO_SQ }, 2741 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2742 .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 2743 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 2744 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2745 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 2746 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2747 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 2748 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2749 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2750 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2751 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2752 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2753 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2754 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2755 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2756 .driver_data = NVME_QUIRK_LIGHTNVM, }, 2757 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2758 .driver_data = NVME_QUIRK_LIGHTNVM, }, 2759 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 2760 .driver_data = NVME_QUIRK_LIGHTNVM, }, 2761 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2762 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2763 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 2764 { 0, } 2765 }; 2766 MODULE_DEVICE_TABLE(pci, nvme_id_table); 2767 2768 static struct pci_driver nvme_driver = { 2769 .name = "nvme", 2770 .id_table = nvme_id_table, 2771 .probe = nvme_probe, 2772 .remove = nvme_remove, 2773 .shutdown = nvme_shutdown, 2774 .driver = { 2775 .pm = &nvme_dev_pm_ops, 2776 }, 2777 .sriov_configure = nvme_pci_sriov_configure, 2778 .err_handler = &nvme_err_handler, 2779 }; 2780 2781 static int __init nvme_init(void) 2782 { 2783 return pci_register_driver(&nvme_driver); 2784 } 2785 2786 static void __exit nvme_exit(void) 2787 { 2788 pci_unregister_driver(&nvme_driver); 2789 flush_workqueue(nvme_wq); 2790 _nvme_check_size(); 2791 } 2792 2793 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 2794 MODULE_LICENSE("GPL"); 2795 MODULE_VERSION("1.0"); 2796 module_init(nvme_init); 2797 module_exit(nvme_exit); 2798