1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include "core.h" 8 #include "dp_tx.h" 9 #include "debug.h" 10 #include "hw.h" 11 12 static enum hal_tcl_encap_type 13 ath12k_dp_tx_get_encap_type(struct ath12k_vif *arvif, struct sk_buff *skb) 14 { 15 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 16 struct ath12k_base *ab = arvif->ar->ab; 17 18 if (test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) 19 return HAL_TCL_ENCAP_TYPE_RAW; 20 21 if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) 22 return HAL_TCL_ENCAP_TYPE_ETHERNET; 23 24 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI; 25 } 26 27 static void ath12k_dp_tx_encap_nwifi(struct sk_buff *skb) 28 { 29 struct ieee80211_hdr *hdr = (void *)skb->data; 30 u8 *qos_ctl; 31 32 if (!ieee80211_is_data_qos(hdr->frame_control)) 33 return; 34 35 qos_ctl = ieee80211_get_qos_ctl(hdr); 36 memmove(skb->data + IEEE80211_QOS_CTL_LEN, 37 skb->data, (void *)qos_ctl - (void *)skb->data); 38 skb_pull(skb, IEEE80211_QOS_CTL_LEN); 39 40 hdr = (void *)skb->data; 41 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 42 } 43 44 static u8 ath12k_dp_tx_get_tid(struct sk_buff *skb) 45 { 46 struct ieee80211_hdr *hdr = (void *)skb->data; 47 struct ath12k_skb_cb *cb = ATH12K_SKB_CB(skb); 48 49 if (cb->flags & ATH12K_SKB_HW_80211_ENCAP) 50 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 51 else if (!ieee80211_is_data_qos(hdr->frame_control)) 52 return HAL_DESC_REO_NON_QOS_TID; 53 else 54 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 55 } 56 57 enum hal_encrypt_type ath12k_dp_tx_get_encrypt_type(u32 cipher) 58 { 59 switch (cipher) { 60 case WLAN_CIPHER_SUITE_WEP40: 61 return HAL_ENCRYPT_TYPE_WEP_40; 62 case WLAN_CIPHER_SUITE_WEP104: 63 return HAL_ENCRYPT_TYPE_WEP_104; 64 case WLAN_CIPHER_SUITE_TKIP: 65 return HAL_ENCRYPT_TYPE_TKIP_MIC; 66 case WLAN_CIPHER_SUITE_CCMP: 67 return HAL_ENCRYPT_TYPE_CCMP_128; 68 case WLAN_CIPHER_SUITE_CCMP_256: 69 return HAL_ENCRYPT_TYPE_CCMP_256; 70 case WLAN_CIPHER_SUITE_GCMP: 71 return HAL_ENCRYPT_TYPE_GCMP_128; 72 case WLAN_CIPHER_SUITE_GCMP_256: 73 return HAL_ENCRYPT_TYPE_AES_GCMP_256; 74 default: 75 return HAL_ENCRYPT_TYPE_OPEN; 76 } 77 } 78 79 static void ath12k_dp_tx_release_txbuf(struct ath12k_dp *dp, 80 struct ath12k_tx_desc_info *tx_desc, 81 u8 pool_id) 82 { 83 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 84 list_move_tail(&tx_desc->list, &dp->tx_desc_free_list[pool_id]); 85 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 86 } 87 88 static struct ath12k_tx_desc_info *ath12k_dp_tx_assign_buffer(struct ath12k_dp *dp, 89 u8 pool_id) 90 { 91 struct ath12k_tx_desc_info *desc; 92 93 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 94 desc = list_first_entry_or_null(&dp->tx_desc_free_list[pool_id], 95 struct ath12k_tx_desc_info, 96 list); 97 if (!desc) { 98 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 99 ath12k_warn(dp->ab, "failed to allocate data Tx buffer\n"); 100 return NULL; 101 } 102 103 list_move_tail(&desc->list, &dp->tx_desc_used_list[pool_id]); 104 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 105 106 return desc; 107 } 108 109 static void ath12k_hal_tx_cmd_ext_desc_setup(struct ath12k_base *ab, 110 struct hal_tx_msdu_ext_desc *tcl_ext_cmd, 111 struct hal_tx_info *ti) 112 { 113 tcl_ext_cmd->info0 = le32_encode_bits(ti->paddr, 114 HAL_TX_MSDU_EXT_INFO0_BUF_PTR_LO); 115 tcl_ext_cmd->info1 = le32_encode_bits(0x0, 116 HAL_TX_MSDU_EXT_INFO1_BUF_PTR_HI) | 117 le32_encode_bits(ti->data_len, 118 HAL_TX_MSDU_EXT_INFO1_BUF_LEN); 119 120 tcl_ext_cmd->info1 = le32_encode_bits(1, HAL_TX_MSDU_EXT_INFO1_EXTN_OVERRIDE) | 121 le32_encode_bits(ti->encap_type, 122 HAL_TX_MSDU_EXT_INFO1_ENCAP_TYPE) | 123 le32_encode_bits(ti->encrypt_type, 124 HAL_TX_MSDU_EXT_INFO1_ENCRYPT_TYPE); 125 } 126 127 #define HTT_META_DATA_ALIGNMENT 0x8 128 129 static void *ath12k_dp_metadata_align_skb(struct sk_buff *skb, u8 tail_len) 130 { 131 struct sk_buff *tail; 132 void *metadata; 133 134 if (unlikely(skb_cow_data(skb, tail_len, &tail) < 0)) 135 return NULL; 136 137 metadata = pskb_put(skb, tail, tail_len); 138 memset(metadata, 0, tail_len); 139 return metadata; 140 } 141 142 /* Preparing HTT Metadata when utilized with ext MSDU */ 143 static int ath12k_dp_prepare_htt_metadata(struct sk_buff *skb) 144 { 145 struct hal_tx_msdu_metadata *desc_ext; 146 u8 htt_desc_size; 147 /* Size rounded of multiple of 8 bytes */ 148 u8 htt_desc_size_aligned; 149 150 htt_desc_size = sizeof(struct hal_tx_msdu_metadata); 151 htt_desc_size_aligned = ALIGN(htt_desc_size, HTT_META_DATA_ALIGNMENT); 152 153 desc_ext = ath12k_dp_metadata_align_skb(skb, htt_desc_size_aligned); 154 if (!desc_ext) 155 return -ENOMEM; 156 157 desc_ext->info0 = le32_encode_bits(1, HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_FLAG) | 158 le32_encode_bits(0, HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_TYPE) | 159 le32_encode_bits(1, 160 HAL_TX_MSDU_METADATA_INFO0_HOST_TX_DESC_POOL); 161 162 return 0; 163 } 164 165 int ath12k_dp_tx(struct ath12k *ar, struct ath12k_vif *arvif, 166 struct sk_buff *skb) 167 { 168 struct ath12k_base *ab = ar->ab; 169 struct ath12k_dp *dp = &ab->dp; 170 struct hal_tx_info ti = {0}; 171 struct ath12k_tx_desc_info *tx_desc; 172 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 173 struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB(skb); 174 struct hal_tcl_data_cmd *hal_tcl_desc; 175 struct hal_tx_msdu_ext_desc *msg; 176 struct sk_buff *skb_ext_desc; 177 struct hal_srng *tcl_ring; 178 struct ieee80211_hdr *hdr = (void *)skb->data; 179 struct dp_tx_ring *tx_ring; 180 u8 pool_id; 181 u8 hal_ring_id; 182 int ret; 183 u8 ring_selector, ring_map = 0; 184 bool tcl_ring_retry; 185 bool msdu_ext_desc = false; 186 bool add_htt_metadata = false; 187 188 if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) 189 return -ESHUTDOWN; 190 191 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 192 !ieee80211_is_data(hdr->frame_control)) 193 return -EOPNOTSUPP; 194 195 pool_id = skb_get_queue_mapping(skb) & (ATH12K_HW_MAX_QUEUES - 1); 196 197 /* Let the default ring selection be based on current processor 198 * number, where one of the 3 tcl rings are selected based on 199 * the smp_processor_id(). In case that ring 200 * is full/busy, we resort to other available rings. 201 * If all rings are full, we drop the packet. 202 * TODO: Add throttling logic when all rings are full 203 */ 204 ring_selector = ab->hw_params->hw_ops->get_ring_selector(skb); 205 206 tcl_ring_sel: 207 tcl_ring_retry = false; 208 ti.ring_id = ring_selector % ab->hw_params->max_tx_ring; 209 210 ring_map |= BIT(ti.ring_id); 211 ti.rbm_id = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map[ti.ring_id].rbm_id; 212 213 tx_ring = &dp->tx_ring[ti.ring_id]; 214 215 tx_desc = ath12k_dp_tx_assign_buffer(dp, pool_id); 216 if (!tx_desc) 217 return -ENOMEM; 218 219 ti.bank_id = arvif->bank_id; 220 ti.meta_data_flags = arvif->tcl_metadata; 221 222 if (arvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW && 223 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags)) { 224 if (skb_cb->flags & ATH12K_SKB_CIPHER_SET) { 225 ti.encrypt_type = 226 ath12k_dp_tx_get_encrypt_type(skb_cb->cipher); 227 228 if (ieee80211_has_protected(hdr->frame_control)) 229 skb_put(skb, IEEE80211_CCMP_MIC_LEN); 230 } else { 231 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 232 } 233 234 msdu_ext_desc = true; 235 } 236 237 ti.encap_type = ath12k_dp_tx_get_encap_type(arvif, skb); 238 ti.addr_search_flags = arvif->hal_addr_search_flags; 239 ti.search_type = arvif->search_type; 240 ti.type = HAL_TCL_DESC_TYPE_BUFFER; 241 ti.pkt_offset = 0; 242 ti.lmac_id = ar->lmac_id; 243 ti.vdev_id = arvif->vdev_id; 244 ti.bss_ast_hash = arvif->ast_hash; 245 ti.bss_ast_idx = arvif->ast_idx; 246 ti.dscp_tid_tbl_idx = 0; 247 248 if (skb->ip_summed == CHECKSUM_PARTIAL && 249 ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW) { 250 ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_IP4_CKSUM_EN) | 251 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP4_CKSUM_EN) | 252 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP6_CKSUM_EN) | 253 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP4_CKSUM_EN) | 254 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP6_CKSUM_EN); 255 } 256 257 ti.flags1 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE); 258 259 ti.tid = ath12k_dp_tx_get_tid(skb); 260 261 switch (ti.encap_type) { 262 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: 263 ath12k_dp_tx_encap_nwifi(skb); 264 break; 265 case HAL_TCL_ENCAP_TYPE_RAW: 266 if (!test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) { 267 ret = -EINVAL; 268 goto fail_remove_tx_buf; 269 } 270 break; 271 case HAL_TCL_ENCAP_TYPE_ETHERNET: 272 /* no need to encap */ 273 break; 274 case HAL_TCL_ENCAP_TYPE_802_3: 275 default: 276 /* TODO: Take care of other encap modes as well */ 277 ret = -EINVAL; 278 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 279 goto fail_remove_tx_buf; 280 } 281 282 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); 283 if (dma_mapping_error(ab->dev, ti.paddr)) { 284 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 285 ath12k_warn(ab, "failed to DMA map data Tx buffer\n"); 286 ret = -ENOMEM; 287 goto fail_remove_tx_buf; 288 } 289 290 if (!test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags) && 291 !(skb_cb->flags & ATH12K_SKB_HW_80211_ENCAP) && 292 !(skb_cb->flags & ATH12K_SKB_CIPHER_SET) && 293 ieee80211_has_protected(hdr->frame_control)) { 294 /* Add metadata for sw encrypted vlan group traffic */ 295 add_htt_metadata = true; 296 msdu_ext_desc = true; 297 ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TO_FW); 298 ti.encap_type = HAL_TCL_ENCAP_TYPE_RAW; 299 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 300 } 301 302 tx_desc->skb = skb; 303 tx_desc->mac_id = ar->pdev_idx; 304 ti.desc_id = tx_desc->desc_id; 305 ti.data_len = skb->len; 306 skb_cb->paddr = ti.paddr; 307 skb_cb->vif = arvif->vif; 308 skb_cb->ar = ar; 309 310 if (msdu_ext_desc) { 311 skb_ext_desc = dev_alloc_skb(sizeof(struct hal_tx_msdu_ext_desc)); 312 if (!skb_ext_desc) { 313 ret = -ENOMEM; 314 goto fail_unmap_dma; 315 } 316 317 skb_put(skb_ext_desc, sizeof(struct hal_tx_msdu_ext_desc)); 318 memset(skb_ext_desc->data, 0, skb_ext_desc->len); 319 320 msg = (struct hal_tx_msdu_ext_desc *)skb_ext_desc->data; 321 ath12k_hal_tx_cmd_ext_desc_setup(ab, msg, &ti); 322 323 if (add_htt_metadata) { 324 ret = ath12k_dp_prepare_htt_metadata(skb_ext_desc); 325 if (ret < 0) { 326 ath12k_dbg(ab, ATH12K_DBG_DP_TX, 327 "Failed to add HTT meta data, dropping packet\n"); 328 goto fail_unmap_dma; 329 } 330 } 331 332 ti.paddr = dma_map_single(ab->dev, skb_ext_desc->data, 333 skb_ext_desc->len, DMA_TO_DEVICE); 334 ret = dma_mapping_error(ab->dev, ti.paddr); 335 if (ret) { 336 kfree_skb(skb_ext_desc); 337 goto fail_unmap_dma; 338 } 339 340 ti.data_len = skb_ext_desc->len; 341 ti.type = HAL_TCL_DESC_TYPE_EXT_DESC; 342 343 skb_cb->paddr_ext_desc = ti.paddr; 344 } 345 346 hal_ring_id = tx_ring->tcl_data_ring.ring_id; 347 tcl_ring = &ab->hal.srng_list[hal_ring_id]; 348 349 spin_lock_bh(&tcl_ring->lock); 350 351 ath12k_hal_srng_access_begin(ab, tcl_ring); 352 353 hal_tcl_desc = ath12k_hal_srng_src_get_next_entry(ab, tcl_ring); 354 if (!hal_tcl_desc) { 355 /* NOTE: It is highly unlikely we'll be running out of tcl_ring 356 * desc because the desc is directly enqueued onto hw queue. 357 */ 358 ath12k_hal_srng_access_end(ab, tcl_ring); 359 ab->soc_stats.tx_err.desc_na[ti.ring_id]++; 360 spin_unlock_bh(&tcl_ring->lock); 361 ret = -ENOMEM; 362 363 /* Checking for available tcl descriptors in another ring in 364 * case of failure due to full tcl ring now, is better than 365 * checking this ring earlier for each pkt tx. 366 * Restart ring selection if some rings are not checked yet. 367 */ 368 if (ring_map != (BIT(ab->hw_params->max_tx_ring) - 1) && 369 ab->hw_params->tcl_ring_retry) { 370 tcl_ring_retry = true; 371 ring_selector++; 372 } 373 374 goto fail_unmap_dma; 375 } 376 377 ath12k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc, &ti); 378 379 ath12k_hal_srng_access_end(ab, tcl_ring); 380 381 spin_unlock_bh(&tcl_ring->lock); 382 383 ath12k_dbg_dump(ab, ATH12K_DBG_DP_TX, NULL, "dp tx msdu: ", 384 skb->data, skb->len); 385 386 atomic_inc(&ar->dp.num_tx_pending); 387 388 return 0; 389 390 fail_unmap_dma: 391 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); 392 393 if (skb_cb->paddr_ext_desc) 394 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 395 sizeof(struct hal_tx_msdu_ext_desc), 396 DMA_TO_DEVICE); 397 398 fail_remove_tx_buf: 399 ath12k_dp_tx_release_txbuf(dp, tx_desc, pool_id); 400 if (tcl_ring_retry) 401 goto tcl_ring_sel; 402 403 return ret; 404 } 405 406 static void ath12k_dp_tx_free_txbuf(struct ath12k_base *ab, 407 struct sk_buff *msdu, u8 mac_id, 408 struct dp_tx_ring *tx_ring) 409 { 410 struct ath12k *ar; 411 struct ath12k_skb_cb *skb_cb; 412 u8 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 413 414 skb_cb = ATH12K_SKB_CB(msdu); 415 ar = ab->pdevs[pdev_id].ar; 416 417 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 418 if (skb_cb->paddr_ext_desc) 419 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 420 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); 421 422 ieee80211_free_txskb(ar->ah->hw, msdu); 423 424 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 425 wake_up(&ar->dp.tx_empty_waitq); 426 } 427 428 static void 429 ath12k_dp_tx_htt_tx_complete_buf(struct ath12k_base *ab, 430 struct sk_buff *msdu, 431 struct dp_tx_ring *tx_ring, 432 struct ath12k_dp_htt_wbm_tx_status *ts) 433 { 434 struct ieee80211_tx_info *info; 435 struct ath12k_skb_cb *skb_cb; 436 struct ath12k *ar; 437 438 skb_cb = ATH12K_SKB_CB(msdu); 439 info = IEEE80211_SKB_CB(msdu); 440 441 ar = skb_cb->ar; 442 443 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 444 wake_up(&ar->dp.tx_empty_waitq); 445 446 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 447 if (skb_cb->paddr_ext_desc) 448 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 449 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); 450 451 memset(&info->status, 0, sizeof(info->status)); 452 453 if (ts->acked) { 454 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 455 info->flags |= IEEE80211_TX_STAT_ACK; 456 info->status.ack_signal = ts->ack_rssi; 457 458 if (!test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT, 459 ab->wmi_ab.svc_map)) 460 info->status.ack_signal += ATH12K_DEFAULT_NOISE_FLOOR; 461 462 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; 463 } else { 464 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 465 } 466 } 467 468 ieee80211_tx_status_skb(ath12k_ar_to_hw(ar), msdu); 469 } 470 471 static void 472 ath12k_dp_tx_process_htt_tx_complete(struct ath12k_base *ab, 473 void *desc, u8 mac_id, 474 struct sk_buff *msdu, 475 struct dp_tx_ring *tx_ring) 476 { 477 struct htt_tx_wbm_completion *status_desc; 478 struct ath12k_dp_htt_wbm_tx_status ts = {0}; 479 enum hal_wbm_htt_tx_comp_status wbm_status; 480 481 status_desc = desc; 482 483 wbm_status = le32_get_bits(status_desc->info0, 484 HTT_TX_WBM_COMP_INFO0_STATUS); 485 486 switch (wbm_status) { 487 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: 488 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: 489 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: 490 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); 491 ts.ack_rssi = le32_get_bits(status_desc->info2, 492 HTT_TX_WBM_COMP_INFO2_ACK_RSSI); 493 ath12k_dp_tx_htt_tx_complete_buf(ab, msdu, tx_ring, &ts); 494 break; 495 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: 496 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: 497 ath12k_dp_tx_free_txbuf(ab, msdu, mac_id, tx_ring); 498 break; 499 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: 500 /* This event is to be handled only when the driver decides to 501 * use WDS offload functionality. 502 */ 503 break; 504 default: 505 ath12k_warn(ab, "Unknown htt tx status %d\n", wbm_status); 506 break; 507 } 508 } 509 510 static void ath12k_dp_tx_complete_msdu(struct ath12k *ar, 511 struct sk_buff *msdu, 512 struct hal_tx_status *ts) 513 { 514 struct ath12k_base *ab = ar->ab; 515 struct ath12k_hw *ah = ar->ah; 516 struct ieee80211_tx_info *info; 517 struct ath12k_skb_cb *skb_cb; 518 519 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { 520 /* Must not happen */ 521 return; 522 } 523 524 skb_cb = ATH12K_SKB_CB(msdu); 525 526 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 527 if (skb_cb->paddr_ext_desc) 528 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 529 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); 530 531 rcu_read_lock(); 532 533 if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) { 534 ieee80211_free_txskb(ah->hw, msdu); 535 goto exit; 536 } 537 538 if (!skb_cb->vif) { 539 ieee80211_free_txskb(ah->hw, msdu); 540 goto exit; 541 } 542 543 info = IEEE80211_SKB_CB(msdu); 544 memset(&info->status, 0, sizeof(info->status)); 545 546 /* skip tx rate update from ieee80211_status*/ 547 info->status.rates[0].idx = -1; 548 549 switch (ts->status) { 550 case HAL_WBM_TQM_REL_REASON_FRAME_ACKED: 551 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 552 info->flags |= IEEE80211_TX_STAT_ACK; 553 info->status.ack_signal = ts->ack_rssi; 554 555 if (!test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT, 556 ab->wmi_ab.svc_map)) 557 info->status.ack_signal += ATH12K_DEFAULT_NOISE_FLOOR; 558 559 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; 560 } 561 break; 562 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: 563 if (info->flags & IEEE80211_TX_CTL_NO_ACK) { 564 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 565 break; 566 } 567 fallthrough; 568 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: 569 case HAL_WBM_TQM_REL_REASON_DROP_THRESHOLD: 570 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: 571 /* The failure status is due to internal firmware tx failure 572 * hence drop the frame; do not update the status of frame to 573 * the upper layer 574 */ 575 ieee80211_free_txskb(ah->hw, msdu); 576 goto exit; 577 default: 578 ath12k_dbg(ab, ATH12K_DBG_DP_TX, "tx frame is not acked status %d\n", 579 ts->status); 580 break; 581 } 582 583 /* NOTE: Tx rate status reporting. Tx completion status does not have 584 * necessary information (for example nss) to build the tx rate. 585 * Might end up reporting it out-of-band from HTT stats. 586 */ 587 588 ieee80211_tx_status_skb(ath12k_ar_to_hw(ar), msdu); 589 590 exit: 591 rcu_read_unlock(); 592 } 593 594 static void ath12k_dp_tx_status_parse(struct ath12k_base *ab, 595 struct hal_wbm_completion_ring_tx *desc, 596 struct hal_tx_status *ts) 597 { 598 ts->buf_rel_source = 599 le32_get_bits(desc->info0, HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE); 600 if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && 601 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM) 602 return; 603 604 if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) 605 return; 606 607 ts->status = le32_get_bits(desc->info0, 608 HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON); 609 610 ts->ppdu_id = le32_get_bits(desc->info1, 611 HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER); 612 if (le32_to_cpu(desc->rate_stats.info0) & HAL_TX_RATE_STATS_INFO0_VALID) 613 ts->rate_stats = le32_to_cpu(desc->rate_stats.info0); 614 else 615 ts->rate_stats = 0; 616 } 617 618 void ath12k_dp_tx_completion_handler(struct ath12k_base *ab, int ring_id) 619 { 620 struct ath12k *ar; 621 struct ath12k_dp *dp = &ab->dp; 622 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; 623 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; 624 struct ath12k_tx_desc_info *tx_desc = NULL; 625 struct sk_buff *msdu; 626 struct hal_tx_status ts = { 0 }; 627 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; 628 struct hal_wbm_release_ring *desc; 629 u8 mac_id, pdev_id; 630 u64 desc_va; 631 632 spin_lock_bh(&status_ring->lock); 633 634 ath12k_hal_srng_access_begin(ab, status_ring); 635 636 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) != tx_ring->tx_status_tail) { 637 desc = ath12k_hal_srng_dst_get_next_entry(ab, status_ring); 638 if (!desc) 639 break; 640 641 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head], 642 desc, sizeof(*desc)); 643 tx_ring->tx_status_head = 644 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head); 645 } 646 647 if (ath12k_hal_srng_dst_peek(ab, status_ring) && 648 (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) { 649 /* TODO: Process pending tx_status messages when kfifo_is_full() */ 650 ath12k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); 651 } 652 653 ath12k_hal_srng_access_end(ab, status_ring); 654 655 spin_unlock_bh(&status_ring->lock); 656 657 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) { 658 struct hal_wbm_completion_ring_tx *tx_status; 659 u32 desc_id; 660 661 tx_ring->tx_status_tail = 662 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail); 663 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail]; 664 ath12k_dp_tx_status_parse(ab, tx_status, &ts); 665 666 if (le32_get_bits(tx_status->info0, HAL_WBM_COMPL_TX_INFO0_CC_DONE)) { 667 /* HW done cookie conversion */ 668 desc_va = ((u64)le32_to_cpu(tx_status->buf_va_hi) << 32 | 669 le32_to_cpu(tx_status->buf_va_lo)); 670 tx_desc = (struct ath12k_tx_desc_info *)((unsigned long)desc_va); 671 } else { 672 /* SW does cookie conversion to VA */ 673 desc_id = le32_get_bits(tx_status->buf_va_hi, 674 BUFFER_ADDR_INFO1_SW_COOKIE); 675 676 tx_desc = ath12k_dp_get_tx_desc(ab, desc_id); 677 } 678 if (!tx_desc) { 679 ath12k_warn(ab, "unable to retrieve tx_desc!"); 680 continue; 681 } 682 683 msdu = tx_desc->skb; 684 mac_id = tx_desc->mac_id; 685 686 /* Release descriptor as soon as extracting necessary info 687 * to reduce contention 688 */ 689 ath12k_dp_tx_release_txbuf(dp, tx_desc, tx_desc->pool_id); 690 if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) { 691 ath12k_dp_tx_process_htt_tx_complete(ab, 692 (void *)tx_status, 693 mac_id, msdu, 694 tx_ring); 695 continue; 696 } 697 698 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 699 ar = ab->pdevs[pdev_id].ar; 700 701 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 702 wake_up(&ar->dp.tx_empty_waitq); 703 704 ath12k_dp_tx_complete_msdu(ar, msdu, &ts); 705 } 706 } 707 708 static int 709 ath12k_dp_tx_get_ring_id_type(struct ath12k_base *ab, 710 int mac_id, u32 ring_id, 711 enum hal_ring_type ring_type, 712 enum htt_srng_ring_type *htt_ring_type, 713 enum htt_srng_ring_id *htt_ring_id) 714 { 715 int ret = 0; 716 717 switch (ring_type) { 718 case HAL_RXDMA_BUF: 719 /* for some targets, host fills rx buffer to fw and fw fills to 720 * rxbuf ring for each rxdma 721 */ 722 if (!ab->hw_params->rx_mac_buf_ring) { 723 if (!(ring_id == HAL_SRNG_SW2RXDMA_BUF0 || 724 ring_id == HAL_SRNG_SW2RXDMA_BUF1)) { 725 ret = -EINVAL; 726 } 727 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 728 *htt_ring_type = HTT_SW_TO_HW_RING; 729 } else { 730 if (ring_id == HAL_SRNG_SW2RXDMA_BUF0) { 731 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING; 732 *htt_ring_type = HTT_SW_TO_SW_RING; 733 } else { 734 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 735 *htt_ring_type = HTT_SW_TO_HW_RING; 736 } 737 } 738 break; 739 case HAL_RXDMA_DST: 740 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING; 741 *htt_ring_type = HTT_HW_TO_SW_RING; 742 break; 743 case HAL_RXDMA_MONITOR_BUF: 744 *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING; 745 *htt_ring_type = HTT_SW_TO_HW_RING; 746 break; 747 case HAL_RXDMA_MONITOR_STATUS: 748 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING; 749 *htt_ring_type = HTT_SW_TO_HW_RING; 750 break; 751 case HAL_RXDMA_MONITOR_DST: 752 *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING; 753 *htt_ring_type = HTT_HW_TO_SW_RING; 754 break; 755 case HAL_RXDMA_MONITOR_DESC: 756 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING; 757 *htt_ring_type = HTT_SW_TO_HW_RING; 758 break; 759 default: 760 ath12k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type); 761 ret = -EINVAL; 762 } 763 return ret; 764 } 765 766 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id, 767 int mac_id, enum hal_ring_type ring_type) 768 { 769 struct htt_srng_setup_cmd *cmd; 770 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 771 struct hal_srng_params params; 772 struct sk_buff *skb; 773 u32 ring_entry_sz; 774 int len = sizeof(*cmd); 775 dma_addr_t hp_addr, tp_addr; 776 enum htt_srng_ring_type htt_ring_type; 777 enum htt_srng_ring_id htt_ring_id; 778 int ret; 779 780 skb = ath12k_htc_alloc_skb(ab, len); 781 if (!skb) 782 return -ENOMEM; 783 784 memset(¶ms, 0, sizeof(params)); 785 ath12k_hal_srng_get_params(ab, srng, ¶ms); 786 787 hp_addr = ath12k_hal_srng_get_hp_addr(ab, srng); 788 tp_addr = ath12k_hal_srng_get_tp_addr(ab, srng); 789 790 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 791 ring_type, &htt_ring_type, 792 &htt_ring_id); 793 if (ret) 794 goto err_free; 795 796 skb_put(skb, len); 797 cmd = (struct htt_srng_setup_cmd *)skb->data; 798 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_SRING_SETUP, 799 HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE); 800 if (htt_ring_type == HTT_SW_TO_HW_RING || 801 htt_ring_type == HTT_HW_TO_SW_RING) 802 cmd->info0 |= le32_encode_bits(DP_SW2HW_MACID(mac_id), 803 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID); 804 else 805 cmd->info0 |= le32_encode_bits(mac_id, 806 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID); 807 cmd->info0 |= le32_encode_bits(htt_ring_type, 808 HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE); 809 cmd->info0 |= le32_encode_bits(htt_ring_id, 810 HTT_SRNG_SETUP_CMD_INFO0_RING_ID); 811 812 cmd->ring_base_addr_lo = cpu_to_le32(params.ring_base_paddr & 813 HAL_ADDR_LSB_REG_MASK); 814 815 cmd->ring_base_addr_hi = cpu_to_le32((u64)params.ring_base_paddr >> 816 HAL_ADDR_MSB_REG_SHIFT); 817 818 ret = ath12k_hal_srng_get_entrysize(ab, ring_type); 819 if (ret < 0) 820 goto err_free; 821 822 ring_entry_sz = ret; 823 824 ring_entry_sz >>= 2; 825 cmd->info1 = le32_encode_bits(ring_entry_sz, 826 HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE); 827 cmd->info1 |= le32_encode_bits(params.num_entries * ring_entry_sz, 828 HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE); 829 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 830 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP); 831 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 832 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP); 833 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP), 834 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP); 835 if (htt_ring_type == HTT_SW_TO_HW_RING) 836 cmd->info1 |= cpu_to_le32(HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS); 837 838 cmd->ring_head_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(hp_addr)); 839 cmd->ring_head_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(hp_addr)); 840 841 cmd->ring_tail_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(tp_addr)); 842 cmd->ring_tail_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(tp_addr)); 843 844 cmd->ring_msi_addr_lo = cpu_to_le32(lower_32_bits(params.msi_addr)); 845 cmd->ring_msi_addr_hi = cpu_to_le32(upper_32_bits(params.msi_addr)); 846 cmd->msi_data = cpu_to_le32(params.msi_data); 847 848 cmd->intr_info = 849 le32_encode_bits(params.intr_batch_cntr_thres_entries * ring_entry_sz, 850 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH); 851 cmd->intr_info |= 852 le32_encode_bits(params.intr_timer_thres_us >> 3, 853 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH); 854 855 cmd->info2 = 0; 856 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 857 cmd->info2 = le32_encode_bits(params.low_threshold, 858 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH); 859 } 860 861 ath12k_dbg(ab, ATH12K_DBG_HAL, 862 "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n", 863 __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi, 864 cmd->msi_data); 865 866 ath12k_dbg(ab, ATH12K_DBG_HAL, 867 "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n", 868 ring_id, ring_type, cmd->intr_info, cmd->info2); 869 870 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 871 if (ret) 872 goto err_free; 873 874 return 0; 875 876 err_free: 877 dev_kfree_skb_any(skb); 878 879 return ret; 880 } 881 882 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ) 883 884 int ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base *ab) 885 { 886 struct ath12k_dp *dp = &ab->dp; 887 struct sk_buff *skb; 888 struct htt_ver_req_cmd *cmd; 889 int len = sizeof(*cmd); 890 int ret; 891 892 init_completion(&dp->htt_tgt_version_received); 893 894 skb = ath12k_htc_alloc_skb(ab, len); 895 if (!skb) 896 return -ENOMEM; 897 898 skb_put(skb, len); 899 cmd = (struct htt_ver_req_cmd *)skb->data; 900 cmd->ver_reg_info = le32_encode_bits(HTT_H2T_MSG_TYPE_VERSION_REQ, 901 HTT_VER_REQ_INFO_MSG_ID); 902 903 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 904 if (ret) { 905 dev_kfree_skb_any(skb); 906 return ret; 907 } 908 909 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received, 910 HTT_TARGET_VERSION_TIMEOUT_HZ); 911 if (ret == 0) { 912 ath12k_warn(ab, "htt target version request timed out\n"); 913 return -ETIMEDOUT; 914 } 915 916 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) { 917 ath12k_err(ab, "unsupported htt major version %d supported version is %d\n", 918 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR); 919 return -EOPNOTSUPP; 920 } 921 922 return 0; 923 } 924 925 int ath12k_dp_tx_htt_h2t_ppdu_stats_req(struct ath12k *ar, u32 mask) 926 { 927 struct ath12k_base *ab = ar->ab; 928 struct ath12k_dp *dp = &ab->dp; 929 struct sk_buff *skb; 930 struct htt_ppdu_stats_cfg_cmd *cmd; 931 int len = sizeof(*cmd); 932 u8 pdev_mask; 933 int ret; 934 int i; 935 936 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) { 937 skb = ath12k_htc_alloc_skb(ab, len); 938 if (!skb) 939 return -ENOMEM; 940 941 skb_put(skb, len); 942 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data; 943 cmd->msg = le32_encode_bits(HTT_H2T_MSG_TYPE_PPDU_STATS_CFG, 944 HTT_PPDU_STATS_CFG_MSG_TYPE); 945 946 pdev_mask = 1 << (i + 1); 947 cmd->msg |= le32_encode_bits(pdev_mask, HTT_PPDU_STATS_CFG_PDEV_ID); 948 cmd->msg |= le32_encode_bits(mask, HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK); 949 950 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 951 if (ret) { 952 dev_kfree_skb_any(skb); 953 return ret; 954 } 955 } 956 957 return 0; 958 } 959 960 int ath12k_dp_tx_htt_rx_filter_setup(struct ath12k_base *ab, u32 ring_id, 961 int mac_id, enum hal_ring_type ring_type, 962 int rx_buf_size, 963 struct htt_rx_ring_tlv_filter *tlv_filter) 964 { 965 struct htt_rx_ring_selection_cfg_cmd *cmd; 966 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 967 struct hal_srng_params params; 968 struct sk_buff *skb; 969 int len = sizeof(*cmd); 970 enum htt_srng_ring_type htt_ring_type; 971 enum htt_srng_ring_id htt_ring_id; 972 int ret; 973 974 skb = ath12k_htc_alloc_skb(ab, len); 975 if (!skb) 976 return -ENOMEM; 977 978 memset(¶ms, 0, sizeof(params)); 979 ath12k_hal_srng_get_params(ab, srng, ¶ms); 980 981 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 982 ring_type, &htt_ring_type, 983 &htt_ring_id); 984 if (ret) 985 goto err_free; 986 987 skb_put(skb, len); 988 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data; 989 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG, 990 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE); 991 if (htt_ring_type == HTT_SW_TO_HW_RING || 992 htt_ring_type == HTT_HW_TO_SW_RING) 993 cmd->info0 |= 994 le32_encode_bits(DP_SW2HW_MACID(mac_id), 995 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 996 else 997 cmd->info0 |= 998 le32_encode_bits(mac_id, 999 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1000 cmd->info0 |= le32_encode_bits(htt_ring_id, 1001 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID); 1002 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 1003 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS); 1004 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 1005 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS); 1006 cmd->info0 |= le32_encode_bits(tlv_filter->offset_valid, 1007 HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID); 1008 cmd->info1 = le32_encode_bits(rx_buf_size, 1009 HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE); 1010 cmd->pkt_type_en_flags0 = cpu_to_le32(tlv_filter->pkt_filter_flags0); 1011 cmd->pkt_type_en_flags1 = cpu_to_le32(tlv_filter->pkt_filter_flags1); 1012 cmd->pkt_type_en_flags2 = cpu_to_le32(tlv_filter->pkt_filter_flags2); 1013 cmd->pkt_type_en_flags3 = cpu_to_le32(tlv_filter->pkt_filter_flags3); 1014 cmd->rx_filter_tlv = cpu_to_le32(tlv_filter->rx_filter); 1015 1016 if (tlv_filter->offset_valid) { 1017 cmd->rx_packet_offset = 1018 le32_encode_bits(tlv_filter->rx_packet_offset, 1019 HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET); 1020 1021 cmd->rx_packet_offset |= 1022 le32_encode_bits(tlv_filter->rx_header_offset, 1023 HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET); 1024 1025 cmd->rx_mpdu_offset = 1026 le32_encode_bits(tlv_filter->rx_mpdu_end_offset, 1027 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET); 1028 1029 cmd->rx_mpdu_offset |= 1030 le32_encode_bits(tlv_filter->rx_mpdu_start_offset, 1031 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET); 1032 1033 cmd->rx_msdu_offset = 1034 le32_encode_bits(tlv_filter->rx_msdu_end_offset, 1035 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET); 1036 1037 cmd->rx_msdu_offset |= 1038 le32_encode_bits(tlv_filter->rx_msdu_start_offset, 1039 HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET); 1040 1041 cmd->rx_attn_offset = 1042 le32_encode_bits(tlv_filter->rx_attn_offset, 1043 HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET); 1044 } 1045 1046 if (tlv_filter->rx_mpdu_start_wmask > 0 && 1047 tlv_filter->rx_msdu_end_wmask > 0) { 1048 cmd->info2 |= 1049 le32_encode_bits(true, 1050 HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET); 1051 cmd->rx_mpdu_start_end_mask = 1052 le32_encode_bits(tlv_filter->rx_mpdu_start_wmask, 1053 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK); 1054 /* mpdu_end is not used for any hardwares so far 1055 * please assign it in future if any chip is 1056 * using through hal ops 1057 */ 1058 cmd->rx_mpdu_start_end_mask |= 1059 le32_encode_bits(tlv_filter->rx_mpdu_end_wmask, 1060 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK); 1061 cmd->rx_msdu_end_word_mask = 1062 le32_encode_bits(tlv_filter->rx_msdu_end_wmask, 1063 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK); 1064 } 1065 1066 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 1067 if (ret) 1068 goto err_free; 1069 1070 return 0; 1071 1072 err_free: 1073 dev_kfree_skb_any(skb); 1074 1075 return ret; 1076 } 1077 1078 int 1079 ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k *ar, u8 type, 1080 struct htt_ext_stats_cfg_params *cfg_params, 1081 u64 cookie) 1082 { 1083 struct ath12k_base *ab = ar->ab; 1084 struct ath12k_dp *dp = &ab->dp; 1085 struct sk_buff *skb; 1086 struct htt_ext_stats_cfg_cmd *cmd; 1087 int len = sizeof(*cmd); 1088 int ret; 1089 u32 pdev_id; 1090 1091 skb = ath12k_htc_alloc_skb(ab, len); 1092 if (!skb) 1093 return -ENOMEM; 1094 1095 skb_put(skb, len); 1096 1097 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data; 1098 memset(cmd, 0, sizeof(*cmd)); 1099 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG; 1100 1101 pdev_id = ath12k_mac_get_target_pdev_id(ar); 1102 cmd->hdr.pdev_mask = 1 << pdev_id; 1103 1104 cmd->hdr.stats_type = type; 1105 cmd->cfg_param0 = cpu_to_le32(cfg_params->cfg0); 1106 cmd->cfg_param1 = cpu_to_le32(cfg_params->cfg1); 1107 cmd->cfg_param2 = cpu_to_le32(cfg_params->cfg2); 1108 cmd->cfg_param3 = cpu_to_le32(cfg_params->cfg3); 1109 cmd->cookie_lsb = cpu_to_le32(lower_32_bits(cookie)); 1110 cmd->cookie_msb = cpu_to_le32(upper_32_bits(cookie)); 1111 1112 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 1113 if (ret) { 1114 ath12k_warn(ab, "failed to send htt type stats request: %d", 1115 ret); 1116 dev_kfree_skb_any(skb); 1117 return ret; 1118 } 1119 1120 return 0; 1121 } 1122 1123 int ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k *ar, bool reset) 1124 { 1125 struct ath12k_base *ab = ar->ab; 1126 int ret; 1127 1128 ret = ath12k_dp_tx_htt_rx_monitor_mode_ring_config(ar, reset); 1129 if (ret) { 1130 ath12k_err(ab, "failed to setup rx monitor filter %d\n", ret); 1131 return ret; 1132 } 1133 1134 return 0; 1135 } 1136 1137 int ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k *ar, bool reset) 1138 { 1139 struct ath12k_base *ab = ar->ab; 1140 struct ath12k_dp *dp = &ab->dp; 1141 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 1142 int ret, ring_id; 1143 1144 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 1145 tlv_filter.offset_valid = false; 1146 1147 if (!reset) { 1148 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING; 1149 tlv_filter.pkt_filter_flags0 = 1150 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 | 1151 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0; 1152 tlv_filter.pkt_filter_flags1 = 1153 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 | 1154 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1; 1155 tlv_filter.pkt_filter_flags2 = 1156 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 | 1157 HTT_RX_MON_MO_CTRL_FILTER_FLASG2; 1158 tlv_filter.pkt_filter_flags3 = 1159 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 | 1160 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | 1161 HTT_RX_MON_FP_DATA_FILTER_FLASG3 | 1162 HTT_RX_MON_MO_DATA_FILTER_FLASG3; 1163 } 1164 1165 if (ab->hw_params->rxdma1_enable) { 1166 ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 0, 1167 HAL_RXDMA_MONITOR_BUF, 1168 DP_RXDMA_REFILL_RING_SIZE, 1169 &tlv_filter); 1170 if (ret) { 1171 ath12k_err(ab, 1172 "failed to setup filter for monitor buf %d\n", ret); 1173 return ret; 1174 } 1175 } 1176 1177 return 0; 1178 } 1179 1180 int ath12k_dp_tx_htt_tx_filter_setup(struct ath12k_base *ab, u32 ring_id, 1181 int mac_id, enum hal_ring_type ring_type, 1182 int tx_buf_size, 1183 struct htt_tx_ring_tlv_filter *htt_tlv_filter) 1184 { 1185 struct htt_tx_ring_selection_cfg_cmd *cmd; 1186 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 1187 struct hal_srng_params params; 1188 struct sk_buff *skb; 1189 int len = sizeof(*cmd); 1190 enum htt_srng_ring_type htt_ring_type; 1191 enum htt_srng_ring_id htt_ring_id; 1192 int ret; 1193 1194 skb = ath12k_htc_alloc_skb(ab, len); 1195 if (!skb) 1196 return -ENOMEM; 1197 1198 memset(¶ms, 0, sizeof(params)); 1199 ath12k_hal_srng_get_params(ab, srng, ¶ms); 1200 1201 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 1202 ring_type, &htt_ring_type, 1203 &htt_ring_id); 1204 1205 if (ret) 1206 goto err_free; 1207 1208 skb_put(skb, len); 1209 cmd = (struct htt_tx_ring_selection_cfg_cmd *)skb->data; 1210 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_TX_MONITOR_CFG, 1211 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE); 1212 if (htt_ring_type == HTT_SW_TO_HW_RING || 1213 htt_ring_type == HTT_HW_TO_SW_RING) 1214 cmd->info0 |= 1215 le32_encode_bits(DP_SW2HW_MACID(mac_id), 1216 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1217 else 1218 cmd->info0 |= 1219 le32_encode_bits(mac_id, 1220 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1221 cmd->info0 |= le32_encode_bits(htt_ring_id, 1222 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID); 1223 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 1224 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS); 1225 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 1226 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS); 1227 1228 cmd->info1 |= 1229 le32_encode_bits(tx_buf_size, 1230 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE); 1231 1232 if (htt_tlv_filter->tx_mon_mgmt_filter) { 1233 cmd->info1 |= 1234 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT, 1235 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1236 cmd->info1 |= 1237 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1238 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT); 1239 cmd->info2 |= 1240 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT, 1241 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1242 } 1243 1244 if (htt_tlv_filter->tx_mon_data_filter) { 1245 cmd->info1 |= 1246 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL, 1247 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1248 cmd->info1 |= 1249 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1250 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL); 1251 cmd->info2 |= 1252 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL, 1253 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1254 } 1255 1256 if (htt_tlv_filter->tx_mon_ctrl_filter) { 1257 cmd->info1 |= 1258 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA, 1259 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1260 cmd->info1 |= 1261 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1262 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA); 1263 cmd->info2 |= 1264 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA, 1265 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1266 } 1267 1268 cmd->tlv_filter_mask_in0 = 1269 cpu_to_le32(htt_tlv_filter->tx_mon_downstream_tlv_flags); 1270 cmd->tlv_filter_mask_in1 = 1271 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags0); 1272 cmd->tlv_filter_mask_in2 = 1273 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags1); 1274 cmd->tlv_filter_mask_in3 = 1275 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags2); 1276 1277 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 1278 if (ret) 1279 goto err_free; 1280 1281 return 0; 1282 1283 err_free: 1284 dev_kfree_skb_any(skb); 1285 return ret; 1286 } 1287