1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ASIX AX8817X based USB 2.0 Ethernet Devices 4 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com> 5 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> 6 * Copyright (C) 2006 James Painter <jamie.painter@iname.com> 7 * Copyright (c) 2002-2003 TiVo Inc. 8 */ 9 10 #include "asix.h" 11 12 #define PHY_MODE_MARVELL 0x0000 13 #define MII_MARVELL_LED_CTRL 0x0018 14 #define MII_MARVELL_STATUS 0x001b 15 #define MII_MARVELL_CTRL 0x0014 16 17 #define MARVELL_LED_MANUAL 0x0019 18 19 #define MARVELL_STATUS_HWCFG 0x0004 20 21 #define MARVELL_CTRL_TXDELAY 0x0002 22 #define MARVELL_CTRL_RXDELAY 0x0080 23 24 #define PHY_MODE_RTL8211CL 0x000C 25 26 #define AX88772A_PHY14H 0x14 27 #define AX88772A_PHY14H_DEFAULT 0x442C 28 29 #define AX88772A_PHY15H 0x15 30 #define AX88772A_PHY15H_DEFAULT 0x03C8 31 32 #define AX88772A_PHY16H 0x16 33 #define AX88772A_PHY16H_DEFAULT 0x4044 34 35 struct ax88172_int_data { 36 __le16 res1; 37 u8 link; 38 __le16 res2; 39 u8 status; 40 __le16 res3; 41 } __packed; 42 43 static void asix_status(struct usbnet *dev, struct urb *urb) 44 { 45 struct ax88172_int_data *event; 46 int link; 47 48 if (urb->actual_length < 8) 49 return; 50 51 event = urb->transfer_buffer; 52 link = event->link & 0x01; 53 if (netif_carrier_ok(dev->net) != link) { 54 usbnet_link_change(dev, link, 1); 55 netdev_dbg(dev->net, "Link Status is: %d\n", link); 56 } 57 } 58 59 static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr) 60 { 61 if (is_valid_ether_addr(addr)) { 62 eth_hw_addr_set(dev->net, addr); 63 } else { 64 netdev_info(dev->net, "invalid hw address, using random\n"); 65 eth_hw_addr_random(dev->net); 66 } 67 } 68 69 /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */ 70 static u32 asix_get_phyid(struct usbnet *dev) 71 { 72 int phy_reg; 73 u32 phy_id; 74 int i; 75 76 /* Poll for the rare case the FW or phy isn't ready yet. */ 77 for (i = 0; i < 100; i++) { 78 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); 79 if (phy_reg < 0) 80 return 0; 81 if (phy_reg != 0 && phy_reg != 0xFFFF) 82 break; 83 mdelay(1); 84 } 85 86 if (phy_reg <= 0 || phy_reg == 0xFFFF) 87 return 0; 88 89 phy_id = (phy_reg & 0xffff) << 16; 90 91 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); 92 if (phy_reg < 0) 93 return 0; 94 95 phy_id |= (phy_reg & 0xffff); 96 97 return phy_id; 98 } 99 100 /* We need to override some ethtool_ops so we require our 101 own structure so we don't interfere with other usbnet 102 devices that may be connected at the same time. */ 103 static const struct ethtool_ops ax88172_ethtool_ops = { 104 .get_drvinfo = usbnet_get_drvinfo, 105 .get_link = usbnet_get_link, 106 .get_msglevel = usbnet_get_msglevel, 107 .set_msglevel = usbnet_set_msglevel, 108 .get_wol = asix_get_wol, 109 .set_wol = asix_set_wol, 110 .get_eeprom_len = asix_get_eeprom_len, 111 .get_eeprom = asix_get_eeprom, 112 .set_eeprom = asix_set_eeprom, 113 .nway_reset = usbnet_nway_reset, 114 .get_link_ksettings = usbnet_get_link_ksettings_mii, 115 .set_link_ksettings = usbnet_set_link_ksettings_mii, 116 }; 117 118 static void ax88172_set_multicast(struct net_device *net) 119 { 120 struct usbnet *dev = netdev_priv(net); 121 struct asix_data *data = (struct asix_data *)&dev->data; 122 u8 rx_ctl = 0x8c; 123 124 if (net->flags & IFF_PROMISC) { 125 rx_ctl |= 0x01; 126 } else if (net->flags & IFF_ALLMULTI || 127 netdev_mc_count(net) > AX_MAX_MCAST) { 128 rx_ctl |= 0x02; 129 } else if (netdev_mc_empty(net)) { 130 /* just broadcast and directed */ 131 } else { 132 /* We use the 20 byte dev->data 133 * for our 8 byte filter buffer 134 * to avoid allocating memory that 135 * is tricky to free later */ 136 struct netdev_hw_addr *ha; 137 u32 crc_bits; 138 139 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); 140 141 /* Build the multicast hash filter. */ 142 netdev_for_each_mc_addr(ha, net) { 143 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; 144 data->multi_filter[crc_bits >> 3] |= 145 1 << (crc_bits & 7); 146 } 147 148 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0, 149 AX_MCAST_FILTER_SIZE, data->multi_filter); 150 151 rx_ctl |= 0x10; 152 } 153 154 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); 155 } 156 157 static int ax88172_link_reset(struct usbnet *dev) 158 { 159 u8 mode; 160 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 161 162 mii_check_media(&dev->mii, 1, 1); 163 mii_ethtool_gset(&dev->mii, &ecmd); 164 mode = AX88172_MEDIUM_DEFAULT; 165 166 if (ecmd.duplex != DUPLEX_FULL) 167 mode |= ~AX88172_MEDIUM_FD; 168 169 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 170 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode); 171 172 asix_write_medium_mode(dev, mode, 0); 173 174 return 0; 175 } 176 177 static const struct net_device_ops ax88172_netdev_ops = { 178 .ndo_open = usbnet_open, 179 .ndo_stop = usbnet_stop, 180 .ndo_start_xmit = usbnet_start_xmit, 181 .ndo_tx_timeout = usbnet_tx_timeout, 182 .ndo_change_mtu = usbnet_change_mtu, 183 .ndo_get_stats64 = dev_get_tstats64, 184 .ndo_set_mac_address = eth_mac_addr, 185 .ndo_validate_addr = eth_validate_addr, 186 .ndo_eth_ioctl = usbnet_mii_ioctl, 187 .ndo_set_rx_mode = ax88172_set_multicast, 188 }; 189 190 static void asix_phy_reset(struct usbnet *dev, unsigned int reset_bits) 191 { 192 unsigned int timeout = 5000; 193 194 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits); 195 196 /* give phy_id a chance to process reset */ 197 udelay(500); 198 199 /* See IEEE 802.3 "22.2.4.1.1 Reset": 500ms max */ 200 while (timeout--) { 201 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR) 202 & BMCR_RESET) 203 udelay(100); 204 else 205 return; 206 } 207 208 netdev_err(dev->net, "BMCR_RESET timeout on phy_id %d\n", 209 dev->mii.phy_id); 210 } 211 212 static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf) 213 { 214 int ret = 0; 215 u8 buf[ETH_ALEN] = {0}; 216 int i; 217 unsigned long gpio_bits = dev->driver_info->data; 218 219 ret = usbnet_get_endpoints(dev, intf); 220 if (ret) 221 goto out; 222 223 /* Toggle the GPIOs in a manufacturer/model specific way */ 224 for (i = 2; i >= 0; i--) { 225 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, 226 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL, 0); 227 if (ret < 0) 228 goto out; 229 msleep(5); 230 } 231 232 ret = asix_write_rx_ctl(dev, 0x80, 0); 233 if (ret < 0) 234 goto out; 235 236 /* Get the MAC address */ 237 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 238 0, 0, ETH_ALEN, buf, 0); 239 if (ret < 0) { 240 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n", 241 ret); 242 goto out; 243 } 244 245 asix_set_netdev_dev_addr(dev, buf); 246 247 /* Initialize MII structure */ 248 dev->mii.dev = dev->net; 249 dev->mii.mdio_read = asix_mdio_read; 250 dev->mii.mdio_write = asix_mdio_write; 251 dev->mii.phy_id_mask = 0x3f; 252 dev->mii.reg_num_mask = 0x1f; 253 254 dev->mii.phy_id = asix_read_phy_addr(dev, true); 255 if (dev->mii.phy_id < 0) 256 return dev->mii.phy_id; 257 258 dev->net->netdev_ops = &ax88172_netdev_ops; 259 dev->net->ethtool_ops = &ax88172_ethtool_ops; 260 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ 261 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ 262 263 asix_phy_reset(dev, BMCR_RESET); 264 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 265 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); 266 mii_nway_restart(&dev->mii); 267 268 return 0; 269 270 out: 271 return ret; 272 } 273 274 static void ax88772_ethtool_get_strings(struct net_device *netdev, u32 sset, 275 u8 *data) 276 { 277 switch (sset) { 278 case ETH_SS_TEST: 279 net_selftest_get_strings(data); 280 break; 281 } 282 } 283 284 static int ax88772_ethtool_get_sset_count(struct net_device *ndev, int sset) 285 { 286 switch (sset) { 287 case ETH_SS_TEST: 288 return net_selftest_get_count(); 289 default: 290 return -EOPNOTSUPP; 291 } 292 } 293 294 static void ax88772_ethtool_get_pauseparam(struct net_device *ndev, 295 struct ethtool_pauseparam *pause) 296 { 297 struct usbnet *dev = netdev_priv(ndev); 298 struct asix_common_private *priv = dev->driver_priv; 299 300 phylink_ethtool_get_pauseparam(priv->phylink, pause); 301 } 302 303 static int ax88772_ethtool_set_pauseparam(struct net_device *ndev, 304 struct ethtool_pauseparam *pause) 305 { 306 struct usbnet *dev = netdev_priv(ndev); 307 struct asix_common_private *priv = dev->driver_priv; 308 309 return phylink_ethtool_set_pauseparam(priv->phylink, pause); 310 } 311 312 static const struct ethtool_ops ax88772_ethtool_ops = { 313 .get_drvinfo = usbnet_get_drvinfo, 314 .get_link = usbnet_get_link, 315 .get_msglevel = usbnet_get_msglevel, 316 .set_msglevel = usbnet_set_msglevel, 317 .get_wol = asix_get_wol, 318 .set_wol = asix_set_wol, 319 .get_eeprom_len = asix_get_eeprom_len, 320 .get_eeprom = asix_get_eeprom, 321 .set_eeprom = asix_set_eeprom, 322 .nway_reset = phy_ethtool_nway_reset, 323 .get_link_ksettings = phy_ethtool_get_link_ksettings, 324 .set_link_ksettings = phy_ethtool_set_link_ksettings, 325 .self_test = net_selftest, 326 .get_strings = ax88772_ethtool_get_strings, 327 .get_sset_count = ax88772_ethtool_get_sset_count, 328 .get_pauseparam = ax88772_ethtool_get_pauseparam, 329 .set_pauseparam = ax88772_ethtool_set_pauseparam, 330 }; 331 332 static int ax88772_reset(struct usbnet *dev) 333 { 334 struct asix_data *data = (struct asix_data *)&dev->data; 335 struct asix_common_private *priv = dev->driver_priv; 336 int ret; 337 338 /* Rewrite MAC address */ 339 ether_addr_copy(data->mac_addr, dev->net->dev_addr); 340 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, 341 ETH_ALEN, data->mac_addr, 0); 342 if (ret < 0) 343 goto out; 344 345 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 346 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0); 347 if (ret < 0) 348 goto out; 349 350 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, 0); 351 if (ret < 0) 352 goto out; 353 354 phylink_start(priv->phylink); 355 356 return 0; 357 358 out: 359 return ret; 360 } 361 362 static int ax88772_hw_reset(struct usbnet *dev, int in_pm) 363 { 364 struct asix_data *data = (struct asix_data *)&dev->data; 365 struct asix_common_private *priv = dev->driver_priv; 366 u16 rx_ctl; 367 int ret; 368 369 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 370 AX_GPIO_GPO2EN, 5, in_pm); 371 if (ret < 0) 372 goto out; 373 374 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, priv->embd_phy, 375 0, 0, NULL, in_pm); 376 if (ret < 0) { 377 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); 378 goto out; 379 } 380 381 if (priv->embd_phy) { 382 ret = asix_sw_reset(dev, AX_SWRESET_IPPD, in_pm); 383 if (ret < 0) 384 goto out; 385 386 usleep_range(10000, 11000); 387 388 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm); 389 if (ret < 0) 390 goto out; 391 392 msleep(60); 393 394 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL, 395 in_pm); 396 if (ret < 0) 397 goto out; 398 } else { 399 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL, 400 in_pm); 401 if (ret < 0) 402 goto out; 403 } 404 405 msleep(150); 406 407 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 408 MII_PHYSID1))){ 409 ret = -EIO; 410 goto out; 411 } 412 413 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 414 if (ret < 0) 415 goto out; 416 417 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm); 418 if (ret < 0) 419 goto out; 420 421 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, 422 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, 423 AX88772_IPG2_DEFAULT, 0, NULL, in_pm); 424 if (ret < 0) { 425 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret); 426 goto out; 427 } 428 429 /* Rewrite MAC address */ 430 ether_addr_copy(data->mac_addr, dev->net->dev_addr); 431 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, 432 ETH_ALEN, data->mac_addr, in_pm); 433 if (ret < 0) 434 goto out; 435 436 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 437 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 438 if (ret < 0) 439 goto out; 440 441 rx_ctl = asix_read_rx_ctl(dev, in_pm); 442 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n", 443 rx_ctl); 444 445 rx_ctl = asix_read_medium_status(dev, in_pm); 446 netdev_dbg(dev->net, 447 "Medium Status is 0x%04x after all initializations\n", 448 rx_ctl); 449 450 return 0; 451 452 out: 453 return ret; 454 } 455 456 static int ax88772a_hw_reset(struct usbnet *dev, int in_pm) 457 { 458 struct asix_data *data = (struct asix_data *)&dev->data; 459 struct asix_common_private *priv = dev->driver_priv; 460 u16 rx_ctl, phy14h, phy15h, phy16h; 461 int ret; 462 463 ret = asix_write_gpio(dev, AX_GPIO_RSE, 5, in_pm); 464 if (ret < 0) 465 goto out; 466 467 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, priv->embd_phy | 468 AX_PHYSEL_SSEN, 0, 0, NULL, in_pm); 469 if (ret < 0) { 470 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); 471 goto out; 472 } 473 usleep_range(10000, 11000); 474 475 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_IPRL, in_pm); 476 if (ret < 0) 477 goto out; 478 479 usleep_range(10000, 11000); 480 481 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm); 482 if (ret < 0) 483 goto out; 484 485 msleep(160); 486 487 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm); 488 if (ret < 0) 489 goto out; 490 491 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm); 492 if (ret < 0) 493 goto out; 494 495 msleep(200); 496 497 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 498 MII_PHYSID1))) { 499 ret = -1; 500 goto out; 501 } 502 503 if (priv->chipcode == AX_AX88772B_CHIPCODE) { 504 ret = asix_write_cmd(dev, AX_QCTCTRL, 0x8000, 0x8001, 505 0, NULL, in_pm); 506 if (ret < 0) { 507 netdev_dbg(dev->net, "Write BQ setting failed: %d\n", 508 ret); 509 goto out; 510 } 511 } else if (priv->chipcode == AX_AX88772A_CHIPCODE) { 512 /* Check if the PHY registers have default settings */ 513 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 514 AX88772A_PHY14H); 515 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 516 AX88772A_PHY15H); 517 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 518 AX88772A_PHY16H); 519 520 netdev_dbg(dev->net, 521 "772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\n", 522 phy14h, phy15h, phy16h); 523 524 /* Restore PHY registers default setting if not */ 525 if (phy14h != AX88772A_PHY14H_DEFAULT) 526 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, 527 AX88772A_PHY14H, 528 AX88772A_PHY14H_DEFAULT); 529 if (phy15h != AX88772A_PHY15H_DEFAULT) 530 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, 531 AX88772A_PHY15H, 532 AX88772A_PHY15H_DEFAULT); 533 if (phy16h != AX88772A_PHY16H_DEFAULT) 534 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, 535 AX88772A_PHY16H, 536 AX88772A_PHY16H_DEFAULT); 537 } 538 539 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, 540 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, 541 AX88772_IPG2_DEFAULT, 0, NULL, in_pm); 542 if (ret < 0) { 543 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret); 544 goto out; 545 } 546 547 /* Rewrite MAC address */ 548 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); 549 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, 550 data->mac_addr, in_pm); 551 if (ret < 0) 552 goto out; 553 554 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 555 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 556 if (ret < 0) 557 goto out; 558 559 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm); 560 if (ret < 0) 561 return ret; 562 563 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 564 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 565 if (ret < 0) 566 goto out; 567 568 rx_ctl = asix_read_rx_ctl(dev, in_pm); 569 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n", 570 rx_ctl); 571 572 rx_ctl = asix_read_medium_status(dev, in_pm); 573 netdev_dbg(dev->net, 574 "Medium Status is 0x%04x after all initializations\n", 575 rx_ctl); 576 577 return 0; 578 579 out: 580 return ret; 581 } 582 583 static const struct net_device_ops ax88772_netdev_ops = { 584 .ndo_open = usbnet_open, 585 .ndo_stop = usbnet_stop, 586 .ndo_start_xmit = usbnet_start_xmit, 587 .ndo_tx_timeout = usbnet_tx_timeout, 588 .ndo_change_mtu = usbnet_change_mtu, 589 .ndo_get_stats64 = dev_get_tstats64, 590 .ndo_set_mac_address = asix_set_mac_address, 591 .ndo_validate_addr = eth_validate_addr, 592 .ndo_eth_ioctl = phy_do_ioctl_running, 593 .ndo_set_rx_mode = asix_set_multicast, 594 }; 595 596 static void ax88772_suspend(struct usbnet *dev) 597 { 598 struct asix_common_private *priv = dev->driver_priv; 599 u16 medium; 600 601 if (netif_running(dev->net)) { 602 rtnl_lock(); 603 phylink_suspend(priv->phylink, false); 604 rtnl_unlock(); 605 } 606 607 /* Stop MAC operation */ 608 medium = asix_read_medium_status(dev, 1); 609 medium &= ~AX_MEDIUM_RE; 610 asix_write_medium_mode(dev, medium, 1); 611 612 netdev_dbg(dev->net, "ax88772_suspend: medium=0x%04x\n", 613 asix_read_medium_status(dev, 1)); 614 } 615 616 /* Notes on PM callbacks and locking context: 617 * 618 * - asix_suspend()/asix_resume() are invoked for both runtime PM and 619 * system-wide suspend/resume. For struct usb_driver the ->resume() 620 * callback does not receive pm_message_t, so the resume type cannot 621 * be distinguished here. 622 * 623 * - The MAC driver must hold RTNL when calling phylink interfaces such as 624 * phylink_suspend()/resume(). Those calls will also perform MDIO I/O. 625 * 626 * - Taking RTNL and doing MDIO from a runtime-PM resume callback (while 627 * the USB PM lock is held) is fragile. Since autosuspend brings no 628 * measurable power saving here, we block it by holding a PM usage 629 * reference in ax88772_bind(). 630 */ 631 static int asix_suspend(struct usb_interface *intf, pm_message_t message) 632 { 633 struct usbnet *dev = usb_get_intfdata(intf); 634 struct asix_common_private *priv = dev->driver_priv; 635 636 if (priv && priv->suspend) 637 priv->suspend(dev); 638 639 return usbnet_suspend(intf, message); 640 } 641 642 static void ax88772_resume(struct usbnet *dev) 643 { 644 struct asix_common_private *priv = dev->driver_priv; 645 int i; 646 647 for (i = 0; i < 3; i++) 648 if (!priv->reset(dev, 1)) 649 break; 650 651 if (netif_running(dev->net)) { 652 rtnl_lock(); 653 phylink_resume(priv->phylink); 654 rtnl_unlock(); 655 } 656 } 657 658 static int asix_resume(struct usb_interface *intf) 659 { 660 struct usbnet *dev = usb_get_intfdata(intf); 661 struct asix_common_private *priv = dev->driver_priv; 662 663 if (priv && priv->resume) 664 priv->resume(dev); 665 666 return usbnet_resume(intf); 667 } 668 669 static int ax88772_init_mdio(struct usbnet *dev) 670 { 671 struct asix_common_private *priv = dev->driver_priv; 672 int ret; 673 674 priv->mdio = mdiobus_alloc(); 675 if (!priv->mdio) 676 return -ENOMEM; 677 678 priv->mdio->priv = dev; 679 priv->mdio->read = &asix_mdio_bus_read; 680 priv->mdio->write = &asix_mdio_bus_write; 681 priv->mdio->name = "Asix MDIO Bus"; 682 priv->mdio->phy_mask = ~(BIT(priv->phy_addr & 0x1f) | BIT(AX_EMBD_PHY_ADDR)); 683 /* mii bus name is usb-<usb bus number>-<usb device number> */ 684 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "usb-%03d:%03d", 685 dev->udev->bus->busnum, dev->udev->devnum); 686 687 ret = mdiobus_register(priv->mdio); 688 if (ret) { 689 netdev_err(dev->net, "Could not register MDIO bus (err %d)\n", ret); 690 mdiobus_free(priv->mdio); 691 priv->mdio = NULL; 692 } 693 694 return ret; 695 } 696 697 static void ax88772_mdio_unregister(struct asix_common_private *priv) 698 { 699 mdiobus_unregister(priv->mdio); 700 mdiobus_free(priv->mdio); 701 } 702 703 static int ax88772_init_phy(struct usbnet *dev) 704 { 705 struct asix_common_private *priv = dev->driver_priv; 706 int ret; 707 708 priv->phydev = mdiobus_get_phy(priv->mdio, priv->phy_addr); 709 if (!priv->phydev) { 710 netdev_err(dev->net, "Could not find PHY\n"); 711 return -ENODEV; 712 } 713 714 ret = phylink_connect_phy(priv->phylink, priv->phydev); 715 if (ret) { 716 netdev_err(dev->net, "Could not connect PHY\n"); 717 return ret; 718 } 719 720 phy_suspend(priv->phydev); 721 priv->phydev->mac_managed_pm = true; 722 723 phy_attached_info(priv->phydev); 724 725 if (priv->embd_phy) 726 return 0; 727 728 /* In case main PHY is not the embedded PHY and MAC is RMII clock 729 * provider, we need to suspend embedded PHY by keeping PLL enabled 730 * (AX_SWRESET_IPPD == 0). 731 */ 732 priv->phydev_int = mdiobus_get_phy(priv->mdio, AX_EMBD_PHY_ADDR); 733 if (!priv->phydev_int) { 734 rtnl_lock(); 735 phylink_disconnect_phy(priv->phylink); 736 rtnl_unlock(); 737 netdev_err(dev->net, "Could not find internal PHY\n"); 738 return -ENODEV; 739 } 740 741 priv->phydev_int->mac_managed_pm = true; 742 phy_suspend(priv->phydev_int); 743 744 return 0; 745 } 746 747 static void ax88772_mac_config(struct phylink_config *config, unsigned int mode, 748 const struct phylink_link_state *state) 749 { 750 /* Nothing to do */ 751 } 752 753 static void ax88772_mac_link_down(struct phylink_config *config, 754 unsigned int mode, phy_interface_t interface) 755 { 756 struct usbnet *dev = netdev_priv(to_net_dev(config->dev)); 757 758 asix_write_medium_mode(dev, 0, 0); 759 usbnet_link_change(dev, false, false); 760 } 761 762 static void ax88772_mac_link_up(struct phylink_config *config, 763 struct phy_device *phy, 764 unsigned int mode, phy_interface_t interface, 765 int speed, int duplex, 766 bool tx_pause, bool rx_pause) 767 { 768 struct usbnet *dev = netdev_priv(to_net_dev(config->dev)); 769 u16 m = AX_MEDIUM_AC | AX_MEDIUM_RE; 770 771 m |= duplex ? AX_MEDIUM_FD : 0; 772 773 switch (speed) { 774 case SPEED_100: 775 m |= AX_MEDIUM_PS; 776 break; 777 case SPEED_10: 778 break; 779 default: 780 return; 781 } 782 783 if (tx_pause) 784 m |= AX_MEDIUM_TFC; 785 786 if (rx_pause) 787 m |= AX_MEDIUM_RFC; 788 789 asix_write_medium_mode(dev, m, 0); 790 usbnet_link_change(dev, true, false); 791 } 792 793 static const struct phylink_mac_ops ax88772_phylink_mac_ops = { 794 .mac_config = ax88772_mac_config, 795 .mac_link_down = ax88772_mac_link_down, 796 .mac_link_up = ax88772_mac_link_up, 797 }; 798 799 static int ax88772_phylink_setup(struct usbnet *dev) 800 { 801 struct asix_common_private *priv = dev->driver_priv; 802 phy_interface_t phy_if_mode; 803 struct phylink *phylink; 804 805 priv->phylink_config.dev = &dev->net->dev; 806 priv->phylink_config.type = PHYLINK_NETDEV; 807 priv->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | 808 MAC_10 | MAC_100; 809 810 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 811 priv->phylink_config.supported_interfaces); 812 __set_bit(PHY_INTERFACE_MODE_RMII, 813 priv->phylink_config.supported_interfaces); 814 815 if (priv->embd_phy) 816 phy_if_mode = PHY_INTERFACE_MODE_INTERNAL; 817 else 818 phy_if_mode = PHY_INTERFACE_MODE_RMII; 819 820 phylink = phylink_create(&priv->phylink_config, dev->net->dev.fwnode, 821 phy_if_mode, &ax88772_phylink_mac_ops); 822 if (IS_ERR(phylink)) 823 return PTR_ERR(phylink); 824 825 priv->phylink = phylink; 826 return 0; 827 } 828 829 static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf) 830 { 831 struct asix_common_private *priv; 832 u8 buf[ETH_ALEN] = {0}; 833 int ret, i; 834 835 priv = devm_kzalloc(&dev->udev->dev, sizeof(*priv), GFP_KERNEL); 836 if (!priv) 837 return -ENOMEM; 838 839 dev->driver_priv = priv; 840 841 ret = usbnet_get_endpoints(dev, intf); 842 if (ret) 843 return ret; 844 845 /* Maybe the boot loader passed the MAC address via device tree */ 846 if (!eth_platform_get_mac_address(&dev->udev->dev, buf)) { 847 netif_dbg(dev, ifup, dev->net, 848 "MAC address read from device tree"); 849 } else { 850 /* Try getting the MAC address from EEPROM */ 851 if (dev->driver_info->data & FLAG_EEPROM_MAC) { 852 for (i = 0; i < (ETH_ALEN >> 1); i++) { 853 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 854 0x04 + i, 0, 2, buf + i * 2, 855 0); 856 if (ret < 0) 857 break; 858 } 859 } else { 860 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 861 0, 0, ETH_ALEN, buf, 0); 862 } 863 864 if (ret < 0) { 865 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", 866 ret); 867 return ret; 868 } 869 } 870 871 asix_set_netdev_dev_addr(dev, buf); 872 873 dev->net->netdev_ops = &ax88772_netdev_ops; 874 dev->net->ethtool_ops = &ax88772_ethtool_ops; 875 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ 876 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ 877 878 ret = asix_read_phy_addr(dev, true); 879 if (ret < 0) 880 return ret; 881 882 priv->phy_addr = ret; 883 priv->embd_phy = ((priv->phy_addr & 0x1f) == AX_EMBD_PHY_ADDR); 884 885 ret = asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 0, 1, 886 &priv->chipcode, 0); 887 if (ret < 0) { 888 netdev_dbg(dev->net, "Failed to read STATMNGSTS_REG: %d\n", ret); 889 return ret; 890 } 891 892 priv->chipcode &= AX_CHIPCODE_MASK; 893 894 priv->resume = ax88772_resume; 895 priv->suspend = ax88772_suspend; 896 if (priv->chipcode == AX_AX88772_CHIPCODE) 897 priv->reset = ax88772_hw_reset; 898 else 899 priv->reset = ax88772a_hw_reset; 900 901 ret = priv->reset(dev, 0); 902 if (ret < 0) { 903 netdev_dbg(dev->net, "Failed to reset AX88772: %d\n", ret); 904 return ret; 905 } 906 907 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ 908 if (dev->driver_info->flags & FLAG_FRAMING_AX) { 909 /* hard_mtu is still the default - the device does not support 910 jumbo eth frames */ 911 dev->rx_urb_size = 2048; 912 } 913 914 priv->presvd_phy_bmcr = 0; 915 priv->presvd_phy_advertise = 0; 916 917 ret = ax88772_init_mdio(dev); 918 if (ret) 919 goto mdio_err; 920 921 ret = ax88772_phylink_setup(dev); 922 if (ret) 923 goto phylink_err; 924 925 ret = ax88772_init_phy(dev); 926 if (ret) 927 goto initphy_err; 928 929 /* Keep this interface runtime-PM active by taking a usage ref. 930 * Prevents runtime suspend while bound and avoids resume paths 931 * that could deadlock (autoresume under RTNL while USB PM lock 932 * is held, phylink/MDIO wants RTNL). 933 */ 934 pm_runtime_get_noresume(&intf->dev); 935 936 return 0; 937 938 initphy_err: 939 phylink_destroy(priv->phylink); 940 phylink_err: 941 ax88772_mdio_unregister(priv); 942 mdio_err: 943 return ret; 944 } 945 946 static int ax88772_stop(struct usbnet *dev) 947 { 948 struct asix_common_private *priv = dev->driver_priv; 949 950 phylink_stop(priv->phylink); 951 952 return 0; 953 } 954 955 static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf) 956 { 957 struct asix_common_private *priv = dev->driver_priv; 958 959 rtnl_lock(); 960 phylink_disconnect_phy(priv->phylink); 961 rtnl_unlock(); 962 phylink_destroy(priv->phylink); 963 ax88772_mdio_unregister(priv); 964 asix_rx_fixup_common_free(dev->driver_priv); 965 /* Drop the PM usage ref taken in bind() */ 966 pm_runtime_put(&intf->dev); 967 } 968 969 static void ax88178_unbind(struct usbnet *dev, struct usb_interface *intf) 970 { 971 asix_rx_fixup_common_free(dev->driver_priv); 972 kfree(dev->driver_priv); 973 } 974 975 static const struct ethtool_ops ax88178_ethtool_ops = { 976 .get_drvinfo = usbnet_get_drvinfo, 977 .get_link = usbnet_get_link, 978 .get_msglevel = usbnet_get_msglevel, 979 .set_msglevel = usbnet_set_msglevel, 980 .get_wol = asix_get_wol, 981 .set_wol = asix_set_wol, 982 .get_eeprom_len = asix_get_eeprom_len, 983 .get_eeprom = asix_get_eeprom, 984 .set_eeprom = asix_set_eeprom, 985 .nway_reset = usbnet_nway_reset, 986 .get_link_ksettings = usbnet_get_link_ksettings_mii, 987 .set_link_ksettings = usbnet_set_link_ksettings_mii, 988 }; 989 990 static int marvell_phy_init(struct usbnet *dev) 991 { 992 struct asix_data *data = (struct asix_data *)&dev->data; 993 u16 reg; 994 995 netdev_dbg(dev->net, "marvell_phy_init()\n"); 996 997 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS); 998 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg); 999 1000 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL, 1001 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY); 1002 1003 if (data->ledmode) { 1004 reg = asix_mdio_read(dev->net, dev->mii.phy_id, 1005 MII_MARVELL_LED_CTRL); 1006 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg); 1007 1008 reg &= 0xf8ff; 1009 reg |= (1 + 0x0100); 1010 asix_mdio_write(dev->net, dev->mii.phy_id, 1011 MII_MARVELL_LED_CTRL, reg); 1012 1013 reg = asix_mdio_read(dev->net, dev->mii.phy_id, 1014 MII_MARVELL_LED_CTRL); 1015 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg); 1016 } 1017 1018 return 0; 1019 } 1020 1021 static int rtl8211cl_phy_init(struct usbnet *dev) 1022 { 1023 struct asix_data *data = (struct asix_data *)&dev->data; 1024 1025 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n"); 1026 1027 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005); 1028 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0); 1029 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01, 1030 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080); 1031 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); 1032 1033 if (data->ledmode == 12) { 1034 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002); 1035 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb); 1036 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); 1037 } 1038 1039 return 0; 1040 } 1041 1042 static int marvell_led_status(struct usbnet *dev, u16 speed) 1043 { 1044 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL); 1045 1046 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg); 1047 1048 /* Clear out the center LED bits - 0x03F0 */ 1049 reg &= 0xfc0f; 1050 1051 switch (speed) { 1052 case SPEED_1000: 1053 reg |= 0x03e0; 1054 break; 1055 case SPEED_100: 1056 reg |= 0x03b0; 1057 break; 1058 default: 1059 reg |= 0x02f0; 1060 } 1061 1062 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg); 1063 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg); 1064 1065 return 0; 1066 } 1067 1068 static int ax88178_reset(struct usbnet *dev) 1069 { 1070 struct asix_data *data = (struct asix_data *)&dev->data; 1071 int ret; 1072 __le16 eeprom; 1073 u8 status; 1074 int gpio0 = 0; 1075 u32 phyid; 1076 1077 ret = asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status, 0); 1078 if (ret < 0) { 1079 netdev_dbg(dev->net, "Failed to read GPIOS: %d\n", ret); 1080 return ret; 1081 } 1082 1083 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status); 1084 1085 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL, 0); 1086 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom, 0); 1087 if (ret < 0) { 1088 netdev_dbg(dev->net, "Failed to read EEPROM: %d\n", ret); 1089 return ret; 1090 } 1091 1092 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL, 0); 1093 1094 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom); 1095 1096 if (eeprom == cpu_to_le16(0xffff)) { 1097 data->phymode = PHY_MODE_MARVELL; 1098 data->ledmode = 0; 1099 gpio0 = 1; 1100 } else { 1101 data->phymode = le16_to_cpu(eeprom) & 0x7F; 1102 data->ledmode = le16_to_cpu(eeprom) >> 8; 1103 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1; 1104 } 1105 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode); 1106 1107 /* Power up external GigaPHY through AX88178 GPIO pin */ 1108 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | 1109 AX_GPIO_GPO1EN, 40, 0); 1110 if ((le16_to_cpu(eeprom) >> 8) != 1) { 1111 asix_write_gpio(dev, 0x003c, 30, 0); 1112 asix_write_gpio(dev, 0x001c, 300, 0); 1113 asix_write_gpio(dev, 0x003c, 30, 0); 1114 } else { 1115 netdev_dbg(dev->net, "gpio phymode == 1 path\n"); 1116 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30, 0); 1117 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30, 0); 1118 } 1119 1120 /* Read PHYID register *AFTER* powering up PHY */ 1121 phyid = asix_get_phyid(dev); 1122 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid); 1123 1124 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */ 1125 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL, 0); 1126 1127 asix_sw_reset(dev, 0, 0); 1128 msleep(150); 1129 1130 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0); 1131 msleep(150); 1132 1133 asix_write_rx_ctl(dev, 0, 0); 1134 1135 if (data->phymode == PHY_MODE_MARVELL) { 1136 marvell_phy_init(dev); 1137 msleep(60); 1138 } else if (data->phymode == PHY_MODE_RTL8211CL) 1139 rtl8211cl_phy_init(dev); 1140 1141 asix_phy_reset(dev, BMCR_RESET | BMCR_ANENABLE); 1142 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 1143 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); 1144 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000, 1145 ADVERTISE_1000FULL); 1146 1147 asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT, 0); 1148 mii_nway_restart(&dev->mii); 1149 1150 /* Rewrite MAC address */ 1151 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); 1152 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, 1153 data->mac_addr, 0); 1154 if (ret < 0) 1155 return ret; 1156 1157 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0); 1158 if (ret < 0) 1159 return ret; 1160 1161 return 0; 1162 } 1163 1164 static int ax88178_link_reset(struct usbnet *dev) 1165 { 1166 u16 mode; 1167 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 1168 struct asix_data *data = (struct asix_data *)&dev->data; 1169 u32 speed; 1170 1171 netdev_dbg(dev->net, "ax88178_link_reset()\n"); 1172 1173 mii_check_media(&dev->mii, 1, 1); 1174 mii_ethtool_gset(&dev->mii, &ecmd); 1175 mode = AX88178_MEDIUM_DEFAULT; 1176 speed = ethtool_cmd_speed(&ecmd); 1177 1178 if (speed == SPEED_1000) 1179 mode |= AX_MEDIUM_GM; 1180 else if (speed == SPEED_100) 1181 mode |= AX_MEDIUM_PS; 1182 else 1183 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM); 1184 1185 mode |= AX_MEDIUM_ENCK; 1186 1187 if (ecmd.duplex == DUPLEX_FULL) 1188 mode |= AX_MEDIUM_FD; 1189 else 1190 mode &= ~AX_MEDIUM_FD; 1191 1192 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 1193 speed, ecmd.duplex, mode); 1194 1195 asix_write_medium_mode(dev, mode, 0); 1196 1197 if (data->phymode == PHY_MODE_MARVELL && data->ledmode) 1198 marvell_led_status(dev, speed); 1199 1200 return 0; 1201 } 1202 1203 static void ax88178_set_mfb(struct usbnet *dev) 1204 { 1205 u16 mfb = AX_RX_CTL_MFB_16384; 1206 u16 rxctl; 1207 u16 medium; 1208 int old_rx_urb_size = dev->rx_urb_size; 1209 1210 if (dev->hard_mtu < 2048) { 1211 dev->rx_urb_size = 2048; 1212 mfb = AX_RX_CTL_MFB_2048; 1213 } else if (dev->hard_mtu < 4096) { 1214 dev->rx_urb_size = 4096; 1215 mfb = AX_RX_CTL_MFB_4096; 1216 } else if (dev->hard_mtu < 8192) { 1217 dev->rx_urb_size = 8192; 1218 mfb = AX_RX_CTL_MFB_8192; 1219 } else if (dev->hard_mtu < 16384) { 1220 dev->rx_urb_size = 16384; 1221 mfb = AX_RX_CTL_MFB_16384; 1222 } 1223 1224 rxctl = asix_read_rx_ctl(dev, 0); 1225 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb, 0); 1226 1227 medium = asix_read_medium_status(dev, 0); 1228 if (dev->net->mtu > 1500) 1229 medium |= AX_MEDIUM_JFE; 1230 else 1231 medium &= ~AX_MEDIUM_JFE; 1232 asix_write_medium_mode(dev, medium, 0); 1233 1234 if (dev->rx_urb_size > old_rx_urb_size) 1235 usbnet_unlink_rx_urbs(dev); 1236 } 1237 1238 static int ax88178_change_mtu(struct net_device *net, int new_mtu) 1239 { 1240 struct usbnet *dev = netdev_priv(net); 1241 int ll_mtu = new_mtu + net->hard_header_len + 4; 1242 1243 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu); 1244 1245 if ((ll_mtu % dev->maxpacket) == 0) 1246 return -EDOM; 1247 1248 WRITE_ONCE(net->mtu, new_mtu); 1249 dev->hard_mtu = net->mtu + net->hard_header_len; 1250 ax88178_set_mfb(dev); 1251 1252 /* max qlen depend on hard_mtu and rx_urb_size */ 1253 usbnet_update_max_qlen(dev); 1254 1255 return 0; 1256 } 1257 1258 static const struct net_device_ops ax88178_netdev_ops = { 1259 .ndo_open = usbnet_open, 1260 .ndo_stop = usbnet_stop, 1261 .ndo_start_xmit = usbnet_start_xmit, 1262 .ndo_tx_timeout = usbnet_tx_timeout, 1263 .ndo_get_stats64 = dev_get_tstats64, 1264 .ndo_set_mac_address = asix_set_mac_address, 1265 .ndo_validate_addr = eth_validate_addr, 1266 .ndo_set_rx_mode = asix_set_multicast, 1267 .ndo_eth_ioctl = usbnet_mii_ioctl, 1268 .ndo_change_mtu = ax88178_change_mtu, 1269 }; 1270 1271 static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf) 1272 { 1273 int ret; 1274 u8 buf[ETH_ALEN] = {0}; 1275 1276 ret = usbnet_get_endpoints(dev, intf); 1277 if (ret) 1278 return ret; 1279 1280 /* Get the MAC address */ 1281 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf, 0); 1282 if (ret < 0) { 1283 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret); 1284 return ret; 1285 } 1286 1287 asix_set_netdev_dev_addr(dev, buf); 1288 1289 /* Initialize MII structure */ 1290 dev->mii.dev = dev->net; 1291 dev->mii.mdio_read = asix_mdio_read; 1292 dev->mii.mdio_write = asix_mdio_write; 1293 dev->mii.phy_id_mask = 0x1f; 1294 dev->mii.reg_num_mask = 0xff; 1295 dev->mii.supports_gmii = 1; 1296 1297 dev->mii.phy_id = asix_read_phy_addr(dev, true); 1298 if (dev->mii.phy_id < 0) 1299 return dev->mii.phy_id; 1300 1301 dev->net->netdev_ops = &ax88178_netdev_ops; 1302 dev->net->ethtool_ops = &ax88178_ethtool_ops; 1303 dev->net->max_mtu = 16384 - (dev->net->hard_header_len + 4); 1304 1305 /* Blink LEDS so users know driver saw dongle */ 1306 asix_sw_reset(dev, 0, 0); 1307 msleep(150); 1308 1309 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0); 1310 msleep(150); 1311 1312 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ 1313 if (dev->driver_info->flags & FLAG_FRAMING_AX) { 1314 /* hard_mtu is still the default - the device does not support 1315 jumbo eth frames */ 1316 dev->rx_urb_size = 2048; 1317 } 1318 1319 dev->driver_priv = kzalloc_obj(struct asix_common_private); 1320 if (!dev->driver_priv) 1321 return -ENOMEM; 1322 1323 return 0; 1324 } 1325 1326 static const struct driver_info ax8817x_info = { 1327 .description = "ASIX AX8817x USB 2.0 Ethernet", 1328 .bind = ax88172_bind, 1329 .status = asix_status, 1330 .link_reset = ax88172_link_reset, 1331 .reset = ax88172_link_reset, 1332 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1333 .data = 0x00130103, 1334 }; 1335 1336 static const struct driver_info dlink_dub_e100_info = { 1337 .description = "DLink DUB-E100 USB Ethernet", 1338 .bind = ax88172_bind, 1339 .status = asix_status, 1340 .link_reset = ax88172_link_reset, 1341 .reset = ax88172_link_reset, 1342 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1343 .data = 0x009f9d9f, 1344 }; 1345 1346 static const struct driver_info netgear_fa120_info = { 1347 .description = "Netgear FA-120 USB Ethernet", 1348 .bind = ax88172_bind, 1349 .status = asix_status, 1350 .link_reset = ax88172_link_reset, 1351 .reset = ax88172_link_reset, 1352 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1353 .data = 0x00130103, 1354 }; 1355 1356 static const struct driver_info hawking_uf200_info = { 1357 .description = "Hawking UF200 USB Ethernet", 1358 .bind = ax88172_bind, 1359 .status = asix_status, 1360 .link_reset = ax88172_link_reset, 1361 .reset = ax88172_link_reset, 1362 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1363 .data = 0x001f1d1f, 1364 }; 1365 1366 static const struct driver_info ax88772_info = { 1367 .description = "ASIX AX88772 USB 2.0 Ethernet", 1368 .bind = ax88772_bind, 1369 .unbind = ax88772_unbind, 1370 .reset = ax88772_reset, 1371 .stop = ax88772_stop, 1372 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_MULTI_PACKET, 1373 .rx_fixup = asix_rx_fixup_common, 1374 .tx_fixup = asix_tx_fixup, 1375 }; 1376 1377 static const struct driver_info ax88772b_info = { 1378 .description = "ASIX AX88772B USB 2.0 Ethernet", 1379 .bind = ax88772_bind, 1380 .unbind = ax88772_unbind, 1381 .reset = ax88772_reset, 1382 .stop = ax88772_stop, 1383 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_MULTI_PACKET, 1384 .rx_fixup = asix_rx_fixup_common, 1385 .tx_fixup = asix_tx_fixup, 1386 .data = FLAG_EEPROM_MAC, 1387 }; 1388 1389 static const struct driver_info lxausb_t1l_info = { 1390 .description = "Linux Automation GmbH USB 10Base-T1L", 1391 .bind = ax88772_bind, 1392 .unbind = ax88772_unbind, 1393 .reset = ax88772_reset, 1394 .stop = ax88772_stop, 1395 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_MULTI_PACKET, 1396 .rx_fixup = asix_rx_fixup_common, 1397 .tx_fixup = asix_tx_fixup, 1398 .data = FLAG_EEPROM_MAC, 1399 }; 1400 1401 static const struct driver_info ax88178_info = { 1402 .description = "ASIX AX88178 USB 2.0 Ethernet", 1403 .bind = ax88178_bind, 1404 .unbind = ax88178_unbind, 1405 .status = asix_status, 1406 .link_reset = ax88178_link_reset, 1407 .reset = ax88178_reset, 1408 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | 1409 FLAG_MULTI_PACKET, 1410 .rx_fixup = asix_rx_fixup_common, 1411 .tx_fixup = asix_tx_fixup, 1412 }; 1413 1414 /* 1415 * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in 1416 * no-name packaging. 1417 * USB device strings are: 1418 * 1: Manufacturer: USBLINK 1419 * 2: Product: HG20F9 USB2.0 1420 * 3: Serial: 000003 1421 * Appears to be compatible with Asix 88772B. 1422 */ 1423 static const struct driver_info hg20f9_info = { 1424 .description = "HG20F9 USB 2.0 Ethernet", 1425 .bind = ax88772_bind, 1426 .unbind = ax88772_unbind, 1427 .reset = ax88772_reset, 1428 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_MULTI_PACKET, 1429 .rx_fixup = asix_rx_fixup_common, 1430 .tx_fixup = asix_tx_fixup, 1431 .data = FLAG_EEPROM_MAC, 1432 }; 1433 1434 static const struct driver_info lyconsys_fibergecko100_info = { 1435 .description = "LyconSys FiberGecko 100 USB 2.0 to SFP Adapter", 1436 .bind = ax88178_bind, 1437 .status = asix_status, 1438 .link_reset = ax88178_link_reset, 1439 .reset = ax88178_link_reset, 1440 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | 1441 FLAG_MULTI_PACKET, 1442 .rx_fixup = asix_rx_fixup_common, 1443 .tx_fixup = asix_tx_fixup, 1444 .data = 0x20061201, 1445 }; 1446 1447 static const struct usb_device_id products [] = { 1448 { 1449 // Linksys USB200M 1450 USB_DEVICE (0x077b, 0x2226), 1451 .driver_info = (unsigned long) &ax8817x_info, 1452 }, { 1453 // Netgear FA120 1454 USB_DEVICE (0x0846, 0x1040), 1455 .driver_info = (unsigned long) &netgear_fa120_info, 1456 }, { 1457 // DLink DUB-E100 1458 USB_DEVICE (0x2001, 0x1a00), 1459 .driver_info = (unsigned long) &dlink_dub_e100_info, 1460 }, { 1461 // Intellinet, ST Lab USB Ethernet 1462 USB_DEVICE (0x0b95, 0x1720), 1463 .driver_info = (unsigned long) &ax8817x_info, 1464 }, { 1465 // Hawking UF200, TrendNet TU2-ET100 1466 USB_DEVICE (0x07b8, 0x420a), 1467 .driver_info = (unsigned long) &hawking_uf200_info, 1468 }, { 1469 // Billionton Systems, USB2AR 1470 USB_DEVICE (0x08dd, 0x90ff), 1471 .driver_info = (unsigned long) &ax8817x_info, 1472 }, { 1473 // Billionton Systems, GUSB2AM-1G-B 1474 USB_DEVICE(0x08dd, 0x0114), 1475 .driver_info = (unsigned long) &ax88178_info, 1476 }, { 1477 // ATEN UC210T 1478 USB_DEVICE (0x0557, 0x2009), 1479 .driver_info = (unsigned long) &ax8817x_info, 1480 }, { 1481 // Buffalo LUA-U2-KTX 1482 USB_DEVICE (0x0411, 0x003d), 1483 .driver_info = (unsigned long) &ax8817x_info, 1484 }, { 1485 // Buffalo LUA-U2-GT 10/100/1000 1486 USB_DEVICE (0x0411, 0x006e), 1487 .driver_info = (unsigned long) &ax88178_info, 1488 }, { 1489 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter" 1490 USB_DEVICE (0x6189, 0x182d), 1491 .driver_info = (unsigned long) &ax8817x_info, 1492 }, { 1493 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter" 1494 USB_DEVICE (0x0df6, 0x0056), 1495 .driver_info = (unsigned long) &ax88178_info, 1496 }, { 1497 // Sitecom LN-028 "USB 2.0 10/100/1000 Ethernet adapter" 1498 USB_DEVICE (0x0df6, 0x061c), 1499 .driver_info = (unsigned long) &ax88178_info, 1500 }, { 1501 // corega FEther USB2-TX 1502 USB_DEVICE (0x07aa, 0x0017), 1503 .driver_info = (unsigned long) &ax8817x_info, 1504 }, { 1505 // Surecom EP-1427X-2 1506 USB_DEVICE (0x1189, 0x0893), 1507 .driver_info = (unsigned long) &ax8817x_info, 1508 }, { 1509 // goodway corp usb gwusb2e 1510 USB_DEVICE (0x1631, 0x6200), 1511 .driver_info = (unsigned long) &ax8817x_info, 1512 }, { 1513 // JVC MP-PRX1 Port Replicator 1514 USB_DEVICE (0x04f1, 0x3008), 1515 .driver_info = (unsigned long) &ax8817x_info, 1516 }, { 1517 // Lenovo U2L100P 10/100 1518 USB_DEVICE (0x17ef, 0x7203), 1519 .driver_info = (unsigned long)&ax88772b_info, 1520 }, { 1521 // ASIX AX88772B 10/100 1522 USB_DEVICE (0x0b95, 0x772b), 1523 .driver_info = (unsigned long) &ax88772b_info, 1524 }, { 1525 // ASIX AX88772 10/100 1526 USB_DEVICE (0x0b95, 0x7720), 1527 .driver_info = (unsigned long) &ax88772_info, 1528 }, { 1529 // ASIX AX88178 10/100/1000 1530 USB_DEVICE (0x0b95, 0x1780), 1531 .driver_info = (unsigned long) &ax88178_info, 1532 }, { 1533 // Logitec LAN-GTJ/U2A 1534 USB_DEVICE (0x0789, 0x0160), 1535 .driver_info = (unsigned long) &ax88178_info, 1536 }, { 1537 // Linksys USB200M Rev 2 1538 USB_DEVICE (0x13b1, 0x0018), 1539 .driver_info = (unsigned long) &ax88772_info, 1540 }, { 1541 // 0Q0 cable ethernet 1542 USB_DEVICE (0x1557, 0x7720), 1543 .driver_info = (unsigned long) &ax88772_info, 1544 }, { 1545 // DLink DUB-E100 H/W Ver B1 1546 USB_DEVICE (0x07d1, 0x3c05), 1547 .driver_info = (unsigned long) &ax88772_info, 1548 }, { 1549 // DLink DUB-E100 H/W Ver B1 Alternate 1550 USB_DEVICE (0x2001, 0x3c05), 1551 .driver_info = (unsigned long) &ax88772_info, 1552 }, { 1553 // DLink DUB-E100 H/W Ver C1 1554 USB_DEVICE (0x2001, 0x1a02), 1555 .driver_info = (unsigned long) &ax88772_info, 1556 }, { 1557 // Linksys USB1000 1558 USB_DEVICE (0x1737, 0x0039), 1559 .driver_info = (unsigned long) &ax88178_info, 1560 }, { 1561 // IO-DATA ETG-US2 1562 USB_DEVICE (0x04bb, 0x0930), 1563 .driver_info = (unsigned long) &ax88178_info, 1564 }, { 1565 // Belkin F5D5055 1566 USB_DEVICE(0x050d, 0x5055), 1567 .driver_info = (unsigned long) &ax88178_info, 1568 }, { 1569 // Apple USB Ethernet Adapter 1570 USB_DEVICE(0x05ac, 0x1402), 1571 .driver_info = (unsigned long) &ax88772_info, 1572 }, { 1573 // Cables-to-Go USB Ethernet Adapter 1574 USB_DEVICE(0x0b95, 0x772a), 1575 .driver_info = (unsigned long) &ax88772_info, 1576 }, { 1577 // ABOCOM for pci 1578 USB_DEVICE(0x14ea, 0xab11), 1579 .driver_info = (unsigned long) &ax88178_info, 1580 }, { 1581 // ASIX 88772a 1582 USB_DEVICE(0x0db0, 0xa877), 1583 .driver_info = (unsigned long) &ax88772_info, 1584 }, { 1585 // Asus USB Ethernet Adapter 1586 USB_DEVICE (0x0b95, 0x7e2b), 1587 .driver_info = (unsigned long)&ax88772b_info, 1588 }, { 1589 /* ASIX 88172a demo board */ 1590 USB_DEVICE(0x0b95, 0x172a), 1591 .driver_info = (unsigned long) &ax88172a_info, 1592 }, { 1593 /* 1594 * USBLINK HG20F9 "USB 2.0 LAN" 1595 * Appears to have gazumped Linksys's manufacturer ID but 1596 * doesn't (yet) conflict with any known Linksys product. 1597 */ 1598 USB_DEVICE(0x066b, 0x20f9), 1599 .driver_info = (unsigned long) &hg20f9_info, 1600 }, { 1601 // Linux Automation GmbH USB 10Base-T1L 1602 USB_DEVICE(0x33f7, 0x0004), 1603 .driver_info = (unsigned long) &lxausb_t1l_info, 1604 }, { 1605 /* LyconSys FiberGecko 100 */ 1606 USB_DEVICE(0x1d2a, 0x0801), 1607 .driver_info = (unsigned long) &lyconsys_fibergecko100_info, 1608 }, 1609 { }, // END 1610 }; 1611 MODULE_DEVICE_TABLE(usb, products); 1612 1613 static struct usb_driver asix_driver = { 1614 .name = DRIVER_NAME, 1615 .id_table = products, 1616 .probe = usbnet_probe, 1617 .suspend = asix_suspend, 1618 .resume = asix_resume, 1619 .reset_resume = asix_resume, 1620 .disconnect = usbnet_disconnect, 1621 /* usbnet enables autosuspend by default (supports_autosuspend=1). 1622 * We keep runtime-PM active for AX88772* by taking a PM usage 1623 * reference in ax88772_bind() (pm_runtime_get_noresume()) and 1624 * dropping it in unbind(), which effectively blocks autosuspend. 1625 */ 1626 .supports_autosuspend = 1, 1627 .disable_hub_initiated_lpm = 1, 1628 }; 1629 1630 module_usb_driver(asix_driver); 1631 1632 MODULE_AUTHOR("David Hollis"); 1633 MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices"); 1634 MODULE_LICENSE("GPL"); 1635