1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Clause 45 PHY support 4 */ 5 #include <linux/ethtool.h> 6 #include <linux/export.h> 7 #include <linux/mdio.h> 8 #include <linux/mii.h> 9 #include <linux/phy.h> 10 #include <linux/ethtool_netlink.h> 11 12 #include "mdio-open-alliance.h" 13 #include "phylib-internal.h" 14 15 /** 16 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities 17 * @phydev: target phy_device struct 18 */ 19 static bool genphy_c45_baset1_able(struct phy_device *phydev) 20 { 21 int val; 22 23 if (phydev->pma_extable == -ENODATA) { 24 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 25 if (val < 0) 26 return false; 27 28 phydev->pma_extable = val; 29 } 30 31 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); 32 } 33 34 /** 35 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support 36 * @phydev: target phy_device struct 37 */ 38 static bool genphy_c45_pma_can_sleep(struct phy_device *phydev) 39 { 40 int stat1; 41 42 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1); 43 if (stat1 < 0) 44 return false; 45 46 return !!(stat1 & MDIO_STAT1_LPOWERABLE); 47 } 48 49 /** 50 * genphy_c45_pma_resume - wakes up the PMA module 51 * @phydev: target phy_device struct 52 */ 53 int genphy_c45_pma_resume(struct phy_device *phydev) 54 { 55 if (!genphy_c45_pma_can_sleep(phydev)) 56 return -EOPNOTSUPP; 57 58 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 59 MDIO_CTRL1_LPOWER); 60 } 61 EXPORT_SYMBOL_GPL(genphy_c45_pma_resume); 62 63 /** 64 * genphy_c45_pma_suspend - suspends the PMA module 65 * @phydev: target phy_device struct 66 */ 67 int genphy_c45_pma_suspend(struct phy_device *phydev) 68 { 69 if (!genphy_c45_pma_can_sleep(phydev)) 70 return -EOPNOTSUPP; 71 72 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 73 MDIO_CTRL1_LPOWER); 74 } 75 EXPORT_SYMBOL_GPL(genphy_c45_pma_suspend); 76 77 /** 78 * genphy_c45_pma_baset1_setup_master_slave - configures forced master/slave 79 * role of BaseT1 devices. 80 * @phydev: target phy_device struct 81 */ 82 int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev) 83 { 84 int ctl = 0; 85 86 switch (phydev->master_slave_set) { 87 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 88 case MASTER_SLAVE_CFG_MASTER_FORCE: 89 ctl = MDIO_PMA_PMD_BT1_CTRL_CFG_MST; 90 break; 91 case MASTER_SLAVE_CFG_SLAVE_FORCE: 92 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 93 break; 94 case MASTER_SLAVE_CFG_UNKNOWN: 95 case MASTER_SLAVE_CFG_UNSUPPORTED: 96 return 0; 97 default: 98 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 99 return -EOPNOTSUPP; 100 } 101 102 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, 103 MDIO_PMA_PMD_BT1_CTRL_CFG_MST, ctl); 104 } 105 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_setup_master_slave); 106 107 /** 108 * genphy_c45_pma_setup_forced - configures a forced speed 109 * @phydev: target phy_device struct 110 */ 111 int genphy_c45_pma_setup_forced(struct phy_device *phydev) 112 { 113 int bt1_ctrl, ctrl1, ctrl2, ret; 114 115 /* Half duplex is not supported */ 116 if (phydev->duplex != DUPLEX_FULL) 117 return -EINVAL; 118 119 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 120 if (ctrl1 < 0) 121 return ctrl1; 122 123 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); 124 if (ctrl2 < 0) 125 return ctrl2; 126 127 ctrl1 &= ~MDIO_CTRL1_SPEEDSEL; 128 /* 129 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1 130 * in 802.3-2012 and 802.3-2015. 131 */ 132 ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30); 133 134 switch (phydev->speed) { 135 case SPEED_10: 136 if (genphy_c45_baset1_able(phydev)) 137 ctrl2 |= MDIO_PMA_CTRL2_BASET1; 138 else 139 ctrl2 |= MDIO_PMA_CTRL2_10BT; 140 break; 141 case SPEED_100: 142 ctrl1 |= MDIO_PMA_CTRL1_SPEED100; 143 ctrl2 |= MDIO_PMA_CTRL2_100BTX; 144 break; 145 case SPEED_1000: 146 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000; 147 /* Assume 1000base-T */ 148 ctrl2 |= MDIO_PMA_CTRL2_1000BT; 149 break; 150 case SPEED_2500: 151 ctrl1 |= MDIO_PMA_CTRL1_SPEED2_5G; 152 /* Assume 2.5Gbase-T */ 153 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT; 154 break; 155 case SPEED_5000: 156 ctrl1 |= MDIO_PMA_CTRL1_SPEED5G; 157 /* Assume 5Gbase-T */ 158 ctrl2 |= MDIO_PMA_CTRL2_5GBT; 159 break; 160 case SPEED_10000: 161 ctrl1 |= MDIO_CTRL1_SPEED10G; 162 /* Assume 10Gbase-T */ 163 ctrl2 |= MDIO_PMA_CTRL2_10GBT; 164 break; 165 default: 166 return -EINVAL; 167 } 168 169 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); 170 if (ret < 0) 171 return ret; 172 173 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); 174 if (ret < 0) 175 return ret; 176 177 if (genphy_c45_baset1_able(phydev)) { 178 ret = genphy_c45_pma_baset1_setup_master_slave(phydev); 179 if (ret < 0) 180 return ret; 181 182 bt1_ctrl = 0; 183 if (phydev->speed == SPEED_1000) 184 bt1_ctrl = MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000; 185 186 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, 187 MDIO_PMA_PMD_BT1_CTRL_STRAP, bt1_ctrl); 188 if (ret < 0) 189 return ret; 190 } 191 192 return genphy_c45_an_disable_aneg(phydev); 193 } 194 EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced); 195 196 /* Sets master/slave preference and supported technologies. 197 * The preference is set in the BIT(4) of BASE-T1 AN 198 * advertisement register 7.515 and whether the status 199 * is forced or not, it is set in the BIT(12) of BASE-T1 200 * AN advertisement register 7.514. 201 * Sets 10BASE-T1L Ability BIT(14) in BASE-T1 autonegotiation 202 * advertisement register [31:16] if supported. 203 */ 204 static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev) 205 { 206 u16 adv_l_mask, adv_l = 0; 207 u16 adv_m_mask, adv_m = 0; 208 int changed = 0; 209 int ret; 210 211 adv_l_mask = MDIO_AN_T1_ADV_L_FORCE_MS | MDIO_AN_T1_ADV_L_PAUSE_CAP | 212 MDIO_AN_T1_ADV_L_PAUSE_ASYM; 213 adv_m_mask = MDIO_AN_T1_ADV_M_1000BT1 | MDIO_AN_T1_ADV_M_100BT1 | 214 MDIO_AN_T1_ADV_M_MST | MDIO_AN_T1_ADV_M_B10L; 215 216 switch (phydev->master_slave_set) { 217 case MASTER_SLAVE_CFG_MASTER_FORCE: 218 adv_m |= MDIO_AN_T1_ADV_M_MST; 219 fallthrough; 220 case MASTER_SLAVE_CFG_SLAVE_FORCE: 221 adv_l |= MDIO_AN_T1_ADV_L_FORCE_MS; 222 break; 223 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 224 adv_m |= MDIO_AN_T1_ADV_M_MST; 225 fallthrough; 226 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 227 break; 228 case MASTER_SLAVE_CFG_UNKNOWN: 229 case MASTER_SLAVE_CFG_UNSUPPORTED: 230 /* if master/slave role is not specified, do not overwrite it */ 231 adv_l_mask &= ~MDIO_AN_T1_ADV_L_FORCE_MS; 232 adv_m_mask &= ~MDIO_AN_T1_ADV_M_MST; 233 break; 234 default: 235 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 236 return -EOPNOTSUPP; 237 } 238 239 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising); 240 241 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L, 242 adv_l_mask, adv_l); 243 if (ret < 0) 244 return ret; 245 if (ret > 0) 246 changed = 1; 247 248 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising); 249 250 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M, 251 adv_m_mask, adv_m); 252 if (ret < 0) 253 return ret; 254 if (ret > 0) 255 changed = 1; 256 257 return changed; 258 } 259 260 /** 261 * genphy_c45_an_config_aneg - configure advertisement registers 262 * @phydev: target phy_device struct 263 * 264 * Configure advertisement registers based on modes set in phydev->advertising 265 * 266 * Returns negative errno code on failure, 0 if advertisement didn't change, 267 * or 1 if advertised modes changed. 268 */ 269 int genphy_c45_an_config_aneg(struct phy_device *phydev) 270 { 271 int changed = 0, ret; 272 u32 adv; 273 274 linkmode_and(phydev->advertising, phydev->advertising, 275 phydev->supported); 276 277 ret = genphy_c45_an_config_eee_aneg(phydev); 278 if (ret < 0) 279 return ret; 280 else if (ret) 281 changed = true; 282 283 if (genphy_c45_baset1_able(phydev)) 284 return genphy_c45_baset1_an_config_aneg(phydev); 285 286 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); 287 288 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, 289 ADVERTISE_ALL | ADVERTISE_100BASE4 | 290 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 291 adv); 292 if (ret < 0) 293 return ret; 294 if (ret > 0) 295 changed = 1; 296 297 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 298 299 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 300 MDIO_AN_10GBT_CTRL_ADV10G | 301 MDIO_AN_10GBT_CTRL_ADV5G | 302 MDIO_AN_10GBT_CTRL_ADV2_5G, adv); 303 if (ret < 0) 304 return ret; 305 if (ret > 0) 306 changed = 1; 307 308 return changed; 309 } 310 EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg); 311 312 /** 313 * genphy_c45_an_disable_aneg - disable auto-negotiation 314 * @phydev: target phy_device struct 315 * 316 * Disable auto-negotiation in the Clause 45 PHY. The link parameters 317 * are controlled through the PMA/PMD MMD registers. 318 * 319 * Returns zero on success, negative errno code on failure. 320 */ 321 int genphy_c45_an_disable_aneg(struct phy_device *phydev) 322 { 323 u16 reg = MDIO_CTRL1; 324 325 if (genphy_c45_baset1_able(phydev)) 326 reg = MDIO_AN_T1_CTRL; 327 328 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, 329 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 330 } 331 EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg); 332 333 /** 334 * genphy_c45_restart_aneg - Enable and restart auto-negotiation 335 * @phydev: target phy_device struct 336 * 337 * This assumes that the auto-negotiation MMD is present. 338 * 339 * Enable and restart auto-negotiation. 340 */ 341 int genphy_c45_restart_aneg(struct phy_device *phydev) 342 { 343 u16 reg = MDIO_CTRL1; 344 345 if (genphy_c45_baset1_able(phydev)) 346 reg = MDIO_AN_T1_CTRL; 347 348 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg, 349 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 350 } 351 EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg); 352 353 /** 354 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation 355 * @phydev: target phy_device struct 356 * @restart: whether aneg restart is requested 357 * 358 * This assumes that the auto-negotiation MMD is present. 359 * 360 * Check, and restart auto-negotiation if needed. 361 */ 362 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart) 363 { 364 u16 reg = MDIO_CTRL1; 365 int ret; 366 367 if (genphy_c45_baset1_able(phydev)) 368 reg = MDIO_AN_T1_CTRL; 369 370 if (!restart) { 371 /* Configure and restart aneg if it wasn't set before */ 372 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg); 373 if (ret < 0) 374 return ret; 375 376 if (!(ret & MDIO_AN_CTRL1_ENABLE)) 377 restart = true; 378 } 379 380 if (restart) 381 return genphy_c45_restart_aneg(phydev); 382 383 return 0; 384 } 385 EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg); 386 387 /** 388 * genphy_c45_aneg_done - return auto-negotiation complete status 389 * @phydev: target phy_device struct 390 * 391 * This assumes that the auto-negotiation MMD is present. 392 * 393 * Reads the status register from the auto-negotiation MMD, returning: 394 * - positive if auto-negotiation is complete 395 * - negative errno code on error 396 * - zero otherwise 397 */ 398 int genphy_c45_aneg_done(struct phy_device *phydev) 399 { 400 int reg = MDIO_STAT1; 401 int val; 402 403 if (genphy_c45_baset1_able(phydev)) 404 reg = MDIO_AN_T1_STAT; 405 406 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); 407 408 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0; 409 } 410 EXPORT_SYMBOL_GPL(genphy_c45_aneg_done); 411 412 /** 413 * genphy_c45_read_link - read the overall link status from the MMDs 414 * @phydev: target phy_device struct 415 * 416 * Read the link status from the specified MMDs, and if they all indicate 417 * that the link is up, set phydev->link to 1. If an error is encountered, 418 * a negative errno will be returned, otherwise zero. 419 */ 420 int genphy_c45_read_link(struct phy_device *phydev) 421 { 422 u32 mmd_mask = MDIO_DEVS_PMAPMD; 423 int val, devad; 424 bool link = true; 425 426 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { 427 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); 428 if (val < 0) 429 return val; 430 431 /* Autoneg is being started, therefore disregard current 432 * link status and report link as down. 433 */ 434 if (val & MDIO_AN_CTRL1_RESTART) { 435 phydev->link = 0; 436 return 0; 437 } 438 } 439 440 while (mmd_mask && link) { 441 devad = __ffs(mmd_mask); 442 mmd_mask &= ~BIT(devad); 443 444 /* The link state is latched low so that momentary link 445 * drops can be detected. Do not double-read the status 446 * in polling mode to detect such short link drops except 447 * the link was already down. 448 */ 449 if (!phy_polling_mode(phydev) || !phydev->link) { 450 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 451 if (val < 0) 452 return val; 453 else if (val & MDIO_STAT1_LSTATUS) 454 continue; 455 } 456 457 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 458 if (val < 0) 459 return val; 460 461 if (!(val & MDIO_STAT1_LSTATUS)) 462 link = false; 463 } 464 465 phydev->link = link; 466 467 return 0; 468 } 469 EXPORT_SYMBOL_GPL(genphy_c45_read_link); 470 471 /* Read the Clause 45 defined BASE-T1 AN (7.513) status register to check 472 * if autoneg is complete. If so read the BASE-T1 Autonegotiation 473 * Advertisement registers filling in the link partner advertisement, 474 * pause and asym_pause members in phydev. 475 */ 476 static int genphy_c45_baset1_read_lpa(struct phy_device *phydev) 477 { 478 int val; 479 480 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); 481 if (val < 0) 482 return val; 483 484 if (!(val & MDIO_AN_STAT1_COMPLETE)) { 485 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising); 486 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0); 487 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0); 488 489 phydev->pause = false; 490 phydev->asym_pause = false; 491 492 return 0; 493 } 494 495 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1); 496 497 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L); 498 if (val < 0) 499 return val; 500 501 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val); 502 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP; 503 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM; 504 505 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M); 506 if (val < 0) 507 return val; 508 509 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val); 510 511 return 0; 512 } 513 514 /** 515 * genphy_c45_read_lpa - read the link partner advertisement and pause 516 * @phydev: target phy_device struct 517 * 518 * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers, 519 * filling in the link partner advertisement, pause and asym_pause members 520 * in @phydev. This assumes that the auto-negotiation MMD is present, and 521 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected 522 * to fill in the remainder of the link partner advert from vendor registers. 523 */ 524 int genphy_c45_read_lpa(struct phy_device *phydev) 525 { 526 int val; 527 528 if (genphy_c45_baset1_able(phydev)) 529 return genphy_c45_baset1_read_lpa(phydev); 530 531 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 532 if (val < 0) 533 return val; 534 535 if (!(val & MDIO_AN_STAT1_COMPLETE)) { 536 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 537 phydev->lp_advertising); 538 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 539 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0); 540 phydev->pause = false; 541 phydev->asym_pause = false; 542 543 return 0; 544 } 545 546 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 547 val & MDIO_AN_STAT1_LPABLE); 548 549 /* Read the link partner's base page advertisement */ 550 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); 551 if (val < 0) 552 return val; 553 554 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); 555 phydev->pause = val & LPA_PAUSE_CAP; 556 phydev->asym_pause = val & LPA_PAUSE_ASYM; 557 558 /* Read the link partner's 10G advertisement */ 559 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 560 if (val < 0) 561 return val; 562 563 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); 564 565 return 0; 566 } 567 EXPORT_SYMBOL_GPL(genphy_c45_read_lpa); 568 569 /** 570 * genphy_c45_pma_baset1_read_master_slave - read forced master/slave 571 * configuration 572 * @phydev: target phy_device struct 573 */ 574 int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev) 575 { 576 int val; 577 578 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 579 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 580 581 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL); 582 if (val < 0) 583 return val; 584 585 if (val & MDIO_PMA_PMD_BT1_CTRL_CFG_MST) { 586 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 587 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 588 } else { 589 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 590 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 591 } 592 593 return 0; 594 } 595 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_master_slave); 596 597 /** 598 * genphy_c45_read_pma - read link speed etc from PMA 599 * @phydev: target phy_device struct 600 */ 601 int genphy_c45_read_pma(struct phy_device *phydev) 602 { 603 int val; 604 605 linkmode_zero(phydev->lp_advertising); 606 607 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 608 if (val < 0) 609 return val; 610 611 switch (val & MDIO_CTRL1_SPEEDSEL) { 612 case 0: 613 phydev->speed = SPEED_10; 614 break; 615 case MDIO_PMA_CTRL1_SPEED100: 616 phydev->speed = SPEED_100; 617 break; 618 case MDIO_PMA_CTRL1_SPEED1000: 619 phydev->speed = SPEED_1000; 620 break; 621 case MDIO_PMA_CTRL1_SPEED2_5G: 622 phydev->speed = SPEED_2500; 623 break; 624 case MDIO_PMA_CTRL1_SPEED5G: 625 phydev->speed = SPEED_5000; 626 break; 627 case MDIO_CTRL1_SPEED10G: 628 phydev->speed = SPEED_10000; 629 break; 630 default: 631 phydev->speed = SPEED_UNKNOWN; 632 break; 633 } 634 635 phydev->duplex = DUPLEX_FULL; 636 637 if (genphy_c45_baset1_able(phydev)) { 638 val = genphy_c45_pma_baset1_read_master_slave(phydev); 639 if (val < 0) 640 return val; 641 } 642 643 return 0; 644 } 645 EXPORT_SYMBOL_GPL(genphy_c45_read_pma); 646 647 /** 648 * genphy_c45_read_mdix - read mdix status from PMA 649 * @phydev: target phy_device struct 650 */ 651 int genphy_c45_read_mdix(struct phy_device *phydev) 652 { 653 int val; 654 655 if (phydev->speed == SPEED_10000) { 656 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 657 MDIO_PMA_10GBT_SWAPPOL); 658 if (val < 0) 659 return val; 660 661 switch (val) { 662 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX: 663 phydev->mdix = ETH_TP_MDI; 664 break; 665 666 case 0: 667 phydev->mdix = ETH_TP_MDI_X; 668 break; 669 670 default: 671 phydev->mdix = ETH_TP_MDI_INVALID; 672 break; 673 } 674 } 675 676 return 0; 677 } 678 EXPORT_SYMBOL_GPL(genphy_c45_read_mdix); 679 680 /** 681 * genphy_c45_write_eee_adv - write advertised EEE link modes 682 * @phydev: target phy_device struct 683 * @adv: the linkmode advertisement settings 684 */ 685 static int genphy_c45_write_eee_adv(struct phy_device *phydev, 686 unsigned long *adv) 687 { 688 int val, changed = 0; 689 690 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { 691 val = linkmode_to_mii_eee_cap1_t(adv); 692 693 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1 694 * (Register 7.60) 695 */ 696 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, 697 MDIO_AN_EEE_ADV, 698 MDIO_EEE_100TX | MDIO_EEE_1000T | 699 MDIO_EEE_10GT | MDIO_EEE_1000KX | 700 MDIO_EEE_10GKX4 | MDIO_EEE_10GKR, 701 val); 702 if (val < 0) 703 return val; 704 if (val > 0) 705 changed = 1; 706 } 707 708 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { 709 val = linkmode_to_mii_eee_cap2_t(adv); 710 711 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2 712 * (Register 7.62) 713 */ 714 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, 715 MDIO_AN_EEE_ADV2, 716 MDIO_EEE_2_5GT | MDIO_EEE_5GT, 717 val); 718 if (val < 0) 719 return val; 720 if (val > 0) 721 changed = 1; 722 } 723 724 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 725 phydev->supported_eee)) { 726 val = linkmode_adv_to_mii_10base_t1_t(adv); 727 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register 728 * (Register 7.526) 729 */ 730 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, 731 MDIO_AN_10BT1_AN_CTRL, 732 MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L, 733 val); 734 if (val < 0) 735 return val; 736 if (val > 0) 737 changed = 1; 738 } 739 740 return changed; 741 } 742 743 /** 744 * genphy_c45_read_eee_adv - read advertised EEE link modes 745 * @phydev: target phy_device struct 746 * @adv: the linkmode advertisement status 747 */ 748 int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv) 749 { 750 int val; 751 752 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { 753 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1 754 * (Register 7.60) 755 */ 756 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 757 if (val < 0) 758 return val; 759 760 mii_eee_cap1_mod_linkmode_t(adv, val); 761 } 762 763 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { 764 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2 765 * (Register 7.62) 766 */ 767 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2); 768 if (val < 0) 769 return val; 770 771 mii_eee_cap2_mod_linkmode_adv_t(adv, val); 772 } 773 774 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 775 phydev->supported_eee)) { 776 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register 777 * (Register 7.526) 778 */ 779 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_CTRL); 780 if (val < 0) 781 return val; 782 783 mii_10base_t1_adv_mod_linkmode_t(adv, val); 784 } 785 786 return 0; 787 } 788 789 /** 790 * genphy_c45_read_eee_lpa - read advertised LP EEE link modes 791 * @phydev: target phy_device struct 792 * @lpa: the linkmode LP advertisement status 793 */ 794 static int genphy_c45_read_eee_lpa(struct phy_device *phydev, 795 unsigned long *lpa) 796 { 797 int val; 798 799 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { 800 /* IEEE 802.3-2018 45.2.7.14 EEE link partner ability 1 801 * (Register 7.61) 802 */ 803 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 804 if (val < 0) 805 return val; 806 807 mii_eee_cap1_mod_linkmode_t(lpa, val); 808 } 809 810 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { 811 /* IEEE 802.3-2022 45.2.7.17 EEE link partner ability 2 812 * (Register 7.63) 813 */ 814 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE2); 815 if (val < 0) 816 return val; 817 818 mii_eee_cap2_mod_linkmode_adv_t(lpa, val); 819 } 820 821 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 822 phydev->supported_eee)) { 823 /* IEEE 802.3cg-2019 45.2.7.26 10BASE-T1 AN status register 824 * (Register 7.527) 825 */ 826 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_STAT); 827 if (val < 0) 828 return val; 829 830 mii_10base_t1_adv_mod_linkmode_t(lpa, val); 831 } 832 833 return 0; 834 } 835 836 /** 837 * genphy_c45_read_eee_cap1 - read supported EEE link modes from register 3.20 838 * @phydev: target phy_device struct 839 */ 840 static int genphy_c45_read_eee_cap1(struct phy_device *phydev) 841 { 842 int val; 843 844 /* IEEE 802.3-2018 45.2.3.10 EEE control and capability 1 845 * (Register 3.20) 846 */ 847 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 848 if (val < 0) 849 return val; 850 851 /* The 802.3 2018 standard says the top 2 bits are reserved and should 852 * read as 0. Also, it seems unlikely anybody will build a PHY which 853 * supports 100GBASE-R deep sleep all the way down to 100BASE-TX EEE. 854 * If MDIO_PCS_EEE_ABLE is 0xffff assume EEE is not supported. 855 */ 856 if (val == 0xffff) 857 return 0; 858 859 mii_eee_cap1_mod_linkmode_t(phydev->supported_eee, val); 860 861 /* Some buggy devices indicate EEE link modes in MDIO_PCS_EEE_ABLE 862 * which they don't support as indicated by BMSR, ESTATUS etc. 863 */ 864 linkmode_and(phydev->supported_eee, phydev->supported_eee, 865 phydev->supported); 866 867 return 0; 868 } 869 870 /** 871 * genphy_c45_read_eee_cap2 - read supported EEE link modes from register 3.21 872 * @phydev: target phy_device struct 873 */ 874 static int genphy_c45_read_eee_cap2(struct phy_device *phydev) 875 { 876 int val; 877 878 /* IEEE 802.3-2022 45.2.3.11 EEE control and capability 2 879 * (Register 3.21) 880 */ 881 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE2); 882 if (val < 0) 883 return val; 884 885 /* IEEE 802.3-2022 45.2.3.11 says 9 bits are reserved. */ 886 if (val == 0xffff) 887 return 0; 888 889 mii_eee_cap2_mod_linkmode_sup_t(phydev->supported_eee, val); 890 891 return 0; 892 } 893 894 /** 895 * genphy_c45_read_eee_abilities - read supported EEE link modes 896 * @phydev: target phy_device struct 897 */ 898 int genphy_c45_read_eee_abilities(struct phy_device *phydev) 899 { 900 int val; 901 902 /* There is not indicator whether optional register 903 * "EEE control and capability 1" (3.20) is supported. Read it only 904 * on devices with appropriate linkmodes. 905 */ 906 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) { 907 val = genphy_c45_read_eee_cap1(phydev); 908 if (val) 909 return val; 910 } 911 912 /* Same for cap2 (3.21) */ 913 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP2_FEATURES)) { 914 val = genphy_c45_read_eee_cap2(phydev); 915 if (val) 916 return val; 917 } 918 919 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 920 phydev->supported)) { 921 /* IEEE 802.3cg-2019 45.2.1.186b 10BASE-T1L PMA status register 922 * (Register 1.2295) 923 */ 924 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT); 925 if (val < 0) 926 return val; 927 928 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 929 phydev->supported_eee, 930 val & MDIO_PMA_10T1L_STAT_EEE); 931 } 932 933 return 0; 934 } 935 EXPORT_SYMBOL_GPL(genphy_c45_read_eee_abilities); 936 937 /** 938 * genphy_c45_an_config_eee_aneg - configure EEE advertisement 939 * @phydev: target phy_device struct 940 */ 941 int genphy_c45_an_config_eee_aneg(struct phy_device *phydev) 942 { 943 /* Writing MMD AN advertisements while autoneg is disabled has no 944 * effect on link-partner negotiation, but on some PHYs (e.g. the 945 * Broadcom BCM54213PE) the write itself disturbs the receive 946 * datapath. Skip it. 947 */ 948 if (phydev->autoneg == AUTONEG_DISABLE) 949 return 0; 950 951 if (!phydev->eee_cfg.eee_enabled) { 952 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv) = {}; 953 954 return genphy_c45_write_eee_adv(phydev, adv); 955 } 956 957 return genphy_c45_write_eee_adv(phydev, phydev->advertising_eee); 958 } 959 EXPORT_SYMBOL_GPL(genphy_c45_an_config_eee_aneg); 960 961 /** 962 * genphy_c45_pma_baset1_read_abilities - read supported baset1 link modes from PMA 963 * @phydev: target phy_device struct 964 * 965 * Read the supported link modes from the extended BASE-T1 ability register 966 */ 967 int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev) 968 { 969 int val; 970 971 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1); 972 if (val < 0) 973 return val; 974 975 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 976 phydev->supported, 977 val & MDIO_PMA_PMD_BT1_B10L_ABLE); 978 979 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT, 980 phydev->supported, 981 val & MDIO_PMA_PMD_BT1_B100_ABLE); 982 983 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT1_Full_BIT, 984 phydev->supported, 985 val & MDIO_PMA_PMD_BT1_B1000_ABLE); 986 987 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); 988 if (val < 0) 989 return val; 990 991 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 992 phydev->supported, 993 val & MDIO_AN_STAT1_ABLE); 994 995 return 0; 996 } 997 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_abilities); 998 999 /** 1000 * genphy_c45_pma_read_ext_abilities - read supported link modes from PMA 1001 * @phydev: target phy_device struct 1002 * 1003 * Read the supported link modes from the PMA/PMD extended ability register 1004 * (Register 1.11). 1005 */ 1006 int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev) 1007 { 1008 int val; 1009 1010 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 1011 if (val < 0) 1012 return val; 1013 1014 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 1015 phydev->supported, 1016 val & MDIO_PMA_EXTABLE_10GBLRM); 1017 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1018 phydev->supported, 1019 val & MDIO_PMA_EXTABLE_10GBT); 1020 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 1021 phydev->supported, 1022 val & MDIO_PMA_EXTABLE_10GBKX4); 1023 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1024 phydev->supported, 1025 val & MDIO_PMA_EXTABLE_10GBKR); 1026 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1027 phydev->supported, 1028 val & MDIO_PMA_EXTABLE_1000BT); 1029 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1030 phydev->supported, 1031 val & MDIO_PMA_EXTABLE_1000BKX); 1032 1033 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1034 phydev->supported, 1035 val & MDIO_PMA_EXTABLE_100BTX); 1036 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1037 phydev->supported, 1038 val & MDIO_PMA_EXTABLE_100BTX); 1039 1040 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, 1041 phydev->supported, 1042 val & MDIO_PMA_EXTABLE_10BT); 1043 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, 1044 phydev->supported, 1045 val & MDIO_PMA_EXTABLE_10BT); 1046 1047 if (val & MDIO_PMA_EXTABLE_NBT) { 1048 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 1049 MDIO_PMA_NG_EXTABLE); 1050 if (val < 0) 1051 return val; 1052 1053 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1054 phydev->supported, 1055 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 1056 1057 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1058 phydev->supported, 1059 val & MDIO_PMA_NG_EXTABLE_5GBT); 1060 } 1061 1062 if (val & MDIO_PMA_EXTABLE_BT1) { 1063 val = genphy_c45_pma_baset1_read_abilities(phydev); 1064 if (val < 0) 1065 return val; 1066 } 1067 1068 return 0; 1069 } 1070 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_ext_abilities); 1071 1072 /** 1073 * genphy_c45_pma_read_abilities - read supported link modes from PMA 1074 * @phydev: target phy_device struct 1075 * 1076 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit 1077 * 1.8.9 is set, the list of supported modes is build using the values in the 1078 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related 1079 * modes. If bit 1.11.14 is set, then the list is also extended with the modes 1080 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and 1081 * 5GBASET are supported. 1082 */ 1083 int genphy_c45_pma_read_abilities(struct phy_device *phydev) 1084 { 1085 int val; 1086 1087 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 1088 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { 1089 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 1090 if (val < 0) 1091 return val; 1092 1093 if (val & MDIO_AN_STAT1_ABLE) 1094 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 1095 phydev->supported); 1096 } 1097 1098 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); 1099 if (val < 0) 1100 return val; 1101 1102 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1103 phydev->supported, 1104 val & MDIO_PMA_STAT2_10GBSR); 1105 1106 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 1107 phydev->supported, 1108 val & MDIO_PMA_STAT2_10GBLR); 1109 1110 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 1111 phydev->supported, 1112 val & MDIO_PMA_STAT2_10GBER); 1113 1114 if (val & MDIO_PMA_STAT2_EXTABLE) { 1115 val = genphy_c45_pma_read_ext_abilities(phydev); 1116 if (val < 0) 1117 return val; 1118 } 1119 1120 /* This is optional functionality. If not supported, we may get an error 1121 * which should be ignored. 1122 */ 1123 genphy_c45_read_eee_abilities(phydev); 1124 1125 return 0; 1126 } 1127 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities); 1128 1129 /* Read master/slave preference from registers. 1130 * The preference is read from the BIT(4) of BASE-T1 AN 1131 * advertisement register 7.515 and whether the preference 1132 * is forced or not, it is read from BASE-T1 AN advertisement 1133 * register 7.514. 1134 */ 1135 int genphy_c45_baset1_read_status(struct phy_device *phydev) 1136 { 1137 int ret; 1138 int cfg; 1139 1140 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1141 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1142 1143 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L); 1144 if (ret < 0) 1145 return ret; 1146 1147 cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M); 1148 if (cfg < 0) 1149 return cfg; 1150 1151 if (ret & MDIO_AN_T1_ADV_L_FORCE_MS) { 1152 if (cfg & MDIO_AN_T1_ADV_M_MST) 1153 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 1154 else 1155 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 1156 } else { 1157 if (cfg & MDIO_AN_T1_ADV_M_MST) 1158 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED; 1159 else 1160 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED; 1161 } 1162 1163 return 0; 1164 } 1165 EXPORT_SYMBOL_GPL(genphy_c45_baset1_read_status); 1166 1167 /** 1168 * genphy_c45_read_status - read PHY status 1169 * @phydev: target phy_device struct 1170 * 1171 * Reads status from PHY and sets phy_device members accordingly. 1172 */ 1173 int genphy_c45_read_status(struct phy_device *phydev) 1174 { 1175 int ret; 1176 1177 ret = genphy_c45_read_link(phydev); 1178 if (ret) 1179 return ret; 1180 1181 phydev->speed = SPEED_UNKNOWN; 1182 phydev->duplex = DUPLEX_UNKNOWN; 1183 phydev->pause = false; 1184 phydev->asym_pause = false; 1185 1186 if (phydev->autoneg == AUTONEG_ENABLE) { 1187 ret = genphy_c45_read_lpa(phydev); 1188 if (ret) 1189 return ret; 1190 1191 if (genphy_c45_baset1_able(phydev)) { 1192 ret = genphy_c45_baset1_read_status(phydev); 1193 if (ret < 0) 1194 return ret; 1195 } 1196 1197 phy_resolve_aneg_linkmode(phydev); 1198 } else { 1199 ret = genphy_c45_read_pma(phydev); 1200 } 1201 1202 return ret; 1203 } 1204 EXPORT_SYMBOL_GPL(genphy_c45_read_status); 1205 1206 /** 1207 * genphy_c45_config_aneg - restart auto-negotiation or forced setup 1208 * @phydev: target phy_device struct 1209 * 1210 * Description: If auto-negotiation is enabled, we configure the 1211 * advertising, and then restart auto-negotiation. If it is not 1212 * enabled, then we force a configuration. 1213 */ 1214 int genphy_c45_config_aneg(struct phy_device *phydev) 1215 { 1216 bool changed = false; 1217 int ret; 1218 1219 if (phydev->autoneg == AUTONEG_DISABLE) 1220 return genphy_c45_pma_setup_forced(phydev); 1221 1222 ret = genphy_c45_an_config_aneg(phydev); 1223 if (ret < 0) 1224 return ret; 1225 if (ret > 0) 1226 changed = true; 1227 1228 return genphy_c45_check_and_restart_aneg(phydev, changed); 1229 } 1230 EXPORT_SYMBOL_GPL(genphy_c45_config_aneg); 1231 1232 /* The gen10g_* functions are the old Clause 45 stub */ 1233 1234 int gen10g_config_aneg(struct phy_device *phydev) 1235 { 1236 return 0; 1237 } 1238 EXPORT_SYMBOL_GPL(gen10g_config_aneg); 1239 1240 int genphy_c45_loopback(struct phy_device *phydev, bool enable, int speed) 1241 { 1242 if (enable && speed) 1243 return -EOPNOTSUPP; 1244 1245 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, 1246 MDIO_PCS_CTRL1_LOOPBACK, 1247 enable ? MDIO_PCS_CTRL1_LOOPBACK : 0); 1248 } 1249 EXPORT_SYMBOL_GPL(genphy_c45_loopback); 1250 1251 /** 1252 * genphy_c45_fast_retrain - configure fast retrain registers 1253 * @phydev: target phy_device struct 1254 * @enable: enable fast retrain or not 1255 * 1256 * Description: If fast-retrain is enabled, we configure PHY as 1257 * advertising fast retrain capable and THP Bypass Request, then 1258 * enable fast retrain. If it is not enabled, we configure fast 1259 * retrain disabled. 1260 */ 1261 int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable) 1262 { 1263 int ret; 1264 1265 if (!enable) 1266 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, 1267 MDIO_PMA_10GBR_FSRT_ENABLE); 1268 1269 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) { 1270 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 1271 MDIO_AN_10GBT_CTRL_ADVFSRT2_5G); 1272 if (ret) 1273 return ret; 1274 1275 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2, 1276 MDIO_AN_THP_BP2_5GT); 1277 if (ret) 1278 return ret; 1279 } 1280 1281 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, 1282 MDIO_PMA_10GBR_FSRT_ENABLE); 1283 } 1284 EXPORT_SYMBOL_GPL(genphy_c45_fast_retrain); 1285 1286 /** 1287 * genphy_c45_plca_get_cfg - get PLCA configuration from standard registers 1288 * @phydev: target phy_device struct 1289 * @plca_cfg: output structure to store the PLCA configuration 1290 * 1291 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA 1292 * Management Registers specifications, this function can be used to retrieve 1293 * the current PLCA configuration from the standard registers in MMD 31. 1294 */ 1295 int genphy_c45_plca_get_cfg(struct phy_device *phydev, 1296 struct phy_plca_cfg *plca_cfg) 1297 { 1298 int ret; 1299 1300 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER); 1301 if (ret < 0) 1302 return ret; 1303 1304 if ((ret & MDIO_OATC14_PLCA_IDM) != OATC14_IDM) 1305 return -ENODEV; 1306 1307 plca_cfg->version = ret & ~MDIO_OATC14_PLCA_IDM; 1308 1309 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0); 1310 if (ret < 0) 1311 return ret; 1312 1313 plca_cfg->enabled = !!(ret & MDIO_OATC14_PLCA_EN); 1314 1315 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1); 1316 if (ret < 0) 1317 return ret; 1318 1319 plca_cfg->node_cnt = (ret & MDIO_OATC14_PLCA_NCNT) >> 8; 1320 plca_cfg->node_id = (ret & MDIO_OATC14_PLCA_ID); 1321 1322 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR); 1323 if (ret < 0) 1324 return ret; 1325 1326 plca_cfg->to_tmr = ret & MDIO_OATC14_PLCA_TOT; 1327 1328 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST); 1329 if (ret < 0) 1330 return ret; 1331 1332 plca_cfg->burst_cnt = (ret & MDIO_OATC14_PLCA_MAXBC) >> 8; 1333 plca_cfg->burst_tmr = (ret & MDIO_OATC14_PLCA_BTMR); 1334 1335 return 0; 1336 } 1337 EXPORT_SYMBOL_GPL(genphy_c45_plca_get_cfg); 1338 1339 /** 1340 * genphy_c45_plca_set_cfg - set PLCA configuration using standard registers 1341 * @phydev: target phy_device struct 1342 * @plca_cfg: structure containing the PLCA configuration. Fields set to -1 are 1343 * not to be changed. 1344 * 1345 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA 1346 * Management Registers specifications, this function can be used to modify 1347 * the PLCA configuration using the standard registers in MMD 31. 1348 */ 1349 int genphy_c45_plca_set_cfg(struct phy_device *phydev, 1350 const struct phy_plca_cfg *plca_cfg) 1351 { 1352 u16 val = 0; 1353 int ret; 1354 1355 // PLCA IDVER is read-only 1356 if (plca_cfg->version >= 0) 1357 return -EINVAL; 1358 1359 // first of all, disable PLCA if required 1360 if (plca_cfg->enabled == 0) { 1361 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 1362 MDIO_OATC14_PLCA_CTRL0, 1363 MDIO_OATC14_PLCA_EN); 1364 1365 if (ret < 0) 1366 return ret; 1367 } 1368 1369 // check if we need to set the PLCA node count, node ID, or both 1370 if (plca_cfg->node_cnt >= 0 || plca_cfg->node_id >= 0) { 1371 /* if one between node count and node ID is -not- to be 1372 * changed, read the register to later perform merge/purge of 1373 * the configuration as appropriate 1374 */ 1375 if (plca_cfg->node_cnt < 0 || plca_cfg->node_id < 0) { 1376 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1377 MDIO_OATC14_PLCA_CTRL1); 1378 1379 if (ret < 0) 1380 return ret; 1381 1382 val = ret; 1383 } 1384 1385 if (plca_cfg->node_cnt >= 0) 1386 val = (val & ~MDIO_OATC14_PLCA_NCNT) | 1387 (plca_cfg->node_cnt << 8); 1388 1389 if (plca_cfg->node_id >= 0) 1390 val = (val & ~MDIO_OATC14_PLCA_ID) | 1391 (plca_cfg->node_id); 1392 1393 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1394 MDIO_OATC14_PLCA_CTRL1, val); 1395 1396 if (ret < 0) 1397 return ret; 1398 } 1399 1400 if (plca_cfg->to_tmr >= 0) { 1401 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1402 MDIO_OATC14_PLCA_TOTMR, 1403 plca_cfg->to_tmr); 1404 1405 if (ret < 0) 1406 return ret; 1407 } 1408 1409 // check if we need to set the PLCA burst count, burst timer, or both 1410 if (plca_cfg->burst_cnt >= 0 || plca_cfg->burst_tmr >= 0) { 1411 /* if one between burst count and burst timer is -not- to be 1412 * changed, read the register to later perform merge/purge of 1413 * the configuration as appropriate 1414 */ 1415 if (plca_cfg->burst_cnt < 0 || plca_cfg->burst_tmr < 0) { 1416 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1417 MDIO_OATC14_PLCA_BURST); 1418 1419 if (ret < 0) 1420 return ret; 1421 1422 val = ret; 1423 } 1424 1425 if (plca_cfg->burst_cnt >= 0) 1426 val = (val & ~MDIO_OATC14_PLCA_MAXBC) | 1427 (plca_cfg->burst_cnt << 8); 1428 1429 if (plca_cfg->burst_tmr >= 0) 1430 val = (val & ~MDIO_OATC14_PLCA_BTMR) | 1431 (plca_cfg->burst_tmr); 1432 1433 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1434 MDIO_OATC14_PLCA_BURST, val); 1435 1436 if (ret < 0) 1437 return ret; 1438 } 1439 1440 // if we need to enable PLCA, do it at the end 1441 if (plca_cfg->enabled > 0) { 1442 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 1443 MDIO_OATC14_PLCA_CTRL0, 1444 MDIO_OATC14_PLCA_EN); 1445 1446 if (ret < 0) 1447 return ret; 1448 } 1449 1450 return 0; 1451 } 1452 EXPORT_SYMBOL_GPL(genphy_c45_plca_set_cfg); 1453 1454 /** 1455 * genphy_c45_plca_get_status - get PLCA status from standard registers 1456 * @phydev: target phy_device struct 1457 * @plca_st: output structure to store the PLCA status 1458 * 1459 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA 1460 * Management Registers specifications, this function can be used to retrieve 1461 * the current PLCA status information from the standard registers in MMD 31. 1462 */ 1463 int genphy_c45_plca_get_status(struct phy_device *phydev, 1464 struct phy_plca_status *plca_st) 1465 { 1466 int ret; 1467 1468 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_STATUS); 1469 if (ret < 0) 1470 return ret; 1471 1472 plca_st->pst = !!(ret & MDIO_OATC14_PLCA_PST); 1473 return 0; 1474 } 1475 EXPORT_SYMBOL_GPL(genphy_c45_plca_get_status); 1476 1477 /** 1478 * genphy_c45_eee_is_active - get EEE status 1479 * @phydev: target phy_device struct 1480 * @lp: variable to store LP advertised linkmodes 1481 * 1482 * Description: this function will read link partner PHY advertisement 1483 * and compare it to local advertisement to return current EEE state. 1484 */ 1485 int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *lp) 1486 { 1487 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp_lp) = {}; 1488 __ETHTOOL_DECLARE_LINK_MODE_MASK(common); 1489 int ret; 1490 1491 if (!phydev->eee_cfg.eee_enabled) 1492 return 0; 1493 1494 ret = genphy_c45_read_eee_lpa(phydev, tmp_lp); 1495 if (ret) 1496 return ret; 1497 1498 if (lp) 1499 linkmode_copy(lp, tmp_lp); 1500 1501 linkmode_and(common, phydev->advertising_eee, tmp_lp); 1502 if (linkmode_empty(common)) 1503 return 0; 1504 1505 return phy_check_valid(phydev->speed, phydev->duplex, common); 1506 } 1507 EXPORT_SYMBOL(genphy_c45_eee_is_active); 1508 1509 /** 1510 * genphy_c45_ethtool_get_eee - get EEE supported and status 1511 * @phydev: target phy_device struct 1512 * @data: ethtool_keee data 1513 * 1514 * Description: it reports the Supported/Advertisement/LP Advertisement 1515 * capabilities. 1516 */ 1517 int genphy_c45_ethtool_get_eee(struct phy_device *phydev, 1518 struct ethtool_keee *data) 1519 { 1520 int ret; 1521 1522 ret = genphy_c45_eee_is_active(phydev, data->lp_advertised); 1523 if (ret < 0) 1524 return ret; 1525 1526 data->eee_active = phydev->eee_active; 1527 linkmode_andnot(data->supported, phydev->supported_eee, 1528 phydev->eee_disabled_modes); 1529 linkmode_copy(data->advertised, phydev->advertising_eee); 1530 return 0; 1531 } 1532 EXPORT_SYMBOL(genphy_c45_ethtool_get_eee); 1533 1534 /** 1535 * genphy_c45_ethtool_set_eee - set EEE supported and status 1536 * @phydev: target phy_device struct 1537 * @data: ethtool_keee data 1538 * 1539 * Description: sets the Supported/Advertisement/LP Advertisement 1540 * capabilities. If eee_enabled is false, no links modes are 1541 * advertised, but the previously advertised link modes are 1542 * retained. This allows EEE to be enabled/disabled in a 1543 * non-destructive way. 1544 * Returns either error code, 0 if there was no change, or positive 1545 * value if there was a change which triggered auto-neg. 1546 */ 1547 int genphy_c45_ethtool_set_eee(struct phy_device *phydev, 1548 struct ethtool_keee *data) 1549 { 1550 int ret; 1551 1552 if (data->eee_enabled) { 1553 unsigned long *adv = data->advertised; 1554 1555 if (!linkmode_empty(adv)) { 1556 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp); 1557 1558 if (linkmode_andnot(tmp, adv, phydev->supported_eee)) { 1559 phydev_warn(phydev, "At least some EEE link modes are not supported.\n"); 1560 return -EINVAL; 1561 } 1562 1563 linkmode_andnot(phydev->advertising_eee, adv, 1564 phydev->eee_disabled_modes); 1565 } else if (linkmode_empty(phydev->advertising_eee)) { 1566 phy_advertise_eee_all(phydev); 1567 } 1568 } 1569 1570 ret = genphy_c45_an_config_eee_aneg(phydev); 1571 if (ret > 0) { 1572 ret = phy_restart_aneg(phydev); 1573 if (ret < 0) 1574 return ret; 1575 1576 /* explicitly return 1, otherwise (ret > 0) value will be 1577 * overwritten by phy_restart_aneg(). 1578 */ 1579 return 1; 1580 } 1581 1582 return ret; 1583 } 1584 EXPORT_SYMBOL(genphy_c45_ethtool_set_eee); 1585 1586 /** 1587 * oatc14_cable_test_get_result_code - Convert hardware cable test status to 1588 * ethtool result code. 1589 * @status: The hardware-reported cable test status 1590 * 1591 * This helper function maps the OATC14 HDD cable test status to the 1592 * corresponding ethtool cable test result code. It provides a translation 1593 * between the device-specific status values and the standardized ethtool 1594 * result codes. 1595 * 1596 * Return: 1597 * * ETHTOOL_A_CABLE_RESULT_CODE_OK - Cable is OK 1598 * * ETHTOOL_A_CABLE_RESULT_CODE_OPEN - Open circuit detected 1599 * * ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT - Short circuit detected 1600 * * ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC - Status not detectable or invalid 1601 */ 1602 static int oatc14_cable_test_get_result_code(enum oatc14_hdd_status status) 1603 { 1604 switch (status) { 1605 case OATC14_HDD_STATUS_CABLE_OK: 1606 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1607 case OATC14_HDD_STATUS_OPEN: 1608 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1609 case OATC14_HDD_STATUS_SHORT: 1610 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1611 case OATC14_HDD_STATUS_NOT_DETECTABLE: 1612 default: 1613 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1614 } 1615 } 1616 1617 /** 1618 * genphy_c45_oatc14_cable_test_get_status - Get status of OATC14 10Base-T1S 1619 * PHY cable test. 1620 * @phydev: pointer to the PHY device structure 1621 * @finished: pointer to a boolean set true if the test is complete 1622 * 1623 * Retrieves the current status of the OATC14 10Base-T1S PHY cable test. 1624 * This function reads the OATC14 HDD register to determine whether the test 1625 * results are valid and whether the test has finished. 1626 * 1627 * If the test is complete, the function reports the cable test result via 1628 * the ethtool cable test interface using ethnl_cable_test_result(), and then 1629 * clears the test control bit in the PHY register to reset the test state. 1630 * 1631 * Return: 0 on success, or a negative error code on failure (e.g. register 1632 * read/write error). 1633 */ 1634 int genphy_c45_oatc14_cable_test_get_status(struct phy_device *phydev, 1635 bool *finished) 1636 { 1637 int ret; 1638 u8 sts; 1639 1640 *finished = false; 1641 1642 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_HDD); 1643 if (ret < 0) 1644 return ret; 1645 1646 if (!(ret & OATC14_HDD_VALID)) 1647 return 0; 1648 1649 *finished = true; 1650 1651 sts = FIELD_GET(OATC14_HDD_SHORT_OPEN_STATUS, ret); 1652 1653 ret = ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, 1654 oatc14_cable_test_get_result_code(sts)); 1655 if (ret) 1656 return ret; 1657 1658 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 1659 MDIO_OATC14_HDD, OATC14_HDD_CONTROL); 1660 } 1661 EXPORT_SYMBOL(genphy_c45_oatc14_cable_test_get_status); 1662 1663 /** 1664 * genphy_c45_oatc14_cable_test_start - Start a cable test on an OATC14 1665 * 10Base-T1S PHY. 1666 * @phydev: Pointer to the PHY device structure 1667 * 1668 * This function initiates a cable diagnostic test on a Clause 45 OATC14 1669 * 10Base-T1S capable PHY device. It first reads the PHY’s advanced diagnostic 1670 * capability register to check if High Definition Diagnostics (HDD) mode is 1671 * supported. If the PHY does not report HDD capability, cable testing is not 1672 * supported and the function returns -EOPNOTSUPP. 1673 * 1674 * For PHYs that support HDD, the function sets the appropriate control bits in 1675 * the OATC14_HDD register to enable and start the cable diagnostic test. 1676 * 1677 * Return: 1678 * * 0 on success 1679 * * -EOPNOTSUPP if the PHY does not support HDD capability 1680 * * A negative error code on I/O or register access failures 1681 */ 1682 int genphy_c45_oatc14_cable_test_start(struct phy_device *phydev) 1683 { 1684 int ret; 1685 1686 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_ADFCAP); 1687 if (ret < 0) 1688 return ret; 1689 1690 if (!(ret & OATC14_ADFCAP_HDD_CAPABILITY)) 1691 return -EOPNOTSUPP; 1692 1693 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_HDD, 1694 OATC14_HDD_CONTROL); 1695 if (ret) 1696 return ret; 1697 1698 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_HDD); 1699 if (ret < 0) 1700 return ret; 1701 1702 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_HDD, 1703 OATC14_HDD_START_CONTROL); 1704 } 1705 EXPORT_SYMBOL(genphy_c45_oatc14_cable_test_start); 1706 1707 /** 1708 * oatc14_update_sqi_capability - Read and update OATC14 10Base-T1S PHY SQI/SQI+ 1709 * capability 1710 * @phydev: Pointer to the PHY device structure 1711 * 1712 * This helper reads the OATC14 ADFCAP capability register to determine whether 1713 * the PHY supports SQI or SQI+ reporting. 1714 * 1715 * SQI+ capability is detected first. The SQI+ field indicates the number of 1716 * valid MSBs (3–8), corresponding to 8–256 SQI+ levels. When present, the 1717 * function stores the number of SQI+ bits and computes the maximum SQI+ value 1718 * as (2^bits - 1). 1719 * 1720 * If SQI+ is not supported, the function checks for basic SQI capability, 1721 * which provides 0–7 SQI levels. 1722 * 1723 * On success, the capability information is stored in 1724 * @phydev->oatc14_sqi_capability and marked as updated. 1725 * 1726 * Return: 1727 * * 0 - capability successfully read and stored 1728 * * -EOPNOTSUPP - SQI/SQI+ not supported by this PHY 1729 * * Negative errno on read failure 1730 */ 1731 static int oatc14_update_sqi_capability(struct phy_device *phydev) 1732 { 1733 u8 bits; 1734 int ret; 1735 1736 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_ADFCAP); 1737 if (ret < 0) 1738 return ret; 1739 1740 /* Check for SQI+ capability 1741 * 0 - SQI+ is not supported 1742 * (3-8) bits for (8-256) SQI+ levels supported 1743 */ 1744 bits = FIELD_GET(OATC14_ADFCAP_SQIPLUS_CAPABILITY, ret); 1745 if (bits) { 1746 phydev->oatc14_sqi_capability.sqiplus_bits = bits; 1747 /* Max sqi+ level supported: (2 ^ bits) - 1 */ 1748 phydev->oatc14_sqi_capability.sqi_max = BIT(bits) - 1; 1749 goto update_done; 1750 } 1751 1752 /* Check for SQI capability 1753 * 0 - SQI is not supported 1754 * 1 - SQI is supported (0-7 levels) 1755 */ 1756 if (ret & OATC14_ADFCAP_SQI_CAPABILITY) { 1757 phydev->oatc14_sqi_capability.sqi_max = OATC14_SQI_MAX_LEVEL; 1758 goto update_done; 1759 } 1760 1761 return -EOPNOTSUPP; 1762 1763 update_done: 1764 phydev->oatc14_sqi_capability.updated = true; 1765 return 0; 1766 } 1767 1768 /** 1769 * genphy_c45_oatc14_get_sqi_max - Get maximum supported SQI or SQI+ level of 1770 * OATC14 10Base-T1S PHY 1771 * @phydev: pointer to the PHY device structure 1772 * 1773 * This function returns the maximum supported Signal Quality Indicator (SQI) or 1774 * SQI+ level. The SQI capability is updated on first invocation if it has not 1775 * already been updated. 1776 * 1777 * Return: 1778 * * Maximum SQI/SQI+ level supported 1779 * * Negative errno on capability read failure 1780 */ 1781 int genphy_c45_oatc14_get_sqi_max(struct phy_device *phydev) 1782 { 1783 int ret; 1784 1785 if (!phydev->oatc14_sqi_capability.updated) { 1786 ret = oatc14_update_sqi_capability(phydev); 1787 if (ret) 1788 return ret; 1789 } 1790 1791 return phydev->oatc14_sqi_capability.sqi_max; 1792 } 1793 EXPORT_SYMBOL(genphy_c45_oatc14_get_sqi_max); 1794 1795 /** 1796 * genphy_c45_oatc14_get_sqi - Get Signal Quality Indicator (SQI) from an OATC14 1797 * 10Base-T1S PHY 1798 * @phydev: pointer to the PHY device structure 1799 * 1800 * This function reads the SQI+ or SQI value from an OATC14-compatible 1801 * 10Base-T1S PHY. If SQI+ capability is supported, the function returns the 1802 * extended SQI+ value; otherwise, it returns the basic SQI value. The SQI 1803 * capability is updated on first invocation if it has not already been updated. 1804 * 1805 * Return: 1806 * * SQI/SQI+ value on success 1807 * * Negative errno on read failure 1808 */ 1809 int genphy_c45_oatc14_get_sqi(struct phy_device *phydev) 1810 { 1811 u8 shift; 1812 int ret; 1813 1814 if (!phydev->oatc14_sqi_capability.updated) { 1815 ret = oatc14_update_sqi_capability(phydev); 1816 if (ret) 1817 return ret; 1818 } 1819 1820 /* Calculate and return SQI+ value if supported */ 1821 if (phydev->oatc14_sqi_capability.sqiplus_bits) { 1822 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1823 MDIO_OATC14_DCQ_SQIPLUS); 1824 if (ret < 0) 1825 return ret; 1826 1827 /* SQI+ uses N MSBs out of 8 bits, left-aligned with padding 1's 1828 * Calculate the right-shift needed to isolate the N bits. 1829 */ 1830 shift = 8 - phydev->oatc14_sqi_capability.sqiplus_bits; 1831 1832 return (ret & OATC14_DCQ_SQIPLUS_VALUE) >> shift; 1833 } 1834 1835 /* Read and return SQI value if SQI+ capability is not supported */ 1836 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_DCQ_SQI); 1837 if (ret < 0) 1838 return ret; 1839 1840 return ret & OATC14_DCQ_SQI_VALUE; 1841 } 1842 EXPORT_SYMBOL(genphy_c45_oatc14_get_sqi); 1843