1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2022 Schneider Electric 4 * 5 * Clément Léger <clement.leger@bootlin.com> 6 */ 7 8 #include <linux/array_size.h> 9 #include <linux/bits.h> 10 #include <linux/clk.h> 11 #include <linux/device.h> 12 #include <linux/mdio.h> 13 #include <linux/of.h> 14 #include <linux/of_platform.h> 15 #include <linux/pcs-rzn1-miic.h> 16 #include <linux/phylink.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/slab.h> 20 #include <dt-bindings/net/pcs-rzn1-miic.h> 21 22 #define MIIC_PRCMD 0x0 23 #define MIIC_ESID_CODE 0x4 24 25 #define MIIC_MODCTRL 0x8 26 #define MIIC_MODCTRL_SW_MODE GENMASK(4, 0) 27 28 #define MIIC_CONVCTRL(port) (0x100 + (port) * 4) 29 30 #define MIIC_CONVCTRL_CONV_SPEED GENMASK(1, 0) 31 #define CONV_MODE_10MBPS 0 32 #define CONV_MODE_100MBPS 1 33 #define CONV_MODE_1000MBPS 2 34 35 #define MIIC_CONVCTRL_CONV_MODE GENMASK(3, 2) 36 #define CONV_MODE_MII 0 37 #define CONV_MODE_RMII 1 38 #define CONV_MODE_RGMII 2 39 40 #define MIIC_CONVCTRL_FULLD BIT(8) 41 #define MIIC_CONVCTRL_RGMII_LINK BIT(12) 42 #define MIIC_CONVCTRL_RGMII_DUPLEX BIT(13) 43 #define MIIC_CONVCTRL_RGMII_SPEED GENMASK(15, 14) 44 45 #define MIIC_CONVRST 0x114 46 #define MIIC_CONVRST_PHYIF_RST(port) BIT(port) 47 #define MIIC_CONVRST_PHYIF_RST_MASK GENMASK(4, 0) 48 49 #define MIIC_SWCTRL 0x304 50 #define MIIC_SWDUPC 0x308 51 52 #define MIIC_MAX_NR_PORTS 5 53 54 #define MIIC_MODCTRL_CONF_CONV_MAX 6 55 #define MIIC_MODCTRL_CONF_NONE -1 56 57 /** 58 * struct modctrl_match - Matching table entry for convctrl configuration 59 * See section 8.2.1 of manual. 60 * @mode_cfg: Configuration value for convctrl 61 * @conv: Configuration of ethernet port muxes. First index is SWITCH_PORTIN, 62 * then index 1 - 5 are CONV1 - CONV5 for RZ/N1 SoCs. In case 63 * of RZ/T2H and RZ/N2H SoCs, the first index is SWITCH_PORTIN then 64 * index 0 - 3 are CONV0 - CONV3. 65 */ 66 struct modctrl_match { 67 u32 mode_cfg; 68 u8 conv[MIIC_MODCTRL_CONF_CONV_MAX]; 69 }; 70 71 static struct modctrl_match modctrl_match_table[] = { 72 {0x0, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 73 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 74 {0x1, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 75 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 76 {0x2, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 77 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 78 {0x3, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 79 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}, 80 81 {0x8, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 82 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 83 {0x9, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 84 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 85 {0xA, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 86 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 87 {0xB, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 88 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}, 89 90 {0x10, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 91 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 92 {0x11, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 93 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 94 {0x12, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 95 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 96 {0x13, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 97 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}} 98 }; 99 100 static const char * const conf_to_string[] = { 101 [MIIC_GMAC1_PORT] = "GMAC1_PORT", 102 [MIIC_GMAC2_PORT] = "GMAC2_PORT", 103 [MIIC_RTOS_PORT] = "RTOS_PORT", 104 [MIIC_SERCOS_PORTA] = "SERCOS_PORTA", 105 [MIIC_SERCOS_PORTB] = "SERCOS_PORTB", 106 [MIIC_ETHERCAT_PORTA] = "ETHERCAT_PORTA", 107 [MIIC_ETHERCAT_PORTB] = "ETHERCAT_PORTB", 108 [MIIC_ETHERCAT_PORTC] = "ETHERCAT_PORTC", 109 [MIIC_SWITCH_PORTA] = "SWITCH_PORTA", 110 [MIIC_SWITCH_PORTB] = "SWITCH_PORTB", 111 [MIIC_SWITCH_PORTC] = "SWITCH_PORTC", 112 [MIIC_SWITCH_PORTD] = "SWITCH_PORTD", 113 [MIIC_HSR_PORTA] = "HSR_PORTA", 114 [MIIC_HSR_PORTB] = "HSR_PORTB", 115 }; 116 117 static const char * const index_to_string[] = { 118 "SWITCH_PORTIN", 119 "CONV1", 120 "CONV2", 121 "CONV3", 122 "CONV4", 123 "CONV5", 124 }; 125 126 /** 127 * struct miic - MII converter structure 128 * @base: base address of the MII converter 129 * @dev: Device associated to the MII converter 130 * @lock: Lock used for read-modify-write access 131 * @of_data: Pointer to OF data 132 */ 133 struct miic { 134 void __iomem *base; 135 struct device *dev; 136 spinlock_t lock; 137 const struct miic_of_data *of_data; 138 }; 139 140 /** 141 * struct miic_of_data - OF data for MII converter 142 * @match_table: Matching table for convctrl configuration 143 * @match_table_count: Number of entries in the matching table 144 * @conf_conv_count: Number of entries in the conf_conv array 145 * @conf_to_string: String representations of the configuration values 146 * @conf_to_string_count: Number of entries in the conf_to_string array 147 * @index_to_string: String representations of the index values 148 * @index_to_string_count: Number of entries in the index_to_string array 149 */ 150 struct miic_of_data { 151 struct modctrl_match *match_table; 152 u8 match_table_count; 153 u8 conf_conv_count; 154 const char * const *conf_to_string; 155 u8 conf_to_string_count; 156 const char * const *index_to_string; 157 u8 index_to_string_count; 158 }; 159 160 /** 161 * struct miic_port - Per port MII converter struct 162 * @miic: backiling to MII converter structure 163 * @pcs: PCS structure associated to the port 164 * @port: port number 165 * @interface: interface mode of the port 166 */ 167 struct miic_port { 168 struct miic *miic; 169 struct phylink_pcs pcs; 170 int port; 171 phy_interface_t interface; 172 }; 173 174 static struct miic_port *phylink_pcs_to_miic_port(struct phylink_pcs *pcs) 175 { 176 return container_of(pcs, struct miic_port, pcs); 177 } 178 179 static void miic_reg_writel(struct miic *miic, int offset, u32 value) 180 { 181 writel(value, miic->base + offset); 182 } 183 184 static u32 miic_reg_readl(struct miic *miic, int offset) 185 { 186 return readl(miic->base + offset); 187 } 188 189 static void miic_reg_rmw(struct miic *miic, int offset, u32 mask, u32 val) 190 { 191 u32 reg; 192 193 spin_lock(&miic->lock); 194 195 reg = miic_reg_readl(miic, offset); 196 reg &= ~mask; 197 reg |= val; 198 miic_reg_writel(miic, offset, reg); 199 200 spin_unlock(&miic->lock); 201 } 202 203 static void miic_converter_enable(struct miic *miic, int port, int enable) 204 { 205 u32 val = 0; 206 207 if (enable) 208 val = MIIC_CONVRST_PHYIF_RST(port); 209 210 miic_reg_rmw(miic, MIIC_CONVRST, MIIC_CONVRST_PHYIF_RST(port), val); 211 } 212 213 static int miic_config(struct phylink_pcs *pcs, unsigned int neg_mode, 214 phy_interface_t interface, 215 const unsigned long *advertising, bool permit) 216 { 217 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 218 struct miic *miic = miic_port->miic; 219 u32 speed, conv_mode, val, mask; 220 int port = miic_port->port; 221 222 switch (interface) { 223 case PHY_INTERFACE_MODE_RMII: 224 conv_mode = CONV_MODE_RMII; 225 speed = CONV_MODE_100MBPS; 226 break; 227 case PHY_INTERFACE_MODE_RGMII: 228 case PHY_INTERFACE_MODE_RGMII_ID: 229 case PHY_INTERFACE_MODE_RGMII_TXID: 230 case PHY_INTERFACE_MODE_RGMII_RXID: 231 conv_mode = CONV_MODE_RGMII; 232 speed = CONV_MODE_1000MBPS; 233 break; 234 case PHY_INTERFACE_MODE_MII: 235 conv_mode = CONV_MODE_MII; 236 /* When in MII mode, speed should be set to 0 (which is actually 237 * CONV_MODE_10MBPS) 238 */ 239 speed = CONV_MODE_10MBPS; 240 break; 241 default: 242 return -EOPNOTSUPP; 243 } 244 245 val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, conv_mode); 246 mask = MIIC_CONVCTRL_CONV_MODE; 247 248 /* Update speed only if we are going to change the interface because 249 * the link might already be up and it would break it if the speed is 250 * changed. 251 */ 252 if (interface != miic_port->interface) { 253 val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, speed); 254 mask |= MIIC_CONVCTRL_CONV_SPEED; 255 miic_port->interface = interface; 256 } 257 258 miic_reg_rmw(miic, MIIC_CONVCTRL(port), mask, val); 259 miic_converter_enable(miic, miic_port->port, 1); 260 261 return 0; 262 } 263 264 static void miic_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, 265 phy_interface_t interface, int speed, int duplex) 266 { 267 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 268 struct miic *miic = miic_port->miic; 269 u32 conv_speed = 0, val = 0; 270 int port = miic_port->port; 271 272 if (duplex == DUPLEX_FULL) 273 val |= MIIC_CONVCTRL_FULLD; 274 275 /* No speed in MII through-mode */ 276 if (interface != PHY_INTERFACE_MODE_MII) { 277 switch (speed) { 278 case SPEED_1000: 279 conv_speed = CONV_MODE_1000MBPS; 280 break; 281 case SPEED_100: 282 conv_speed = CONV_MODE_100MBPS; 283 break; 284 case SPEED_10: 285 conv_speed = CONV_MODE_10MBPS; 286 break; 287 default: 288 return; 289 } 290 } 291 292 val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, conv_speed); 293 294 miic_reg_rmw(miic, MIIC_CONVCTRL(port), 295 (MIIC_CONVCTRL_CONV_SPEED | MIIC_CONVCTRL_FULLD), val); 296 } 297 298 static int miic_pre_init(struct phylink_pcs *pcs) 299 { 300 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 301 struct miic *miic = miic_port->miic; 302 u32 val, mask; 303 304 /* Start RX clock if required */ 305 if (pcs->rxc_always_on) { 306 /* In MII through mode, the clock signals will be driven by the 307 * external PHY, which might not be initialized yet. Set RMII 308 * as default mode to ensure that a reference clock signal is 309 * generated. 310 */ 311 miic_port->interface = PHY_INTERFACE_MODE_RMII; 312 313 val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, CONV_MODE_RMII) | 314 FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, CONV_MODE_100MBPS); 315 mask = MIIC_CONVCTRL_CONV_MODE | MIIC_CONVCTRL_CONV_SPEED; 316 317 miic_reg_rmw(miic, MIIC_CONVCTRL(miic_port->port), mask, val); 318 319 miic_converter_enable(miic, miic_port->port, 1); 320 } 321 322 return 0; 323 } 324 325 static const struct phylink_pcs_ops miic_phylink_ops = { 326 .pcs_config = miic_config, 327 .pcs_link_up = miic_link_up, 328 .pcs_pre_init = miic_pre_init, 329 }; 330 331 struct phylink_pcs *miic_create(struct device *dev, struct device_node *np) 332 { 333 struct platform_device *pdev; 334 struct miic_port *miic_port; 335 struct device_node *pcs_np; 336 struct miic *miic; 337 u32 port; 338 339 if (!of_device_is_available(np)) 340 return ERR_PTR(-ENODEV); 341 342 if (of_property_read_u32(np, "reg", &port)) 343 return ERR_PTR(-EINVAL); 344 345 if (port > MIIC_MAX_NR_PORTS || port < 1) 346 return ERR_PTR(-EINVAL); 347 348 /* The PCS pdev is attached to the parent node */ 349 pcs_np = of_get_parent(np); 350 if (!pcs_np) 351 return ERR_PTR(-ENODEV); 352 353 if (!of_device_is_available(pcs_np)) { 354 of_node_put(pcs_np); 355 return ERR_PTR(-ENODEV); 356 } 357 358 pdev = of_find_device_by_node(pcs_np); 359 of_node_put(pcs_np); 360 if (!pdev || !platform_get_drvdata(pdev)) { 361 if (pdev) 362 put_device(&pdev->dev); 363 return ERR_PTR(-EPROBE_DEFER); 364 } 365 366 miic_port = kzalloc(sizeof(*miic_port), GFP_KERNEL); 367 if (!miic_port) { 368 put_device(&pdev->dev); 369 return ERR_PTR(-ENOMEM); 370 } 371 372 miic = platform_get_drvdata(pdev); 373 device_link_add(dev, miic->dev, DL_FLAG_AUTOREMOVE_CONSUMER); 374 put_device(&pdev->dev); 375 376 miic_port->miic = miic; 377 miic_port->port = port - 1; 378 miic_port->pcs.ops = &miic_phylink_ops; 379 380 phy_interface_set_rgmii(miic_port->pcs.supported_interfaces); 381 __set_bit(PHY_INTERFACE_MODE_RMII, miic_port->pcs.supported_interfaces); 382 __set_bit(PHY_INTERFACE_MODE_MII, miic_port->pcs.supported_interfaces); 383 384 return &miic_port->pcs; 385 } 386 EXPORT_SYMBOL(miic_create); 387 388 void miic_destroy(struct phylink_pcs *pcs) 389 { 390 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 391 392 miic_converter_enable(miic_port->miic, miic_port->port, 0); 393 kfree(miic_port); 394 } 395 EXPORT_SYMBOL(miic_destroy); 396 397 static int miic_init_hw(struct miic *miic, u32 cfg_mode) 398 { 399 int port; 400 401 /* Unlock write access to accessory registers (cf datasheet). If this 402 * is going to be used in conjunction with the Cortex-M3, this sequence 403 * will have to be moved in register write 404 */ 405 miic_reg_writel(miic, MIIC_PRCMD, 0x00A5); 406 miic_reg_writel(miic, MIIC_PRCMD, 0x0001); 407 miic_reg_writel(miic, MIIC_PRCMD, 0xFFFE); 408 miic_reg_writel(miic, MIIC_PRCMD, 0x0001); 409 410 miic_reg_writel(miic, MIIC_MODCTRL, 411 FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode)); 412 413 for (port = 0; port < MIIC_MAX_NR_PORTS; port++) { 414 miic_converter_enable(miic, port, 0); 415 /* Disable speed/duplex control from these registers, datasheet 416 * says switch registers should be used to setup switch port 417 * speed and duplex. 418 */ 419 miic_reg_writel(miic, MIIC_SWCTRL, 0x0); 420 miic_reg_writel(miic, MIIC_SWDUPC, 0x0); 421 } 422 423 return 0; 424 } 425 426 static bool miic_modctrl_match(s8 *table_val, s8 *dt_val, u8 count) 427 { 428 int i; 429 430 for (i = 0; i < count; i++) { 431 if (dt_val[i] == MIIC_MODCTRL_CONF_NONE) 432 continue; 433 434 if (dt_val[i] != table_val[i]) 435 return false; 436 } 437 438 return true; 439 } 440 441 static void miic_dump_conf(struct miic *miic, s8 *conf) 442 { 443 const struct miic_of_data *of_data = miic->of_data; 444 const char *conf_name; 445 int i; 446 447 for (i = 0; i < of_data->conf_conv_count; i++) { 448 if (conf[i] != MIIC_MODCTRL_CONF_NONE) 449 conf_name = of_data->conf_to_string[conf[i]]; 450 else 451 conf_name = "NONE"; 452 453 dev_err(miic->dev, "%s: %s\n", 454 of_data->index_to_string[i], conf_name); 455 } 456 } 457 458 static int miic_match_dt_conf(struct miic *miic, s8 *dt_val, u32 *mode_cfg) 459 { 460 const struct miic_of_data *of_data = miic->of_data; 461 struct modctrl_match *table_entry; 462 int i; 463 464 for (i = 0; i < of_data->match_table_count; i++) { 465 table_entry = &of_data->match_table[i]; 466 467 if (miic_modctrl_match(table_entry->conv, dt_val, 468 miic->of_data->conf_conv_count)) { 469 *mode_cfg = table_entry->mode_cfg; 470 return 0; 471 } 472 } 473 474 dev_err(miic->dev, "Failed to apply requested configuration\n"); 475 miic_dump_conf(miic, dt_val); 476 477 return -EINVAL; 478 } 479 480 static int miic_parse_dt(struct miic *miic, u32 *mode_cfg) 481 { 482 struct device_node *np = miic->dev->of_node; 483 struct device_node *conv; 484 int port, ret; 485 s8 *dt_val; 486 u32 conf; 487 488 dt_val = kmalloc_array(miic->of_data->conf_conv_count, 489 sizeof(*dt_val), GFP_KERNEL); 490 if (!dt_val) 491 return -ENOMEM; 492 493 memset(dt_val, MIIC_MODCTRL_CONF_NONE, sizeof(*dt_val)); 494 495 if (of_property_read_u32(np, "renesas,miic-switch-portin", &conf) == 0) 496 dt_val[0] = conf; 497 498 for_each_available_child_of_node(np, conv) { 499 if (of_property_read_u32(conv, "reg", &port)) 500 continue; 501 502 if (of_property_read_u32(conv, "renesas,miic-input", &conf) == 0) 503 dt_val[port] = conf; 504 } 505 506 ret = miic_match_dt_conf(miic, dt_val, mode_cfg); 507 kfree(dt_val); 508 509 return ret; 510 } 511 512 static int miic_probe(struct platform_device *pdev) 513 { 514 struct device *dev = &pdev->dev; 515 struct miic *miic; 516 u32 mode_cfg; 517 int ret; 518 519 miic = devm_kzalloc(dev, sizeof(*miic), GFP_KERNEL); 520 if (!miic) 521 return -ENOMEM; 522 523 miic->of_data = of_device_get_match_data(dev); 524 miic->dev = dev; 525 526 ret = miic_parse_dt(miic, &mode_cfg); 527 if (ret < 0) 528 return ret; 529 530 spin_lock_init(&miic->lock); 531 miic->base = devm_platform_ioremap_resource(pdev, 0); 532 if (IS_ERR(miic->base)) 533 return PTR_ERR(miic->base); 534 535 ret = devm_pm_runtime_enable(dev); 536 if (ret < 0) 537 return ret; 538 539 ret = pm_runtime_resume_and_get(dev); 540 if (ret < 0) 541 return ret; 542 543 ret = miic_init_hw(miic, mode_cfg); 544 if (ret) 545 goto disable_runtime_pm; 546 547 /* miic_create() relies on that fact that data are attached to the 548 * platform device to determine if the driver is ready so this needs to 549 * be the last thing to be done after everything is initialized 550 * properly. 551 */ 552 platform_set_drvdata(pdev, miic); 553 554 return 0; 555 556 disable_runtime_pm: 557 pm_runtime_put(dev); 558 559 return ret; 560 } 561 562 static void miic_remove(struct platform_device *pdev) 563 { 564 pm_runtime_put(&pdev->dev); 565 } 566 567 static struct miic_of_data rzn1_miic_of_data = { 568 .match_table = modctrl_match_table, 569 .match_table_count = ARRAY_SIZE(modctrl_match_table), 570 .conf_conv_count = MIIC_MODCTRL_CONF_CONV_MAX, 571 .conf_to_string = conf_to_string, 572 .conf_to_string_count = ARRAY_SIZE(conf_to_string), 573 .index_to_string = index_to_string, 574 .index_to_string_count = ARRAY_SIZE(index_to_string), 575 }; 576 577 static const struct of_device_id miic_of_mtable[] = { 578 { .compatible = "renesas,rzn1-miic", .data = &rzn1_miic_of_data }, 579 { /* sentinel */ } 580 }; 581 MODULE_DEVICE_TABLE(of, miic_of_mtable); 582 583 static struct platform_driver miic_driver = { 584 .driver = { 585 .name = "rzn1_miic", 586 .suppress_bind_attrs = true, 587 .of_match_table = miic_of_mtable, 588 }, 589 .probe = miic_probe, 590 .remove = miic_remove, 591 }; 592 module_platform_driver(miic_driver); 593 594 MODULE_LICENSE("GPL"); 595 MODULE_DESCRIPTION("Renesas MII converter PCS driver"); 596 MODULE_AUTHOR("Clément Léger <clement.leger@bootlin.com>"); 597