1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2022 Schneider Electric 4 * 5 * Clément Léger <clement.leger@bootlin.com> 6 */ 7 8 #include <linux/array_size.h> 9 #include <linux/bits.h> 10 #include <linux/clk.h> 11 #include <linux/device.h> 12 #include <linux/mdio.h> 13 #include <linux/of.h> 14 #include <linux/of_platform.h> 15 #include <linux/pcs-rzn1-miic.h> 16 #include <linux/phylink.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/slab.h> 20 #include <dt-bindings/net/pcs-rzn1-miic.h> 21 22 #define MIIC_PRCMD 0x0 23 #define MIIC_ESID_CODE 0x4 24 25 #define MIIC_MODCTRL 0x8 26 #define MIIC_MODCTRL_SW_MODE GENMASK(4, 0) 27 28 #define MIIC_CONVCTRL(port) (0x100 + (port) * 4) 29 30 #define MIIC_CONVCTRL_CONV_SPEED GENMASK(1, 0) 31 #define CONV_MODE_10MBPS 0 32 #define CONV_MODE_100MBPS 1 33 #define CONV_MODE_1000MBPS 2 34 35 #define MIIC_CONVCTRL_CONV_MODE GENMASK(3, 2) 36 #define CONV_MODE_MII 0 37 #define CONV_MODE_RMII 1 38 #define CONV_MODE_RGMII 2 39 40 #define MIIC_CONVCTRL_FULLD BIT(8) 41 #define MIIC_CONVCTRL_RGMII_LINK BIT(12) 42 #define MIIC_CONVCTRL_RGMII_DUPLEX BIT(13) 43 #define MIIC_CONVCTRL_RGMII_SPEED GENMASK(15, 14) 44 45 #define MIIC_CONVRST 0x114 46 #define MIIC_CONVRST_PHYIF_RST(port) BIT(port) 47 #define MIIC_CONVRST_PHYIF_RST_MASK GENMASK(4, 0) 48 49 #define MIIC_SWCTRL 0x304 50 #define MIIC_SWDUPC 0x308 51 52 #define MIIC_MODCTRL_CONF_CONV_MAX 6 53 #define MIIC_MODCTRL_CONF_NONE -1 54 55 /** 56 * struct modctrl_match - Matching table entry for convctrl configuration 57 * See section 8.2.1 of manual. 58 * @mode_cfg: Configuration value for convctrl 59 * @conv: Configuration of ethernet port muxes. First index is SWITCH_PORTIN, 60 * then index 1 - 5 are CONV1 - CONV5 for RZ/N1 SoCs. In case 61 * of RZ/T2H and RZ/N2H SoCs, the first index is SWITCH_PORTIN then 62 * index 0 - 3 are CONV0 - CONV3. 63 */ 64 struct modctrl_match { 65 u32 mode_cfg; 66 u8 conv[MIIC_MODCTRL_CONF_CONV_MAX]; 67 }; 68 69 static struct modctrl_match modctrl_match_table[] = { 70 {0x0, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 71 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 72 {0x1, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 73 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 74 {0x2, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 75 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 76 {0x3, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 77 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}, 78 79 {0x8, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 80 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 81 {0x9, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 82 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 83 {0xA, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 84 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 85 {0xB, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 86 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}, 87 88 {0x10, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 89 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 90 {0x11, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 91 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 92 {0x12, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 93 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 94 {0x13, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 95 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}} 96 }; 97 98 static const char * const conf_to_string[] = { 99 [MIIC_GMAC1_PORT] = "GMAC1_PORT", 100 [MIIC_GMAC2_PORT] = "GMAC2_PORT", 101 [MIIC_RTOS_PORT] = "RTOS_PORT", 102 [MIIC_SERCOS_PORTA] = "SERCOS_PORTA", 103 [MIIC_SERCOS_PORTB] = "SERCOS_PORTB", 104 [MIIC_ETHERCAT_PORTA] = "ETHERCAT_PORTA", 105 [MIIC_ETHERCAT_PORTB] = "ETHERCAT_PORTB", 106 [MIIC_ETHERCAT_PORTC] = "ETHERCAT_PORTC", 107 [MIIC_SWITCH_PORTA] = "SWITCH_PORTA", 108 [MIIC_SWITCH_PORTB] = "SWITCH_PORTB", 109 [MIIC_SWITCH_PORTC] = "SWITCH_PORTC", 110 [MIIC_SWITCH_PORTD] = "SWITCH_PORTD", 111 [MIIC_HSR_PORTA] = "HSR_PORTA", 112 [MIIC_HSR_PORTB] = "HSR_PORTB", 113 }; 114 115 static const char * const index_to_string[] = { 116 "SWITCH_PORTIN", 117 "CONV1", 118 "CONV2", 119 "CONV3", 120 "CONV4", 121 "CONV5", 122 }; 123 124 /** 125 * struct miic - MII converter structure 126 * @base: base address of the MII converter 127 * @dev: Device associated to the MII converter 128 * @lock: Lock used for read-modify-write access 129 * @of_data: Pointer to OF data 130 */ 131 struct miic { 132 void __iomem *base; 133 struct device *dev; 134 spinlock_t lock; 135 const struct miic_of_data *of_data; 136 }; 137 138 /** 139 * struct miic_of_data - OF data for MII converter 140 * @match_table: Matching table for convctrl configuration 141 * @match_table_count: Number of entries in the matching table 142 * @conf_conv_count: Number of entries in the conf_conv array 143 * @conf_to_string: String representations of the configuration values 144 * @conf_to_string_count: Number of entries in the conf_to_string array 145 * @index_to_string: String representations of the index values 146 * @index_to_string_count: Number of entries in the index_to_string array 147 * @miic_port_start: MIIC port start number 148 * @miic_port_max: Maximum MIIC supported 149 */ 150 struct miic_of_data { 151 struct modctrl_match *match_table; 152 u8 match_table_count; 153 u8 conf_conv_count; 154 const char * const *conf_to_string; 155 u8 conf_to_string_count; 156 const char * const *index_to_string; 157 u8 index_to_string_count; 158 u8 miic_port_start; 159 u8 miic_port_max; 160 }; 161 162 /** 163 * struct miic_port - Per port MII converter struct 164 * @miic: backiling to MII converter structure 165 * @pcs: PCS structure associated to the port 166 * @port: port number 167 * @interface: interface mode of the port 168 */ 169 struct miic_port { 170 struct miic *miic; 171 struct phylink_pcs pcs; 172 int port; 173 phy_interface_t interface; 174 }; 175 176 static struct miic_port *phylink_pcs_to_miic_port(struct phylink_pcs *pcs) 177 { 178 return container_of(pcs, struct miic_port, pcs); 179 } 180 181 static void miic_reg_writel(struct miic *miic, int offset, u32 value) 182 { 183 writel(value, miic->base + offset); 184 } 185 186 static u32 miic_reg_readl(struct miic *miic, int offset) 187 { 188 return readl(miic->base + offset); 189 } 190 191 static void miic_reg_rmw(struct miic *miic, int offset, u32 mask, u32 val) 192 { 193 u32 reg; 194 195 spin_lock(&miic->lock); 196 197 reg = miic_reg_readl(miic, offset); 198 reg &= ~mask; 199 reg |= val; 200 miic_reg_writel(miic, offset, reg); 201 202 spin_unlock(&miic->lock); 203 } 204 205 static void miic_converter_enable(struct miic *miic, int port, int enable) 206 { 207 u32 val = 0; 208 209 if (enable) 210 val = MIIC_CONVRST_PHYIF_RST(port); 211 212 miic_reg_rmw(miic, MIIC_CONVRST, MIIC_CONVRST_PHYIF_RST(port), val); 213 } 214 215 static int miic_config(struct phylink_pcs *pcs, unsigned int neg_mode, 216 phy_interface_t interface, 217 const unsigned long *advertising, bool permit) 218 { 219 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 220 struct miic *miic = miic_port->miic; 221 u32 speed, conv_mode, val, mask; 222 int port = miic_port->port; 223 224 switch (interface) { 225 case PHY_INTERFACE_MODE_RMII: 226 conv_mode = CONV_MODE_RMII; 227 speed = CONV_MODE_100MBPS; 228 break; 229 case PHY_INTERFACE_MODE_RGMII: 230 case PHY_INTERFACE_MODE_RGMII_ID: 231 case PHY_INTERFACE_MODE_RGMII_TXID: 232 case PHY_INTERFACE_MODE_RGMII_RXID: 233 conv_mode = CONV_MODE_RGMII; 234 speed = CONV_MODE_1000MBPS; 235 break; 236 case PHY_INTERFACE_MODE_MII: 237 conv_mode = CONV_MODE_MII; 238 /* When in MII mode, speed should be set to 0 (which is actually 239 * CONV_MODE_10MBPS) 240 */ 241 speed = CONV_MODE_10MBPS; 242 break; 243 default: 244 return -EOPNOTSUPP; 245 } 246 247 val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, conv_mode); 248 mask = MIIC_CONVCTRL_CONV_MODE; 249 250 /* Update speed only if we are going to change the interface because 251 * the link might already be up and it would break it if the speed is 252 * changed. 253 */ 254 if (interface != miic_port->interface) { 255 val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, speed); 256 mask |= MIIC_CONVCTRL_CONV_SPEED; 257 miic_port->interface = interface; 258 } 259 260 miic_reg_rmw(miic, MIIC_CONVCTRL(port), mask, val); 261 miic_converter_enable(miic, miic_port->port, 1); 262 263 return 0; 264 } 265 266 static void miic_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, 267 phy_interface_t interface, int speed, int duplex) 268 { 269 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 270 struct miic *miic = miic_port->miic; 271 u32 conv_speed = 0, val = 0; 272 int port = miic_port->port; 273 274 if (duplex == DUPLEX_FULL) 275 val |= MIIC_CONVCTRL_FULLD; 276 277 /* No speed in MII through-mode */ 278 if (interface != PHY_INTERFACE_MODE_MII) { 279 switch (speed) { 280 case SPEED_1000: 281 conv_speed = CONV_MODE_1000MBPS; 282 break; 283 case SPEED_100: 284 conv_speed = CONV_MODE_100MBPS; 285 break; 286 case SPEED_10: 287 conv_speed = CONV_MODE_10MBPS; 288 break; 289 default: 290 return; 291 } 292 } 293 294 val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, conv_speed); 295 296 miic_reg_rmw(miic, MIIC_CONVCTRL(port), 297 (MIIC_CONVCTRL_CONV_SPEED | MIIC_CONVCTRL_FULLD), val); 298 } 299 300 static int miic_pre_init(struct phylink_pcs *pcs) 301 { 302 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 303 struct miic *miic = miic_port->miic; 304 u32 val, mask; 305 306 /* Start RX clock if required */ 307 if (pcs->rxc_always_on) { 308 /* In MII through mode, the clock signals will be driven by the 309 * external PHY, which might not be initialized yet. Set RMII 310 * as default mode to ensure that a reference clock signal is 311 * generated. 312 */ 313 miic_port->interface = PHY_INTERFACE_MODE_RMII; 314 315 val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, CONV_MODE_RMII) | 316 FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, CONV_MODE_100MBPS); 317 mask = MIIC_CONVCTRL_CONV_MODE | MIIC_CONVCTRL_CONV_SPEED; 318 319 miic_reg_rmw(miic, MIIC_CONVCTRL(miic_port->port), mask, val); 320 321 miic_converter_enable(miic, miic_port->port, 1); 322 } 323 324 return 0; 325 } 326 327 static const struct phylink_pcs_ops miic_phylink_ops = { 328 .pcs_config = miic_config, 329 .pcs_link_up = miic_link_up, 330 .pcs_pre_init = miic_pre_init, 331 }; 332 333 struct phylink_pcs *miic_create(struct device *dev, struct device_node *np) 334 { 335 const struct miic_of_data *of_data; 336 struct platform_device *pdev; 337 struct miic_port *miic_port; 338 struct device_node *pcs_np; 339 struct miic *miic; 340 u32 port; 341 342 if (!of_device_is_available(np)) 343 return ERR_PTR(-ENODEV); 344 345 if (of_property_read_u32(np, "reg", &port)) 346 return ERR_PTR(-EINVAL); 347 348 /* The PCS pdev is attached to the parent node */ 349 pcs_np = of_get_parent(np); 350 if (!pcs_np) 351 return ERR_PTR(-ENODEV); 352 353 if (!of_device_is_available(pcs_np)) { 354 of_node_put(pcs_np); 355 return ERR_PTR(-ENODEV); 356 } 357 358 pdev = of_find_device_by_node(pcs_np); 359 of_node_put(pcs_np); 360 if (!pdev || !platform_get_drvdata(pdev)) { 361 if (pdev) 362 put_device(&pdev->dev); 363 return ERR_PTR(-EPROBE_DEFER); 364 } 365 366 miic = platform_get_drvdata(pdev); 367 of_data = miic->of_data; 368 if (port > of_data->miic_port_max || port < of_data->miic_port_start) { 369 put_device(&pdev->dev); 370 return ERR_PTR(-EINVAL); 371 } 372 373 miic_port = kzalloc(sizeof(*miic_port), GFP_KERNEL); 374 if (!miic_port) { 375 put_device(&pdev->dev); 376 return ERR_PTR(-ENOMEM); 377 } 378 379 device_link_add(dev, miic->dev, DL_FLAG_AUTOREMOVE_CONSUMER); 380 put_device(&pdev->dev); 381 382 miic_port->miic = miic; 383 miic_port->port = port - of_data->miic_port_start; 384 miic_port->pcs.ops = &miic_phylink_ops; 385 386 phy_interface_set_rgmii(miic_port->pcs.supported_interfaces); 387 __set_bit(PHY_INTERFACE_MODE_RMII, miic_port->pcs.supported_interfaces); 388 __set_bit(PHY_INTERFACE_MODE_MII, miic_port->pcs.supported_interfaces); 389 390 return &miic_port->pcs; 391 } 392 EXPORT_SYMBOL(miic_create); 393 394 void miic_destroy(struct phylink_pcs *pcs) 395 { 396 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 397 398 miic_converter_enable(miic_port->miic, miic_port->port, 0); 399 kfree(miic_port); 400 } 401 EXPORT_SYMBOL(miic_destroy); 402 403 static int miic_init_hw(struct miic *miic, u32 cfg_mode) 404 { 405 int port; 406 407 /* Unlock write access to accessory registers (cf datasheet). If this 408 * is going to be used in conjunction with the Cortex-M3, this sequence 409 * will have to be moved in register write 410 */ 411 miic_reg_writel(miic, MIIC_PRCMD, 0x00A5); 412 miic_reg_writel(miic, MIIC_PRCMD, 0x0001); 413 miic_reg_writel(miic, MIIC_PRCMD, 0xFFFE); 414 miic_reg_writel(miic, MIIC_PRCMD, 0x0001); 415 416 miic_reg_writel(miic, MIIC_MODCTRL, 417 FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode)); 418 419 for (port = 0; port < miic->of_data->miic_port_max; port++) { 420 miic_converter_enable(miic, port, 0); 421 /* Disable speed/duplex control from these registers, datasheet 422 * says switch registers should be used to setup switch port 423 * speed and duplex. 424 */ 425 miic_reg_writel(miic, MIIC_SWCTRL, 0x0); 426 miic_reg_writel(miic, MIIC_SWDUPC, 0x0); 427 } 428 429 return 0; 430 } 431 432 static bool miic_modctrl_match(s8 *table_val, s8 *dt_val, u8 count) 433 { 434 int i; 435 436 for (i = 0; i < count; i++) { 437 if (dt_val[i] == MIIC_MODCTRL_CONF_NONE) 438 continue; 439 440 if (dt_val[i] != table_val[i]) 441 return false; 442 } 443 444 return true; 445 } 446 447 static void miic_dump_conf(struct miic *miic, s8 *conf) 448 { 449 const struct miic_of_data *of_data = miic->of_data; 450 const char *conf_name; 451 int i; 452 453 for (i = 0; i < of_data->conf_conv_count; i++) { 454 if (conf[i] != MIIC_MODCTRL_CONF_NONE) 455 conf_name = of_data->conf_to_string[conf[i]]; 456 else 457 conf_name = "NONE"; 458 459 dev_err(miic->dev, "%s: %s\n", 460 of_data->index_to_string[i], conf_name); 461 } 462 } 463 464 static int miic_match_dt_conf(struct miic *miic, s8 *dt_val, u32 *mode_cfg) 465 { 466 const struct miic_of_data *of_data = miic->of_data; 467 struct modctrl_match *table_entry; 468 int i; 469 470 for (i = 0; i < of_data->match_table_count; i++) { 471 table_entry = &of_data->match_table[i]; 472 473 if (miic_modctrl_match(table_entry->conv, dt_val, 474 miic->of_data->conf_conv_count)) { 475 *mode_cfg = table_entry->mode_cfg; 476 return 0; 477 } 478 } 479 480 dev_err(miic->dev, "Failed to apply requested configuration\n"); 481 miic_dump_conf(miic, dt_val); 482 483 return -EINVAL; 484 } 485 486 static int miic_parse_dt(struct miic *miic, u32 *mode_cfg) 487 { 488 struct device_node *np = miic->dev->of_node; 489 struct device_node *conv; 490 int port, ret; 491 s8 *dt_val; 492 u32 conf; 493 494 dt_val = kmalloc_array(miic->of_data->conf_conv_count, 495 sizeof(*dt_val), GFP_KERNEL); 496 if (!dt_val) 497 return -ENOMEM; 498 499 memset(dt_val, MIIC_MODCTRL_CONF_NONE, sizeof(*dt_val)); 500 501 if (of_property_read_u32(np, "renesas,miic-switch-portin", &conf) == 0) 502 dt_val[0] = conf; 503 504 for_each_available_child_of_node(np, conv) { 505 if (of_property_read_u32(conv, "reg", &port)) 506 continue; 507 508 /* Adjust for 0 based index */ 509 port += !miic->of_data->miic_port_start; 510 if (of_property_read_u32(conv, "renesas,miic-input", &conf) == 0) 511 dt_val[port] = conf; 512 } 513 514 ret = miic_match_dt_conf(miic, dt_val, mode_cfg); 515 kfree(dt_val); 516 517 return ret; 518 } 519 520 static int miic_probe(struct platform_device *pdev) 521 { 522 struct device *dev = &pdev->dev; 523 struct miic *miic; 524 u32 mode_cfg; 525 int ret; 526 527 miic = devm_kzalloc(dev, sizeof(*miic), GFP_KERNEL); 528 if (!miic) 529 return -ENOMEM; 530 531 miic->of_data = of_device_get_match_data(dev); 532 miic->dev = dev; 533 534 ret = miic_parse_dt(miic, &mode_cfg); 535 if (ret < 0) 536 return ret; 537 538 spin_lock_init(&miic->lock); 539 miic->base = devm_platform_ioremap_resource(pdev, 0); 540 if (IS_ERR(miic->base)) 541 return PTR_ERR(miic->base); 542 543 ret = devm_pm_runtime_enable(dev); 544 if (ret < 0) 545 return ret; 546 547 ret = pm_runtime_resume_and_get(dev); 548 if (ret < 0) 549 return ret; 550 551 ret = miic_init_hw(miic, mode_cfg); 552 if (ret) 553 goto disable_runtime_pm; 554 555 /* miic_create() relies on that fact that data are attached to the 556 * platform device to determine if the driver is ready so this needs to 557 * be the last thing to be done after everything is initialized 558 * properly. 559 */ 560 platform_set_drvdata(pdev, miic); 561 562 return 0; 563 564 disable_runtime_pm: 565 pm_runtime_put(dev); 566 567 return ret; 568 } 569 570 static void miic_remove(struct platform_device *pdev) 571 { 572 pm_runtime_put(&pdev->dev); 573 } 574 575 static struct miic_of_data rzn1_miic_of_data = { 576 .match_table = modctrl_match_table, 577 .match_table_count = ARRAY_SIZE(modctrl_match_table), 578 .conf_conv_count = MIIC_MODCTRL_CONF_CONV_MAX, 579 .conf_to_string = conf_to_string, 580 .conf_to_string_count = ARRAY_SIZE(conf_to_string), 581 .index_to_string = index_to_string, 582 .index_to_string_count = ARRAY_SIZE(index_to_string), 583 .miic_port_start = 1, 584 .miic_port_max = 5, 585 }; 586 587 static const struct of_device_id miic_of_mtable[] = { 588 { .compatible = "renesas,rzn1-miic", .data = &rzn1_miic_of_data }, 589 { /* sentinel */ } 590 }; 591 MODULE_DEVICE_TABLE(of, miic_of_mtable); 592 593 static struct platform_driver miic_driver = { 594 .driver = { 595 .name = "rzn1_miic", 596 .suppress_bind_attrs = true, 597 .of_match_table = miic_of_mtable, 598 }, 599 .probe = miic_probe, 600 .remove = miic_remove, 601 }; 602 module_platform_driver(miic_driver); 603 604 MODULE_LICENSE("GPL"); 605 MODULE_DESCRIPTION("Renesas MII converter PCS driver"); 606 MODULE_AUTHOR("Clément Léger <clement.leger@bootlin.com>"); 607