1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2022 Schneider Electric 4 * 5 * Clément Léger <clement.leger@bootlin.com> 6 */ 7 8 #include <linux/array_size.h> 9 #include <linux/bits.h> 10 #include <linux/clk.h> 11 #include <linux/device.h> 12 #include <linux/mdio.h> 13 #include <linux/of.h> 14 #include <linux/of_platform.h> 15 #include <linux/pcs-rzn1-miic.h> 16 #include <linux/phylink.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <dt-bindings/net/pcs-rzn1-miic.h> 20 21 #define MIIC_PRCMD 0x0 22 #define MIIC_ESID_CODE 0x4 23 24 #define MIIC_MODCTRL 0x8 25 #define MIIC_MODCTRL_SW_MODE GENMASK(4, 0) 26 27 #define MIIC_CONVCTRL(port) (0x100 + (port) * 4) 28 29 #define MIIC_CONVCTRL_CONV_SPEED GENMASK(1, 0) 30 #define CONV_MODE_10MBPS 0 31 #define CONV_MODE_100MBPS 1 32 #define CONV_MODE_1000MBPS 2 33 34 #define MIIC_CONVCTRL_CONV_MODE GENMASK(3, 2) 35 #define CONV_MODE_MII 0 36 #define CONV_MODE_RMII 1 37 #define CONV_MODE_RGMII 2 38 39 #define MIIC_CONVCTRL_FULLD BIT(8) 40 #define MIIC_CONVCTRL_RGMII_LINK BIT(12) 41 #define MIIC_CONVCTRL_RGMII_DUPLEX BIT(13) 42 #define MIIC_CONVCTRL_RGMII_SPEED GENMASK(15, 14) 43 44 #define MIIC_CONVRST 0x114 45 #define MIIC_CONVRST_PHYIF_RST(port) BIT(port) 46 #define MIIC_CONVRST_PHYIF_RST_MASK GENMASK(4, 0) 47 48 #define MIIC_SWCTRL 0x304 49 #define MIIC_SWDUPC 0x308 50 51 #define MIIC_MAX_NR_PORTS 5 52 53 #define MIIC_MODCTRL_CONF_CONV_NUM 6 54 #define MIIC_MODCTRL_CONF_NONE -1 55 56 /** 57 * struct modctrl_match - Matching table entry for convctrl configuration 58 * See section 8.2.1 of manual. 59 * @mode_cfg: Configuration value for convctrl 60 * @conv: Configuration of ethernet port muxes. First index is SWITCH_PORTIN, 61 * then index 1 - 5 are CONV1 - CONV5. 62 */ 63 struct modctrl_match { 64 u32 mode_cfg; 65 u8 conv[MIIC_MODCTRL_CONF_CONV_NUM]; 66 }; 67 68 static struct modctrl_match modctrl_match_table[] = { 69 {0x0, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 70 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 71 {0x1, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 72 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 73 {0x2, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 74 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 75 {0x3, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 76 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}, 77 78 {0x8, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 79 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 80 {0x9, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 81 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 82 {0xA, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 83 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 84 {0xB, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 85 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}, 86 87 {0x10, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 88 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 89 {0x11, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 90 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 91 {0x12, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 92 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 93 {0x13, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 94 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}} 95 }; 96 97 static const char * const conf_to_string[] = { 98 [MIIC_GMAC1_PORT] = "GMAC1_PORT", 99 [MIIC_GMAC2_PORT] = "GMAC2_PORT", 100 [MIIC_RTOS_PORT] = "RTOS_PORT", 101 [MIIC_SERCOS_PORTA] = "SERCOS_PORTA", 102 [MIIC_SERCOS_PORTB] = "SERCOS_PORTB", 103 [MIIC_ETHERCAT_PORTA] = "ETHERCAT_PORTA", 104 [MIIC_ETHERCAT_PORTB] = "ETHERCAT_PORTB", 105 [MIIC_ETHERCAT_PORTC] = "ETHERCAT_PORTC", 106 [MIIC_SWITCH_PORTA] = "SWITCH_PORTA", 107 [MIIC_SWITCH_PORTB] = "SWITCH_PORTB", 108 [MIIC_SWITCH_PORTC] = "SWITCH_PORTC", 109 [MIIC_SWITCH_PORTD] = "SWITCH_PORTD", 110 [MIIC_HSR_PORTA] = "HSR_PORTA", 111 [MIIC_HSR_PORTB] = "HSR_PORTB", 112 }; 113 114 static const char *index_to_string[MIIC_MODCTRL_CONF_CONV_NUM] = { 115 "SWITCH_PORTIN", 116 "CONV1", 117 "CONV2", 118 "CONV3", 119 "CONV4", 120 "CONV5", 121 }; 122 123 /** 124 * struct miic - MII converter structure 125 * @base: base address of the MII converter 126 * @dev: Device associated to the MII converter 127 * @lock: Lock used for read-modify-write access 128 */ 129 struct miic { 130 void __iomem *base; 131 struct device *dev; 132 spinlock_t lock; 133 }; 134 135 /** 136 * struct miic_port - Per port MII converter struct 137 * @miic: backiling to MII converter structure 138 * @pcs: PCS structure associated to the port 139 * @port: port number 140 * @interface: interface mode of the port 141 */ 142 struct miic_port { 143 struct miic *miic; 144 struct phylink_pcs pcs; 145 int port; 146 phy_interface_t interface; 147 }; 148 149 static struct miic_port *phylink_pcs_to_miic_port(struct phylink_pcs *pcs) 150 { 151 return container_of(pcs, struct miic_port, pcs); 152 } 153 154 static void miic_reg_writel(struct miic *miic, int offset, u32 value) 155 { 156 writel(value, miic->base + offset); 157 } 158 159 static u32 miic_reg_readl(struct miic *miic, int offset) 160 { 161 return readl(miic->base + offset); 162 } 163 164 static void miic_reg_rmw(struct miic *miic, int offset, u32 mask, u32 val) 165 { 166 u32 reg; 167 168 spin_lock(&miic->lock); 169 170 reg = miic_reg_readl(miic, offset); 171 reg &= ~mask; 172 reg |= val; 173 miic_reg_writel(miic, offset, reg); 174 175 spin_unlock(&miic->lock); 176 } 177 178 static void miic_converter_enable(struct miic *miic, int port, int enable) 179 { 180 u32 val = 0; 181 182 if (enable) 183 val = MIIC_CONVRST_PHYIF_RST(port); 184 185 miic_reg_rmw(miic, MIIC_CONVRST, MIIC_CONVRST_PHYIF_RST(port), val); 186 } 187 188 static int miic_config(struct phylink_pcs *pcs, unsigned int neg_mode, 189 phy_interface_t interface, 190 const unsigned long *advertising, bool permit) 191 { 192 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 193 struct miic *miic = miic_port->miic; 194 u32 speed, conv_mode, val, mask; 195 int port = miic_port->port; 196 197 switch (interface) { 198 case PHY_INTERFACE_MODE_RMII: 199 conv_mode = CONV_MODE_RMII; 200 speed = CONV_MODE_100MBPS; 201 break; 202 case PHY_INTERFACE_MODE_RGMII: 203 case PHY_INTERFACE_MODE_RGMII_ID: 204 case PHY_INTERFACE_MODE_RGMII_TXID: 205 case PHY_INTERFACE_MODE_RGMII_RXID: 206 conv_mode = CONV_MODE_RGMII; 207 speed = CONV_MODE_1000MBPS; 208 break; 209 case PHY_INTERFACE_MODE_MII: 210 conv_mode = CONV_MODE_MII; 211 /* When in MII mode, speed should be set to 0 (which is actually 212 * CONV_MODE_10MBPS) 213 */ 214 speed = CONV_MODE_10MBPS; 215 break; 216 default: 217 return -EOPNOTSUPP; 218 } 219 220 val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, conv_mode); 221 mask = MIIC_CONVCTRL_CONV_MODE; 222 223 /* Update speed only if we are going to change the interface because 224 * the link might already be up and it would break it if the speed is 225 * changed. 226 */ 227 if (interface != miic_port->interface) { 228 val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, speed); 229 mask |= MIIC_CONVCTRL_CONV_SPEED; 230 miic_port->interface = interface; 231 } 232 233 miic_reg_rmw(miic, MIIC_CONVCTRL(port), mask, val); 234 miic_converter_enable(miic, miic_port->port, 1); 235 236 return 0; 237 } 238 239 static void miic_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, 240 phy_interface_t interface, int speed, int duplex) 241 { 242 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 243 struct miic *miic = miic_port->miic; 244 u32 conv_speed = 0, val = 0; 245 int port = miic_port->port; 246 247 if (duplex == DUPLEX_FULL) 248 val |= MIIC_CONVCTRL_FULLD; 249 250 /* No speed in MII through-mode */ 251 if (interface != PHY_INTERFACE_MODE_MII) { 252 switch (speed) { 253 case SPEED_1000: 254 conv_speed = CONV_MODE_1000MBPS; 255 break; 256 case SPEED_100: 257 conv_speed = CONV_MODE_100MBPS; 258 break; 259 case SPEED_10: 260 conv_speed = CONV_MODE_10MBPS; 261 break; 262 default: 263 return; 264 } 265 } 266 267 val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, conv_speed); 268 269 miic_reg_rmw(miic, MIIC_CONVCTRL(port), 270 (MIIC_CONVCTRL_CONV_SPEED | MIIC_CONVCTRL_FULLD), val); 271 } 272 273 static int miic_pre_init(struct phylink_pcs *pcs) 274 { 275 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 276 struct miic *miic = miic_port->miic; 277 u32 val, mask; 278 279 /* Start RX clock if required */ 280 if (pcs->rxc_always_on) { 281 /* In MII through mode, the clock signals will be driven by the 282 * external PHY, which might not be initialized yet. Set RMII 283 * as default mode to ensure that a reference clock signal is 284 * generated. 285 */ 286 miic_port->interface = PHY_INTERFACE_MODE_RMII; 287 288 val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, CONV_MODE_RMII) | 289 FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, CONV_MODE_100MBPS); 290 mask = MIIC_CONVCTRL_CONV_MODE | MIIC_CONVCTRL_CONV_SPEED; 291 292 miic_reg_rmw(miic, MIIC_CONVCTRL(miic_port->port), mask, val); 293 294 miic_converter_enable(miic, miic_port->port, 1); 295 } 296 297 return 0; 298 } 299 300 static const struct phylink_pcs_ops miic_phylink_ops = { 301 .pcs_config = miic_config, 302 .pcs_link_up = miic_link_up, 303 .pcs_pre_init = miic_pre_init, 304 }; 305 306 struct phylink_pcs *miic_create(struct device *dev, struct device_node *np) 307 { 308 struct platform_device *pdev; 309 struct miic_port *miic_port; 310 struct device_node *pcs_np; 311 struct miic *miic; 312 u32 port; 313 314 if (!of_device_is_available(np)) 315 return ERR_PTR(-ENODEV); 316 317 if (of_property_read_u32(np, "reg", &port)) 318 return ERR_PTR(-EINVAL); 319 320 if (port > MIIC_MAX_NR_PORTS || port < 1) 321 return ERR_PTR(-EINVAL); 322 323 /* The PCS pdev is attached to the parent node */ 324 pcs_np = of_get_parent(np); 325 if (!pcs_np) 326 return ERR_PTR(-ENODEV); 327 328 if (!of_device_is_available(pcs_np)) { 329 of_node_put(pcs_np); 330 return ERR_PTR(-ENODEV); 331 } 332 333 pdev = of_find_device_by_node(pcs_np); 334 of_node_put(pcs_np); 335 if (!pdev || !platform_get_drvdata(pdev)) { 336 if (pdev) 337 put_device(&pdev->dev); 338 return ERR_PTR(-EPROBE_DEFER); 339 } 340 341 miic_port = kzalloc(sizeof(*miic_port), GFP_KERNEL); 342 if (!miic_port) { 343 put_device(&pdev->dev); 344 return ERR_PTR(-ENOMEM); 345 } 346 347 miic = platform_get_drvdata(pdev); 348 device_link_add(dev, miic->dev, DL_FLAG_AUTOREMOVE_CONSUMER); 349 put_device(&pdev->dev); 350 351 miic_port->miic = miic; 352 miic_port->port = port - 1; 353 miic_port->pcs.ops = &miic_phylink_ops; 354 355 phy_interface_set_rgmii(miic_port->pcs.supported_interfaces); 356 __set_bit(PHY_INTERFACE_MODE_RMII, miic_port->pcs.supported_interfaces); 357 __set_bit(PHY_INTERFACE_MODE_MII, miic_port->pcs.supported_interfaces); 358 359 return &miic_port->pcs; 360 } 361 EXPORT_SYMBOL(miic_create); 362 363 void miic_destroy(struct phylink_pcs *pcs) 364 { 365 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 366 367 miic_converter_enable(miic_port->miic, miic_port->port, 0); 368 kfree(miic_port); 369 } 370 EXPORT_SYMBOL(miic_destroy); 371 372 static int miic_init_hw(struct miic *miic, u32 cfg_mode) 373 { 374 int port; 375 376 /* Unlock write access to accessory registers (cf datasheet). If this 377 * is going to be used in conjunction with the Cortex-M3, this sequence 378 * will have to be moved in register write 379 */ 380 miic_reg_writel(miic, MIIC_PRCMD, 0x00A5); 381 miic_reg_writel(miic, MIIC_PRCMD, 0x0001); 382 miic_reg_writel(miic, MIIC_PRCMD, 0xFFFE); 383 miic_reg_writel(miic, MIIC_PRCMD, 0x0001); 384 385 miic_reg_writel(miic, MIIC_MODCTRL, 386 FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode)); 387 388 for (port = 0; port < MIIC_MAX_NR_PORTS; port++) { 389 miic_converter_enable(miic, port, 0); 390 /* Disable speed/duplex control from these registers, datasheet 391 * says switch registers should be used to setup switch port 392 * speed and duplex. 393 */ 394 miic_reg_writel(miic, MIIC_SWCTRL, 0x0); 395 miic_reg_writel(miic, MIIC_SWDUPC, 0x0); 396 } 397 398 return 0; 399 } 400 401 static bool miic_modctrl_match(s8 table_val[MIIC_MODCTRL_CONF_CONV_NUM], 402 s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM]) 403 { 404 int i; 405 406 for (i = 0; i < MIIC_MODCTRL_CONF_CONV_NUM; i++) { 407 if (dt_val[i] == MIIC_MODCTRL_CONF_NONE) 408 continue; 409 410 if (dt_val[i] != table_val[i]) 411 return false; 412 } 413 414 return true; 415 } 416 417 static void miic_dump_conf(struct device *dev, 418 s8 conf[MIIC_MODCTRL_CONF_CONV_NUM]) 419 { 420 const char *conf_name; 421 int i; 422 423 for (i = 0; i < MIIC_MODCTRL_CONF_CONV_NUM; i++) { 424 if (conf[i] != MIIC_MODCTRL_CONF_NONE) 425 conf_name = conf_to_string[conf[i]]; 426 else 427 conf_name = "NONE"; 428 429 dev_err(dev, "%s: %s\n", index_to_string[i], conf_name); 430 } 431 } 432 433 static int miic_match_dt_conf(struct device *dev, 434 s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM], 435 u32 *mode_cfg) 436 { 437 struct modctrl_match *table_entry; 438 int i; 439 440 for (i = 0; i < ARRAY_SIZE(modctrl_match_table); i++) { 441 table_entry = &modctrl_match_table[i]; 442 443 if (miic_modctrl_match(table_entry->conv, dt_val)) { 444 *mode_cfg = table_entry->mode_cfg; 445 return 0; 446 } 447 } 448 449 dev_err(dev, "Failed to apply requested configuration\n"); 450 miic_dump_conf(dev, dt_val); 451 452 return -EINVAL; 453 } 454 455 static int miic_parse_dt(struct device *dev, u32 *mode_cfg) 456 { 457 s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM]; 458 struct device_node *np = dev->of_node; 459 struct device_node *conv; 460 u32 conf; 461 int port; 462 463 memset(dt_val, MIIC_MODCTRL_CONF_NONE, sizeof(dt_val)); 464 465 if (of_property_read_u32(np, "renesas,miic-switch-portin", &conf) == 0) 466 dt_val[0] = conf; 467 468 for_each_available_child_of_node(np, conv) { 469 if (of_property_read_u32(conv, "reg", &port)) 470 continue; 471 472 if (of_property_read_u32(conv, "renesas,miic-input", &conf) == 0) 473 dt_val[port] = conf; 474 } 475 476 return miic_match_dt_conf(dev, dt_val, mode_cfg); 477 } 478 479 static int miic_probe(struct platform_device *pdev) 480 { 481 struct device *dev = &pdev->dev; 482 struct miic *miic; 483 u32 mode_cfg; 484 int ret; 485 486 ret = miic_parse_dt(dev, &mode_cfg); 487 if (ret < 0) 488 return ret; 489 490 miic = devm_kzalloc(dev, sizeof(*miic), GFP_KERNEL); 491 if (!miic) 492 return -ENOMEM; 493 494 spin_lock_init(&miic->lock); 495 miic->dev = dev; 496 miic->base = devm_platform_ioremap_resource(pdev, 0); 497 if (IS_ERR(miic->base)) 498 return PTR_ERR(miic->base); 499 500 ret = devm_pm_runtime_enable(dev); 501 if (ret < 0) 502 return ret; 503 504 ret = pm_runtime_resume_and_get(dev); 505 if (ret < 0) 506 return ret; 507 508 ret = miic_init_hw(miic, mode_cfg); 509 if (ret) 510 goto disable_runtime_pm; 511 512 /* miic_create() relies on that fact that data are attached to the 513 * platform device to determine if the driver is ready so this needs to 514 * be the last thing to be done after everything is initialized 515 * properly. 516 */ 517 platform_set_drvdata(pdev, miic); 518 519 return 0; 520 521 disable_runtime_pm: 522 pm_runtime_put(dev); 523 524 return ret; 525 } 526 527 static void miic_remove(struct platform_device *pdev) 528 { 529 pm_runtime_put(&pdev->dev); 530 } 531 532 static const struct of_device_id miic_of_mtable[] = { 533 { .compatible = "renesas,rzn1-miic" }, 534 { /* sentinel */ } 535 }; 536 MODULE_DEVICE_TABLE(of, miic_of_mtable); 537 538 static struct platform_driver miic_driver = { 539 .driver = { 540 .name = "rzn1_miic", 541 .suppress_bind_attrs = true, 542 .of_match_table = miic_of_mtable, 543 }, 544 .probe = miic_probe, 545 .remove = miic_remove, 546 }; 547 module_platform_driver(miic_driver); 548 549 MODULE_LICENSE("GPL"); 550 MODULE_DESCRIPTION("Renesas MII converter PCS driver"); 551 MODULE_AUTHOR("Clément Léger <clement.leger@bootlin.com>"); 552