xref: /linux/drivers/net/mdio/mdio-ipq8064.c (revision 0ea5c948cb64bab5bc7a5516774eb8536f05aa0d)
1a9770eacSAndrew Lunn // SPDX-License-Identifier: GPL-2.0
2a9770eacSAndrew Lunn /* Qualcomm IPQ8064 MDIO interface driver
3a9770eacSAndrew Lunn  *
4a9770eacSAndrew Lunn  * Copyright (C) 2019 Christian Lamparter <chunkeey@gmail.com>
5a9770eacSAndrew Lunn  * Copyright (C) 2020 Ansuel Smith <ansuelsmth@gmail.com>
6a9770eacSAndrew Lunn  */
7a9770eacSAndrew Lunn 
8a9770eacSAndrew Lunn #include <linux/delay.h>
9a9770eacSAndrew Lunn #include <linux/kernel.h>
10a9770eacSAndrew Lunn #include <linux/module.h>
11a9770eacSAndrew Lunn #include <linux/of_mdio.h>
12b097bea1SAnsuel Smith #include <linux/of_address.h>
13a9770eacSAndrew Lunn #include <linux/platform_device.h>
141bf34366SCalvin Johnson #include <linux/regmap.h>
15a9770eacSAndrew Lunn 
16a9770eacSAndrew Lunn /* MII address register definitions */
17a9770eacSAndrew Lunn #define MII_ADDR_REG_ADDR			0x10
18a9770eacSAndrew Lunn #define MII_BUSY				BIT(0)
19a9770eacSAndrew Lunn #define MII_WRITE				BIT(1)
2094864069SAnsuel Smith #define MII_CLKRANGE(x)				((x) << 2)
2194864069SAnsuel Smith #define MII_CLKRANGE_60_100M			MII_CLKRANGE(0)
2294864069SAnsuel Smith #define MII_CLKRANGE_100_150M			MII_CLKRANGE(1)
2394864069SAnsuel Smith #define MII_CLKRANGE_20_35M			MII_CLKRANGE(2)
2494864069SAnsuel Smith #define MII_CLKRANGE_35_60M			MII_CLKRANGE(3)
2594864069SAnsuel Smith #define MII_CLKRANGE_150_250M			MII_CLKRANGE(4)
2694864069SAnsuel Smith #define MII_CLKRANGE_250_300M			MII_CLKRANGE(5)
27a9770eacSAndrew Lunn #define MII_CLKRANGE_MASK			GENMASK(4, 2)
28a9770eacSAndrew Lunn #define MII_REG_SHIFT				6
29a9770eacSAndrew Lunn #define MII_REG_MASK				GENMASK(10, 6)
30a9770eacSAndrew Lunn #define MII_ADDR_SHIFT				11
31a9770eacSAndrew Lunn #define MII_ADDR_MASK				GENMASK(15, 11)
32a9770eacSAndrew Lunn 
33a9770eacSAndrew Lunn #define MII_DATA_REG_ADDR			0x14
34a9770eacSAndrew Lunn 
35a9770eacSAndrew Lunn #define MII_MDIO_DELAY_USEC			(1000)
36a9770eacSAndrew Lunn #define MII_MDIO_RETRY_MSEC			(10)
37a9770eacSAndrew Lunn 
38a9770eacSAndrew Lunn struct ipq8064_mdio {
39a9770eacSAndrew Lunn 	struct regmap *base; /* NSS_GMAC0_BASE */
40a9770eacSAndrew Lunn };
41a9770eacSAndrew Lunn 
42a9770eacSAndrew Lunn static int
ipq8064_mdio_wait_busy(struct ipq8064_mdio * priv)43a9770eacSAndrew Lunn ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv)
44a9770eacSAndrew Lunn {
45a9770eacSAndrew Lunn 	u32 busy;
46a9770eacSAndrew Lunn 
47a9770eacSAndrew Lunn 	return regmap_read_poll_timeout(priv->base, MII_ADDR_REG_ADDR, busy,
48a9770eacSAndrew Lunn 					!(busy & MII_BUSY), MII_MDIO_DELAY_USEC,
49a9770eacSAndrew Lunn 					MII_MDIO_RETRY_MSEC * USEC_PER_MSEC);
50a9770eacSAndrew Lunn }
51a9770eacSAndrew Lunn 
52a9770eacSAndrew Lunn static int
ipq8064_mdio_read(struct mii_bus * bus,int phy_addr,int reg_offset)53a9770eacSAndrew Lunn ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset)
54a9770eacSAndrew Lunn {
55a9770eacSAndrew Lunn 	u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M;
56a9770eacSAndrew Lunn 	struct ipq8064_mdio *priv = bus->priv;
57a9770eacSAndrew Lunn 	u32 ret_val;
58a9770eacSAndrew Lunn 	int err;
59a9770eacSAndrew Lunn 
60a9770eacSAndrew Lunn 	miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
61a9770eacSAndrew Lunn 		   ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
62a9770eacSAndrew Lunn 
63a9770eacSAndrew Lunn 	regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
6477091933SAnsuel Smith 	usleep_range(10, 13);
65a9770eacSAndrew Lunn 
66a9770eacSAndrew Lunn 	err = ipq8064_mdio_wait_busy(priv);
67a9770eacSAndrew Lunn 	if (err)
68a9770eacSAndrew Lunn 		return err;
69a9770eacSAndrew Lunn 
70a9770eacSAndrew Lunn 	regmap_read(priv->base, MII_DATA_REG_ADDR, &ret_val);
71a9770eacSAndrew Lunn 	return (int)ret_val;
72a9770eacSAndrew Lunn }
73a9770eacSAndrew Lunn 
74a9770eacSAndrew Lunn static int
ipq8064_mdio_write(struct mii_bus * bus,int phy_addr,int reg_offset,u16 data)75a9770eacSAndrew Lunn ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data)
76a9770eacSAndrew Lunn {
77a9770eacSAndrew Lunn 	u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M;
78a9770eacSAndrew Lunn 	struct ipq8064_mdio *priv = bus->priv;
79a9770eacSAndrew Lunn 
80a9770eacSAndrew Lunn 	regmap_write(priv->base, MII_DATA_REG_ADDR, data);
81a9770eacSAndrew Lunn 
82a9770eacSAndrew Lunn 	miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
83a9770eacSAndrew Lunn 		   ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
84a9770eacSAndrew Lunn 
85a9770eacSAndrew Lunn 	regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
8677091933SAnsuel Smith 
8777091933SAnsuel Smith 	/* For the specific reg 31 extra time is needed or the next
8877091933SAnsuel Smith 	 * read will produce garbage data.
8977091933SAnsuel Smith 	 */
9077091933SAnsuel Smith 	if (reg_offset == 31)
9177091933SAnsuel Smith 		usleep_range(30, 43);
9277091933SAnsuel Smith 	else
9377091933SAnsuel Smith 		usleep_range(10, 13);
94a9770eacSAndrew Lunn 
95a9770eacSAndrew Lunn 	return ipq8064_mdio_wait_busy(priv);
96a9770eacSAndrew Lunn }
97a9770eacSAndrew Lunn 
98b097bea1SAnsuel Smith static const struct regmap_config ipq8064_mdio_regmap_config = {
99b097bea1SAnsuel Smith 	.reg_bits = 32,
100b097bea1SAnsuel Smith 	.reg_stride = 4,
101b097bea1SAnsuel Smith 	.val_bits = 32,
102b097bea1SAnsuel Smith 	.can_multi_write = false,
103b097bea1SAnsuel Smith 	/* the mdio lock is used by any user of this mdio driver */
104b097bea1SAnsuel Smith 	.disable_locking = true,
105b097bea1SAnsuel Smith 
106b097bea1SAnsuel Smith 	.cache_type = REGCACHE_NONE,
107b097bea1SAnsuel Smith };
108b097bea1SAnsuel Smith 
109a9770eacSAndrew Lunn static int
ipq8064_mdio_probe(struct platform_device * pdev)110a9770eacSAndrew Lunn ipq8064_mdio_probe(struct platform_device *pdev)
111a9770eacSAndrew Lunn {
112a9770eacSAndrew Lunn 	struct device_node *np = pdev->dev.of_node;
113a9770eacSAndrew Lunn 	struct ipq8064_mdio *priv;
114b097bea1SAnsuel Smith 	struct resource res;
115a9770eacSAndrew Lunn 	struct mii_bus *bus;
116b097bea1SAnsuel Smith 	void __iomem *base;
117a9770eacSAndrew Lunn 	int ret;
118a9770eacSAndrew Lunn 
119b097bea1SAnsuel Smith 	if (of_address_to_resource(np, 0, &res))
120b097bea1SAnsuel Smith 		return -ENOMEM;
121b097bea1SAnsuel Smith 
1222f7ed29fSYang Yingliang 	base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
123b097bea1SAnsuel Smith 	if (!base)
124b097bea1SAnsuel Smith 		return -ENOMEM;
125b097bea1SAnsuel Smith 
126a9770eacSAndrew Lunn 	bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv));
127a9770eacSAndrew Lunn 	if (!bus)
128a9770eacSAndrew Lunn 		return -ENOMEM;
129a9770eacSAndrew Lunn 
130a9770eacSAndrew Lunn 	bus->name = "ipq8064_mdio_bus";
131a9770eacSAndrew Lunn 	bus->read = ipq8064_mdio_read;
132a9770eacSAndrew Lunn 	bus->write = ipq8064_mdio_write;
133a9770eacSAndrew Lunn 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
134a9770eacSAndrew Lunn 	bus->parent = &pdev->dev;
135a9770eacSAndrew Lunn 
136a9770eacSAndrew Lunn 	priv = bus->priv;
137b097bea1SAnsuel Smith 	priv->base = devm_regmap_init_mmio(&pdev->dev, base,
138b097bea1SAnsuel Smith 					   &ipq8064_mdio_regmap_config);
139b097bea1SAnsuel Smith 	if (IS_ERR(priv->base))
140a9770eacSAndrew Lunn 		return PTR_ERR(priv->base);
141a9770eacSAndrew Lunn 
142a9770eacSAndrew Lunn 	ret = of_mdiobus_register(bus, np);
143a9770eacSAndrew Lunn 	if (ret)
144a9770eacSAndrew Lunn 		return ret;
145a9770eacSAndrew Lunn 
146a9770eacSAndrew Lunn 	platform_set_drvdata(pdev, bus);
147a9770eacSAndrew Lunn 	return 0;
148a9770eacSAndrew Lunn }
149a9770eacSAndrew Lunn 
ipq8064_mdio_remove(struct platform_device * pdev)150*cd5510c2SUwe Kleine-König static void ipq8064_mdio_remove(struct platform_device *pdev)
151a9770eacSAndrew Lunn {
152a9770eacSAndrew Lunn 	struct mii_bus *bus = platform_get_drvdata(pdev);
153a9770eacSAndrew Lunn 
154a9770eacSAndrew Lunn 	mdiobus_unregister(bus);
155a9770eacSAndrew Lunn }
156a9770eacSAndrew Lunn 
157a9770eacSAndrew Lunn static const struct of_device_id ipq8064_mdio_dt_ids[] = {
158a9770eacSAndrew Lunn 	{ .compatible = "qcom,ipq8064-mdio" },
159a9770eacSAndrew Lunn 	{ }
160a9770eacSAndrew Lunn };
161a9770eacSAndrew Lunn MODULE_DEVICE_TABLE(of, ipq8064_mdio_dt_ids);
162a9770eacSAndrew Lunn 
163a9770eacSAndrew Lunn static struct platform_driver ipq8064_mdio_driver = {
164a9770eacSAndrew Lunn 	.probe = ipq8064_mdio_probe,
165*cd5510c2SUwe Kleine-König 	.remove_new = ipq8064_mdio_remove,
166a9770eacSAndrew Lunn 	.driver = {
167a9770eacSAndrew Lunn 		.name = "ipq8064-mdio",
168a9770eacSAndrew Lunn 		.of_match_table = ipq8064_mdio_dt_ids,
169a9770eacSAndrew Lunn 	},
170a9770eacSAndrew Lunn };
171a9770eacSAndrew Lunn 
172a9770eacSAndrew Lunn module_platform_driver(ipq8064_mdio_driver);
173a9770eacSAndrew Lunn 
174a9770eacSAndrew Lunn MODULE_DESCRIPTION("Qualcomm IPQ8064 MDIO interface driver");
175a9770eacSAndrew Lunn MODULE_AUTHOR("Christian Lamparter <chunkeey@gmail.com>");
176a9770eacSAndrew Lunn MODULE_AUTHOR("Ansuel Smith <ansuelsmth@gmail.com>");
177a9770eacSAndrew Lunn MODULE_LICENSE("GPL");
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