1cb7550b4SAlex Elder // SPDX-License-Identifier: GPL-2.0 2cb7550b4SAlex Elder 3*ff39eefdSAlex Elder /* Copyright (C) 2023-2024 Linaro Ltd. */ 4cb7550b4SAlex Elder 5*ff39eefdSAlex Elder #include <linux/array_size.h> 6cb7550b4SAlex Elder #include <linux/log2.h> 7cb7550b4SAlex Elder 8cb7550b4SAlex Elder #include "../gsi.h" 9cb7550b4SAlex Elder #include "../ipa_data.h" 10cb7550b4SAlex Elder #include "../ipa_endpoint.h" 11cb7550b4SAlex Elder #include "../ipa_mem.h" 12cb7550b4SAlex Elder 13cb7550b4SAlex Elder /** enum ipa_resource_type - IPA resource types for an SoC having IPA v5.0 */ 14cb7550b4SAlex Elder enum ipa_resource_type { 15cb7550b4SAlex Elder /* Source resource types; first must have value 0 */ 16cb7550b4SAlex Elder IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, 17cb7550b4SAlex Elder IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, 18cb7550b4SAlex Elder IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, 19cb7550b4SAlex Elder IPA_RESOURCE_TYPE_SRC_HPS_DMARS, 20cb7550b4SAlex Elder IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, 21cb7550b4SAlex Elder 22cb7550b4SAlex Elder /* Destination resource types; first must have value 0 */ 23cb7550b4SAlex Elder IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, 24cb7550b4SAlex Elder IPA_RESOURCE_TYPE_DST_DPS_DMARS, 25cb7550b4SAlex Elder IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS, 26cb7550b4SAlex Elder }; 27cb7550b4SAlex Elder 28cb7550b4SAlex Elder /* Resource groups used for an SoC having IPA v5.0 */ 29cb7550b4SAlex Elder enum ipa_rsrc_group_id { 30cb7550b4SAlex Elder /* Source resource group identifiers */ 31cb7550b4SAlex Elder IPA_RSRC_GROUP_SRC_UL = 0, 32cb7550b4SAlex Elder IPA_RSRC_GROUP_SRC_DL, 33cb7550b4SAlex Elder IPA_RSRC_GROUP_SRC_UNUSED_2, 34cb7550b4SAlex Elder IPA_RSRC_GROUP_SRC_UNUSED_3, 35cb7550b4SAlex Elder IPA_RSRC_GROUP_SRC_URLLC, 36cb7550b4SAlex Elder IPA_RSRC_GROUP_SRC_U_RX_QC, 37cb7550b4SAlex Elder IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ 38cb7550b4SAlex Elder 39cb7550b4SAlex Elder /* Destination resource group identifiers */ 40cb7550b4SAlex Elder IPA_RSRC_GROUP_DST_UL = 0, 41cb7550b4SAlex Elder IPA_RSRC_GROUP_DST_DL, 42cb7550b4SAlex Elder IPA_RSRC_GROUP_DST_DMA, 43cb7550b4SAlex Elder IPA_RSRC_GROUP_DST_QDSS, 44cb7550b4SAlex Elder IPA_RSRC_GROUP_DST_CV2X, 45cb7550b4SAlex Elder IPA_RSRC_GROUP_DST_UC, 46cb7550b4SAlex Elder IPA_RSRC_GROUP_DST_DRB_IP, 47cb7550b4SAlex Elder IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ 48cb7550b4SAlex Elder }; 49cb7550b4SAlex Elder 50cb7550b4SAlex Elder /* QSB configuration data for an SoC having IPA v5.0 */ 51cb7550b4SAlex Elder static const struct ipa_qsb_data ipa_qsb_data[] = { 52cb7550b4SAlex Elder [IPA_QSB_MASTER_DDR] = { 53cb7550b4SAlex Elder .max_writes = 0, 54cb7550b4SAlex Elder .max_reads = 0, /* no limit (hardware max) */ 55cb7550b4SAlex Elder .max_reads_beats = 0, 56cb7550b4SAlex Elder }, 57cb7550b4SAlex Elder [IPA_QSB_MASTER_PCIE] = { 58cb7550b4SAlex Elder .max_writes = 0, 59cb7550b4SAlex Elder .max_reads = 0, /* no limit (hardware max) */ 60cb7550b4SAlex Elder .max_reads_beats = 0, 61cb7550b4SAlex Elder }, 62cb7550b4SAlex Elder }; 63cb7550b4SAlex Elder 64cb7550b4SAlex Elder /* Endpoint configuration data for an SoC having IPA v5.0 */ 65cb7550b4SAlex Elder static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { 66cb7550b4SAlex Elder [IPA_ENDPOINT_AP_COMMAND_TX] = { 67cb7550b4SAlex Elder .ee_id = GSI_EE_AP, 68cb7550b4SAlex Elder .channel_id = 12, 69cb7550b4SAlex Elder .endpoint_id = 14, 70cb7550b4SAlex Elder .toward_ipa = true, 71cb7550b4SAlex Elder .channel = { 72cb7550b4SAlex Elder .tre_count = 256, 73cb7550b4SAlex Elder .event_count = 256, 74cb7550b4SAlex Elder .tlv_count = 20, 75cb7550b4SAlex Elder }, 76cb7550b4SAlex Elder .endpoint = { 77cb7550b4SAlex Elder .config = { 78cb7550b4SAlex Elder .resource_group = IPA_RSRC_GROUP_SRC_UL, 79cb7550b4SAlex Elder .dma_mode = true, 80cb7550b4SAlex Elder .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, 81cb7550b4SAlex Elder .tx = { 82cb7550b4SAlex Elder .seq_type = IPA_SEQ_DMA, 83cb7550b4SAlex Elder }, 84cb7550b4SAlex Elder }, 85cb7550b4SAlex Elder }, 86cb7550b4SAlex Elder }, 87cb7550b4SAlex Elder [IPA_ENDPOINT_AP_LAN_RX] = { 88cb7550b4SAlex Elder .ee_id = GSI_EE_AP, 89cb7550b4SAlex Elder .channel_id = 13, 90cb7550b4SAlex Elder .endpoint_id = 16, 91cb7550b4SAlex Elder .toward_ipa = false, 92cb7550b4SAlex Elder .channel = { 93cb7550b4SAlex Elder .tre_count = 256, 94cb7550b4SAlex Elder .event_count = 256, 95cb7550b4SAlex Elder .tlv_count = 9, 96cb7550b4SAlex Elder }, 97cb7550b4SAlex Elder .endpoint = { 98cb7550b4SAlex Elder .config = { 99cb7550b4SAlex Elder .resource_group = IPA_RSRC_GROUP_DST_UL, 100cb7550b4SAlex Elder .aggregation = true, 101cb7550b4SAlex Elder .status_enable = true, 102cb7550b4SAlex Elder .rx = { 103cb7550b4SAlex Elder .buffer_size = 8192, 104cb7550b4SAlex Elder .pad_align = ilog2(sizeof(u32)), 105cb7550b4SAlex Elder .aggr_time_limit = 500, 106cb7550b4SAlex Elder }, 107cb7550b4SAlex Elder }, 108cb7550b4SAlex Elder }, 109cb7550b4SAlex Elder }, 110cb7550b4SAlex Elder [IPA_ENDPOINT_AP_MODEM_TX] = { 111cb7550b4SAlex Elder .ee_id = GSI_EE_AP, 112cb7550b4SAlex Elder .channel_id = 11, 113cb7550b4SAlex Elder .endpoint_id = 2, 114cb7550b4SAlex Elder .toward_ipa = true, 115cb7550b4SAlex Elder .channel = { 116cb7550b4SAlex Elder .tre_count = 512, 117cb7550b4SAlex Elder .event_count = 512, 118cb7550b4SAlex Elder .tlv_count = 25, 119cb7550b4SAlex Elder }, 120cb7550b4SAlex Elder .endpoint = { 121cb7550b4SAlex Elder .filter_support = true, 122cb7550b4SAlex Elder .config = { 123cb7550b4SAlex Elder .resource_group = IPA_RSRC_GROUP_SRC_UL, 124cb7550b4SAlex Elder .checksum = true, 125cb7550b4SAlex Elder .qmap = true, 126cb7550b4SAlex Elder .status_enable = true, 127cb7550b4SAlex Elder .tx = { 128cb7550b4SAlex Elder .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, 129cb7550b4SAlex Elder .status_endpoint = 130cb7550b4SAlex Elder IPA_ENDPOINT_MODEM_AP_RX, 131cb7550b4SAlex Elder }, 132cb7550b4SAlex Elder }, 133cb7550b4SAlex Elder }, 134cb7550b4SAlex Elder }, 135cb7550b4SAlex Elder [IPA_ENDPOINT_AP_MODEM_RX] = { 136cb7550b4SAlex Elder .ee_id = GSI_EE_AP, 137cb7550b4SAlex Elder .channel_id = 1, 138cb7550b4SAlex Elder .endpoint_id = 23, 139cb7550b4SAlex Elder .toward_ipa = false, 140cb7550b4SAlex Elder .channel = { 141cb7550b4SAlex Elder .tre_count = 256, 142cb7550b4SAlex Elder .event_count = 256, 143cb7550b4SAlex Elder .tlv_count = 9, 144cb7550b4SAlex Elder }, 145cb7550b4SAlex Elder .endpoint = { 146cb7550b4SAlex Elder .config = { 147cb7550b4SAlex Elder .resource_group = IPA_RSRC_GROUP_DST_DL, 148cb7550b4SAlex Elder .checksum = true, 149cb7550b4SAlex Elder .qmap = true, 150cb7550b4SAlex Elder .aggregation = true, 151cb7550b4SAlex Elder .rx = { 152cb7550b4SAlex Elder .buffer_size = 8192, 153cb7550b4SAlex Elder .aggr_time_limit = 500, 154cb7550b4SAlex Elder .aggr_close_eof = true, 155cb7550b4SAlex Elder }, 156cb7550b4SAlex Elder }, 157cb7550b4SAlex Elder }, 158cb7550b4SAlex Elder }, 159cb7550b4SAlex Elder [IPA_ENDPOINT_MODEM_AP_TX] = { 160cb7550b4SAlex Elder .ee_id = GSI_EE_MODEM, 161cb7550b4SAlex Elder .channel_id = 0, 162cb7550b4SAlex Elder .endpoint_id = 12, 163cb7550b4SAlex Elder .toward_ipa = true, 164cb7550b4SAlex Elder .endpoint = { 165cb7550b4SAlex Elder .filter_support = true, 166cb7550b4SAlex Elder }, 167cb7550b4SAlex Elder }, 168cb7550b4SAlex Elder [IPA_ENDPOINT_MODEM_AP_RX] = { 169cb7550b4SAlex Elder .ee_id = GSI_EE_MODEM, 170cb7550b4SAlex Elder .channel_id = 7, 171cb7550b4SAlex Elder .endpoint_id = 21, 172cb7550b4SAlex Elder .toward_ipa = false, 173cb7550b4SAlex Elder }, 174cb7550b4SAlex Elder [IPA_ENDPOINT_MODEM_DL_NLO_TX] = { 175cb7550b4SAlex Elder .ee_id = GSI_EE_MODEM, 176cb7550b4SAlex Elder .channel_id = 2, 177cb7550b4SAlex Elder .endpoint_id = 15, 178cb7550b4SAlex Elder .toward_ipa = true, 179cb7550b4SAlex Elder .endpoint = { 180cb7550b4SAlex Elder .filter_support = true, 181cb7550b4SAlex Elder }, 182cb7550b4SAlex Elder }, 183cb7550b4SAlex Elder }; 184cb7550b4SAlex Elder 185cb7550b4SAlex Elder /* Source resource configuration data for an SoC having IPA v5.0 */ 186cb7550b4SAlex Elder static const struct ipa_resource ipa_resource_src[] = { 187cb7550b4SAlex Elder [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { 188cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL] = { 189cb7550b4SAlex Elder .min = 3, .max = 9, 190cb7550b4SAlex Elder }, 191cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_DL] = { 192cb7550b4SAlex Elder .min = 4, .max = 10, 193cb7550b4SAlex Elder }, 194cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_URLLC] = { 195cb7550b4SAlex Elder .min = 1, .max = 63, 196cb7550b4SAlex Elder }, 197cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = { 198cb7550b4SAlex Elder .min = 0, .max = 63, 199cb7550b4SAlex Elder }, 200cb7550b4SAlex Elder }, 201cb7550b4SAlex Elder [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { 202cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL] = { 203cb7550b4SAlex Elder .min = 9, .max = 9, 204cb7550b4SAlex Elder }, 205cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_DL] = { 206cb7550b4SAlex Elder .min = 12, .max = 12, 207cb7550b4SAlex Elder }, 208cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_URLLC] = { 209cb7550b4SAlex Elder .min = 10, .max = 10, 210cb7550b4SAlex Elder }, 211cb7550b4SAlex Elder }, 212cb7550b4SAlex Elder [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { 213cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL] = { 214cb7550b4SAlex Elder .min = 9, .max = 9, 215cb7550b4SAlex Elder }, 216cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_DL] = { 217cb7550b4SAlex Elder .min = 24, .max = 24, 218cb7550b4SAlex Elder }, 219cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_URLLC] = { 220cb7550b4SAlex Elder .min = 20, .max = 20, 221cb7550b4SAlex Elder }, 222cb7550b4SAlex Elder }, 223cb7550b4SAlex Elder [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { 224cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL] = { 225cb7550b4SAlex Elder .min = 0, .max = 63, 226cb7550b4SAlex Elder }, 227cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_DL] = { 228cb7550b4SAlex Elder .min = 0, .max = 63, 229cb7550b4SAlex Elder }, 230cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_URLLC] = { 231cb7550b4SAlex Elder .min = 1, .max = 63, 232cb7550b4SAlex Elder }, 233cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = { 234cb7550b4SAlex Elder .min = 0, .max = 63, 235cb7550b4SAlex Elder }, 236cb7550b4SAlex Elder }, 237cb7550b4SAlex Elder [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { 238cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL] = { 239cb7550b4SAlex Elder .min = 22, .max = 22, 240cb7550b4SAlex Elder }, 241cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_DL] = { 242cb7550b4SAlex Elder .min = 16, .max = 16, 243cb7550b4SAlex Elder }, 244cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_URLLC] = { 245cb7550b4SAlex Elder .min = 16, .max = 16, 246cb7550b4SAlex Elder }, 247cb7550b4SAlex Elder }, 248cb7550b4SAlex Elder }; 249cb7550b4SAlex Elder 250cb7550b4SAlex Elder /* Destination resource configuration data for an SoC having IPA v5.0 */ 251cb7550b4SAlex Elder static const struct ipa_resource ipa_resource_dst[] = { 252cb7550b4SAlex Elder [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { 253cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_DST_UL] = { 254cb7550b4SAlex Elder .min = 6, .max = 6, 255cb7550b4SAlex Elder }, 256cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_DST_DL] = { 257cb7550b4SAlex Elder .min = 5, .max = 5, 258cb7550b4SAlex Elder }, 259cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_DST_DRB_IP] = { 260cb7550b4SAlex Elder .min = 39, .max = 39, 261cb7550b4SAlex Elder }, 262cb7550b4SAlex Elder }, 263cb7550b4SAlex Elder [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { 264cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_DST_UL] = { 265cb7550b4SAlex Elder .min = 0, .max = 3, 266cb7550b4SAlex Elder }, 267cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_DST_DL] = { 268cb7550b4SAlex Elder .min = 0, .max = 3, 269cb7550b4SAlex Elder }, 270cb7550b4SAlex Elder }, 271cb7550b4SAlex Elder [IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS] = { 272cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_DST_UL] = { 273cb7550b4SAlex Elder .min = 0, .max = 63, 274cb7550b4SAlex Elder }, 275cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_DST_DL] = { 276cb7550b4SAlex Elder .min = 0, .max = 63, 277cb7550b4SAlex Elder }, 278cb7550b4SAlex Elder }, 279cb7550b4SAlex Elder }; 280cb7550b4SAlex Elder 281cb7550b4SAlex Elder /* Resource configuration data for an SoC having IPA v5.0 */ 282cb7550b4SAlex Elder static const struct ipa_resource_data ipa_resource_data = { 283cb7550b4SAlex Elder .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, 284cb7550b4SAlex Elder .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, 285cb7550b4SAlex Elder .resource_src_count = ARRAY_SIZE(ipa_resource_src), 286cb7550b4SAlex Elder .resource_src = ipa_resource_src, 287cb7550b4SAlex Elder .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), 288cb7550b4SAlex Elder .resource_dst = ipa_resource_dst, 289cb7550b4SAlex Elder }; 290cb7550b4SAlex Elder 291cb7550b4SAlex Elder /* IPA-resident memory region data for an SoC having IPA v5.0 */ 292cb7550b4SAlex Elder static const struct ipa_mem ipa_mem_local_data[] = { 293cb7550b4SAlex Elder { 294cb7550b4SAlex Elder .id = IPA_MEM_UC_EVENT_RING, 295cb7550b4SAlex Elder .offset = 0x0000, 296cb7550b4SAlex Elder .size = 0x1000, 297cb7550b4SAlex Elder .canary_count = 0, 298cb7550b4SAlex Elder }, 299cb7550b4SAlex Elder { 300cb7550b4SAlex Elder .id = IPA_MEM_UC_SHARED, 301cb7550b4SAlex Elder .offset = 0x1000, 302cb7550b4SAlex Elder .size = 0x0080, 303cb7550b4SAlex Elder .canary_count = 0, 304cb7550b4SAlex Elder }, 305cb7550b4SAlex Elder { 306cb7550b4SAlex Elder .id = IPA_MEM_UC_INFO, 307cb7550b4SAlex Elder .offset = 0x1080, 308cb7550b4SAlex Elder .size = 0x0200, 309cb7550b4SAlex Elder .canary_count = 0, 310cb7550b4SAlex Elder }, 311cb7550b4SAlex Elder { 312cb7550b4SAlex Elder .id = IPA_MEM_V4_FILTER_HASHED, 313cb7550b4SAlex Elder .offset = 0x1288, 314cb7550b4SAlex Elder .size = 0x0078, 315cb7550b4SAlex Elder .canary_count = 2, 316cb7550b4SAlex Elder }, 317cb7550b4SAlex Elder { 318cb7550b4SAlex Elder .id = IPA_MEM_V4_FILTER, 319cb7550b4SAlex Elder .offset = 0x1308, 320cb7550b4SAlex Elder .size = 0x0078, 321cb7550b4SAlex Elder .canary_count = 2, 322cb7550b4SAlex Elder }, 323cb7550b4SAlex Elder { 324cb7550b4SAlex Elder .id = IPA_MEM_V6_FILTER_HASHED, 325cb7550b4SAlex Elder .offset = 0x1388, 326cb7550b4SAlex Elder .size = 0x0078, 327cb7550b4SAlex Elder .canary_count = 2, 328cb7550b4SAlex Elder }, 329cb7550b4SAlex Elder { 330cb7550b4SAlex Elder .id = IPA_MEM_V6_FILTER, 331cb7550b4SAlex Elder .offset = 0x1408, 332cb7550b4SAlex Elder .size = 0x0078, 333cb7550b4SAlex Elder .canary_count = 2, 334cb7550b4SAlex Elder }, 335cb7550b4SAlex Elder { 336cb7550b4SAlex Elder .id = IPA_MEM_V4_ROUTE_HASHED, 337cb7550b4SAlex Elder .offset = 0x1488, 338cb7550b4SAlex Elder .size = 0x0098, 339cb7550b4SAlex Elder .canary_count = 2, 340cb7550b4SAlex Elder }, 341cb7550b4SAlex Elder { 342cb7550b4SAlex Elder .id = IPA_MEM_V4_ROUTE, 343cb7550b4SAlex Elder .offset = 0x1528, 344cb7550b4SAlex Elder .size = 0x0098, 345cb7550b4SAlex Elder .canary_count = 2, 346cb7550b4SAlex Elder }, 347cb7550b4SAlex Elder { 348cb7550b4SAlex Elder .id = IPA_MEM_V6_ROUTE_HASHED, 349cb7550b4SAlex Elder .offset = 0x15c8, 350cb7550b4SAlex Elder .size = 0x0098, 351cb7550b4SAlex Elder .canary_count = 2, 352cb7550b4SAlex Elder }, 353cb7550b4SAlex Elder { 354cb7550b4SAlex Elder .id = IPA_MEM_V6_ROUTE, 355cb7550b4SAlex Elder .offset = 0x1668, 356cb7550b4SAlex Elder .size = 0x0098, 357cb7550b4SAlex Elder .canary_count = 2, 358cb7550b4SAlex Elder }, 359cb7550b4SAlex Elder { 360cb7550b4SAlex Elder .id = IPA_MEM_MODEM_HEADER, 361cb7550b4SAlex Elder .offset = 0x1708, 362cb7550b4SAlex Elder .size = 0x0240, 363cb7550b4SAlex Elder .canary_count = 2, 364cb7550b4SAlex Elder }, 365cb7550b4SAlex Elder { 366cb7550b4SAlex Elder .id = IPA_MEM_AP_HEADER, 367cb7550b4SAlex Elder .offset = 0x1948, 368cb7550b4SAlex Elder .size = 0x01e0, 369cb7550b4SAlex Elder .canary_count = 0, 370cb7550b4SAlex Elder }, 371cb7550b4SAlex Elder { 372cb7550b4SAlex Elder .id = IPA_MEM_MODEM_PROC_CTX, 373cb7550b4SAlex Elder .offset = 0x1b40, 374cb7550b4SAlex Elder .size = 0x0b20, 375cb7550b4SAlex Elder .canary_count = 2, 376cb7550b4SAlex Elder }, 377cb7550b4SAlex Elder { 378cb7550b4SAlex Elder .id = IPA_MEM_AP_PROC_CTX, 379cb7550b4SAlex Elder .offset = 0x2660, 380cb7550b4SAlex Elder .size = 0x0200, 381cb7550b4SAlex Elder .canary_count = 0, 382cb7550b4SAlex Elder }, 383cb7550b4SAlex Elder { 384cb7550b4SAlex Elder .id = IPA_MEM_STATS_QUOTA_MODEM, 385cb7550b4SAlex Elder .offset = 0x2868, 386cb7550b4SAlex Elder .size = 0x0060, 387cb7550b4SAlex Elder .canary_count = 2, 388cb7550b4SAlex Elder }, 389cb7550b4SAlex Elder { 390cb7550b4SAlex Elder .id = IPA_MEM_STATS_QUOTA_AP, 391cb7550b4SAlex Elder .offset = 0x28c8, 392cb7550b4SAlex Elder .size = 0x0048, 393cb7550b4SAlex Elder .canary_count = 0, 394cb7550b4SAlex Elder }, 395cb7550b4SAlex Elder { 396cb7550b4SAlex Elder .id = IPA_MEM_AP_V4_FILTER, 397cb7550b4SAlex Elder .offset = 0x2918, 398cb7550b4SAlex Elder .size = 0x0118, 399cb7550b4SAlex Elder .canary_count = 2, 400cb7550b4SAlex Elder }, 401cb7550b4SAlex Elder { 402cb7550b4SAlex Elder .id = IPA_MEM_AP_V6_FILTER, 403cb7550b4SAlex Elder .offset = 0x2aa0, 404cb7550b4SAlex Elder .size = 0x0228, 405cb7550b4SAlex Elder .canary_count = 0, 406cb7550b4SAlex Elder }, 407cb7550b4SAlex Elder { 408cb7550b4SAlex Elder .id = IPA_MEM_STATS_FILTER_ROUTE, 409cb7550b4SAlex Elder .offset = 0x2cd0, 410cb7550b4SAlex Elder .size = 0x0ba0, 411cb7550b4SAlex Elder .canary_count = 2, 412cb7550b4SAlex Elder }, 413cb7550b4SAlex Elder { 414cb7550b4SAlex Elder .id = IPA_MEM_STATS_DROP, 415cb7550b4SAlex Elder .offset = 0x3870, 416cb7550b4SAlex Elder .size = 0x0020, 417cb7550b4SAlex Elder .canary_count = 0, 418cb7550b4SAlex Elder }, 419cb7550b4SAlex Elder { 420cb7550b4SAlex Elder .id = IPA_MEM_MODEM, 421cb7550b4SAlex Elder .offset = 0x3898, 422cb7550b4SAlex Elder .size = 0x0d48, 423cb7550b4SAlex Elder .canary_count = 2, 424cb7550b4SAlex Elder }, 425cb7550b4SAlex Elder { 426cb7550b4SAlex Elder .id = IPA_MEM_NAT_TABLE, 427cb7550b4SAlex Elder .offset = 0x45e0, 428cb7550b4SAlex Elder .size = 0x0900, 429cb7550b4SAlex Elder .canary_count = 0, 430cb7550b4SAlex Elder }, 431cb7550b4SAlex Elder { 432cb7550b4SAlex Elder .id = IPA_MEM_PDN_CONFIG, 433cb7550b4SAlex Elder .offset = 0x4ee8, 434cb7550b4SAlex Elder .size = 0x0100, 435cb7550b4SAlex Elder .canary_count = 2, 436cb7550b4SAlex Elder }, 437cb7550b4SAlex Elder }; 438cb7550b4SAlex Elder 439cb7550b4SAlex Elder /* Memory configuration data for an SoC having IPA v5.0 */ 440cb7550b4SAlex Elder static const struct ipa_mem_data ipa_mem_data = { 441cb7550b4SAlex Elder .local_count = ARRAY_SIZE(ipa_mem_local_data), 442cb7550b4SAlex Elder .local = ipa_mem_local_data, 443cb7550b4SAlex Elder .imem_addr = 0x14688000, 444cb7550b4SAlex Elder .imem_size = 0x00003000, 445cb7550b4SAlex Elder .smem_id = 497, 446cb7550b4SAlex Elder .smem_size = 0x00009000, 447cb7550b4SAlex Elder }; 448cb7550b4SAlex Elder 449cb7550b4SAlex Elder /* Interconnect rates are in 1000 byte/second units */ 450cb7550b4SAlex Elder static const struct ipa_interconnect_data ipa_interconnect_data[] = { 451cb7550b4SAlex Elder { 452cb7550b4SAlex Elder .name = "memory", 453cb7550b4SAlex Elder .peak_bandwidth = 1900000, /* 1.9 GBps */ 454cb7550b4SAlex Elder .average_bandwidth = 600000, /* 600 MBps */ 455cb7550b4SAlex Elder }, 456cb7550b4SAlex Elder /* Average rate is unused for the next interconnect */ 457cb7550b4SAlex Elder { 458cb7550b4SAlex Elder .name = "config", 459cb7550b4SAlex Elder .peak_bandwidth = 76800, /* 76.8 MBps */ 460cb7550b4SAlex Elder .average_bandwidth = 0, /* unused */ 461cb7550b4SAlex Elder }, 462cb7550b4SAlex Elder }; 463cb7550b4SAlex Elder 464cb7550b4SAlex Elder /* Clock and interconnect configuration data for an SoC having IPA v5.0 */ 465cb7550b4SAlex Elder static const struct ipa_power_data ipa_power_data = { 466cb7550b4SAlex Elder .core_clock_rate = 120 * 1000 * 1000, /* Hz */ 467cb7550b4SAlex Elder .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), 468cb7550b4SAlex Elder .interconnect_data = ipa_interconnect_data, 469cb7550b4SAlex Elder }; 470cb7550b4SAlex Elder 471cb7550b4SAlex Elder /* Configuration data for an SoC having IPA v5.0. */ 472cb7550b4SAlex Elder const struct ipa_data ipa_data_v5_0 = { 473cb7550b4SAlex Elder .version = IPA_VERSION_5_0, 474cb7550b4SAlex Elder .qsb_count = ARRAY_SIZE(ipa_qsb_data), 475cb7550b4SAlex Elder .qsb_data = ipa_qsb_data, 476cb7550b4SAlex Elder .modem_route_count = 11, 477cb7550b4SAlex Elder .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), 478cb7550b4SAlex Elder .endpoint_data = ipa_gsi_endpoint_data, 479cb7550b4SAlex Elder .resource_data = &ipa_resource_data, 480cb7550b4SAlex Elder .mem_data = &ipa_mem_data, 481cb7550b4SAlex Elder .power_data = &ipa_power_data, 482cb7550b4SAlex Elder }; 483