1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2020, Intel Corporation 3 */ 4 5 #include <linux/clk-provider.h> 6 #include <linux/pci.h> 7 #include <linux/dmi.h> 8 #include <linux/platform_data/x86/intel_pmc_ipc.h> 9 #include "dwmac-intel.h" 10 #include "dwmac4.h" 11 #include "stmmac.h" 12 #include "stmmac_ptp.h" 13 14 struct pmc_serdes_regs { 15 u8 index; 16 u32 val; 17 }; 18 19 struct pmc_serdes_reg_info { 20 const struct pmc_serdes_regs *regs; 21 u8 num_regs; 22 }; 23 24 struct intel_priv_data { 25 int mdio_adhoc_addr; /* mdio address for serdes & etc */ 26 unsigned long crossts_adj; 27 bool is_pse; 28 const int *tsn_lane_regs; 29 int max_tsn_lane_regs; 30 struct pmc_serdes_reg_info pid_1g; 31 struct pmc_serdes_reg_info pid_2p5g; 32 }; 33 34 /* This struct is used to associate PCI Function of MAC controller on a board, 35 * discovered via DMI, with the address of PHY connected to the MAC. The 36 * negative value of the address means that MAC controller is not connected 37 * with PHY. 38 */ 39 struct stmmac_pci_func_data { 40 unsigned int func; 41 int phy_addr; 42 }; 43 44 struct stmmac_pci_dmi_data { 45 const struct stmmac_pci_func_data *func; 46 size_t nfuncs; 47 }; 48 49 struct stmmac_pci_info { 50 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat); 51 }; 52 53 static const struct pmc_serdes_regs pid_modphy3_1g_regs[] = { 54 { PID_MODPHY3_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_1G }, 55 { PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_1G }, 56 { PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_1G }, 57 { PID_MODPHY3_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_1G }, 58 { PID_MODPHY3_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_1G }, 59 {} 60 }; 61 62 static const struct pmc_serdes_regs pid_modphy3_2p5g_regs[] = { 63 { PID_MODPHY3_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_2P5G }, 64 { PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_2P5G }, 65 { PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_2P5G }, 66 { PID_MODPHY3_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_2P5G }, 67 { PID_MODPHY3_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_2P5G }, 68 {} 69 }; 70 71 static const struct pmc_serdes_regs pid_modphy1_1g_regs[] = { 72 { PID_MODPHY1_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_1G }, 73 { PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_1G }, 74 { PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_1G }, 75 { PID_MODPHY1_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_1G }, 76 { PID_MODPHY1_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_1G }, 77 {} 78 }; 79 80 static const struct pmc_serdes_regs pid_modphy1_2p5g_regs[] = { 81 { PID_MODPHY1_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_2P5G }, 82 { PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_2P5G }, 83 { PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_2P5G }, 84 { PID_MODPHY1_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_2P5G }, 85 { PID_MODPHY1_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_2P5G }, 86 {} 87 }; 88 89 static const int ehl_tsn_lane_regs[] = {7, 8, 9, 10, 11}; 90 static const int adln_tsn_lane_regs[] = {6}; 91 92 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev, 93 const struct dmi_system_id *dmi_list) 94 { 95 const struct stmmac_pci_func_data *func_data; 96 const struct stmmac_pci_dmi_data *dmi_data; 97 const struct dmi_system_id *dmi_id; 98 int func = PCI_FUNC(pdev->devfn); 99 size_t n; 100 101 dmi_id = dmi_first_match(dmi_list); 102 if (!dmi_id) 103 return -ENODEV; 104 105 dmi_data = dmi_id->driver_data; 106 func_data = dmi_data->func; 107 108 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) 109 if (func_data->func == func) 110 return func_data->phy_addr; 111 112 return -ENODEV; 113 } 114 115 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr, 116 int phyreg, u32 mask, u32 val) 117 { 118 unsigned int retries = 10; 119 int val_rd; 120 121 do { 122 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg); 123 if ((val_rd & mask) == (val & mask)) 124 return 0; 125 udelay(POLL_DELAY_US); 126 } while (--retries); 127 128 return -ETIMEDOUT; 129 } 130 131 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data) 132 { 133 struct intel_priv_data *intel_priv = priv_data; 134 struct stmmac_priv *priv = netdev_priv(ndev); 135 int serdes_phy_addr = 0; 136 u32 data = 0; 137 138 if (!intel_priv->mdio_adhoc_addr) 139 return 0; 140 141 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 142 143 /* Set the serdes rate and the PCLK rate */ 144 data = mdiobus_read(priv->mii, serdes_phy_addr, 145 SERDES_GCR0); 146 147 data &= ~SERDES_RATE_MASK; 148 data &= ~SERDES_PCLK_MASK; 149 150 if (priv->plat->phy_interface == PHY_INTERFACE_MODE_2500BASEX) 151 data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT | 152 SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT; 153 else 154 data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT | 155 SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT; 156 157 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 158 159 /* assert clk_req */ 160 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 161 data |= SERDES_PLL_CLK; 162 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 163 164 /* check for clk_ack assertion */ 165 data = serdes_status_poll(priv, serdes_phy_addr, 166 SERDES_GSR0, 167 SERDES_PLL_CLK, 168 SERDES_PLL_CLK); 169 170 if (data) { 171 dev_err(priv->device, "Serdes PLL clk request timeout\n"); 172 return data; 173 } 174 175 /* assert lane reset */ 176 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 177 data |= SERDES_RST; 178 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 179 180 /* check for assert lane reset reflection */ 181 data = serdes_status_poll(priv, serdes_phy_addr, 182 SERDES_GSR0, 183 SERDES_RST, 184 SERDES_RST); 185 186 if (data) { 187 dev_err(priv->device, "Serdes assert lane reset timeout\n"); 188 return data; 189 } 190 191 /* move power state to P0 */ 192 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 193 194 data &= ~SERDES_PWR_ST_MASK; 195 data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT; 196 197 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 198 199 /* Check for P0 state */ 200 data = serdes_status_poll(priv, serdes_phy_addr, 201 SERDES_GSR0, 202 SERDES_PWR_ST_MASK, 203 SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT); 204 205 if (data) { 206 dev_err(priv->device, "Serdes power state P0 timeout.\n"); 207 return data; 208 } 209 210 /* PSE only - ungate SGMII PHY Rx Clock */ 211 if (intel_priv->is_pse) 212 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0, 213 0, SERDES_PHY_RX_CLK); 214 215 return 0; 216 } 217 218 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data) 219 { 220 struct intel_priv_data *intel_priv = intel_data; 221 struct stmmac_priv *priv = netdev_priv(ndev); 222 int serdes_phy_addr = 0; 223 u32 data = 0; 224 225 if (!intel_priv->mdio_adhoc_addr) 226 return; 227 228 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 229 230 /* PSE only - gate SGMII PHY Rx Clock */ 231 if (intel_priv->is_pse) 232 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0, 233 SERDES_PHY_RX_CLK, 0); 234 235 /* move power state to P3 */ 236 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 237 238 data &= ~SERDES_PWR_ST_MASK; 239 data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT; 240 241 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 242 243 /* Check for P3 state */ 244 data = serdes_status_poll(priv, serdes_phy_addr, 245 SERDES_GSR0, 246 SERDES_PWR_ST_MASK, 247 SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT); 248 249 if (data) { 250 dev_err(priv->device, "Serdes power state P3 timeout\n"); 251 return; 252 } 253 254 /* de-assert clk_req */ 255 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 256 data &= ~SERDES_PLL_CLK; 257 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 258 259 /* check for clk_ack de-assert */ 260 data = serdes_status_poll(priv, serdes_phy_addr, 261 SERDES_GSR0, 262 SERDES_PLL_CLK, 263 (u32)~SERDES_PLL_CLK); 264 265 if (data) { 266 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n"); 267 return; 268 } 269 270 /* de-assert lane reset */ 271 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 272 data &= ~SERDES_RST; 273 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 274 275 /* check for de-assert lane reset reflection */ 276 data = serdes_status_poll(priv, serdes_phy_addr, 277 SERDES_GSR0, 278 SERDES_RST, 279 (u32)~SERDES_RST); 280 281 if (data) { 282 dev_err(priv->device, "Serdes de-assert lane reset timeout\n"); 283 return; 284 } 285 } 286 287 static void tgl_get_interfaces(struct stmmac_priv *priv, void *bsp_priv, 288 unsigned long *interfaces) 289 { 290 struct intel_priv_data *intel_priv = bsp_priv; 291 phy_interface_t interface; 292 int data; 293 294 /* Determine the link speed mode: 2.5Gbps/1Gbps */ 295 data = mdiobus_read(priv->mii, intel_priv->mdio_adhoc_addr, SERDES_GCR); 296 if (data < 0) 297 return; 298 299 if (FIELD_GET(SERDES_LINK_MODE_MASK, data) == SERDES_LINK_MODE_2G5) { 300 dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n"); 301 priv->plat->mdio_bus_data->default_an_inband = false; 302 interface = PHY_INTERFACE_MODE_2500BASEX; 303 } else { 304 interface = PHY_INTERFACE_MODE_SGMII; 305 } 306 307 __set_bit(interface, interfaces); 308 priv->plat->phy_interface = interface; 309 } 310 311 /* Program PTP Clock Frequency for different variant of 312 * Intel mGBE that has slightly different GPO mapping 313 */ 314 static void intel_mgbe_ptp_clk_freq_config(struct stmmac_priv *priv) 315 { 316 struct intel_priv_data *intel_priv; 317 u32 gpio_value; 318 319 intel_priv = (struct intel_priv_data *)priv->plat->bsp_priv; 320 321 gpio_value = readl(priv->ioaddr + GMAC_GPIO_STATUS); 322 323 if (intel_priv->is_pse) { 324 /* For PSE GbE, use 200MHz */ 325 gpio_value &= ~PSE_PTP_CLK_FREQ_MASK; 326 gpio_value |= PSE_PTP_CLK_FREQ_200MHZ; 327 } else { 328 /* For PCH GbE, use 200MHz */ 329 gpio_value &= ~PCH_PTP_CLK_FREQ_MASK; 330 gpio_value |= PCH_PTP_CLK_FREQ_200MHZ; 331 } 332 333 writel(gpio_value, priv->ioaddr + GMAC_GPIO_STATUS); 334 } 335 336 static void get_arttime(struct mii_bus *mii, int intel_adhoc_addr, 337 u64 *art_time) 338 { 339 u64 ns; 340 341 ns = mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE3); 342 ns <<= GMAC4_ART_TIME_SHIFT; 343 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE2); 344 ns <<= GMAC4_ART_TIME_SHIFT; 345 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE1); 346 ns <<= GMAC4_ART_TIME_SHIFT; 347 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE0); 348 349 *art_time = ns; 350 } 351 352 static int stmmac_cross_ts_isr(struct stmmac_priv *priv) 353 { 354 return (readl(priv->ioaddr + GMAC_INT_STATUS) & GMAC_INT_TSIE); 355 } 356 357 static int intel_crosststamp(ktime_t *device, 358 struct system_counterval_t *system, 359 void *ctx) 360 { 361 struct intel_priv_data *intel_priv; 362 363 struct stmmac_priv *priv = (struct stmmac_priv *)ctx; 364 void __iomem *ptpaddr = priv->ptpaddr; 365 void __iomem *ioaddr = priv->hw->pcsr; 366 unsigned long flags; 367 u64 art_time = 0; 368 u64 ptp_time = 0; 369 u32 num_snapshot; 370 u32 gpio_value; 371 u32 acr_value; 372 int i; 373 374 intel_priv = priv->plat->bsp_priv; 375 376 /* Both internal crosstimestamping and external triggered event 377 * timestamping cannot be run concurrently. 378 */ 379 if (priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN) 380 return -EBUSY; 381 382 priv->plat->flags |= STMMAC_FLAG_INT_SNAPSHOT_EN; 383 384 mutex_lock(&priv->aux_ts_lock); 385 /* Enable Internal snapshot trigger */ 386 acr_value = readl(ptpaddr + PTP_ACR); 387 acr_value &= ~PTP_ACR_MASK; 388 switch (priv->plat->int_snapshot_num) { 389 case AUX_SNAPSHOT0: 390 acr_value |= PTP_ACR_ATSEN0; 391 break; 392 case AUX_SNAPSHOT1: 393 acr_value |= PTP_ACR_ATSEN1; 394 break; 395 case AUX_SNAPSHOT2: 396 acr_value |= PTP_ACR_ATSEN2; 397 break; 398 case AUX_SNAPSHOT3: 399 acr_value |= PTP_ACR_ATSEN3; 400 break; 401 default: 402 mutex_unlock(&priv->aux_ts_lock); 403 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; 404 return -EINVAL; 405 } 406 writel(acr_value, ptpaddr + PTP_ACR); 407 408 /* Clear FIFO */ 409 acr_value = readl(ptpaddr + PTP_ACR); 410 acr_value |= PTP_ACR_ATSFC; 411 writel(acr_value, ptpaddr + PTP_ACR); 412 /* Release the mutex */ 413 mutex_unlock(&priv->aux_ts_lock); 414 415 /* Trigger Internal snapshot signal 416 * Create a rising edge by just toggle the GPO1 to low 417 * and back to high. 418 */ 419 gpio_value = readl(ioaddr + GMAC_GPIO_STATUS); 420 gpio_value &= ~GMAC_GPO1; 421 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS); 422 gpio_value |= GMAC_GPO1; 423 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS); 424 425 /* Time sync done Indication - Interrupt method */ 426 if (!wait_event_interruptible_timeout(priv->tstamp_busy_wait, 427 stmmac_cross_ts_isr(priv), 428 HZ / 100)) { 429 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; 430 return -ETIMEDOUT; 431 } 432 433 *system = (struct system_counterval_t) { 434 .cycles = 0, 435 .cs_id = CSID_X86_ART, 436 .use_nsecs = false, 437 }; 438 439 num_snapshot = (readl(ioaddr + GMAC_TIMESTAMP_STATUS) & 440 GMAC_TIMESTAMP_ATSNS_MASK) >> 441 GMAC_TIMESTAMP_ATSNS_SHIFT; 442 443 /* Repeat until the timestamps are from the FIFO last segment */ 444 for (i = 0; i < num_snapshot; i++) { 445 read_lock_irqsave(&priv->ptp_lock, flags); 446 stmmac_get_ptptime(priv, ptpaddr, &ptp_time); 447 *device = ns_to_ktime(ptp_time); 448 read_unlock_irqrestore(&priv->ptp_lock, flags); 449 get_arttime(priv->mii, intel_priv->mdio_adhoc_addr, &art_time); 450 system->cycles = art_time; 451 } 452 453 system->cycles *= intel_priv->crossts_adj; 454 455 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; 456 457 return 0; 458 } 459 460 static void intel_mgbe_pse_crossts_adj(struct intel_priv_data *intel_priv, 461 int base) 462 { 463 if (boot_cpu_has(X86_FEATURE_ART)) { 464 unsigned int art_freq; 465 466 /* On systems that support ART, ART frequency can be obtained 467 * from ECX register of CPUID leaf (0x15). 468 */ 469 art_freq = cpuid_ecx(ART_CPUID_LEAF); 470 do_div(art_freq, base); 471 intel_priv->crossts_adj = art_freq; 472 } 473 } 474 475 static int intel_tsn_lane_is_available(struct net_device *ndev, 476 struct intel_priv_data *intel_priv) 477 { 478 struct stmmac_priv *priv = netdev_priv(ndev); 479 struct pmc_ipc_cmd tmp = {}; 480 struct pmc_ipc_rbuf rbuf = {}; 481 int ret = 0, i, j; 482 const int max_fia_regs = 5; 483 484 tmp.cmd = IPC_SOC_REGISTER_ACCESS; 485 tmp.sub_cmd = IPC_SOC_SUB_CMD_READ; 486 487 for (i = 0; i < max_fia_regs; i++) { 488 tmp.wbuf[0] = R_PCH_FIA_15_PCR_LOS1_REG_BASE + i; 489 490 ret = intel_pmc_ipc(&tmp, &rbuf); 491 if (ret < 0) { 492 netdev_info(priv->dev, "Failed to read from PMC.\n"); 493 return ret; 494 } 495 496 for (j = 0; j <= intel_priv->max_tsn_lane_regs; j++) 497 if ((rbuf.buf[0] >> 498 (4 * (intel_priv->tsn_lane_regs[j] % 8)) & 499 B_PCH_FIA_PCR_L0O) == 0xB) 500 return 0; 501 } 502 503 return -EINVAL; 504 } 505 506 static int intel_set_reg_access(const struct pmc_serdes_regs *regs, int max_regs) 507 { 508 int ret = 0, i; 509 510 for (i = 0; i < max_regs; i++) { 511 struct pmc_ipc_cmd tmp = {}; 512 struct pmc_ipc_rbuf rbuf = {}; 513 514 tmp.cmd = IPC_SOC_REGISTER_ACCESS; 515 tmp.sub_cmd = IPC_SOC_SUB_CMD_WRITE; 516 tmp.wbuf[0] = (u32)regs[i].index; 517 tmp.wbuf[1] = regs[i].val; 518 519 ret = intel_pmc_ipc(&tmp, &rbuf); 520 if (ret < 0) 521 return ret; 522 } 523 524 return ret; 525 } 526 527 static int intel_mac_finish(struct net_device *ndev, 528 void *intel_data, 529 unsigned int mode, 530 phy_interface_t interface) 531 { 532 struct intel_priv_data *intel_priv = intel_data; 533 struct stmmac_priv *priv = netdev_priv(ndev); 534 const struct pmc_serdes_regs *regs; 535 int max_regs = 0; 536 int ret = 0; 537 538 ret = intel_tsn_lane_is_available(ndev, intel_priv); 539 if (ret < 0) { 540 netdev_info(priv->dev, "No TSN lane available to set the registers.\n"); 541 return ret; 542 } 543 544 if (interface == PHY_INTERFACE_MODE_2500BASEX) { 545 regs = intel_priv->pid_2p5g.regs; 546 max_regs = intel_priv->pid_2p5g.num_regs; 547 } else { 548 regs = intel_priv->pid_1g.regs; 549 max_regs = intel_priv->pid_1g.num_regs; 550 } 551 552 ret = intel_set_reg_access(regs, max_regs); 553 if (ret < 0) 554 return ret; 555 556 priv->plat->phy_interface = interface; 557 558 intel_serdes_powerdown(ndev, intel_priv); 559 intel_serdes_powerup(ndev, intel_priv); 560 561 return ret; 562 } 563 564 static void common_default_data(struct plat_stmmacenet_data *plat) 565 { 566 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ 567 plat->has_gmac = 1; 568 plat->force_sf_dma_mode = 1; 569 570 plat->mdio_bus_data->needs_reset = true; 571 572 /* Set default value for multicast hash bins */ 573 plat->multicast_filter_bins = HASH_TABLE_SIZE; 574 575 /* Set default value for unicast filter entries */ 576 plat->unicast_filter_entries = 1; 577 578 /* Set the maxmtu to a default of JUMBO_LEN */ 579 plat->maxmtu = JUMBO_LEN; 580 581 /* Set default number of RX and TX queues to use */ 582 plat->tx_queues_to_use = 1; 583 plat->rx_queues_to_use = 1; 584 585 /* Disable Priority config by default */ 586 plat->tx_queues_cfg[0].use_prio = false; 587 plat->rx_queues_cfg[0].use_prio = false; 588 589 /* Disable RX queues routing by default */ 590 plat->rx_queues_cfg[0].pkt_route = 0x0; 591 } 592 593 static struct phylink_pcs *intel_mgbe_select_pcs(struct stmmac_priv *priv, 594 phy_interface_t interface) 595 { 596 /* plat->mdio_bus_data->has_xpcs has been set true, so there 597 * should always be an XPCS. The original code would always 598 * return this if present. 599 */ 600 return xpcs_to_phylink_pcs(priv->hw->xpcs); 601 } 602 603 static int intel_mgbe_common_data(struct pci_dev *pdev, 604 struct plat_stmmacenet_data *plat) 605 { 606 struct fwnode_handle *fwnode; 607 char clk_name[20]; 608 int ret; 609 int i; 610 611 plat->pdev = pdev; 612 plat->phy_addr = -1; 613 plat->clk_csr = 5; 614 plat->has_gmac = 0; 615 plat->has_gmac4 = 1; 616 plat->force_sf_dma_mode = 0; 617 plat->flags |= (STMMAC_FLAG_TSO_EN | STMMAC_FLAG_SPH_DISABLE); 618 619 /* Multiplying factor to the clk_eee_i clock time 620 * period to make it closer to 100 ns. This value 621 * should be programmed such that the clk_eee_time_period * 622 * (MULT_FACT_100NS + 1) should be within 80 ns to 120 ns 623 * clk_eee frequency is 19.2Mhz 624 * clk_eee_time_period is 52ns 625 * 52ns * (1 + 1) = 104ns 626 * MULT_FACT_100NS = 1 627 */ 628 plat->mult_fact_100ns = 1; 629 630 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; 631 632 for (i = 0; i < plat->rx_queues_to_use; i++) { 633 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 634 plat->rx_queues_cfg[i].chan = i; 635 636 /* Disable Priority config by default */ 637 plat->rx_queues_cfg[i].use_prio = false; 638 639 /* Disable RX queues routing by default */ 640 plat->rx_queues_cfg[i].pkt_route = 0x0; 641 } 642 643 for (i = 0; i < plat->tx_queues_to_use; i++) { 644 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 645 646 /* Disable Priority config by default */ 647 plat->tx_queues_cfg[i].use_prio = false; 648 /* Default TX Q0 to use TSO and rest TXQ for TBS */ 649 if (i > 0) 650 plat->tx_queues_cfg[i].tbs_en = 1; 651 } 652 653 /* FIFO size is 4096 bytes for 1 tx/rx queue */ 654 plat->tx_fifo_size = plat->tx_queues_to_use * 4096; 655 plat->rx_fifo_size = plat->rx_queues_to_use * 4096; 656 657 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; 658 plat->tx_queues_cfg[0].weight = 0x09; 659 plat->tx_queues_cfg[1].weight = 0x0A; 660 plat->tx_queues_cfg[2].weight = 0x0B; 661 plat->tx_queues_cfg[3].weight = 0x0C; 662 plat->tx_queues_cfg[4].weight = 0x0D; 663 plat->tx_queues_cfg[5].weight = 0x0E; 664 plat->tx_queues_cfg[6].weight = 0x0F; 665 plat->tx_queues_cfg[7].weight = 0x10; 666 667 plat->dma_cfg->pbl = 32; 668 plat->dma_cfg->pblx8 = true; 669 plat->dma_cfg->fixed_burst = 0; 670 plat->dma_cfg->mixed_burst = 0; 671 plat->dma_cfg->aal = 0; 672 plat->dma_cfg->dche = true; 673 674 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), 675 GFP_KERNEL); 676 if (!plat->axi) 677 return -ENOMEM; 678 679 plat->axi->axi_lpi_en = 0; 680 plat->axi->axi_xit_frm = 0; 681 plat->axi->axi_wr_osr_lmt = 1; 682 plat->axi->axi_rd_osr_lmt = 1; 683 plat->axi->axi_blen[0] = 4; 684 plat->axi->axi_blen[1] = 8; 685 plat->axi->axi_blen[2] = 16; 686 687 plat->ptp_max_adj = plat->clk_ptp_rate; 688 689 /* Set system clock */ 690 sprintf(clk_name, "%s-%s", "stmmac", pci_name(pdev)); 691 692 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, 693 clk_name, NULL, 0, 694 plat->clk_ptp_rate); 695 696 if (IS_ERR(plat->stmmac_clk)) { 697 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n"); 698 plat->stmmac_clk = NULL; 699 } 700 701 ret = clk_prepare_enable(plat->stmmac_clk); 702 if (ret) { 703 clk_unregister_fixed_rate(plat->stmmac_clk); 704 return ret; 705 } 706 707 plat->ptp_clk_freq_config = intel_mgbe_ptp_clk_freq_config; 708 709 /* Set default value for multicast hash bins */ 710 plat->multicast_filter_bins = HASH_TABLE_SIZE; 711 712 /* Set default value for unicast filter entries */ 713 plat->unicast_filter_entries = 1; 714 715 /* Set the maxmtu to a default of JUMBO_LEN */ 716 plat->maxmtu = JUMBO_LEN; 717 718 plat->flags |= STMMAC_FLAG_VLAN_FAIL_Q_EN; 719 720 /* Use the last Rx queue */ 721 plat->vlan_fail_q = plat->rx_queues_to_use - 1; 722 723 /* For fixed-link setup, we allow phy-mode setting */ 724 fwnode = dev_fwnode(&pdev->dev); 725 if (fwnode) { 726 int phy_mode; 727 728 /* "phy-mode" setting is optional. If it is set, 729 * we allow either sgmii or 1000base-x for now. 730 */ 731 phy_mode = fwnode_get_phy_mode(fwnode); 732 if (phy_mode >= 0) { 733 if (phy_mode == PHY_INTERFACE_MODE_SGMII || 734 phy_mode == PHY_INTERFACE_MODE_1000BASEX) 735 plat->phy_interface = phy_mode; 736 else 737 dev_warn(&pdev->dev, "Invalid phy-mode\n"); 738 } 739 } 740 741 /* Intel mgbe SGMII interface uses pcs-xcps */ 742 if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII || 743 plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { 744 plat->mdio_bus_data->pcs_mask = BIT(INTEL_MGBE_XPCS_ADDR); 745 plat->mdio_bus_data->default_an_inband = true; 746 plat->select_pcs = intel_mgbe_select_pcs; 747 } 748 749 /* Ensure mdio bus scan skips intel serdes and pcs-xpcs */ 750 plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR; 751 plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR; 752 753 plat->int_snapshot_num = AUX_SNAPSHOT1; 754 755 if (boot_cpu_has(X86_FEATURE_ART)) 756 plat->crosststamp = intel_crosststamp; 757 758 plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; 759 760 /* Setup MSI vector offset specific to Intel mGbE controller */ 761 plat->msi_mac_vec = 29; 762 plat->msi_lpi_vec = 28; 763 plat->msi_sfty_ce_vec = 27; 764 plat->msi_sfty_ue_vec = 26; 765 plat->msi_rx_base_vec = 0; 766 plat->msi_tx_base_vec = 1; 767 768 return 0; 769 } 770 771 static int ehl_common_data(struct pci_dev *pdev, 772 struct plat_stmmacenet_data *plat) 773 { 774 struct intel_priv_data *intel_priv = plat->bsp_priv; 775 776 plat->rx_queues_to_use = 8; 777 plat->tx_queues_to_use = 8; 778 plat->flags |= STMMAC_FLAG_USE_PHY_WOL; 779 plat->flags |= STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY; 780 781 plat->safety_feat_cfg->tsoee = 1; 782 plat->safety_feat_cfg->mrxpee = 1; 783 plat->safety_feat_cfg->mestee = 1; 784 plat->safety_feat_cfg->mrxee = 1; 785 plat->safety_feat_cfg->mtxee = 1; 786 plat->safety_feat_cfg->epsi = 0; 787 plat->safety_feat_cfg->edpp = 0; 788 plat->safety_feat_cfg->prtyen = 0; 789 plat->safety_feat_cfg->tmouten = 0; 790 791 intel_priv->tsn_lane_regs = ehl_tsn_lane_regs; 792 intel_priv->max_tsn_lane_regs = ARRAY_SIZE(ehl_tsn_lane_regs); 793 794 return intel_mgbe_common_data(pdev, plat); 795 } 796 797 static int ehl_sgmii_data(struct pci_dev *pdev, 798 struct plat_stmmacenet_data *plat) 799 { 800 struct intel_priv_data *intel_priv = plat->bsp_priv; 801 802 plat->bus_id = 1; 803 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 804 plat->serdes_powerup = intel_serdes_powerup; 805 plat->serdes_powerdown = intel_serdes_powerdown; 806 plat->mac_finish = intel_mac_finish; 807 plat->clk_ptp_rate = 204800000; 808 809 intel_priv->pid_1g.regs = pid_modphy3_1g_regs; 810 intel_priv->pid_1g.num_regs = ARRAY_SIZE(pid_modphy3_1g_regs); 811 intel_priv->pid_2p5g.regs = pid_modphy3_2p5g_regs; 812 intel_priv->pid_2p5g.num_regs = ARRAY_SIZE(pid_modphy3_2p5g_regs); 813 814 return ehl_common_data(pdev, plat); 815 } 816 817 static struct stmmac_pci_info ehl_sgmii1g_info = { 818 .setup = ehl_sgmii_data, 819 }; 820 821 static int ehl_rgmii_data(struct pci_dev *pdev, 822 struct plat_stmmacenet_data *plat) 823 { 824 plat->bus_id = 1; 825 plat->phy_interface = PHY_INTERFACE_MODE_RGMII; 826 827 plat->clk_ptp_rate = 204800000; 828 829 return ehl_common_data(pdev, plat); 830 } 831 832 static struct stmmac_pci_info ehl_rgmii1g_info = { 833 .setup = ehl_rgmii_data, 834 }; 835 836 static int ehl_pse0_common_data(struct pci_dev *pdev, 837 struct plat_stmmacenet_data *plat) 838 { 839 struct intel_priv_data *intel_priv = plat->bsp_priv; 840 841 intel_priv->is_pse = true; 842 plat->bus_id = 2; 843 plat->host_dma_width = 32; 844 845 plat->clk_ptp_rate = 200000000; 846 847 intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ); 848 849 return ehl_common_data(pdev, plat); 850 } 851 852 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev, 853 struct plat_stmmacenet_data *plat) 854 { 855 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 856 return ehl_pse0_common_data(pdev, plat); 857 } 858 859 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = { 860 .setup = ehl_pse0_rgmii1g_data, 861 }; 862 863 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev, 864 struct plat_stmmacenet_data *plat) 865 { 866 struct intel_priv_data *intel_priv = plat->bsp_priv; 867 868 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 869 plat->serdes_powerup = intel_serdes_powerup; 870 plat->serdes_powerdown = intel_serdes_powerdown; 871 plat->mac_finish = intel_mac_finish; 872 873 intel_priv->pid_1g.regs = pid_modphy1_1g_regs; 874 intel_priv->pid_1g.num_regs = ARRAY_SIZE(pid_modphy1_1g_regs); 875 intel_priv->pid_2p5g.regs = pid_modphy1_2p5g_regs; 876 intel_priv->pid_2p5g.num_regs = ARRAY_SIZE(pid_modphy1_2p5g_regs); 877 878 return ehl_pse0_common_data(pdev, plat); 879 } 880 881 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = { 882 .setup = ehl_pse0_sgmii1g_data, 883 }; 884 885 static int ehl_pse1_common_data(struct pci_dev *pdev, 886 struct plat_stmmacenet_data *plat) 887 { 888 struct intel_priv_data *intel_priv = plat->bsp_priv; 889 890 intel_priv->is_pse = true; 891 plat->bus_id = 3; 892 plat->host_dma_width = 32; 893 894 plat->clk_ptp_rate = 200000000; 895 896 intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ); 897 898 return ehl_common_data(pdev, plat); 899 } 900 901 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev, 902 struct plat_stmmacenet_data *plat) 903 { 904 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 905 return ehl_pse1_common_data(pdev, plat); 906 } 907 908 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = { 909 .setup = ehl_pse1_rgmii1g_data, 910 }; 911 912 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev, 913 struct plat_stmmacenet_data *plat) 914 { 915 struct intel_priv_data *intel_priv = plat->bsp_priv; 916 917 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 918 plat->serdes_powerup = intel_serdes_powerup; 919 plat->serdes_powerdown = intel_serdes_powerdown; 920 plat->mac_finish = intel_mac_finish; 921 922 intel_priv->pid_1g.regs = pid_modphy1_1g_regs; 923 intel_priv->pid_1g.num_regs = ARRAY_SIZE(pid_modphy1_1g_regs); 924 intel_priv->pid_2p5g.regs = pid_modphy1_2p5g_regs; 925 intel_priv->pid_2p5g.num_regs = ARRAY_SIZE(pid_modphy1_2p5g_regs); 926 927 return ehl_pse1_common_data(pdev, plat); 928 } 929 930 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = { 931 .setup = ehl_pse1_sgmii1g_data, 932 }; 933 934 static int tgl_common_data(struct pci_dev *pdev, 935 struct plat_stmmacenet_data *plat) 936 { 937 plat->rx_queues_to_use = 6; 938 plat->tx_queues_to_use = 4; 939 plat->clk_ptp_rate = 204800000; 940 plat->get_interfaces = tgl_get_interfaces; 941 942 plat->safety_feat_cfg->tsoee = 1; 943 plat->safety_feat_cfg->mrxpee = 0; 944 plat->safety_feat_cfg->mestee = 1; 945 plat->safety_feat_cfg->mrxee = 1; 946 plat->safety_feat_cfg->mtxee = 1; 947 plat->safety_feat_cfg->epsi = 0; 948 plat->safety_feat_cfg->edpp = 0; 949 plat->safety_feat_cfg->prtyen = 0; 950 plat->safety_feat_cfg->tmouten = 0; 951 952 return intel_mgbe_common_data(pdev, plat); 953 } 954 955 static int tgl_sgmii_phy0_data(struct pci_dev *pdev, 956 struct plat_stmmacenet_data *plat) 957 { 958 plat->bus_id = 1; 959 plat->serdes_powerup = intel_serdes_powerup; 960 plat->serdes_powerdown = intel_serdes_powerdown; 961 return tgl_common_data(pdev, plat); 962 } 963 964 static struct stmmac_pci_info tgl_sgmii1g_phy0_info = { 965 .setup = tgl_sgmii_phy0_data, 966 }; 967 968 static int tgl_sgmii_phy1_data(struct pci_dev *pdev, 969 struct plat_stmmacenet_data *plat) 970 { 971 plat->bus_id = 2; 972 plat->serdes_powerup = intel_serdes_powerup; 973 plat->serdes_powerdown = intel_serdes_powerdown; 974 return tgl_common_data(pdev, plat); 975 } 976 977 static struct stmmac_pci_info tgl_sgmii1g_phy1_info = { 978 .setup = tgl_sgmii_phy1_data, 979 }; 980 981 static int adls_sgmii_phy0_data(struct pci_dev *pdev, 982 struct plat_stmmacenet_data *plat) 983 { 984 plat->bus_id = 1; 985 986 /* SerDes power up and power down are done in BIOS for ADL */ 987 988 return tgl_common_data(pdev, plat); 989 } 990 991 static struct stmmac_pci_info adls_sgmii1g_phy0_info = { 992 .setup = adls_sgmii_phy0_data, 993 }; 994 995 static int adls_sgmii_phy1_data(struct pci_dev *pdev, 996 struct plat_stmmacenet_data *plat) 997 { 998 plat->bus_id = 2; 999 1000 /* SerDes power up and power down are done in BIOS for ADL */ 1001 1002 return tgl_common_data(pdev, plat); 1003 } 1004 1005 static struct stmmac_pci_info adls_sgmii1g_phy1_info = { 1006 .setup = adls_sgmii_phy1_data, 1007 }; 1008 1009 static int adln_common_data(struct pci_dev *pdev, 1010 struct plat_stmmacenet_data *plat) 1011 { 1012 struct intel_priv_data *intel_priv = plat->bsp_priv; 1013 1014 plat->rx_queues_to_use = 6; 1015 plat->tx_queues_to_use = 4; 1016 plat->clk_ptp_rate = 204800000; 1017 1018 plat->safety_feat_cfg->tsoee = 1; 1019 plat->safety_feat_cfg->mrxpee = 0; 1020 plat->safety_feat_cfg->mestee = 1; 1021 plat->safety_feat_cfg->mrxee = 1; 1022 plat->safety_feat_cfg->mtxee = 1; 1023 plat->safety_feat_cfg->epsi = 0; 1024 plat->safety_feat_cfg->edpp = 0; 1025 plat->safety_feat_cfg->prtyen = 0; 1026 plat->safety_feat_cfg->tmouten = 0; 1027 1028 intel_priv->tsn_lane_regs = adln_tsn_lane_regs; 1029 intel_priv->max_tsn_lane_regs = ARRAY_SIZE(adln_tsn_lane_regs); 1030 1031 return intel_mgbe_common_data(pdev, plat); 1032 } 1033 1034 static int adln_sgmii_phy0_data(struct pci_dev *pdev, 1035 struct plat_stmmacenet_data *plat) 1036 { 1037 struct intel_priv_data *intel_priv = plat->bsp_priv; 1038 1039 plat->bus_id = 1; 1040 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 1041 plat->serdes_powerup = intel_serdes_powerup; 1042 plat->serdes_powerdown = intel_serdes_powerdown; 1043 plat->mac_finish = intel_mac_finish; 1044 1045 intel_priv->pid_1g.regs = pid_modphy1_1g_regs; 1046 intel_priv->pid_1g.num_regs = ARRAY_SIZE(pid_modphy1_1g_regs); 1047 intel_priv->pid_2p5g.regs = pid_modphy1_2p5g_regs; 1048 intel_priv->pid_2p5g.num_regs = ARRAY_SIZE(pid_modphy1_2p5g_regs); 1049 1050 return adln_common_data(pdev, plat); 1051 } 1052 1053 static struct stmmac_pci_info adln_sgmii1g_phy0_info = { 1054 .setup = adln_sgmii_phy0_data, 1055 }; 1056 1057 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { 1058 { 1059 .func = 6, 1060 .phy_addr = 1, 1061 }, 1062 }; 1063 1064 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = { 1065 .func = galileo_stmmac_func_data, 1066 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data), 1067 }; 1068 1069 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = { 1070 { 1071 .func = 6, 1072 .phy_addr = 1, 1073 }, 1074 { 1075 .func = 7, 1076 .phy_addr = 1, 1077 }, 1078 }; 1079 1080 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = { 1081 .func = iot2040_stmmac_func_data, 1082 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data), 1083 }; 1084 1085 static const struct dmi_system_id quark_pci_dmi[] = { 1086 { 1087 .matches = { 1088 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), 1089 }, 1090 .driver_data = (void *)&galileo_stmmac_dmi_data, 1091 }, 1092 { 1093 .matches = { 1094 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 1095 }, 1096 .driver_data = (void *)&galileo_stmmac_dmi_data, 1097 }, 1098 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040. 1099 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which 1100 * has only one pci network device while other asset tags are 1101 * for IOT2040 which has two. 1102 */ 1103 { 1104 .matches = { 1105 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 1106 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG, 1107 "6ES7647-0AA00-0YA2"), 1108 }, 1109 .driver_data = (void *)&galileo_stmmac_dmi_data, 1110 }, 1111 { 1112 .matches = { 1113 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 1114 }, 1115 .driver_data = (void *)&iot2040_stmmac_dmi_data, 1116 }, 1117 {} 1118 }; 1119 1120 static int quark_default_data(struct pci_dev *pdev, 1121 struct plat_stmmacenet_data *plat) 1122 { 1123 int ret; 1124 1125 /* Set common default data first */ 1126 common_default_data(plat); 1127 1128 /* Refuse to load the driver and register net device if MAC controller 1129 * does not connect to any PHY interface. 1130 */ 1131 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi); 1132 if (ret < 0) { 1133 /* Return error to the caller on DMI enabled boards. */ 1134 if (dmi_get_system_info(DMI_BOARD_NAME)) 1135 return ret; 1136 1137 /* Galileo boards with old firmware don't support DMI. We always 1138 * use 1 here as PHY address, so at least the first found MAC 1139 * controller would be probed. 1140 */ 1141 ret = 1; 1142 } 1143 1144 plat->bus_id = pci_dev_id(pdev); 1145 plat->phy_addr = ret; 1146 plat->phy_interface = PHY_INTERFACE_MODE_RMII; 1147 1148 plat->dma_cfg->pbl = 16; 1149 plat->dma_cfg->pblx8 = true; 1150 plat->dma_cfg->fixed_burst = 1; 1151 /* AXI (TODO) */ 1152 1153 return 0; 1154 } 1155 1156 static const struct stmmac_pci_info quark_info = { 1157 .setup = quark_default_data, 1158 }; 1159 1160 static int stmmac_config_single_msi(struct pci_dev *pdev, 1161 struct plat_stmmacenet_data *plat, 1162 struct stmmac_resources *res) 1163 { 1164 int ret; 1165 1166 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 1167 if (ret < 0) { 1168 dev_info(&pdev->dev, "%s: Single IRQ enablement failed\n", 1169 __func__); 1170 return ret; 1171 } 1172 1173 res->irq = pci_irq_vector(pdev, 0); 1174 res->wol_irq = res->irq; 1175 plat->flags &= ~STMMAC_FLAG_MULTI_MSI_EN; 1176 dev_info(&pdev->dev, "%s: Single IRQ enablement successful\n", 1177 __func__); 1178 1179 return 0; 1180 } 1181 1182 static int stmmac_config_multi_msi(struct pci_dev *pdev, 1183 struct plat_stmmacenet_data *plat, 1184 struct stmmac_resources *res) 1185 { 1186 int ret; 1187 int i; 1188 1189 if (plat->msi_rx_base_vec >= STMMAC_MSI_VEC_MAX || 1190 plat->msi_tx_base_vec >= STMMAC_MSI_VEC_MAX) { 1191 dev_info(&pdev->dev, "%s: Invalid RX & TX vector defined\n", 1192 __func__); 1193 return -1; 1194 } 1195 1196 ret = pci_alloc_irq_vectors(pdev, 2, STMMAC_MSI_VEC_MAX, 1197 PCI_IRQ_MSI | PCI_IRQ_MSIX); 1198 if (ret < 0) { 1199 dev_info(&pdev->dev, "%s: multi MSI enablement failed\n", 1200 __func__); 1201 return ret; 1202 } 1203 1204 /* For RX MSI */ 1205 for (i = 0; i < plat->rx_queues_to_use; i++) { 1206 res->rx_irq[i] = pci_irq_vector(pdev, 1207 plat->msi_rx_base_vec + i * 2); 1208 } 1209 1210 /* For TX MSI */ 1211 for (i = 0; i < plat->tx_queues_to_use; i++) { 1212 res->tx_irq[i] = pci_irq_vector(pdev, 1213 plat->msi_tx_base_vec + i * 2); 1214 } 1215 1216 if (plat->msi_mac_vec < STMMAC_MSI_VEC_MAX) 1217 res->irq = pci_irq_vector(pdev, plat->msi_mac_vec); 1218 if (plat->msi_wol_vec < STMMAC_MSI_VEC_MAX) 1219 res->wol_irq = pci_irq_vector(pdev, plat->msi_wol_vec); 1220 if (plat->msi_lpi_vec < STMMAC_MSI_VEC_MAX) 1221 res->lpi_irq = pci_irq_vector(pdev, plat->msi_lpi_vec); 1222 if (plat->msi_sfty_ce_vec < STMMAC_MSI_VEC_MAX) 1223 res->sfty_ce_irq = pci_irq_vector(pdev, plat->msi_sfty_ce_vec); 1224 if (plat->msi_sfty_ue_vec < STMMAC_MSI_VEC_MAX) 1225 res->sfty_ue_irq = pci_irq_vector(pdev, plat->msi_sfty_ue_vec); 1226 1227 plat->flags |= STMMAC_FLAG_MULTI_MSI_EN; 1228 dev_info(&pdev->dev, "%s: multi MSI enablement successful\n", __func__); 1229 1230 return 0; 1231 } 1232 1233 static int intel_eth_pci_suspend(struct device *dev, void *bsp_priv) 1234 { 1235 struct pci_dev *pdev = to_pci_dev(dev); 1236 int ret; 1237 1238 ret = pci_save_state(pdev); 1239 if (ret) 1240 return ret; 1241 1242 pci_wake_from_d3(pdev, true); 1243 pci_set_power_state(pdev, PCI_D3hot); 1244 return 0; 1245 } 1246 1247 static int intel_eth_pci_resume(struct device *dev, void *bsp_priv) 1248 { 1249 struct pci_dev *pdev = to_pci_dev(dev); 1250 int ret; 1251 1252 pci_restore_state(pdev); 1253 pci_set_power_state(pdev, PCI_D0); 1254 1255 ret = pcim_enable_device(pdev); 1256 if (ret) 1257 return ret; 1258 1259 pci_set_master(pdev); 1260 1261 return 0; 1262 } 1263 1264 /** 1265 * intel_eth_pci_probe 1266 * 1267 * @pdev: pci device pointer 1268 * @id: pointer to table of device id/id's. 1269 * 1270 * Description: This probing function gets called for all PCI devices which 1271 * match the ID table and are not "owned" by other driver yet. This function 1272 * gets passed a "struct pci_dev *" for each device whose entry in the ID table 1273 * matches the device. The probe functions returns zero when the driver choose 1274 * to take "ownership" of the device or an error code(-ve no) otherwise. 1275 */ 1276 static int intel_eth_pci_probe(struct pci_dev *pdev, 1277 const struct pci_device_id *id) 1278 { 1279 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data; 1280 struct intel_priv_data *intel_priv; 1281 struct plat_stmmacenet_data *plat; 1282 struct stmmac_resources res; 1283 int ret; 1284 1285 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL); 1286 if (!intel_priv) 1287 return -ENOMEM; 1288 1289 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); 1290 if (!plat) 1291 return -ENOMEM; 1292 1293 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, 1294 sizeof(*plat->mdio_bus_data), 1295 GFP_KERNEL); 1296 if (!plat->mdio_bus_data) 1297 return -ENOMEM; 1298 1299 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), 1300 GFP_KERNEL); 1301 if (!plat->dma_cfg) 1302 return -ENOMEM; 1303 1304 plat->safety_feat_cfg = devm_kzalloc(&pdev->dev, 1305 sizeof(*plat->safety_feat_cfg), 1306 GFP_KERNEL); 1307 if (!plat->safety_feat_cfg) 1308 return -ENOMEM; 1309 1310 /* Enable pci device */ 1311 ret = pcim_enable_device(pdev); 1312 if (ret) { 1313 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", 1314 __func__); 1315 return ret; 1316 } 1317 1318 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); 1319 if (ret) 1320 return ret; 1321 1322 pci_set_master(pdev); 1323 1324 plat->bsp_priv = intel_priv; 1325 plat->suspend = intel_eth_pci_suspend; 1326 plat->resume = intel_eth_pci_resume; 1327 1328 intel_priv->mdio_adhoc_addr = INTEL_MGBE_ADHOC_ADDR; 1329 intel_priv->crossts_adj = 1; 1330 1331 /* Initialize all MSI vectors to invalid so that it can be set 1332 * according to platform data settings below. 1333 * Note: MSI vector takes value from 0 upto 31 (STMMAC_MSI_VEC_MAX) 1334 */ 1335 plat->msi_mac_vec = STMMAC_MSI_VEC_MAX; 1336 plat->msi_wol_vec = STMMAC_MSI_VEC_MAX; 1337 plat->msi_lpi_vec = STMMAC_MSI_VEC_MAX; 1338 plat->msi_sfty_ce_vec = STMMAC_MSI_VEC_MAX; 1339 plat->msi_sfty_ue_vec = STMMAC_MSI_VEC_MAX; 1340 plat->msi_rx_base_vec = STMMAC_MSI_VEC_MAX; 1341 plat->msi_tx_base_vec = STMMAC_MSI_VEC_MAX; 1342 1343 ret = info->setup(pdev, plat); 1344 if (ret) 1345 return ret; 1346 1347 memset(&res, 0, sizeof(res)); 1348 res.addr = pcim_iomap_table(pdev)[0]; 1349 1350 ret = stmmac_config_multi_msi(pdev, plat, &res); 1351 if (ret) { 1352 ret = stmmac_config_single_msi(pdev, plat, &res); 1353 if (ret) { 1354 dev_err(&pdev->dev, "%s: ERROR: failed to enable IRQ\n", 1355 __func__); 1356 goto err_alloc_irq; 1357 } 1358 } 1359 1360 ret = stmmac_dvr_probe(&pdev->dev, plat, &res); 1361 if (ret) { 1362 goto err_alloc_irq; 1363 } 1364 1365 return 0; 1366 1367 err_alloc_irq: 1368 clk_disable_unprepare(plat->stmmac_clk); 1369 clk_unregister_fixed_rate(plat->stmmac_clk); 1370 return ret; 1371 } 1372 1373 /** 1374 * intel_eth_pci_remove 1375 * 1376 * @pdev: pci device pointer 1377 * Description: this function calls the main to free the net resources 1378 * and releases the PCI resources. 1379 */ 1380 static void intel_eth_pci_remove(struct pci_dev *pdev) 1381 { 1382 struct net_device *ndev = dev_get_drvdata(&pdev->dev); 1383 struct stmmac_priv *priv = netdev_priv(ndev); 1384 1385 stmmac_dvr_remove(&pdev->dev); 1386 1387 clk_disable_unprepare(priv->plat->stmmac_clk); 1388 clk_unregister_fixed_rate(priv->plat->stmmac_clk); 1389 } 1390 1391 #define PCI_DEVICE_ID_INTEL_QUARK 0x0937 1392 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G 0x4b30 1393 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G 0x4b31 1394 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5 0x4b32 1395 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC 1396 * which are named PSE0 and PSE1 1397 */ 1398 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G 0x4ba0 1399 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G 0x4ba1 1400 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5 0x4ba2 1401 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G 0x4bb0 1402 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G 0x4bb1 1403 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5 0x4bb2 1404 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0 0x43ac 1405 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1 0x43a2 1406 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G 0xa0ac 1407 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0 0x7aac 1408 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1 0x7aad 1409 #define PCI_DEVICE_ID_INTEL_ADLN_SGMII1G 0x54ac 1410 #define PCI_DEVICE_ID_INTEL_RPLP_SGMII1G 0x51ac 1411 1412 static const struct pci_device_id intel_eth_pci_id_table[] = { 1413 { PCI_DEVICE_DATA(INTEL, QUARK, &quark_info) }, 1414 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G, &ehl_rgmii1g_info) }, 1415 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G, &ehl_sgmii1g_info) }, 1416 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5, &ehl_sgmii1g_info) }, 1417 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G, &ehl_pse0_rgmii1g_info) }, 1418 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G, &ehl_pse0_sgmii1g_info) }, 1419 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5, &ehl_pse0_sgmii1g_info) }, 1420 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G, &ehl_pse1_rgmii1g_info) }, 1421 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G, &ehl_pse1_sgmii1g_info) }, 1422 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5, &ehl_pse1_sgmii1g_info) }, 1423 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G, &tgl_sgmii1g_phy0_info) }, 1424 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0, &tgl_sgmii1g_phy0_info) }, 1425 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, &tgl_sgmii1g_phy1_info) }, 1426 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0, &adls_sgmii1g_phy0_info) }, 1427 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1, &adls_sgmii1g_phy1_info) }, 1428 { PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &adln_sgmii1g_phy0_info) }, 1429 { PCI_DEVICE_DATA(INTEL, RPLP_SGMII1G, &adln_sgmii1g_phy0_info) }, 1430 {} 1431 }; 1432 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table); 1433 1434 static struct pci_driver intel_eth_pci_driver = { 1435 .name = "intel-eth-pci", 1436 .id_table = intel_eth_pci_id_table, 1437 .probe = intel_eth_pci_probe, 1438 .remove = intel_eth_pci_remove, 1439 .driver = { 1440 .pm = &stmmac_simple_pm_ops, 1441 }, 1442 }; 1443 1444 module_pci_driver(intel_eth_pci_driver); 1445 1446 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver"); 1447 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>"); 1448 MODULE_LICENSE("GPL v2"); 1449