1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. 4 * All rights reserved. 5 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36 #include <linux/sched.h> 37 #include <linux/pci.h> 38 #include <linux/errno.h> 39 #include <linux/kernel.h> 40 #include <linux/io.h> 41 #include <linux/slab.h> 42 #include <linux/mlx4/cmd.h> 43 #include <linux/mlx4/qp.h> 44 #include <linux/if_ether.h> 45 #include <linux/etherdevice.h> 46 47 #include "mlx4.h" 48 #include "fw.h" 49 #include "mlx4_stats.h" 50 51 #define MLX4_MAC_VALID (1ull << 63) 52 #define MLX4_PF_COUNTERS_PER_PORT 2 53 #define MLX4_VF_COUNTERS_PER_PORT 1 54 55 struct mac_res { 56 struct list_head list; 57 u64 mac; 58 int ref_count; 59 u8 smac_index; 60 u8 port; 61 }; 62 63 struct vlan_res { 64 struct list_head list; 65 u16 vlan; 66 int ref_count; 67 int vlan_index; 68 u8 port; 69 }; 70 71 struct res_common { 72 struct list_head list; 73 struct rb_node node; 74 u64 res_id; 75 int owner; 76 int state; 77 int from_state; 78 int to_state; 79 int removing; 80 }; 81 82 enum { 83 RES_ANY_BUSY = 1 84 }; 85 86 struct res_gid { 87 struct list_head list; 88 u8 gid[16]; 89 enum mlx4_protocol prot; 90 enum mlx4_steer_type steer; 91 u64 reg_id; 92 }; 93 94 enum res_qp_states { 95 RES_QP_BUSY = RES_ANY_BUSY, 96 97 /* QP number was allocated */ 98 RES_QP_RESERVED, 99 100 /* ICM memory for QP context was mapped */ 101 RES_QP_MAPPED, 102 103 /* QP is in hw ownership */ 104 RES_QP_HW 105 }; 106 107 struct res_qp { 108 struct res_common com; 109 struct res_mtt *mtt; 110 struct res_cq *rcq; 111 struct res_cq *scq; 112 struct res_srq *srq; 113 struct list_head mcg_list; 114 spinlock_t mcg_spl; 115 int local_qpn; 116 atomic_t ref_count; 117 u32 qpc_flags; 118 /* saved qp params before VST enforcement in order to restore on VGT */ 119 u8 sched_queue; 120 __be32 param3; 121 u8 vlan_control; 122 u8 fvl_rx; 123 u8 pri_path_fl; 124 u8 vlan_index; 125 u8 feup; 126 }; 127 128 enum res_mtt_states { 129 RES_MTT_BUSY = RES_ANY_BUSY, 130 RES_MTT_ALLOCATED, 131 }; 132 133 static inline const char *mtt_states_str(enum res_mtt_states state) 134 { 135 switch (state) { 136 case RES_MTT_BUSY: return "RES_MTT_BUSY"; 137 case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED"; 138 default: return "Unknown"; 139 } 140 } 141 142 struct res_mtt { 143 struct res_common com; 144 int order; 145 atomic_t ref_count; 146 }; 147 148 enum res_mpt_states { 149 RES_MPT_BUSY = RES_ANY_BUSY, 150 RES_MPT_RESERVED, 151 RES_MPT_MAPPED, 152 RES_MPT_HW, 153 }; 154 155 struct res_mpt { 156 struct res_common com; 157 struct res_mtt *mtt; 158 int key; 159 }; 160 161 enum res_eq_states { 162 RES_EQ_BUSY = RES_ANY_BUSY, 163 RES_EQ_RESERVED, 164 RES_EQ_HW, 165 }; 166 167 struct res_eq { 168 struct res_common com; 169 struct res_mtt *mtt; 170 }; 171 172 enum res_cq_states { 173 RES_CQ_BUSY = RES_ANY_BUSY, 174 RES_CQ_ALLOCATED, 175 RES_CQ_HW, 176 }; 177 178 struct res_cq { 179 struct res_common com; 180 struct res_mtt *mtt; 181 atomic_t ref_count; 182 }; 183 184 enum res_srq_states { 185 RES_SRQ_BUSY = RES_ANY_BUSY, 186 RES_SRQ_ALLOCATED, 187 RES_SRQ_HW, 188 }; 189 190 struct res_srq { 191 struct res_common com; 192 struct res_mtt *mtt; 193 struct res_cq *cq; 194 atomic_t ref_count; 195 }; 196 197 enum res_counter_states { 198 RES_COUNTER_BUSY = RES_ANY_BUSY, 199 RES_COUNTER_ALLOCATED, 200 }; 201 202 struct res_counter { 203 struct res_common com; 204 int port; 205 }; 206 207 enum res_xrcdn_states { 208 RES_XRCD_BUSY = RES_ANY_BUSY, 209 RES_XRCD_ALLOCATED, 210 }; 211 212 struct res_xrcdn { 213 struct res_common com; 214 int port; 215 }; 216 217 enum res_fs_rule_states { 218 RES_FS_RULE_BUSY = RES_ANY_BUSY, 219 RES_FS_RULE_ALLOCATED, 220 }; 221 222 struct res_fs_rule { 223 struct res_common com; 224 int qpn; 225 /* VF DMFS mbox with port flipped */ 226 void *mirr_mbox; 227 /* > 0 --> apply mirror when getting into HA mode */ 228 /* = 0 --> un-apply mirror when getting out of HA mode */ 229 u32 mirr_mbox_size; 230 struct list_head mirr_list; 231 u64 mirr_rule_id; 232 }; 233 234 static void *res_tracker_lookup(struct rb_root *root, u64 res_id) 235 { 236 struct rb_node *node = root->rb_node; 237 238 while (node) { 239 struct res_common *res = container_of(node, struct res_common, 240 node); 241 242 if (res_id < res->res_id) 243 node = node->rb_left; 244 else if (res_id > res->res_id) 245 node = node->rb_right; 246 else 247 return res; 248 } 249 return NULL; 250 } 251 252 static int res_tracker_insert(struct rb_root *root, struct res_common *res) 253 { 254 struct rb_node **new = &(root->rb_node), *parent = NULL; 255 256 /* Figure out where to put new node */ 257 while (*new) { 258 struct res_common *this = container_of(*new, struct res_common, 259 node); 260 261 parent = *new; 262 if (res->res_id < this->res_id) 263 new = &((*new)->rb_left); 264 else if (res->res_id > this->res_id) 265 new = &((*new)->rb_right); 266 else 267 return -EEXIST; 268 } 269 270 /* Add new node and rebalance tree. */ 271 rb_link_node(&res->node, parent, new); 272 rb_insert_color(&res->node, root); 273 274 return 0; 275 } 276 277 enum qp_transition { 278 QP_TRANS_INIT2RTR, 279 QP_TRANS_RTR2RTS, 280 QP_TRANS_RTS2RTS, 281 QP_TRANS_SQERR2RTS, 282 QP_TRANS_SQD2SQD, 283 QP_TRANS_SQD2RTS 284 }; 285 286 /* For Debug uses */ 287 static const char *resource_str(enum mlx4_resource rt) 288 { 289 switch (rt) { 290 case RES_QP: return "RES_QP"; 291 case RES_CQ: return "RES_CQ"; 292 case RES_SRQ: return "RES_SRQ"; 293 case RES_MPT: return "RES_MPT"; 294 case RES_MTT: return "RES_MTT"; 295 case RES_MAC: return "RES_MAC"; 296 case RES_VLAN: return "RES_VLAN"; 297 case RES_EQ: return "RES_EQ"; 298 case RES_COUNTER: return "RES_COUNTER"; 299 case RES_FS_RULE: return "RES_FS_RULE"; 300 case RES_XRCD: return "RES_XRCD"; 301 default: return "Unknown resource type !!!"; 302 }; 303 } 304 305 static void rem_slave_vlans(struct mlx4_dev *dev, int slave); 306 static inline int mlx4_grant_resource(struct mlx4_dev *dev, int slave, 307 enum mlx4_resource res_type, int count, 308 int port) 309 { 310 struct mlx4_priv *priv = mlx4_priv(dev); 311 struct resource_allocator *res_alloc = 312 &priv->mfunc.master.res_tracker.res_alloc[res_type]; 313 int err = -EINVAL; 314 int allocated, free, reserved, guaranteed, from_free; 315 int from_rsvd; 316 317 if (slave > dev->persist->num_vfs) 318 return -EINVAL; 319 320 spin_lock(&res_alloc->alloc_lock); 321 allocated = (port > 0) ? 322 res_alloc->allocated[(port - 1) * 323 (dev->persist->num_vfs + 1) + slave] : 324 res_alloc->allocated[slave]; 325 free = (port > 0) ? res_alloc->res_port_free[port - 1] : 326 res_alloc->res_free; 327 reserved = (port > 0) ? res_alloc->res_port_rsvd[port - 1] : 328 res_alloc->res_reserved; 329 guaranteed = res_alloc->guaranteed[slave]; 330 331 if (allocated + count > res_alloc->quota[slave]) { 332 mlx4_warn(dev, "VF %d port %d res %s: quota exceeded, count %d alloc %d quota %d\n", 333 slave, port, resource_str(res_type), count, 334 allocated, res_alloc->quota[slave]); 335 goto out; 336 } 337 338 if (allocated + count <= guaranteed) { 339 err = 0; 340 from_rsvd = count; 341 } else { 342 /* portion may need to be obtained from free area */ 343 if (guaranteed - allocated > 0) 344 from_free = count - (guaranteed - allocated); 345 else 346 from_free = count; 347 348 from_rsvd = count - from_free; 349 350 if (free - from_free >= reserved) 351 err = 0; 352 else 353 mlx4_warn(dev, "VF %d port %d res %s: free pool empty, free %d from_free %d rsvd %d\n", 354 slave, port, resource_str(res_type), free, 355 from_free, reserved); 356 } 357 358 if (!err) { 359 /* grant the request */ 360 if (port > 0) { 361 res_alloc->allocated[(port - 1) * 362 (dev->persist->num_vfs + 1) + slave] += count; 363 res_alloc->res_port_free[port - 1] -= count; 364 res_alloc->res_port_rsvd[port - 1] -= from_rsvd; 365 } else { 366 res_alloc->allocated[slave] += count; 367 res_alloc->res_free -= count; 368 res_alloc->res_reserved -= from_rsvd; 369 } 370 } 371 372 out: 373 spin_unlock(&res_alloc->alloc_lock); 374 return err; 375 } 376 377 static inline void mlx4_release_resource(struct mlx4_dev *dev, int slave, 378 enum mlx4_resource res_type, int count, 379 int port) 380 { 381 struct mlx4_priv *priv = mlx4_priv(dev); 382 struct resource_allocator *res_alloc = 383 &priv->mfunc.master.res_tracker.res_alloc[res_type]; 384 int allocated, guaranteed, from_rsvd; 385 386 if (slave > dev->persist->num_vfs) 387 return; 388 389 spin_lock(&res_alloc->alloc_lock); 390 391 allocated = (port > 0) ? 392 res_alloc->allocated[(port - 1) * 393 (dev->persist->num_vfs + 1) + slave] : 394 res_alloc->allocated[slave]; 395 guaranteed = res_alloc->guaranteed[slave]; 396 397 if (allocated - count >= guaranteed) { 398 from_rsvd = 0; 399 } else { 400 /* portion may need to be returned to reserved area */ 401 if (allocated - guaranteed > 0) 402 from_rsvd = count - (allocated - guaranteed); 403 else 404 from_rsvd = count; 405 } 406 407 if (port > 0) { 408 res_alloc->allocated[(port - 1) * 409 (dev->persist->num_vfs + 1) + slave] -= count; 410 res_alloc->res_port_free[port - 1] += count; 411 res_alloc->res_port_rsvd[port - 1] += from_rsvd; 412 } else { 413 res_alloc->allocated[slave] -= count; 414 res_alloc->res_free += count; 415 res_alloc->res_reserved += from_rsvd; 416 } 417 418 spin_unlock(&res_alloc->alloc_lock); 419 return; 420 } 421 422 static inline void initialize_res_quotas(struct mlx4_dev *dev, 423 struct resource_allocator *res_alloc, 424 enum mlx4_resource res_type, 425 int vf, int num_instances) 426 { 427 res_alloc->guaranteed[vf] = num_instances / 428 (2 * (dev->persist->num_vfs + 1)); 429 res_alloc->quota[vf] = (num_instances / 2) + res_alloc->guaranteed[vf]; 430 if (vf == mlx4_master_func_num(dev)) { 431 res_alloc->res_free = num_instances; 432 if (res_type == RES_MTT) { 433 /* reserved mtts will be taken out of the PF allocation */ 434 res_alloc->res_free += dev->caps.reserved_mtts; 435 res_alloc->guaranteed[vf] += dev->caps.reserved_mtts; 436 res_alloc->quota[vf] += dev->caps.reserved_mtts; 437 } 438 } 439 } 440 441 void mlx4_init_quotas(struct mlx4_dev *dev) 442 { 443 struct mlx4_priv *priv = mlx4_priv(dev); 444 int pf; 445 446 /* quotas for VFs are initialized in mlx4_slave_cap */ 447 if (mlx4_is_slave(dev)) 448 return; 449 450 if (!mlx4_is_mfunc(dev)) { 451 dev->quotas.qp = dev->caps.num_qps - dev->caps.reserved_qps - 452 mlx4_num_reserved_sqps(dev); 453 dev->quotas.cq = dev->caps.num_cqs - dev->caps.reserved_cqs; 454 dev->quotas.srq = dev->caps.num_srqs - dev->caps.reserved_srqs; 455 dev->quotas.mtt = dev->caps.num_mtts - dev->caps.reserved_mtts; 456 dev->quotas.mpt = dev->caps.num_mpts - dev->caps.reserved_mrws; 457 return; 458 } 459 460 pf = mlx4_master_func_num(dev); 461 dev->quotas.qp = 462 priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[pf]; 463 dev->quotas.cq = 464 priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[pf]; 465 dev->quotas.srq = 466 priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[pf]; 467 dev->quotas.mtt = 468 priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[pf]; 469 dev->quotas.mpt = 470 priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[pf]; 471 } 472 473 static int get_max_gauranteed_vfs_counter(struct mlx4_dev *dev) 474 { 475 /* reduce the sink counter */ 476 return (dev->caps.max_counters - 1 - 477 (MLX4_PF_COUNTERS_PER_PORT * MLX4_MAX_PORTS)) 478 / MLX4_MAX_PORTS; 479 } 480 481 int mlx4_init_resource_tracker(struct mlx4_dev *dev) 482 { 483 struct mlx4_priv *priv = mlx4_priv(dev); 484 int i, j; 485 int t; 486 int max_vfs_guarantee_counter = get_max_gauranteed_vfs_counter(dev); 487 488 priv->mfunc.master.res_tracker.slave_list = 489 kzalloc(dev->num_slaves * sizeof(struct slave_list), 490 GFP_KERNEL); 491 if (!priv->mfunc.master.res_tracker.slave_list) 492 return -ENOMEM; 493 494 for (i = 0 ; i < dev->num_slaves; i++) { 495 for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t) 496 INIT_LIST_HEAD(&priv->mfunc.master.res_tracker. 497 slave_list[i].res_list[t]); 498 mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex); 499 } 500 501 mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n", 502 dev->num_slaves); 503 for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) 504 priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT; 505 506 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) { 507 struct resource_allocator *res_alloc = 508 &priv->mfunc.master.res_tracker.res_alloc[i]; 509 res_alloc->quota = kmalloc((dev->persist->num_vfs + 1) * 510 sizeof(int), GFP_KERNEL); 511 res_alloc->guaranteed = kmalloc((dev->persist->num_vfs + 1) * 512 sizeof(int), GFP_KERNEL); 513 if (i == RES_MAC || i == RES_VLAN) 514 res_alloc->allocated = kzalloc(MLX4_MAX_PORTS * 515 (dev->persist->num_vfs 516 + 1) * 517 sizeof(int), GFP_KERNEL); 518 else 519 res_alloc->allocated = kzalloc((dev->persist-> 520 num_vfs + 1) * 521 sizeof(int), GFP_KERNEL); 522 /* Reduce the sink counter */ 523 if (i == RES_COUNTER) 524 res_alloc->res_free = dev->caps.max_counters - 1; 525 526 if (!res_alloc->quota || !res_alloc->guaranteed || 527 !res_alloc->allocated) 528 goto no_mem_err; 529 530 spin_lock_init(&res_alloc->alloc_lock); 531 for (t = 0; t < dev->persist->num_vfs + 1; t++) { 532 struct mlx4_active_ports actv_ports = 533 mlx4_get_active_ports(dev, t); 534 switch (i) { 535 case RES_QP: 536 initialize_res_quotas(dev, res_alloc, RES_QP, 537 t, dev->caps.num_qps - 538 dev->caps.reserved_qps - 539 mlx4_num_reserved_sqps(dev)); 540 break; 541 case RES_CQ: 542 initialize_res_quotas(dev, res_alloc, RES_CQ, 543 t, dev->caps.num_cqs - 544 dev->caps.reserved_cqs); 545 break; 546 case RES_SRQ: 547 initialize_res_quotas(dev, res_alloc, RES_SRQ, 548 t, dev->caps.num_srqs - 549 dev->caps.reserved_srqs); 550 break; 551 case RES_MPT: 552 initialize_res_quotas(dev, res_alloc, RES_MPT, 553 t, dev->caps.num_mpts - 554 dev->caps.reserved_mrws); 555 break; 556 case RES_MTT: 557 initialize_res_quotas(dev, res_alloc, RES_MTT, 558 t, dev->caps.num_mtts - 559 dev->caps.reserved_mtts); 560 break; 561 case RES_MAC: 562 if (t == mlx4_master_func_num(dev)) { 563 int max_vfs_pport = 0; 564 /* Calculate the max vfs per port for */ 565 /* both ports. */ 566 for (j = 0; j < dev->caps.num_ports; 567 j++) { 568 struct mlx4_slaves_pport slaves_pport = 569 mlx4_phys_to_slaves_pport(dev, j + 1); 570 unsigned current_slaves = 571 bitmap_weight(slaves_pport.slaves, 572 dev->caps.num_ports) - 1; 573 if (max_vfs_pport < current_slaves) 574 max_vfs_pport = 575 current_slaves; 576 } 577 res_alloc->quota[t] = 578 MLX4_MAX_MAC_NUM - 579 2 * max_vfs_pport; 580 res_alloc->guaranteed[t] = 2; 581 for (j = 0; j < MLX4_MAX_PORTS; j++) 582 res_alloc->res_port_free[j] = 583 MLX4_MAX_MAC_NUM; 584 } else { 585 res_alloc->quota[t] = MLX4_MAX_MAC_NUM; 586 res_alloc->guaranteed[t] = 2; 587 } 588 break; 589 case RES_VLAN: 590 if (t == mlx4_master_func_num(dev)) { 591 res_alloc->quota[t] = MLX4_MAX_VLAN_NUM; 592 res_alloc->guaranteed[t] = MLX4_MAX_VLAN_NUM / 2; 593 for (j = 0; j < MLX4_MAX_PORTS; j++) 594 res_alloc->res_port_free[j] = 595 res_alloc->quota[t]; 596 } else { 597 res_alloc->quota[t] = MLX4_MAX_VLAN_NUM / 2; 598 res_alloc->guaranteed[t] = 0; 599 } 600 break; 601 case RES_COUNTER: 602 res_alloc->quota[t] = dev->caps.max_counters; 603 if (t == mlx4_master_func_num(dev)) 604 res_alloc->guaranteed[t] = 605 MLX4_PF_COUNTERS_PER_PORT * 606 MLX4_MAX_PORTS; 607 else if (t <= max_vfs_guarantee_counter) 608 res_alloc->guaranteed[t] = 609 MLX4_VF_COUNTERS_PER_PORT * 610 MLX4_MAX_PORTS; 611 else 612 res_alloc->guaranteed[t] = 0; 613 res_alloc->res_free -= res_alloc->guaranteed[t]; 614 break; 615 default: 616 break; 617 } 618 if (i == RES_MAC || i == RES_VLAN) { 619 for (j = 0; j < dev->caps.num_ports; j++) 620 if (test_bit(j, actv_ports.ports)) 621 res_alloc->res_port_rsvd[j] += 622 res_alloc->guaranteed[t]; 623 } else { 624 res_alloc->res_reserved += res_alloc->guaranteed[t]; 625 } 626 } 627 } 628 spin_lock_init(&priv->mfunc.master.res_tracker.lock); 629 return 0; 630 631 no_mem_err: 632 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) { 633 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated); 634 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL; 635 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed); 636 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL; 637 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota); 638 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL; 639 } 640 return -ENOMEM; 641 } 642 643 void mlx4_free_resource_tracker(struct mlx4_dev *dev, 644 enum mlx4_res_tracker_free_type type) 645 { 646 struct mlx4_priv *priv = mlx4_priv(dev); 647 int i; 648 649 if (priv->mfunc.master.res_tracker.slave_list) { 650 if (type != RES_TR_FREE_STRUCTS_ONLY) { 651 for (i = 0; i < dev->num_slaves; i++) { 652 if (type == RES_TR_FREE_ALL || 653 dev->caps.function != i) 654 mlx4_delete_all_resources_for_slave(dev, i); 655 } 656 /* free master's vlans */ 657 i = dev->caps.function; 658 mlx4_reset_roce_gids(dev, i); 659 mutex_lock(&priv->mfunc.master.res_tracker.slave_list[i].mutex); 660 rem_slave_vlans(dev, i); 661 mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[i].mutex); 662 } 663 664 if (type != RES_TR_FREE_SLAVES_ONLY) { 665 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) { 666 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated); 667 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL; 668 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed); 669 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL; 670 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota); 671 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL; 672 } 673 kfree(priv->mfunc.master.res_tracker.slave_list); 674 priv->mfunc.master.res_tracker.slave_list = NULL; 675 } 676 } 677 } 678 679 static void update_pkey_index(struct mlx4_dev *dev, int slave, 680 struct mlx4_cmd_mailbox *inbox) 681 { 682 u8 sched = *(u8 *)(inbox->buf + 64); 683 u8 orig_index = *(u8 *)(inbox->buf + 35); 684 u8 new_index; 685 struct mlx4_priv *priv = mlx4_priv(dev); 686 int port; 687 688 port = (sched >> 6 & 1) + 1; 689 690 new_index = priv->virt2phys_pkey[slave][port - 1][orig_index]; 691 *(u8 *)(inbox->buf + 35) = new_index; 692 } 693 694 static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox, 695 u8 slave) 696 { 697 struct mlx4_qp_context *qp_ctx = inbox->buf + 8; 698 enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *) inbox->buf); 699 u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff; 700 int port; 701 702 if (MLX4_QP_ST_UD == ts) { 703 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1; 704 if (mlx4_is_eth(dev, port)) 705 qp_ctx->pri_path.mgid_index = 706 mlx4_get_base_gid_ix(dev, slave, port) | 0x80; 707 else 708 qp_ctx->pri_path.mgid_index = slave | 0x80; 709 710 } else if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_XRC == ts || MLX4_QP_ST_UC == ts) { 711 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) { 712 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1; 713 if (mlx4_is_eth(dev, port)) { 714 qp_ctx->pri_path.mgid_index += 715 mlx4_get_base_gid_ix(dev, slave, port); 716 qp_ctx->pri_path.mgid_index &= 0x7f; 717 } else { 718 qp_ctx->pri_path.mgid_index = slave & 0x7F; 719 } 720 } 721 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) { 722 port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1; 723 if (mlx4_is_eth(dev, port)) { 724 qp_ctx->alt_path.mgid_index += 725 mlx4_get_base_gid_ix(dev, slave, port); 726 qp_ctx->alt_path.mgid_index &= 0x7f; 727 } else { 728 qp_ctx->alt_path.mgid_index = slave & 0x7F; 729 } 730 } 731 } 732 } 733 734 static int handle_counter(struct mlx4_dev *dev, struct mlx4_qp_context *qpc, 735 u8 slave, int port); 736 737 static int update_vport_qp_param(struct mlx4_dev *dev, 738 struct mlx4_cmd_mailbox *inbox, 739 u8 slave, u32 qpn) 740 { 741 struct mlx4_qp_context *qpc = inbox->buf + 8; 742 struct mlx4_vport_oper_state *vp_oper; 743 struct mlx4_priv *priv; 744 u32 qp_type; 745 int port, err = 0; 746 747 port = (qpc->pri_path.sched_queue & 0x40) ? 2 : 1; 748 priv = mlx4_priv(dev); 749 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; 750 qp_type = (be32_to_cpu(qpc->flags) >> 16) & 0xff; 751 752 err = handle_counter(dev, qpc, slave, port); 753 if (err) 754 goto out; 755 756 if (MLX4_VGT != vp_oper->state.default_vlan) { 757 /* the reserved QPs (special, proxy, tunnel) 758 * do not operate over vlans 759 */ 760 if (mlx4_is_qp_reserved(dev, qpn)) 761 return 0; 762 763 /* force strip vlan by clear vsd, MLX QP refers to Raw Ethernet */ 764 if (qp_type == MLX4_QP_ST_UD || 765 (qp_type == MLX4_QP_ST_MLX && mlx4_is_eth(dev, port))) { 766 if (dev->caps.bmme_flags & MLX4_BMME_FLAG_VSD_INIT2RTR) { 767 *(__be32 *)inbox->buf = 768 cpu_to_be32(be32_to_cpu(*(__be32 *)inbox->buf) | 769 MLX4_QP_OPTPAR_VLAN_STRIPPING); 770 qpc->param3 &= ~cpu_to_be32(MLX4_STRIP_VLAN); 771 } else { 772 struct mlx4_update_qp_params params = {.flags = 0}; 773 774 err = mlx4_update_qp(dev, qpn, MLX4_UPDATE_QP_VSD, ¶ms); 775 if (err) 776 goto out; 777 } 778 } 779 780 /* preserve IF_COUNTER flag */ 781 qpc->pri_path.vlan_control &= 782 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER; 783 if (vp_oper->state.link_state == IFLA_VF_LINK_STATE_DISABLE && 784 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP) { 785 qpc->pri_path.vlan_control |= 786 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED | 787 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED | 788 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED | 789 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED | 790 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED | 791 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED; 792 } else if (0 != vp_oper->state.default_vlan) { 793 qpc->pri_path.vlan_control |= 794 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED | 795 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED | 796 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED; 797 } else { /* priority tagged */ 798 qpc->pri_path.vlan_control |= 799 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED | 800 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED; 801 } 802 803 qpc->pri_path.fvl_rx |= MLX4_FVL_RX_FORCE_ETH_VLAN; 804 qpc->pri_path.vlan_index = vp_oper->vlan_idx; 805 qpc->pri_path.fl |= MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN; 806 qpc->pri_path.feup |= MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN; 807 qpc->pri_path.sched_queue &= 0xC7; 808 qpc->pri_path.sched_queue |= (vp_oper->state.default_qos) << 3; 809 qpc->qos_vport = vp_oper->state.qos_vport; 810 } 811 if (vp_oper->state.spoofchk) { 812 qpc->pri_path.feup |= MLX4_FSM_FORCE_ETH_SRC_MAC; 813 qpc->pri_path.grh_mylmc = (0x80 & qpc->pri_path.grh_mylmc) + vp_oper->mac_idx; 814 } 815 out: 816 return err; 817 } 818 819 static int mpt_mask(struct mlx4_dev *dev) 820 { 821 return dev->caps.num_mpts - 1; 822 } 823 824 static void *find_res(struct mlx4_dev *dev, u64 res_id, 825 enum mlx4_resource type) 826 { 827 struct mlx4_priv *priv = mlx4_priv(dev); 828 829 return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type], 830 res_id); 831 } 832 833 static int get_res(struct mlx4_dev *dev, int slave, u64 res_id, 834 enum mlx4_resource type, 835 void *res) 836 { 837 struct res_common *r; 838 int err = 0; 839 840 spin_lock_irq(mlx4_tlock(dev)); 841 r = find_res(dev, res_id, type); 842 if (!r) { 843 err = -ENONET; 844 goto exit; 845 } 846 847 if (r->state == RES_ANY_BUSY) { 848 err = -EBUSY; 849 goto exit; 850 } 851 852 if (r->owner != slave) { 853 err = -EPERM; 854 goto exit; 855 } 856 857 r->from_state = r->state; 858 r->state = RES_ANY_BUSY; 859 860 if (res) 861 *((struct res_common **)res) = r; 862 863 exit: 864 spin_unlock_irq(mlx4_tlock(dev)); 865 return err; 866 } 867 868 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, 869 enum mlx4_resource type, 870 u64 res_id, int *slave) 871 { 872 873 struct res_common *r; 874 int err = -ENOENT; 875 int id = res_id; 876 877 if (type == RES_QP) 878 id &= 0x7fffff; 879 spin_lock(mlx4_tlock(dev)); 880 881 r = find_res(dev, id, type); 882 if (r) { 883 *slave = r->owner; 884 err = 0; 885 } 886 spin_unlock(mlx4_tlock(dev)); 887 888 return err; 889 } 890 891 static void put_res(struct mlx4_dev *dev, int slave, u64 res_id, 892 enum mlx4_resource type) 893 { 894 struct res_common *r; 895 896 spin_lock_irq(mlx4_tlock(dev)); 897 r = find_res(dev, res_id, type); 898 if (r) 899 r->state = r->from_state; 900 spin_unlock_irq(mlx4_tlock(dev)); 901 } 902 903 static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd, 904 u64 in_param, u64 *out_param, int port); 905 906 static int handle_existing_counter(struct mlx4_dev *dev, u8 slave, int port, 907 int counter_index) 908 { 909 struct res_common *r; 910 struct res_counter *counter; 911 int ret = 0; 912 913 if (counter_index == MLX4_SINK_COUNTER_INDEX(dev)) 914 return ret; 915 916 spin_lock_irq(mlx4_tlock(dev)); 917 r = find_res(dev, counter_index, RES_COUNTER); 918 if (!r || r->owner != slave) { 919 ret = -EINVAL; 920 } else { 921 counter = container_of(r, struct res_counter, com); 922 if (!counter->port) 923 counter->port = port; 924 } 925 926 spin_unlock_irq(mlx4_tlock(dev)); 927 return ret; 928 } 929 930 static int handle_unexisting_counter(struct mlx4_dev *dev, 931 struct mlx4_qp_context *qpc, u8 slave, 932 int port) 933 { 934 struct mlx4_priv *priv = mlx4_priv(dev); 935 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 936 struct res_common *tmp; 937 struct res_counter *counter; 938 u64 counter_idx = MLX4_SINK_COUNTER_INDEX(dev); 939 int err = 0; 940 941 spin_lock_irq(mlx4_tlock(dev)); 942 list_for_each_entry(tmp, 943 &tracker->slave_list[slave].res_list[RES_COUNTER], 944 list) { 945 counter = container_of(tmp, struct res_counter, com); 946 if (port == counter->port) { 947 qpc->pri_path.counter_index = counter->com.res_id; 948 spin_unlock_irq(mlx4_tlock(dev)); 949 return 0; 950 } 951 } 952 spin_unlock_irq(mlx4_tlock(dev)); 953 954 /* No existing counter, need to allocate a new counter */ 955 err = counter_alloc_res(dev, slave, RES_OP_RESERVE, 0, 0, &counter_idx, 956 port); 957 if (err == -ENOENT) { 958 err = 0; 959 } else if (err && err != -ENOSPC) { 960 mlx4_err(dev, "%s: failed to create new counter for slave %d err %d\n", 961 __func__, slave, err); 962 } else { 963 qpc->pri_path.counter_index = counter_idx; 964 mlx4_dbg(dev, "%s: alloc new counter for slave %d index %d\n", 965 __func__, slave, qpc->pri_path.counter_index); 966 err = 0; 967 } 968 969 return err; 970 } 971 972 static int handle_counter(struct mlx4_dev *dev, struct mlx4_qp_context *qpc, 973 u8 slave, int port) 974 { 975 if (qpc->pri_path.counter_index != MLX4_SINK_COUNTER_INDEX(dev)) 976 return handle_existing_counter(dev, slave, port, 977 qpc->pri_path.counter_index); 978 979 return handle_unexisting_counter(dev, qpc, slave, port); 980 } 981 982 static struct res_common *alloc_qp_tr(int id) 983 { 984 struct res_qp *ret; 985 986 ret = kzalloc(sizeof *ret, GFP_KERNEL); 987 if (!ret) 988 return NULL; 989 990 ret->com.res_id = id; 991 ret->com.state = RES_QP_RESERVED; 992 ret->local_qpn = id; 993 INIT_LIST_HEAD(&ret->mcg_list); 994 spin_lock_init(&ret->mcg_spl); 995 atomic_set(&ret->ref_count, 0); 996 997 return &ret->com; 998 } 999 1000 static struct res_common *alloc_mtt_tr(int id, int order) 1001 { 1002 struct res_mtt *ret; 1003 1004 ret = kzalloc(sizeof *ret, GFP_KERNEL); 1005 if (!ret) 1006 return NULL; 1007 1008 ret->com.res_id = id; 1009 ret->order = order; 1010 ret->com.state = RES_MTT_ALLOCATED; 1011 atomic_set(&ret->ref_count, 0); 1012 1013 return &ret->com; 1014 } 1015 1016 static struct res_common *alloc_mpt_tr(int id, int key) 1017 { 1018 struct res_mpt *ret; 1019 1020 ret = kzalloc(sizeof *ret, GFP_KERNEL); 1021 if (!ret) 1022 return NULL; 1023 1024 ret->com.res_id = id; 1025 ret->com.state = RES_MPT_RESERVED; 1026 ret->key = key; 1027 1028 return &ret->com; 1029 } 1030 1031 static struct res_common *alloc_eq_tr(int id) 1032 { 1033 struct res_eq *ret; 1034 1035 ret = kzalloc(sizeof *ret, GFP_KERNEL); 1036 if (!ret) 1037 return NULL; 1038 1039 ret->com.res_id = id; 1040 ret->com.state = RES_EQ_RESERVED; 1041 1042 return &ret->com; 1043 } 1044 1045 static struct res_common *alloc_cq_tr(int id) 1046 { 1047 struct res_cq *ret; 1048 1049 ret = kzalloc(sizeof *ret, GFP_KERNEL); 1050 if (!ret) 1051 return NULL; 1052 1053 ret->com.res_id = id; 1054 ret->com.state = RES_CQ_ALLOCATED; 1055 atomic_set(&ret->ref_count, 0); 1056 1057 return &ret->com; 1058 } 1059 1060 static struct res_common *alloc_srq_tr(int id) 1061 { 1062 struct res_srq *ret; 1063 1064 ret = kzalloc(sizeof *ret, GFP_KERNEL); 1065 if (!ret) 1066 return NULL; 1067 1068 ret->com.res_id = id; 1069 ret->com.state = RES_SRQ_ALLOCATED; 1070 atomic_set(&ret->ref_count, 0); 1071 1072 return &ret->com; 1073 } 1074 1075 static struct res_common *alloc_counter_tr(int id, int port) 1076 { 1077 struct res_counter *ret; 1078 1079 ret = kzalloc(sizeof *ret, GFP_KERNEL); 1080 if (!ret) 1081 return NULL; 1082 1083 ret->com.res_id = id; 1084 ret->com.state = RES_COUNTER_ALLOCATED; 1085 ret->port = port; 1086 1087 return &ret->com; 1088 } 1089 1090 static struct res_common *alloc_xrcdn_tr(int id) 1091 { 1092 struct res_xrcdn *ret; 1093 1094 ret = kzalloc(sizeof *ret, GFP_KERNEL); 1095 if (!ret) 1096 return NULL; 1097 1098 ret->com.res_id = id; 1099 ret->com.state = RES_XRCD_ALLOCATED; 1100 1101 return &ret->com; 1102 } 1103 1104 static struct res_common *alloc_fs_rule_tr(u64 id, int qpn) 1105 { 1106 struct res_fs_rule *ret; 1107 1108 ret = kzalloc(sizeof *ret, GFP_KERNEL); 1109 if (!ret) 1110 return NULL; 1111 1112 ret->com.res_id = id; 1113 ret->com.state = RES_FS_RULE_ALLOCATED; 1114 ret->qpn = qpn; 1115 return &ret->com; 1116 } 1117 1118 static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave, 1119 int extra) 1120 { 1121 struct res_common *ret; 1122 1123 switch (type) { 1124 case RES_QP: 1125 ret = alloc_qp_tr(id); 1126 break; 1127 case RES_MPT: 1128 ret = alloc_mpt_tr(id, extra); 1129 break; 1130 case RES_MTT: 1131 ret = alloc_mtt_tr(id, extra); 1132 break; 1133 case RES_EQ: 1134 ret = alloc_eq_tr(id); 1135 break; 1136 case RES_CQ: 1137 ret = alloc_cq_tr(id); 1138 break; 1139 case RES_SRQ: 1140 ret = alloc_srq_tr(id); 1141 break; 1142 case RES_MAC: 1143 pr_err("implementation missing\n"); 1144 return NULL; 1145 case RES_COUNTER: 1146 ret = alloc_counter_tr(id, extra); 1147 break; 1148 case RES_XRCD: 1149 ret = alloc_xrcdn_tr(id); 1150 break; 1151 case RES_FS_RULE: 1152 ret = alloc_fs_rule_tr(id, extra); 1153 break; 1154 default: 1155 return NULL; 1156 } 1157 if (ret) 1158 ret->owner = slave; 1159 1160 return ret; 1161 } 1162 1163 int mlx4_calc_vf_counters(struct mlx4_dev *dev, int slave, int port, 1164 struct mlx4_counter *data) 1165 { 1166 struct mlx4_priv *priv = mlx4_priv(dev); 1167 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 1168 struct res_common *tmp; 1169 struct res_counter *counter; 1170 int *counters_arr; 1171 int i = 0, err = 0; 1172 1173 memset(data, 0, sizeof(*data)); 1174 1175 counters_arr = kmalloc_array(dev->caps.max_counters, 1176 sizeof(*counters_arr), GFP_KERNEL); 1177 if (!counters_arr) 1178 return -ENOMEM; 1179 1180 spin_lock_irq(mlx4_tlock(dev)); 1181 list_for_each_entry(tmp, 1182 &tracker->slave_list[slave].res_list[RES_COUNTER], 1183 list) { 1184 counter = container_of(tmp, struct res_counter, com); 1185 if (counter->port == port) { 1186 counters_arr[i] = (int)tmp->res_id; 1187 i++; 1188 } 1189 } 1190 spin_unlock_irq(mlx4_tlock(dev)); 1191 counters_arr[i] = -1; 1192 1193 i = 0; 1194 1195 while (counters_arr[i] != -1) { 1196 err = mlx4_get_counter_stats(dev, counters_arr[i], data, 1197 0); 1198 if (err) { 1199 memset(data, 0, sizeof(*data)); 1200 goto table_changed; 1201 } 1202 i++; 1203 } 1204 1205 table_changed: 1206 kfree(counters_arr); 1207 return 0; 1208 } 1209 1210 static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count, 1211 enum mlx4_resource type, int extra) 1212 { 1213 int i; 1214 int err; 1215 struct mlx4_priv *priv = mlx4_priv(dev); 1216 struct res_common **res_arr; 1217 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 1218 struct rb_root *root = &tracker->res_tree[type]; 1219 1220 res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL); 1221 if (!res_arr) 1222 return -ENOMEM; 1223 1224 for (i = 0; i < count; ++i) { 1225 res_arr[i] = alloc_tr(base + i, type, slave, extra); 1226 if (!res_arr[i]) { 1227 for (--i; i >= 0; --i) 1228 kfree(res_arr[i]); 1229 1230 kfree(res_arr); 1231 return -ENOMEM; 1232 } 1233 } 1234 1235 spin_lock_irq(mlx4_tlock(dev)); 1236 for (i = 0; i < count; ++i) { 1237 if (find_res(dev, base + i, type)) { 1238 err = -EEXIST; 1239 goto undo; 1240 } 1241 err = res_tracker_insert(root, res_arr[i]); 1242 if (err) 1243 goto undo; 1244 list_add_tail(&res_arr[i]->list, 1245 &tracker->slave_list[slave].res_list[type]); 1246 } 1247 spin_unlock_irq(mlx4_tlock(dev)); 1248 kfree(res_arr); 1249 1250 return 0; 1251 1252 undo: 1253 for (--i; i >= 0; --i) { 1254 rb_erase(&res_arr[i]->node, root); 1255 list_del_init(&res_arr[i]->list); 1256 } 1257 1258 spin_unlock_irq(mlx4_tlock(dev)); 1259 1260 for (i = 0; i < count; ++i) 1261 kfree(res_arr[i]); 1262 1263 kfree(res_arr); 1264 1265 return err; 1266 } 1267 1268 static int remove_qp_ok(struct res_qp *res) 1269 { 1270 if (res->com.state == RES_QP_BUSY || atomic_read(&res->ref_count) || 1271 !list_empty(&res->mcg_list)) { 1272 pr_err("resource tracker: fail to remove qp, state %d, ref_count %d\n", 1273 res->com.state, atomic_read(&res->ref_count)); 1274 return -EBUSY; 1275 } else if (res->com.state != RES_QP_RESERVED) { 1276 return -EPERM; 1277 } 1278 1279 return 0; 1280 } 1281 1282 static int remove_mtt_ok(struct res_mtt *res, int order) 1283 { 1284 if (res->com.state == RES_MTT_BUSY || 1285 atomic_read(&res->ref_count)) { 1286 pr_devel("%s-%d: state %s, ref_count %d\n", 1287 __func__, __LINE__, 1288 mtt_states_str(res->com.state), 1289 atomic_read(&res->ref_count)); 1290 return -EBUSY; 1291 } else if (res->com.state != RES_MTT_ALLOCATED) 1292 return -EPERM; 1293 else if (res->order != order) 1294 return -EINVAL; 1295 1296 return 0; 1297 } 1298 1299 static int remove_mpt_ok(struct res_mpt *res) 1300 { 1301 if (res->com.state == RES_MPT_BUSY) 1302 return -EBUSY; 1303 else if (res->com.state != RES_MPT_RESERVED) 1304 return -EPERM; 1305 1306 return 0; 1307 } 1308 1309 static int remove_eq_ok(struct res_eq *res) 1310 { 1311 if (res->com.state == RES_MPT_BUSY) 1312 return -EBUSY; 1313 else if (res->com.state != RES_MPT_RESERVED) 1314 return -EPERM; 1315 1316 return 0; 1317 } 1318 1319 static int remove_counter_ok(struct res_counter *res) 1320 { 1321 if (res->com.state == RES_COUNTER_BUSY) 1322 return -EBUSY; 1323 else if (res->com.state != RES_COUNTER_ALLOCATED) 1324 return -EPERM; 1325 1326 return 0; 1327 } 1328 1329 static int remove_xrcdn_ok(struct res_xrcdn *res) 1330 { 1331 if (res->com.state == RES_XRCD_BUSY) 1332 return -EBUSY; 1333 else if (res->com.state != RES_XRCD_ALLOCATED) 1334 return -EPERM; 1335 1336 return 0; 1337 } 1338 1339 static int remove_fs_rule_ok(struct res_fs_rule *res) 1340 { 1341 if (res->com.state == RES_FS_RULE_BUSY) 1342 return -EBUSY; 1343 else if (res->com.state != RES_FS_RULE_ALLOCATED) 1344 return -EPERM; 1345 1346 return 0; 1347 } 1348 1349 static int remove_cq_ok(struct res_cq *res) 1350 { 1351 if (res->com.state == RES_CQ_BUSY) 1352 return -EBUSY; 1353 else if (res->com.state != RES_CQ_ALLOCATED) 1354 return -EPERM; 1355 1356 return 0; 1357 } 1358 1359 static int remove_srq_ok(struct res_srq *res) 1360 { 1361 if (res->com.state == RES_SRQ_BUSY) 1362 return -EBUSY; 1363 else if (res->com.state != RES_SRQ_ALLOCATED) 1364 return -EPERM; 1365 1366 return 0; 1367 } 1368 1369 static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra) 1370 { 1371 switch (type) { 1372 case RES_QP: 1373 return remove_qp_ok((struct res_qp *)res); 1374 case RES_CQ: 1375 return remove_cq_ok((struct res_cq *)res); 1376 case RES_SRQ: 1377 return remove_srq_ok((struct res_srq *)res); 1378 case RES_MPT: 1379 return remove_mpt_ok((struct res_mpt *)res); 1380 case RES_MTT: 1381 return remove_mtt_ok((struct res_mtt *)res, extra); 1382 case RES_MAC: 1383 return -ENOSYS; 1384 case RES_EQ: 1385 return remove_eq_ok((struct res_eq *)res); 1386 case RES_COUNTER: 1387 return remove_counter_ok((struct res_counter *)res); 1388 case RES_XRCD: 1389 return remove_xrcdn_ok((struct res_xrcdn *)res); 1390 case RES_FS_RULE: 1391 return remove_fs_rule_ok((struct res_fs_rule *)res); 1392 default: 1393 return -EINVAL; 1394 } 1395 } 1396 1397 static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count, 1398 enum mlx4_resource type, int extra) 1399 { 1400 u64 i; 1401 int err; 1402 struct mlx4_priv *priv = mlx4_priv(dev); 1403 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 1404 struct res_common *r; 1405 1406 spin_lock_irq(mlx4_tlock(dev)); 1407 for (i = base; i < base + count; ++i) { 1408 r = res_tracker_lookup(&tracker->res_tree[type], i); 1409 if (!r) { 1410 err = -ENOENT; 1411 goto out; 1412 } 1413 if (r->owner != slave) { 1414 err = -EPERM; 1415 goto out; 1416 } 1417 err = remove_ok(r, type, extra); 1418 if (err) 1419 goto out; 1420 } 1421 1422 for (i = base; i < base + count; ++i) { 1423 r = res_tracker_lookup(&tracker->res_tree[type], i); 1424 rb_erase(&r->node, &tracker->res_tree[type]); 1425 list_del(&r->list); 1426 kfree(r); 1427 } 1428 err = 0; 1429 1430 out: 1431 spin_unlock_irq(mlx4_tlock(dev)); 1432 1433 return err; 1434 } 1435 1436 static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn, 1437 enum res_qp_states state, struct res_qp **qp, 1438 int alloc) 1439 { 1440 struct mlx4_priv *priv = mlx4_priv(dev); 1441 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 1442 struct res_qp *r; 1443 int err = 0; 1444 1445 spin_lock_irq(mlx4_tlock(dev)); 1446 r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn); 1447 if (!r) 1448 err = -ENOENT; 1449 else if (r->com.owner != slave) 1450 err = -EPERM; 1451 else { 1452 switch (state) { 1453 case RES_QP_BUSY: 1454 mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n", 1455 __func__, r->com.res_id); 1456 err = -EBUSY; 1457 break; 1458 1459 case RES_QP_RESERVED: 1460 if (r->com.state == RES_QP_MAPPED && !alloc) 1461 break; 1462 1463 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id); 1464 err = -EINVAL; 1465 break; 1466 1467 case RES_QP_MAPPED: 1468 if ((r->com.state == RES_QP_RESERVED && alloc) || 1469 r->com.state == RES_QP_HW) 1470 break; 1471 else { 1472 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", 1473 r->com.res_id); 1474 err = -EINVAL; 1475 } 1476 1477 break; 1478 1479 case RES_QP_HW: 1480 if (r->com.state != RES_QP_MAPPED) 1481 err = -EINVAL; 1482 break; 1483 default: 1484 err = -EINVAL; 1485 } 1486 1487 if (!err) { 1488 r->com.from_state = r->com.state; 1489 r->com.to_state = state; 1490 r->com.state = RES_QP_BUSY; 1491 if (qp) 1492 *qp = r; 1493 } 1494 } 1495 1496 spin_unlock_irq(mlx4_tlock(dev)); 1497 1498 return err; 1499 } 1500 1501 static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index, 1502 enum res_mpt_states state, struct res_mpt **mpt) 1503 { 1504 struct mlx4_priv *priv = mlx4_priv(dev); 1505 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 1506 struct res_mpt *r; 1507 int err = 0; 1508 1509 spin_lock_irq(mlx4_tlock(dev)); 1510 r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index); 1511 if (!r) 1512 err = -ENOENT; 1513 else if (r->com.owner != slave) 1514 err = -EPERM; 1515 else { 1516 switch (state) { 1517 case RES_MPT_BUSY: 1518 err = -EINVAL; 1519 break; 1520 1521 case RES_MPT_RESERVED: 1522 if (r->com.state != RES_MPT_MAPPED) 1523 err = -EINVAL; 1524 break; 1525 1526 case RES_MPT_MAPPED: 1527 if (r->com.state != RES_MPT_RESERVED && 1528 r->com.state != RES_MPT_HW) 1529 err = -EINVAL; 1530 break; 1531 1532 case RES_MPT_HW: 1533 if (r->com.state != RES_MPT_MAPPED) 1534 err = -EINVAL; 1535 break; 1536 default: 1537 err = -EINVAL; 1538 } 1539 1540 if (!err) { 1541 r->com.from_state = r->com.state; 1542 r->com.to_state = state; 1543 r->com.state = RES_MPT_BUSY; 1544 if (mpt) 1545 *mpt = r; 1546 } 1547 } 1548 1549 spin_unlock_irq(mlx4_tlock(dev)); 1550 1551 return err; 1552 } 1553 1554 static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index, 1555 enum res_eq_states state, struct res_eq **eq) 1556 { 1557 struct mlx4_priv *priv = mlx4_priv(dev); 1558 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 1559 struct res_eq *r; 1560 int err = 0; 1561 1562 spin_lock_irq(mlx4_tlock(dev)); 1563 r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index); 1564 if (!r) 1565 err = -ENOENT; 1566 else if (r->com.owner != slave) 1567 err = -EPERM; 1568 else { 1569 switch (state) { 1570 case RES_EQ_BUSY: 1571 err = -EINVAL; 1572 break; 1573 1574 case RES_EQ_RESERVED: 1575 if (r->com.state != RES_EQ_HW) 1576 err = -EINVAL; 1577 break; 1578 1579 case RES_EQ_HW: 1580 if (r->com.state != RES_EQ_RESERVED) 1581 err = -EINVAL; 1582 break; 1583 1584 default: 1585 err = -EINVAL; 1586 } 1587 1588 if (!err) { 1589 r->com.from_state = r->com.state; 1590 r->com.to_state = state; 1591 r->com.state = RES_EQ_BUSY; 1592 if (eq) 1593 *eq = r; 1594 } 1595 } 1596 1597 spin_unlock_irq(mlx4_tlock(dev)); 1598 1599 return err; 1600 } 1601 1602 static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn, 1603 enum res_cq_states state, struct res_cq **cq) 1604 { 1605 struct mlx4_priv *priv = mlx4_priv(dev); 1606 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 1607 struct res_cq *r; 1608 int err; 1609 1610 spin_lock_irq(mlx4_tlock(dev)); 1611 r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn); 1612 if (!r) { 1613 err = -ENOENT; 1614 } else if (r->com.owner != slave) { 1615 err = -EPERM; 1616 } else if (state == RES_CQ_ALLOCATED) { 1617 if (r->com.state != RES_CQ_HW) 1618 err = -EINVAL; 1619 else if (atomic_read(&r->ref_count)) 1620 err = -EBUSY; 1621 else 1622 err = 0; 1623 } else if (state != RES_CQ_HW || r->com.state != RES_CQ_ALLOCATED) { 1624 err = -EINVAL; 1625 } else { 1626 err = 0; 1627 } 1628 1629 if (!err) { 1630 r->com.from_state = r->com.state; 1631 r->com.to_state = state; 1632 r->com.state = RES_CQ_BUSY; 1633 if (cq) 1634 *cq = r; 1635 } 1636 1637 spin_unlock_irq(mlx4_tlock(dev)); 1638 1639 return err; 1640 } 1641 1642 static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index, 1643 enum res_srq_states state, struct res_srq **srq) 1644 { 1645 struct mlx4_priv *priv = mlx4_priv(dev); 1646 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 1647 struct res_srq *r; 1648 int err = 0; 1649 1650 spin_lock_irq(mlx4_tlock(dev)); 1651 r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index); 1652 if (!r) { 1653 err = -ENOENT; 1654 } else if (r->com.owner != slave) { 1655 err = -EPERM; 1656 } else if (state == RES_SRQ_ALLOCATED) { 1657 if (r->com.state != RES_SRQ_HW) 1658 err = -EINVAL; 1659 else if (atomic_read(&r->ref_count)) 1660 err = -EBUSY; 1661 } else if (state != RES_SRQ_HW || r->com.state != RES_SRQ_ALLOCATED) { 1662 err = -EINVAL; 1663 } 1664 1665 if (!err) { 1666 r->com.from_state = r->com.state; 1667 r->com.to_state = state; 1668 r->com.state = RES_SRQ_BUSY; 1669 if (srq) 1670 *srq = r; 1671 } 1672 1673 spin_unlock_irq(mlx4_tlock(dev)); 1674 1675 return err; 1676 } 1677 1678 static void res_abort_move(struct mlx4_dev *dev, int slave, 1679 enum mlx4_resource type, int id) 1680 { 1681 struct mlx4_priv *priv = mlx4_priv(dev); 1682 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 1683 struct res_common *r; 1684 1685 spin_lock_irq(mlx4_tlock(dev)); 1686 r = res_tracker_lookup(&tracker->res_tree[type], id); 1687 if (r && (r->owner == slave)) 1688 r->state = r->from_state; 1689 spin_unlock_irq(mlx4_tlock(dev)); 1690 } 1691 1692 static void res_end_move(struct mlx4_dev *dev, int slave, 1693 enum mlx4_resource type, int id) 1694 { 1695 struct mlx4_priv *priv = mlx4_priv(dev); 1696 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 1697 struct res_common *r; 1698 1699 spin_lock_irq(mlx4_tlock(dev)); 1700 r = res_tracker_lookup(&tracker->res_tree[type], id); 1701 if (r && (r->owner == slave)) 1702 r->state = r->to_state; 1703 spin_unlock_irq(mlx4_tlock(dev)); 1704 } 1705 1706 static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn) 1707 { 1708 return mlx4_is_qp_reserved(dev, qpn) && 1709 (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn)); 1710 } 1711 1712 static int fw_reserved(struct mlx4_dev *dev, int qpn) 1713 { 1714 return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 1715 } 1716 1717 static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd, 1718 u64 in_param, u64 *out_param) 1719 { 1720 int err; 1721 int count; 1722 int align; 1723 int base; 1724 int qpn; 1725 u8 flags; 1726 1727 switch (op) { 1728 case RES_OP_RESERVE: 1729 count = get_param_l(&in_param) & 0xffffff; 1730 /* Turn off all unsupported QP allocation flags that the 1731 * slave tries to set. 1732 */ 1733 flags = (get_param_l(&in_param) >> 24) & dev->caps.alloc_res_qp_mask; 1734 align = get_param_h(&in_param); 1735 err = mlx4_grant_resource(dev, slave, RES_QP, count, 0); 1736 if (err) 1737 return err; 1738 1739 err = __mlx4_qp_reserve_range(dev, count, align, &base, flags); 1740 if (err) { 1741 mlx4_release_resource(dev, slave, RES_QP, count, 0); 1742 return err; 1743 } 1744 1745 err = add_res_range(dev, slave, base, count, RES_QP, 0); 1746 if (err) { 1747 mlx4_release_resource(dev, slave, RES_QP, count, 0); 1748 __mlx4_qp_release_range(dev, base, count); 1749 return err; 1750 } 1751 set_param_l(out_param, base); 1752 break; 1753 case RES_OP_MAP_ICM: 1754 qpn = get_param_l(&in_param) & 0x7fffff; 1755 if (valid_reserved(dev, slave, qpn)) { 1756 err = add_res_range(dev, slave, qpn, 1, RES_QP, 0); 1757 if (err) 1758 return err; 1759 } 1760 1761 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, 1762 NULL, 1); 1763 if (err) 1764 return err; 1765 1766 if (!fw_reserved(dev, qpn)) { 1767 err = __mlx4_qp_alloc_icm(dev, qpn, GFP_KERNEL); 1768 if (err) { 1769 res_abort_move(dev, slave, RES_QP, qpn); 1770 return err; 1771 } 1772 } 1773 1774 res_end_move(dev, slave, RES_QP, qpn); 1775 break; 1776 1777 default: 1778 err = -EINVAL; 1779 break; 1780 } 1781 return err; 1782 } 1783 1784 static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd, 1785 u64 in_param, u64 *out_param) 1786 { 1787 int err = -EINVAL; 1788 int base; 1789 int order; 1790 1791 if (op != RES_OP_RESERVE_AND_MAP) 1792 return err; 1793 1794 order = get_param_l(&in_param); 1795 1796 err = mlx4_grant_resource(dev, slave, RES_MTT, 1 << order, 0); 1797 if (err) 1798 return err; 1799 1800 base = __mlx4_alloc_mtt_range(dev, order); 1801 if (base == -1) { 1802 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0); 1803 return -ENOMEM; 1804 } 1805 1806 err = add_res_range(dev, slave, base, 1, RES_MTT, order); 1807 if (err) { 1808 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0); 1809 __mlx4_free_mtt_range(dev, base, order); 1810 } else { 1811 set_param_l(out_param, base); 1812 } 1813 1814 return err; 1815 } 1816 1817 static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd, 1818 u64 in_param, u64 *out_param) 1819 { 1820 int err = -EINVAL; 1821 int index; 1822 int id; 1823 struct res_mpt *mpt; 1824 1825 switch (op) { 1826 case RES_OP_RESERVE: 1827 err = mlx4_grant_resource(dev, slave, RES_MPT, 1, 0); 1828 if (err) 1829 break; 1830 1831 index = __mlx4_mpt_reserve(dev); 1832 if (index == -1) { 1833 mlx4_release_resource(dev, slave, RES_MPT, 1, 0); 1834 break; 1835 } 1836 id = index & mpt_mask(dev); 1837 1838 err = add_res_range(dev, slave, id, 1, RES_MPT, index); 1839 if (err) { 1840 mlx4_release_resource(dev, slave, RES_MPT, 1, 0); 1841 __mlx4_mpt_release(dev, index); 1842 break; 1843 } 1844 set_param_l(out_param, index); 1845 break; 1846 case RES_OP_MAP_ICM: 1847 index = get_param_l(&in_param); 1848 id = index & mpt_mask(dev); 1849 err = mr_res_start_move_to(dev, slave, id, 1850 RES_MPT_MAPPED, &mpt); 1851 if (err) 1852 return err; 1853 1854 err = __mlx4_mpt_alloc_icm(dev, mpt->key, GFP_KERNEL); 1855 if (err) { 1856 res_abort_move(dev, slave, RES_MPT, id); 1857 return err; 1858 } 1859 1860 res_end_move(dev, slave, RES_MPT, id); 1861 break; 1862 } 1863 return err; 1864 } 1865 1866 static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd, 1867 u64 in_param, u64 *out_param) 1868 { 1869 int cqn; 1870 int err; 1871 1872 switch (op) { 1873 case RES_OP_RESERVE_AND_MAP: 1874 err = mlx4_grant_resource(dev, slave, RES_CQ, 1, 0); 1875 if (err) 1876 break; 1877 1878 err = __mlx4_cq_alloc_icm(dev, &cqn); 1879 if (err) { 1880 mlx4_release_resource(dev, slave, RES_CQ, 1, 0); 1881 break; 1882 } 1883 1884 err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0); 1885 if (err) { 1886 mlx4_release_resource(dev, slave, RES_CQ, 1, 0); 1887 __mlx4_cq_free_icm(dev, cqn); 1888 break; 1889 } 1890 1891 set_param_l(out_param, cqn); 1892 break; 1893 1894 default: 1895 err = -EINVAL; 1896 } 1897 1898 return err; 1899 } 1900 1901 static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd, 1902 u64 in_param, u64 *out_param) 1903 { 1904 int srqn; 1905 int err; 1906 1907 switch (op) { 1908 case RES_OP_RESERVE_AND_MAP: 1909 err = mlx4_grant_resource(dev, slave, RES_SRQ, 1, 0); 1910 if (err) 1911 break; 1912 1913 err = __mlx4_srq_alloc_icm(dev, &srqn); 1914 if (err) { 1915 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0); 1916 break; 1917 } 1918 1919 err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0); 1920 if (err) { 1921 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0); 1922 __mlx4_srq_free_icm(dev, srqn); 1923 break; 1924 } 1925 1926 set_param_l(out_param, srqn); 1927 break; 1928 1929 default: 1930 err = -EINVAL; 1931 } 1932 1933 return err; 1934 } 1935 1936 static int mac_find_smac_ix_in_slave(struct mlx4_dev *dev, int slave, int port, 1937 u8 smac_index, u64 *mac) 1938 { 1939 struct mlx4_priv *priv = mlx4_priv(dev); 1940 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 1941 struct list_head *mac_list = 1942 &tracker->slave_list[slave].res_list[RES_MAC]; 1943 struct mac_res *res, *tmp; 1944 1945 list_for_each_entry_safe(res, tmp, mac_list, list) { 1946 if (res->smac_index == smac_index && res->port == (u8) port) { 1947 *mac = res->mac; 1948 return 0; 1949 } 1950 } 1951 return -ENOENT; 1952 } 1953 1954 static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port, u8 smac_index) 1955 { 1956 struct mlx4_priv *priv = mlx4_priv(dev); 1957 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 1958 struct list_head *mac_list = 1959 &tracker->slave_list[slave].res_list[RES_MAC]; 1960 struct mac_res *res, *tmp; 1961 1962 list_for_each_entry_safe(res, tmp, mac_list, list) { 1963 if (res->mac == mac && res->port == (u8) port) { 1964 /* mac found. update ref count */ 1965 ++res->ref_count; 1966 return 0; 1967 } 1968 } 1969 1970 if (mlx4_grant_resource(dev, slave, RES_MAC, 1, port)) 1971 return -EINVAL; 1972 res = kzalloc(sizeof *res, GFP_KERNEL); 1973 if (!res) { 1974 mlx4_release_resource(dev, slave, RES_MAC, 1, port); 1975 return -ENOMEM; 1976 } 1977 res->mac = mac; 1978 res->port = (u8) port; 1979 res->smac_index = smac_index; 1980 res->ref_count = 1; 1981 list_add_tail(&res->list, 1982 &tracker->slave_list[slave].res_list[RES_MAC]); 1983 return 0; 1984 } 1985 1986 static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac, 1987 int port) 1988 { 1989 struct mlx4_priv *priv = mlx4_priv(dev); 1990 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 1991 struct list_head *mac_list = 1992 &tracker->slave_list[slave].res_list[RES_MAC]; 1993 struct mac_res *res, *tmp; 1994 1995 list_for_each_entry_safe(res, tmp, mac_list, list) { 1996 if (res->mac == mac && res->port == (u8) port) { 1997 if (!--res->ref_count) { 1998 list_del(&res->list); 1999 mlx4_release_resource(dev, slave, RES_MAC, 1, port); 2000 kfree(res); 2001 } 2002 break; 2003 } 2004 } 2005 } 2006 2007 static void rem_slave_macs(struct mlx4_dev *dev, int slave) 2008 { 2009 struct mlx4_priv *priv = mlx4_priv(dev); 2010 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 2011 struct list_head *mac_list = 2012 &tracker->slave_list[slave].res_list[RES_MAC]; 2013 struct mac_res *res, *tmp; 2014 int i; 2015 2016 list_for_each_entry_safe(res, tmp, mac_list, list) { 2017 list_del(&res->list); 2018 /* dereference the mac the num times the slave referenced it */ 2019 for (i = 0; i < res->ref_count; i++) 2020 __mlx4_unregister_mac(dev, res->port, res->mac); 2021 mlx4_release_resource(dev, slave, RES_MAC, 1, res->port); 2022 kfree(res); 2023 } 2024 } 2025 2026 static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd, 2027 u64 in_param, u64 *out_param, int in_port) 2028 { 2029 int err = -EINVAL; 2030 int port; 2031 u64 mac; 2032 u8 smac_index; 2033 2034 if (op != RES_OP_RESERVE_AND_MAP) 2035 return err; 2036 2037 port = !in_port ? get_param_l(out_param) : in_port; 2038 port = mlx4_slave_convert_port( 2039 dev, slave, port); 2040 2041 if (port < 0) 2042 return -EINVAL; 2043 mac = in_param; 2044 2045 err = __mlx4_register_mac(dev, port, mac); 2046 if (err >= 0) { 2047 smac_index = err; 2048 set_param_l(out_param, err); 2049 err = 0; 2050 } 2051 2052 if (!err) { 2053 err = mac_add_to_slave(dev, slave, mac, port, smac_index); 2054 if (err) 2055 __mlx4_unregister_mac(dev, port, mac); 2056 } 2057 return err; 2058 } 2059 2060 static int vlan_add_to_slave(struct mlx4_dev *dev, int slave, u16 vlan, 2061 int port, int vlan_index) 2062 { 2063 struct mlx4_priv *priv = mlx4_priv(dev); 2064 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 2065 struct list_head *vlan_list = 2066 &tracker->slave_list[slave].res_list[RES_VLAN]; 2067 struct vlan_res *res, *tmp; 2068 2069 list_for_each_entry_safe(res, tmp, vlan_list, list) { 2070 if (res->vlan == vlan && res->port == (u8) port) { 2071 /* vlan found. update ref count */ 2072 ++res->ref_count; 2073 return 0; 2074 } 2075 } 2076 2077 if (mlx4_grant_resource(dev, slave, RES_VLAN, 1, port)) 2078 return -EINVAL; 2079 res = kzalloc(sizeof(*res), GFP_KERNEL); 2080 if (!res) { 2081 mlx4_release_resource(dev, slave, RES_VLAN, 1, port); 2082 return -ENOMEM; 2083 } 2084 res->vlan = vlan; 2085 res->port = (u8) port; 2086 res->vlan_index = vlan_index; 2087 res->ref_count = 1; 2088 list_add_tail(&res->list, 2089 &tracker->slave_list[slave].res_list[RES_VLAN]); 2090 return 0; 2091 } 2092 2093 2094 static void vlan_del_from_slave(struct mlx4_dev *dev, int slave, u16 vlan, 2095 int port) 2096 { 2097 struct mlx4_priv *priv = mlx4_priv(dev); 2098 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 2099 struct list_head *vlan_list = 2100 &tracker->slave_list[slave].res_list[RES_VLAN]; 2101 struct vlan_res *res, *tmp; 2102 2103 list_for_each_entry_safe(res, tmp, vlan_list, list) { 2104 if (res->vlan == vlan && res->port == (u8) port) { 2105 if (!--res->ref_count) { 2106 list_del(&res->list); 2107 mlx4_release_resource(dev, slave, RES_VLAN, 2108 1, port); 2109 kfree(res); 2110 } 2111 break; 2112 } 2113 } 2114 } 2115 2116 static void rem_slave_vlans(struct mlx4_dev *dev, int slave) 2117 { 2118 struct mlx4_priv *priv = mlx4_priv(dev); 2119 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 2120 struct list_head *vlan_list = 2121 &tracker->slave_list[slave].res_list[RES_VLAN]; 2122 struct vlan_res *res, *tmp; 2123 int i; 2124 2125 list_for_each_entry_safe(res, tmp, vlan_list, list) { 2126 list_del(&res->list); 2127 /* dereference the vlan the num times the slave referenced it */ 2128 for (i = 0; i < res->ref_count; i++) 2129 __mlx4_unregister_vlan(dev, res->port, res->vlan); 2130 mlx4_release_resource(dev, slave, RES_VLAN, 1, res->port); 2131 kfree(res); 2132 } 2133 } 2134 2135 static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd, 2136 u64 in_param, u64 *out_param, int in_port) 2137 { 2138 struct mlx4_priv *priv = mlx4_priv(dev); 2139 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state; 2140 int err; 2141 u16 vlan; 2142 int vlan_index; 2143 int port; 2144 2145 port = !in_port ? get_param_l(out_param) : in_port; 2146 2147 if (!port || op != RES_OP_RESERVE_AND_MAP) 2148 return -EINVAL; 2149 2150 port = mlx4_slave_convert_port( 2151 dev, slave, port); 2152 2153 if (port < 0) 2154 return -EINVAL; 2155 /* upstream kernels had NOP for reg/unreg vlan. Continue this. */ 2156 if (!in_port && port > 0 && port <= dev->caps.num_ports) { 2157 slave_state[slave].old_vlan_api = true; 2158 return 0; 2159 } 2160 2161 vlan = (u16) in_param; 2162 2163 err = __mlx4_register_vlan(dev, port, vlan, &vlan_index); 2164 if (!err) { 2165 set_param_l(out_param, (u32) vlan_index); 2166 err = vlan_add_to_slave(dev, slave, vlan, port, vlan_index); 2167 if (err) 2168 __mlx4_unregister_vlan(dev, port, vlan); 2169 } 2170 return err; 2171 } 2172 2173 static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd, 2174 u64 in_param, u64 *out_param, int port) 2175 { 2176 u32 index; 2177 int err; 2178 2179 if (op != RES_OP_RESERVE) 2180 return -EINVAL; 2181 2182 err = mlx4_grant_resource(dev, slave, RES_COUNTER, 1, 0); 2183 if (err) 2184 return err; 2185 2186 err = __mlx4_counter_alloc(dev, &index); 2187 if (err) { 2188 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0); 2189 return err; 2190 } 2191 2192 err = add_res_range(dev, slave, index, 1, RES_COUNTER, port); 2193 if (err) { 2194 __mlx4_counter_free(dev, index); 2195 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0); 2196 } else { 2197 set_param_l(out_param, index); 2198 } 2199 2200 return err; 2201 } 2202 2203 static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd, 2204 u64 in_param, u64 *out_param) 2205 { 2206 u32 xrcdn; 2207 int err; 2208 2209 if (op != RES_OP_RESERVE) 2210 return -EINVAL; 2211 2212 err = __mlx4_xrcd_alloc(dev, &xrcdn); 2213 if (err) 2214 return err; 2215 2216 err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0); 2217 if (err) 2218 __mlx4_xrcd_free(dev, xrcdn); 2219 else 2220 set_param_l(out_param, xrcdn); 2221 2222 return err; 2223 } 2224 2225 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, 2226 struct mlx4_vhcr *vhcr, 2227 struct mlx4_cmd_mailbox *inbox, 2228 struct mlx4_cmd_mailbox *outbox, 2229 struct mlx4_cmd_info *cmd) 2230 { 2231 int err; 2232 int alop = vhcr->op_modifier; 2233 2234 switch (vhcr->in_modifier & 0xFF) { 2235 case RES_QP: 2236 err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop, 2237 vhcr->in_param, &vhcr->out_param); 2238 break; 2239 2240 case RES_MTT: 2241 err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop, 2242 vhcr->in_param, &vhcr->out_param); 2243 break; 2244 2245 case RES_MPT: 2246 err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop, 2247 vhcr->in_param, &vhcr->out_param); 2248 break; 2249 2250 case RES_CQ: 2251 err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop, 2252 vhcr->in_param, &vhcr->out_param); 2253 break; 2254 2255 case RES_SRQ: 2256 err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop, 2257 vhcr->in_param, &vhcr->out_param); 2258 break; 2259 2260 case RES_MAC: 2261 err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop, 2262 vhcr->in_param, &vhcr->out_param, 2263 (vhcr->in_modifier >> 8) & 0xFF); 2264 break; 2265 2266 case RES_VLAN: 2267 err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop, 2268 vhcr->in_param, &vhcr->out_param, 2269 (vhcr->in_modifier >> 8) & 0xFF); 2270 break; 2271 2272 case RES_COUNTER: 2273 err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop, 2274 vhcr->in_param, &vhcr->out_param, 0); 2275 break; 2276 2277 case RES_XRCD: 2278 err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop, 2279 vhcr->in_param, &vhcr->out_param); 2280 break; 2281 2282 default: 2283 err = -EINVAL; 2284 break; 2285 } 2286 2287 return err; 2288 } 2289 2290 static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd, 2291 u64 in_param) 2292 { 2293 int err; 2294 int count; 2295 int base; 2296 int qpn; 2297 2298 switch (op) { 2299 case RES_OP_RESERVE: 2300 base = get_param_l(&in_param) & 0x7fffff; 2301 count = get_param_h(&in_param); 2302 err = rem_res_range(dev, slave, base, count, RES_QP, 0); 2303 if (err) 2304 break; 2305 mlx4_release_resource(dev, slave, RES_QP, count, 0); 2306 __mlx4_qp_release_range(dev, base, count); 2307 break; 2308 case RES_OP_MAP_ICM: 2309 qpn = get_param_l(&in_param) & 0x7fffff; 2310 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED, 2311 NULL, 0); 2312 if (err) 2313 return err; 2314 2315 if (!fw_reserved(dev, qpn)) 2316 __mlx4_qp_free_icm(dev, qpn); 2317 2318 res_end_move(dev, slave, RES_QP, qpn); 2319 2320 if (valid_reserved(dev, slave, qpn)) 2321 err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0); 2322 break; 2323 default: 2324 err = -EINVAL; 2325 break; 2326 } 2327 return err; 2328 } 2329 2330 static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd, 2331 u64 in_param, u64 *out_param) 2332 { 2333 int err = -EINVAL; 2334 int base; 2335 int order; 2336 2337 if (op != RES_OP_RESERVE_AND_MAP) 2338 return err; 2339 2340 base = get_param_l(&in_param); 2341 order = get_param_h(&in_param); 2342 err = rem_res_range(dev, slave, base, 1, RES_MTT, order); 2343 if (!err) { 2344 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0); 2345 __mlx4_free_mtt_range(dev, base, order); 2346 } 2347 return err; 2348 } 2349 2350 static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd, 2351 u64 in_param) 2352 { 2353 int err = -EINVAL; 2354 int index; 2355 int id; 2356 struct res_mpt *mpt; 2357 2358 switch (op) { 2359 case RES_OP_RESERVE: 2360 index = get_param_l(&in_param); 2361 id = index & mpt_mask(dev); 2362 err = get_res(dev, slave, id, RES_MPT, &mpt); 2363 if (err) 2364 break; 2365 index = mpt->key; 2366 put_res(dev, slave, id, RES_MPT); 2367 2368 err = rem_res_range(dev, slave, id, 1, RES_MPT, 0); 2369 if (err) 2370 break; 2371 mlx4_release_resource(dev, slave, RES_MPT, 1, 0); 2372 __mlx4_mpt_release(dev, index); 2373 break; 2374 case RES_OP_MAP_ICM: 2375 index = get_param_l(&in_param); 2376 id = index & mpt_mask(dev); 2377 err = mr_res_start_move_to(dev, slave, id, 2378 RES_MPT_RESERVED, &mpt); 2379 if (err) 2380 return err; 2381 2382 __mlx4_mpt_free_icm(dev, mpt->key); 2383 res_end_move(dev, slave, RES_MPT, id); 2384 return err; 2385 break; 2386 default: 2387 err = -EINVAL; 2388 break; 2389 } 2390 return err; 2391 } 2392 2393 static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd, 2394 u64 in_param, u64 *out_param) 2395 { 2396 int cqn; 2397 int err; 2398 2399 switch (op) { 2400 case RES_OP_RESERVE_AND_MAP: 2401 cqn = get_param_l(&in_param); 2402 err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0); 2403 if (err) 2404 break; 2405 2406 mlx4_release_resource(dev, slave, RES_CQ, 1, 0); 2407 __mlx4_cq_free_icm(dev, cqn); 2408 break; 2409 2410 default: 2411 err = -EINVAL; 2412 break; 2413 } 2414 2415 return err; 2416 } 2417 2418 static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd, 2419 u64 in_param, u64 *out_param) 2420 { 2421 int srqn; 2422 int err; 2423 2424 switch (op) { 2425 case RES_OP_RESERVE_AND_MAP: 2426 srqn = get_param_l(&in_param); 2427 err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0); 2428 if (err) 2429 break; 2430 2431 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0); 2432 __mlx4_srq_free_icm(dev, srqn); 2433 break; 2434 2435 default: 2436 err = -EINVAL; 2437 break; 2438 } 2439 2440 return err; 2441 } 2442 2443 static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd, 2444 u64 in_param, u64 *out_param, int in_port) 2445 { 2446 int port; 2447 int err = 0; 2448 2449 switch (op) { 2450 case RES_OP_RESERVE_AND_MAP: 2451 port = !in_port ? get_param_l(out_param) : in_port; 2452 port = mlx4_slave_convert_port( 2453 dev, slave, port); 2454 2455 if (port < 0) 2456 return -EINVAL; 2457 mac_del_from_slave(dev, slave, in_param, port); 2458 __mlx4_unregister_mac(dev, port, in_param); 2459 break; 2460 default: 2461 err = -EINVAL; 2462 break; 2463 } 2464 2465 return err; 2466 2467 } 2468 2469 static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd, 2470 u64 in_param, u64 *out_param, int port) 2471 { 2472 struct mlx4_priv *priv = mlx4_priv(dev); 2473 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state; 2474 int err = 0; 2475 2476 port = mlx4_slave_convert_port( 2477 dev, slave, port); 2478 2479 if (port < 0) 2480 return -EINVAL; 2481 switch (op) { 2482 case RES_OP_RESERVE_AND_MAP: 2483 if (slave_state[slave].old_vlan_api) 2484 return 0; 2485 if (!port) 2486 return -EINVAL; 2487 vlan_del_from_slave(dev, slave, in_param, port); 2488 __mlx4_unregister_vlan(dev, port, in_param); 2489 break; 2490 default: 2491 err = -EINVAL; 2492 break; 2493 } 2494 2495 return err; 2496 } 2497 2498 static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd, 2499 u64 in_param, u64 *out_param) 2500 { 2501 int index; 2502 int err; 2503 2504 if (op != RES_OP_RESERVE) 2505 return -EINVAL; 2506 2507 index = get_param_l(&in_param); 2508 if (index == MLX4_SINK_COUNTER_INDEX(dev)) 2509 return 0; 2510 2511 err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0); 2512 if (err) 2513 return err; 2514 2515 __mlx4_counter_free(dev, index); 2516 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0); 2517 2518 return err; 2519 } 2520 2521 static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd, 2522 u64 in_param, u64 *out_param) 2523 { 2524 int xrcdn; 2525 int err; 2526 2527 if (op != RES_OP_RESERVE) 2528 return -EINVAL; 2529 2530 xrcdn = get_param_l(&in_param); 2531 err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0); 2532 if (err) 2533 return err; 2534 2535 __mlx4_xrcd_free(dev, xrcdn); 2536 2537 return err; 2538 } 2539 2540 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, 2541 struct mlx4_vhcr *vhcr, 2542 struct mlx4_cmd_mailbox *inbox, 2543 struct mlx4_cmd_mailbox *outbox, 2544 struct mlx4_cmd_info *cmd) 2545 { 2546 int err = -EINVAL; 2547 int alop = vhcr->op_modifier; 2548 2549 switch (vhcr->in_modifier & 0xFF) { 2550 case RES_QP: 2551 err = qp_free_res(dev, slave, vhcr->op_modifier, alop, 2552 vhcr->in_param); 2553 break; 2554 2555 case RES_MTT: 2556 err = mtt_free_res(dev, slave, vhcr->op_modifier, alop, 2557 vhcr->in_param, &vhcr->out_param); 2558 break; 2559 2560 case RES_MPT: 2561 err = mpt_free_res(dev, slave, vhcr->op_modifier, alop, 2562 vhcr->in_param); 2563 break; 2564 2565 case RES_CQ: 2566 err = cq_free_res(dev, slave, vhcr->op_modifier, alop, 2567 vhcr->in_param, &vhcr->out_param); 2568 break; 2569 2570 case RES_SRQ: 2571 err = srq_free_res(dev, slave, vhcr->op_modifier, alop, 2572 vhcr->in_param, &vhcr->out_param); 2573 break; 2574 2575 case RES_MAC: 2576 err = mac_free_res(dev, slave, vhcr->op_modifier, alop, 2577 vhcr->in_param, &vhcr->out_param, 2578 (vhcr->in_modifier >> 8) & 0xFF); 2579 break; 2580 2581 case RES_VLAN: 2582 err = vlan_free_res(dev, slave, vhcr->op_modifier, alop, 2583 vhcr->in_param, &vhcr->out_param, 2584 (vhcr->in_modifier >> 8) & 0xFF); 2585 break; 2586 2587 case RES_COUNTER: 2588 err = counter_free_res(dev, slave, vhcr->op_modifier, alop, 2589 vhcr->in_param, &vhcr->out_param); 2590 break; 2591 2592 case RES_XRCD: 2593 err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop, 2594 vhcr->in_param, &vhcr->out_param); 2595 2596 default: 2597 break; 2598 } 2599 return err; 2600 } 2601 2602 /* ugly but other choices are uglier */ 2603 static int mr_phys_mpt(struct mlx4_mpt_entry *mpt) 2604 { 2605 return (be32_to_cpu(mpt->flags) >> 9) & 1; 2606 } 2607 2608 static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt) 2609 { 2610 return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8; 2611 } 2612 2613 static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt) 2614 { 2615 return be32_to_cpu(mpt->mtt_sz); 2616 } 2617 2618 static u32 mr_get_pd(struct mlx4_mpt_entry *mpt) 2619 { 2620 return be32_to_cpu(mpt->pd_flags) & 0x00ffffff; 2621 } 2622 2623 static int mr_is_fmr(struct mlx4_mpt_entry *mpt) 2624 { 2625 return be32_to_cpu(mpt->pd_flags) & MLX4_MPT_PD_FLAG_FAST_REG; 2626 } 2627 2628 static int mr_is_bind_enabled(struct mlx4_mpt_entry *mpt) 2629 { 2630 return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_BIND_ENABLE; 2631 } 2632 2633 static int mr_is_region(struct mlx4_mpt_entry *mpt) 2634 { 2635 return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_REGION; 2636 } 2637 2638 static int qp_get_mtt_addr(struct mlx4_qp_context *qpc) 2639 { 2640 return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8; 2641 } 2642 2643 static int srq_get_mtt_addr(struct mlx4_srq_context *srqc) 2644 { 2645 return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8; 2646 } 2647 2648 static int qp_get_mtt_size(struct mlx4_qp_context *qpc) 2649 { 2650 int page_shift = (qpc->log_page_size & 0x3f) + 12; 2651 int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf; 2652 int log_sq_sride = qpc->sq_size_stride & 7; 2653 int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf; 2654 int log_rq_stride = qpc->rq_size_stride & 7; 2655 int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1; 2656 int rss = (be32_to_cpu(qpc->flags) >> 13) & 1; 2657 u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff; 2658 int xrc = (ts == MLX4_QP_ST_XRC) ? 1 : 0; 2659 int sq_size; 2660 int rq_size; 2661 int total_pages; 2662 int total_mem; 2663 int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f; 2664 2665 sq_size = 1 << (log_sq_size + log_sq_sride + 4); 2666 rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4)); 2667 total_mem = sq_size + rq_size; 2668 total_pages = 2669 roundup_pow_of_two((total_mem + (page_offset << 6)) >> 2670 page_shift); 2671 2672 return total_pages; 2673 } 2674 2675 static int check_mtt_range(struct mlx4_dev *dev, int slave, int start, 2676 int size, struct res_mtt *mtt) 2677 { 2678 int res_start = mtt->com.res_id; 2679 int res_size = (1 << mtt->order); 2680 2681 if (start < res_start || start + size > res_start + res_size) 2682 return -EPERM; 2683 return 0; 2684 } 2685 2686 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, 2687 struct mlx4_vhcr *vhcr, 2688 struct mlx4_cmd_mailbox *inbox, 2689 struct mlx4_cmd_mailbox *outbox, 2690 struct mlx4_cmd_info *cmd) 2691 { 2692 int err; 2693 int index = vhcr->in_modifier; 2694 struct res_mtt *mtt; 2695 struct res_mpt *mpt; 2696 int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz; 2697 int phys; 2698 int id; 2699 u32 pd; 2700 int pd_slave; 2701 2702 id = index & mpt_mask(dev); 2703 err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt); 2704 if (err) 2705 return err; 2706 2707 /* Disable memory windows for VFs. */ 2708 if (!mr_is_region(inbox->buf)) { 2709 err = -EPERM; 2710 goto ex_abort; 2711 } 2712 2713 /* Make sure that the PD bits related to the slave id are zeros. */ 2714 pd = mr_get_pd(inbox->buf); 2715 pd_slave = (pd >> 17) & 0x7f; 2716 if (pd_slave != 0 && --pd_slave != slave) { 2717 err = -EPERM; 2718 goto ex_abort; 2719 } 2720 2721 if (mr_is_fmr(inbox->buf)) { 2722 /* FMR and Bind Enable are forbidden in slave devices. */ 2723 if (mr_is_bind_enabled(inbox->buf)) { 2724 err = -EPERM; 2725 goto ex_abort; 2726 } 2727 /* FMR and Memory Windows are also forbidden. */ 2728 if (!mr_is_region(inbox->buf)) { 2729 err = -EPERM; 2730 goto ex_abort; 2731 } 2732 } 2733 2734 phys = mr_phys_mpt(inbox->buf); 2735 if (!phys) { 2736 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt); 2737 if (err) 2738 goto ex_abort; 2739 2740 err = check_mtt_range(dev, slave, mtt_base, 2741 mr_get_mtt_size(inbox->buf), mtt); 2742 if (err) 2743 goto ex_put; 2744 2745 mpt->mtt = mtt; 2746 } 2747 2748 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 2749 if (err) 2750 goto ex_put; 2751 2752 if (!phys) { 2753 atomic_inc(&mtt->ref_count); 2754 put_res(dev, slave, mtt->com.res_id, RES_MTT); 2755 } 2756 2757 res_end_move(dev, slave, RES_MPT, id); 2758 return 0; 2759 2760 ex_put: 2761 if (!phys) 2762 put_res(dev, slave, mtt->com.res_id, RES_MTT); 2763 ex_abort: 2764 res_abort_move(dev, slave, RES_MPT, id); 2765 2766 return err; 2767 } 2768 2769 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, 2770 struct mlx4_vhcr *vhcr, 2771 struct mlx4_cmd_mailbox *inbox, 2772 struct mlx4_cmd_mailbox *outbox, 2773 struct mlx4_cmd_info *cmd) 2774 { 2775 int err; 2776 int index = vhcr->in_modifier; 2777 struct res_mpt *mpt; 2778 int id; 2779 2780 id = index & mpt_mask(dev); 2781 err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt); 2782 if (err) 2783 return err; 2784 2785 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 2786 if (err) 2787 goto ex_abort; 2788 2789 if (mpt->mtt) 2790 atomic_dec(&mpt->mtt->ref_count); 2791 2792 res_end_move(dev, slave, RES_MPT, id); 2793 return 0; 2794 2795 ex_abort: 2796 res_abort_move(dev, slave, RES_MPT, id); 2797 2798 return err; 2799 } 2800 2801 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, 2802 struct mlx4_vhcr *vhcr, 2803 struct mlx4_cmd_mailbox *inbox, 2804 struct mlx4_cmd_mailbox *outbox, 2805 struct mlx4_cmd_info *cmd) 2806 { 2807 int err; 2808 int index = vhcr->in_modifier; 2809 struct res_mpt *mpt; 2810 int id; 2811 2812 id = index & mpt_mask(dev); 2813 err = get_res(dev, slave, id, RES_MPT, &mpt); 2814 if (err) 2815 return err; 2816 2817 if (mpt->com.from_state == RES_MPT_MAPPED) { 2818 /* In order to allow rereg in SRIOV, we need to alter the MPT entry. To do 2819 * that, the VF must read the MPT. But since the MPT entry memory is not 2820 * in the VF's virtual memory space, it must use QUERY_MPT to obtain the 2821 * entry contents. To guarantee that the MPT cannot be changed, the driver 2822 * must perform HW2SW_MPT before this query and return the MPT entry to HW 2823 * ownership fofollowing the change. The change here allows the VF to 2824 * perform QUERY_MPT also when the entry is in SW ownership. 2825 */ 2826 struct mlx4_mpt_entry *mpt_entry = mlx4_table_find( 2827 &mlx4_priv(dev)->mr_table.dmpt_table, 2828 mpt->key, NULL); 2829 2830 if (NULL == mpt_entry || NULL == outbox->buf) { 2831 err = -EINVAL; 2832 goto out; 2833 } 2834 2835 memcpy(outbox->buf, mpt_entry, sizeof(*mpt_entry)); 2836 2837 err = 0; 2838 } else if (mpt->com.from_state == RES_MPT_HW) { 2839 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 2840 } else { 2841 err = -EBUSY; 2842 goto out; 2843 } 2844 2845 2846 out: 2847 put_res(dev, slave, id, RES_MPT); 2848 return err; 2849 } 2850 2851 static int qp_get_rcqn(struct mlx4_qp_context *qpc) 2852 { 2853 return be32_to_cpu(qpc->cqn_recv) & 0xffffff; 2854 } 2855 2856 static int qp_get_scqn(struct mlx4_qp_context *qpc) 2857 { 2858 return be32_to_cpu(qpc->cqn_send) & 0xffffff; 2859 } 2860 2861 static u32 qp_get_srqn(struct mlx4_qp_context *qpc) 2862 { 2863 return be32_to_cpu(qpc->srqn) & 0x1ffffff; 2864 } 2865 2866 static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr, 2867 struct mlx4_qp_context *context) 2868 { 2869 u32 qpn = vhcr->in_modifier & 0xffffff; 2870 u32 qkey = 0; 2871 2872 if (mlx4_get_parav_qkey(dev, qpn, &qkey)) 2873 return; 2874 2875 /* adjust qkey in qp context */ 2876 context->qkey = cpu_to_be32(qkey); 2877 } 2878 2879 static int adjust_qp_sched_queue(struct mlx4_dev *dev, int slave, 2880 struct mlx4_qp_context *qpc, 2881 struct mlx4_cmd_mailbox *inbox); 2882 2883 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 2884 struct mlx4_vhcr *vhcr, 2885 struct mlx4_cmd_mailbox *inbox, 2886 struct mlx4_cmd_mailbox *outbox, 2887 struct mlx4_cmd_info *cmd) 2888 { 2889 int err; 2890 int qpn = vhcr->in_modifier & 0x7fffff; 2891 struct res_mtt *mtt; 2892 struct res_qp *qp; 2893 struct mlx4_qp_context *qpc = inbox->buf + 8; 2894 int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz; 2895 int mtt_size = qp_get_mtt_size(qpc); 2896 struct res_cq *rcq; 2897 struct res_cq *scq; 2898 int rcqn = qp_get_rcqn(qpc); 2899 int scqn = qp_get_scqn(qpc); 2900 u32 srqn = qp_get_srqn(qpc) & 0xffffff; 2901 int use_srq = (qp_get_srqn(qpc) >> 24) & 1; 2902 struct res_srq *srq; 2903 int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff; 2904 2905 err = adjust_qp_sched_queue(dev, slave, qpc, inbox); 2906 if (err) 2907 return err; 2908 2909 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0); 2910 if (err) 2911 return err; 2912 qp->local_qpn = local_qpn; 2913 qp->sched_queue = 0; 2914 qp->param3 = 0; 2915 qp->vlan_control = 0; 2916 qp->fvl_rx = 0; 2917 qp->pri_path_fl = 0; 2918 qp->vlan_index = 0; 2919 qp->feup = 0; 2920 qp->qpc_flags = be32_to_cpu(qpc->flags); 2921 2922 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt); 2923 if (err) 2924 goto ex_abort; 2925 2926 err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt); 2927 if (err) 2928 goto ex_put_mtt; 2929 2930 err = get_res(dev, slave, rcqn, RES_CQ, &rcq); 2931 if (err) 2932 goto ex_put_mtt; 2933 2934 if (scqn != rcqn) { 2935 err = get_res(dev, slave, scqn, RES_CQ, &scq); 2936 if (err) 2937 goto ex_put_rcq; 2938 } else 2939 scq = rcq; 2940 2941 if (use_srq) { 2942 err = get_res(dev, slave, srqn, RES_SRQ, &srq); 2943 if (err) 2944 goto ex_put_scq; 2945 } 2946 2947 adjust_proxy_tun_qkey(dev, vhcr, qpc); 2948 update_pkey_index(dev, slave, inbox); 2949 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 2950 if (err) 2951 goto ex_put_srq; 2952 atomic_inc(&mtt->ref_count); 2953 qp->mtt = mtt; 2954 atomic_inc(&rcq->ref_count); 2955 qp->rcq = rcq; 2956 atomic_inc(&scq->ref_count); 2957 qp->scq = scq; 2958 2959 if (scqn != rcqn) 2960 put_res(dev, slave, scqn, RES_CQ); 2961 2962 if (use_srq) { 2963 atomic_inc(&srq->ref_count); 2964 put_res(dev, slave, srqn, RES_SRQ); 2965 qp->srq = srq; 2966 } 2967 put_res(dev, slave, rcqn, RES_CQ); 2968 put_res(dev, slave, mtt_base, RES_MTT); 2969 res_end_move(dev, slave, RES_QP, qpn); 2970 2971 return 0; 2972 2973 ex_put_srq: 2974 if (use_srq) 2975 put_res(dev, slave, srqn, RES_SRQ); 2976 ex_put_scq: 2977 if (scqn != rcqn) 2978 put_res(dev, slave, scqn, RES_CQ); 2979 ex_put_rcq: 2980 put_res(dev, slave, rcqn, RES_CQ); 2981 ex_put_mtt: 2982 put_res(dev, slave, mtt_base, RES_MTT); 2983 ex_abort: 2984 res_abort_move(dev, slave, RES_QP, qpn); 2985 2986 return err; 2987 } 2988 2989 static int eq_get_mtt_addr(struct mlx4_eq_context *eqc) 2990 { 2991 return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8; 2992 } 2993 2994 static int eq_get_mtt_size(struct mlx4_eq_context *eqc) 2995 { 2996 int log_eq_size = eqc->log_eq_size & 0x1f; 2997 int page_shift = (eqc->log_page_size & 0x3f) + 12; 2998 2999 if (log_eq_size + 5 < page_shift) 3000 return 1; 3001 3002 return 1 << (log_eq_size + 5 - page_shift); 3003 } 3004 3005 static int cq_get_mtt_addr(struct mlx4_cq_context *cqc) 3006 { 3007 return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8; 3008 } 3009 3010 static int cq_get_mtt_size(struct mlx4_cq_context *cqc) 3011 { 3012 int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f; 3013 int page_shift = (cqc->log_page_size & 0x3f) + 12; 3014 3015 if (log_cq_size + 5 < page_shift) 3016 return 1; 3017 3018 return 1 << (log_cq_size + 5 - page_shift); 3019 } 3020 3021 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, 3022 struct mlx4_vhcr *vhcr, 3023 struct mlx4_cmd_mailbox *inbox, 3024 struct mlx4_cmd_mailbox *outbox, 3025 struct mlx4_cmd_info *cmd) 3026 { 3027 int err; 3028 int eqn = vhcr->in_modifier; 3029 int res_id = (slave << 10) | eqn; 3030 struct mlx4_eq_context *eqc = inbox->buf; 3031 int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz; 3032 int mtt_size = eq_get_mtt_size(eqc); 3033 struct res_eq *eq; 3034 struct res_mtt *mtt; 3035 3036 err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0); 3037 if (err) 3038 return err; 3039 err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq); 3040 if (err) 3041 goto out_add; 3042 3043 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt); 3044 if (err) 3045 goto out_move; 3046 3047 err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt); 3048 if (err) 3049 goto out_put; 3050 3051 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3052 if (err) 3053 goto out_put; 3054 3055 atomic_inc(&mtt->ref_count); 3056 eq->mtt = mtt; 3057 put_res(dev, slave, mtt->com.res_id, RES_MTT); 3058 res_end_move(dev, slave, RES_EQ, res_id); 3059 return 0; 3060 3061 out_put: 3062 put_res(dev, slave, mtt->com.res_id, RES_MTT); 3063 out_move: 3064 res_abort_move(dev, slave, RES_EQ, res_id); 3065 out_add: 3066 rem_res_range(dev, slave, res_id, 1, RES_EQ, 0); 3067 return err; 3068 } 3069 3070 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave, 3071 struct mlx4_vhcr *vhcr, 3072 struct mlx4_cmd_mailbox *inbox, 3073 struct mlx4_cmd_mailbox *outbox, 3074 struct mlx4_cmd_info *cmd) 3075 { 3076 int err; 3077 u8 get = vhcr->op_modifier; 3078 3079 if (get != 1) 3080 return -EPERM; 3081 3082 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3083 3084 return err; 3085 } 3086 3087 static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start, 3088 int len, struct res_mtt **res) 3089 { 3090 struct mlx4_priv *priv = mlx4_priv(dev); 3091 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 3092 struct res_mtt *mtt; 3093 int err = -EINVAL; 3094 3095 spin_lock_irq(mlx4_tlock(dev)); 3096 list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT], 3097 com.list) { 3098 if (!check_mtt_range(dev, slave, start, len, mtt)) { 3099 *res = mtt; 3100 mtt->com.from_state = mtt->com.state; 3101 mtt->com.state = RES_MTT_BUSY; 3102 err = 0; 3103 break; 3104 } 3105 } 3106 spin_unlock_irq(mlx4_tlock(dev)); 3107 3108 return err; 3109 } 3110 3111 static int verify_qp_parameters(struct mlx4_dev *dev, 3112 struct mlx4_vhcr *vhcr, 3113 struct mlx4_cmd_mailbox *inbox, 3114 enum qp_transition transition, u8 slave) 3115 { 3116 u32 qp_type; 3117 u32 qpn; 3118 struct mlx4_qp_context *qp_ctx; 3119 enum mlx4_qp_optpar optpar; 3120 int port; 3121 int num_gids; 3122 3123 qp_ctx = inbox->buf + 8; 3124 qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff; 3125 optpar = be32_to_cpu(*(__be32 *) inbox->buf); 3126 3127 if (slave != mlx4_master_func_num(dev)) { 3128 qp_ctx->params2 &= ~MLX4_QP_BIT_FPP; 3129 /* setting QP rate-limit is disallowed for VFs */ 3130 if (qp_ctx->rate_limit_params) 3131 return -EPERM; 3132 } 3133 3134 switch (qp_type) { 3135 case MLX4_QP_ST_RC: 3136 case MLX4_QP_ST_XRC: 3137 case MLX4_QP_ST_UC: 3138 switch (transition) { 3139 case QP_TRANS_INIT2RTR: 3140 case QP_TRANS_RTR2RTS: 3141 case QP_TRANS_RTS2RTS: 3142 case QP_TRANS_SQD2SQD: 3143 case QP_TRANS_SQD2RTS: 3144 if (slave != mlx4_master_func_num(dev)) 3145 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) { 3146 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1; 3147 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) 3148 num_gids = mlx4_get_slave_num_gids(dev, slave, port); 3149 else 3150 num_gids = 1; 3151 if (qp_ctx->pri_path.mgid_index >= num_gids) 3152 return -EINVAL; 3153 } 3154 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) { 3155 port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1; 3156 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) 3157 num_gids = mlx4_get_slave_num_gids(dev, slave, port); 3158 else 3159 num_gids = 1; 3160 if (qp_ctx->alt_path.mgid_index >= num_gids) 3161 return -EINVAL; 3162 } 3163 break; 3164 default: 3165 break; 3166 } 3167 break; 3168 3169 case MLX4_QP_ST_MLX: 3170 qpn = vhcr->in_modifier & 0x7fffff; 3171 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1; 3172 if (transition == QP_TRANS_INIT2RTR && 3173 slave != mlx4_master_func_num(dev) && 3174 mlx4_is_qp_reserved(dev, qpn) && 3175 !mlx4_vf_smi_enabled(dev, slave, port)) { 3176 /* only enabled VFs may create MLX proxy QPs */ 3177 mlx4_err(dev, "%s: unprivileged slave %d attempting to create an MLX proxy special QP on port %d\n", 3178 __func__, slave, port); 3179 return -EPERM; 3180 } 3181 break; 3182 3183 default: 3184 break; 3185 } 3186 3187 return 0; 3188 } 3189 3190 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, 3191 struct mlx4_vhcr *vhcr, 3192 struct mlx4_cmd_mailbox *inbox, 3193 struct mlx4_cmd_mailbox *outbox, 3194 struct mlx4_cmd_info *cmd) 3195 { 3196 struct mlx4_mtt mtt; 3197 __be64 *page_list = inbox->buf; 3198 u64 *pg_list = (u64 *)page_list; 3199 int i; 3200 struct res_mtt *rmtt = NULL; 3201 int start = be64_to_cpu(page_list[0]); 3202 int npages = vhcr->in_modifier; 3203 int err; 3204 3205 err = get_containing_mtt(dev, slave, start, npages, &rmtt); 3206 if (err) 3207 return err; 3208 3209 /* Call the SW implementation of write_mtt: 3210 * - Prepare a dummy mtt struct 3211 * - Translate inbox contents to simple addresses in host endianness */ 3212 mtt.offset = 0; /* TBD this is broken but I don't handle it since 3213 we don't really use it */ 3214 mtt.order = 0; 3215 mtt.page_shift = 0; 3216 for (i = 0; i < npages; ++i) 3217 pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL); 3218 3219 err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages, 3220 ((u64 *)page_list + 2)); 3221 3222 if (rmtt) 3223 put_res(dev, slave, rmtt->com.res_id, RES_MTT); 3224 3225 return err; 3226 } 3227 3228 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, 3229 struct mlx4_vhcr *vhcr, 3230 struct mlx4_cmd_mailbox *inbox, 3231 struct mlx4_cmd_mailbox *outbox, 3232 struct mlx4_cmd_info *cmd) 3233 { 3234 int eqn = vhcr->in_modifier; 3235 int res_id = eqn | (slave << 10); 3236 struct res_eq *eq; 3237 int err; 3238 3239 err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq); 3240 if (err) 3241 return err; 3242 3243 err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL); 3244 if (err) 3245 goto ex_abort; 3246 3247 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3248 if (err) 3249 goto ex_put; 3250 3251 atomic_dec(&eq->mtt->ref_count); 3252 put_res(dev, slave, eq->mtt->com.res_id, RES_MTT); 3253 res_end_move(dev, slave, RES_EQ, res_id); 3254 rem_res_range(dev, slave, res_id, 1, RES_EQ, 0); 3255 3256 return 0; 3257 3258 ex_put: 3259 put_res(dev, slave, eq->mtt->com.res_id, RES_MTT); 3260 ex_abort: 3261 res_abort_move(dev, slave, RES_EQ, res_id); 3262 3263 return err; 3264 } 3265 3266 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe) 3267 { 3268 struct mlx4_priv *priv = mlx4_priv(dev); 3269 struct mlx4_slave_event_eq_info *event_eq; 3270 struct mlx4_cmd_mailbox *mailbox; 3271 u32 in_modifier = 0; 3272 int err; 3273 int res_id; 3274 struct res_eq *req; 3275 3276 if (!priv->mfunc.master.slave_state) 3277 return -EINVAL; 3278 3279 /* check for slave valid, slave not PF, and slave active */ 3280 if (slave < 0 || slave > dev->persist->num_vfs || 3281 slave == dev->caps.function || 3282 !priv->mfunc.master.slave_state[slave].active) 3283 return 0; 3284 3285 event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type]; 3286 3287 /* Create the event only if the slave is registered */ 3288 if (event_eq->eqn < 0) 3289 return 0; 3290 3291 mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]); 3292 res_id = (slave << 10) | event_eq->eqn; 3293 err = get_res(dev, slave, res_id, RES_EQ, &req); 3294 if (err) 3295 goto unlock; 3296 3297 if (req->com.from_state != RES_EQ_HW) { 3298 err = -EINVAL; 3299 goto put; 3300 } 3301 3302 mailbox = mlx4_alloc_cmd_mailbox(dev); 3303 if (IS_ERR(mailbox)) { 3304 err = PTR_ERR(mailbox); 3305 goto put; 3306 } 3307 3308 if (eqe->type == MLX4_EVENT_TYPE_CMD) { 3309 ++event_eq->token; 3310 eqe->event.cmd.token = cpu_to_be16(event_eq->token); 3311 } 3312 3313 memcpy(mailbox->buf, (u8 *) eqe, 28); 3314 3315 in_modifier = (slave & 0xff) | ((event_eq->eqn & 0x3ff) << 16); 3316 3317 err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0, 3318 MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B, 3319 MLX4_CMD_NATIVE); 3320 3321 put_res(dev, slave, res_id, RES_EQ); 3322 mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]); 3323 mlx4_free_cmd_mailbox(dev, mailbox); 3324 return err; 3325 3326 put: 3327 put_res(dev, slave, res_id, RES_EQ); 3328 3329 unlock: 3330 mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]); 3331 return err; 3332 } 3333 3334 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, 3335 struct mlx4_vhcr *vhcr, 3336 struct mlx4_cmd_mailbox *inbox, 3337 struct mlx4_cmd_mailbox *outbox, 3338 struct mlx4_cmd_info *cmd) 3339 { 3340 int eqn = vhcr->in_modifier; 3341 int res_id = eqn | (slave << 10); 3342 struct res_eq *eq; 3343 int err; 3344 3345 err = get_res(dev, slave, res_id, RES_EQ, &eq); 3346 if (err) 3347 return err; 3348 3349 if (eq->com.from_state != RES_EQ_HW) { 3350 err = -EINVAL; 3351 goto ex_put; 3352 } 3353 3354 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3355 3356 ex_put: 3357 put_res(dev, slave, res_id, RES_EQ); 3358 return err; 3359 } 3360 3361 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, 3362 struct mlx4_vhcr *vhcr, 3363 struct mlx4_cmd_mailbox *inbox, 3364 struct mlx4_cmd_mailbox *outbox, 3365 struct mlx4_cmd_info *cmd) 3366 { 3367 int err; 3368 int cqn = vhcr->in_modifier; 3369 struct mlx4_cq_context *cqc = inbox->buf; 3370 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz; 3371 struct res_cq *cq = NULL; 3372 struct res_mtt *mtt; 3373 3374 err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq); 3375 if (err) 3376 return err; 3377 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt); 3378 if (err) 3379 goto out_move; 3380 err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt); 3381 if (err) 3382 goto out_put; 3383 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3384 if (err) 3385 goto out_put; 3386 atomic_inc(&mtt->ref_count); 3387 cq->mtt = mtt; 3388 put_res(dev, slave, mtt->com.res_id, RES_MTT); 3389 res_end_move(dev, slave, RES_CQ, cqn); 3390 return 0; 3391 3392 out_put: 3393 put_res(dev, slave, mtt->com.res_id, RES_MTT); 3394 out_move: 3395 res_abort_move(dev, slave, RES_CQ, cqn); 3396 return err; 3397 } 3398 3399 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, 3400 struct mlx4_vhcr *vhcr, 3401 struct mlx4_cmd_mailbox *inbox, 3402 struct mlx4_cmd_mailbox *outbox, 3403 struct mlx4_cmd_info *cmd) 3404 { 3405 int err; 3406 int cqn = vhcr->in_modifier; 3407 struct res_cq *cq = NULL; 3408 3409 err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq); 3410 if (err) 3411 return err; 3412 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3413 if (err) 3414 goto out_move; 3415 atomic_dec(&cq->mtt->ref_count); 3416 res_end_move(dev, slave, RES_CQ, cqn); 3417 return 0; 3418 3419 out_move: 3420 res_abort_move(dev, slave, RES_CQ, cqn); 3421 return err; 3422 } 3423 3424 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, 3425 struct mlx4_vhcr *vhcr, 3426 struct mlx4_cmd_mailbox *inbox, 3427 struct mlx4_cmd_mailbox *outbox, 3428 struct mlx4_cmd_info *cmd) 3429 { 3430 int cqn = vhcr->in_modifier; 3431 struct res_cq *cq; 3432 int err; 3433 3434 err = get_res(dev, slave, cqn, RES_CQ, &cq); 3435 if (err) 3436 return err; 3437 3438 if (cq->com.from_state != RES_CQ_HW) 3439 goto ex_put; 3440 3441 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3442 ex_put: 3443 put_res(dev, slave, cqn, RES_CQ); 3444 3445 return err; 3446 } 3447 3448 static int handle_resize(struct mlx4_dev *dev, int slave, 3449 struct mlx4_vhcr *vhcr, 3450 struct mlx4_cmd_mailbox *inbox, 3451 struct mlx4_cmd_mailbox *outbox, 3452 struct mlx4_cmd_info *cmd, 3453 struct res_cq *cq) 3454 { 3455 int err; 3456 struct res_mtt *orig_mtt; 3457 struct res_mtt *mtt; 3458 struct mlx4_cq_context *cqc = inbox->buf; 3459 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz; 3460 3461 err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt); 3462 if (err) 3463 return err; 3464 3465 if (orig_mtt != cq->mtt) { 3466 err = -EINVAL; 3467 goto ex_put; 3468 } 3469 3470 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt); 3471 if (err) 3472 goto ex_put; 3473 3474 err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt); 3475 if (err) 3476 goto ex_put1; 3477 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3478 if (err) 3479 goto ex_put1; 3480 atomic_dec(&orig_mtt->ref_count); 3481 put_res(dev, slave, orig_mtt->com.res_id, RES_MTT); 3482 atomic_inc(&mtt->ref_count); 3483 cq->mtt = mtt; 3484 put_res(dev, slave, mtt->com.res_id, RES_MTT); 3485 return 0; 3486 3487 ex_put1: 3488 put_res(dev, slave, mtt->com.res_id, RES_MTT); 3489 ex_put: 3490 put_res(dev, slave, orig_mtt->com.res_id, RES_MTT); 3491 3492 return err; 3493 3494 } 3495 3496 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, 3497 struct mlx4_vhcr *vhcr, 3498 struct mlx4_cmd_mailbox *inbox, 3499 struct mlx4_cmd_mailbox *outbox, 3500 struct mlx4_cmd_info *cmd) 3501 { 3502 int cqn = vhcr->in_modifier; 3503 struct res_cq *cq; 3504 int err; 3505 3506 err = get_res(dev, slave, cqn, RES_CQ, &cq); 3507 if (err) 3508 return err; 3509 3510 if (cq->com.from_state != RES_CQ_HW) 3511 goto ex_put; 3512 3513 if (vhcr->op_modifier == 0) { 3514 err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq); 3515 goto ex_put; 3516 } 3517 3518 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3519 ex_put: 3520 put_res(dev, slave, cqn, RES_CQ); 3521 3522 return err; 3523 } 3524 3525 static int srq_get_mtt_size(struct mlx4_srq_context *srqc) 3526 { 3527 int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf; 3528 int log_rq_stride = srqc->logstride & 7; 3529 int page_shift = (srqc->log_page_size & 0x3f) + 12; 3530 3531 if (log_srq_size + log_rq_stride + 4 < page_shift) 3532 return 1; 3533 3534 return 1 << (log_srq_size + log_rq_stride + 4 - page_shift); 3535 } 3536 3537 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 3538 struct mlx4_vhcr *vhcr, 3539 struct mlx4_cmd_mailbox *inbox, 3540 struct mlx4_cmd_mailbox *outbox, 3541 struct mlx4_cmd_info *cmd) 3542 { 3543 int err; 3544 int srqn = vhcr->in_modifier; 3545 struct res_mtt *mtt; 3546 struct res_srq *srq = NULL; 3547 struct mlx4_srq_context *srqc = inbox->buf; 3548 int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz; 3549 3550 if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff)) 3551 return -EINVAL; 3552 3553 err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq); 3554 if (err) 3555 return err; 3556 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt); 3557 if (err) 3558 goto ex_abort; 3559 err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc), 3560 mtt); 3561 if (err) 3562 goto ex_put_mtt; 3563 3564 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3565 if (err) 3566 goto ex_put_mtt; 3567 3568 atomic_inc(&mtt->ref_count); 3569 srq->mtt = mtt; 3570 put_res(dev, slave, mtt->com.res_id, RES_MTT); 3571 res_end_move(dev, slave, RES_SRQ, srqn); 3572 return 0; 3573 3574 ex_put_mtt: 3575 put_res(dev, slave, mtt->com.res_id, RES_MTT); 3576 ex_abort: 3577 res_abort_move(dev, slave, RES_SRQ, srqn); 3578 3579 return err; 3580 } 3581 3582 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 3583 struct mlx4_vhcr *vhcr, 3584 struct mlx4_cmd_mailbox *inbox, 3585 struct mlx4_cmd_mailbox *outbox, 3586 struct mlx4_cmd_info *cmd) 3587 { 3588 int err; 3589 int srqn = vhcr->in_modifier; 3590 struct res_srq *srq = NULL; 3591 3592 err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq); 3593 if (err) 3594 return err; 3595 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3596 if (err) 3597 goto ex_abort; 3598 atomic_dec(&srq->mtt->ref_count); 3599 if (srq->cq) 3600 atomic_dec(&srq->cq->ref_count); 3601 res_end_move(dev, slave, RES_SRQ, srqn); 3602 3603 return 0; 3604 3605 ex_abort: 3606 res_abort_move(dev, slave, RES_SRQ, srqn); 3607 3608 return err; 3609 } 3610 3611 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, 3612 struct mlx4_vhcr *vhcr, 3613 struct mlx4_cmd_mailbox *inbox, 3614 struct mlx4_cmd_mailbox *outbox, 3615 struct mlx4_cmd_info *cmd) 3616 { 3617 int err; 3618 int srqn = vhcr->in_modifier; 3619 struct res_srq *srq; 3620 3621 err = get_res(dev, slave, srqn, RES_SRQ, &srq); 3622 if (err) 3623 return err; 3624 if (srq->com.from_state != RES_SRQ_HW) { 3625 err = -EBUSY; 3626 goto out; 3627 } 3628 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3629 out: 3630 put_res(dev, slave, srqn, RES_SRQ); 3631 return err; 3632 } 3633 3634 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, 3635 struct mlx4_vhcr *vhcr, 3636 struct mlx4_cmd_mailbox *inbox, 3637 struct mlx4_cmd_mailbox *outbox, 3638 struct mlx4_cmd_info *cmd) 3639 { 3640 int err; 3641 int srqn = vhcr->in_modifier; 3642 struct res_srq *srq; 3643 3644 err = get_res(dev, slave, srqn, RES_SRQ, &srq); 3645 if (err) 3646 return err; 3647 3648 if (srq->com.from_state != RES_SRQ_HW) { 3649 err = -EBUSY; 3650 goto out; 3651 } 3652 3653 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3654 out: 3655 put_res(dev, slave, srqn, RES_SRQ); 3656 return err; 3657 } 3658 3659 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, 3660 struct mlx4_vhcr *vhcr, 3661 struct mlx4_cmd_mailbox *inbox, 3662 struct mlx4_cmd_mailbox *outbox, 3663 struct mlx4_cmd_info *cmd) 3664 { 3665 int err; 3666 int qpn = vhcr->in_modifier & 0x7fffff; 3667 struct res_qp *qp; 3668 3669 err = get_res(dev, slave, qpn, RES_QP, &qp); 3670 if (err) 3671 return err; 3672 if (qp->com.from_state != RES_QP_HW) { 3673 err = -EBUSY; 3674 goto out; 3675 } 3676 3677 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3678 out: 3679 put_res(dev, slave, qpn, RES_QP); 3680 return err; 3681 } 3682 3683 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 3684 struct mlx4_vhcr *vhcr, 3685 struct mlx4_cmd_mailbox *inbox, 3686 struct mlx4_cmd_mailbox *outbox, 3687 struct mlx4_cmd_info *cmd) 3688 { 3689 struct mlx4_qp_context *context = inbox->buf + 8; 3690 adjust_proxy_tun_qkey(dev, vhcr, context); 3691 update_pkey_index(dev, slave, inbox); 3692 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3693 } 3694 3695 static int adjust_qp_sched_queue(struct mlx4_dev *dev, int slave, 3696 struct mlx4_qp_context *qpc, 3697 struct mlx4_cmd_mailbox *inbox) 3698 { 3699 enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *)inbox->buf); 3700 u8 pri_sched_queue; 3701 int port = mlx4_slave_convert_port( 3702 dev, slave, (qpc->pri_path.sched_queue >> 6 & 1) + 1) - 1; 3703 3704 if (port < 0) 3705 return -EINVAL; 3706 3707 pri_sched_queue = (qpc->pri_path.sched_queue & ~(1 << 6)) | 3708 ((port & 1) << 6); 3709 3710 if (optpar & (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | MLX4_QP_OPTPAR_SCHED_QUEUE) || 3711 qpc->pri_path.sched_queue || mlx4_is_eth(dev, port + 1)) { 3712 qpc->pri_path.sched_queue = pri_sched_queue; 3713 } 3714 3715 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) { 3716 port = mlx4_slave_convert_port( 3717 dev, slave, (qpc->alt_path.sched_queue >> 6 & 1) 3718 + 1) - 1; 3719 if (port < 0) 3720 return -EINVAL; 3721 qpc->alt_path.sched_queue = 3722 (qpc->alt_path.sched_queue & ~(1 << 6)) | 3723 (port & 1) << 6; 3724 } 3725 return 0; 3726 } 3727 3728 static int roce_verify_mac(struct mlx4_dev *dev, int slave, 3729 struct mlx4_qp_context *qpc, 3730 struct mlx4_cmd_mailbox *inbox) 3731 { 3732 u64 mac; 3733 int port; 3734 u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff; 3735 u8 sched = *(u8 *)(inbox->buf + 64); 3736 u8 smac_ix; 3737 3738 port = (sched >> 6 & 1) + 1; 3739 if (mlx4_is_eth(dev, port) && (ts != MLX4_QP_ST_MLX)) { 3740 smac_ix = qpc->pri_path.grh_mylmc & 0x7f; 3741 if (mac_find_smac_ix_in_slave(dev, slave, port, smac_ix, &mac)) 3742 return -ENOENT; 3743 } 3744 return 0; 3745 } 3746 3747 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, 3748 struct mlx4_vhcr *vhcr, 3749 struct mlx4_cmd_mailbox *inbox, 3750 struct mlx4_cmd_mailbox *outbox, 3751 struct mlx4_cmd_info *cmd) 3752 { 3753 int err; 3754 struct mlx4_qp_context *qpc = inbox->buf + 8; 3755 int qpn = vhcr->in_modifier & 0x7fffff; 3756 struct res_qp *qp; 3757 u8 orig_sched_queue; 3758 __be32 orig_param3 = qpc->param3; 3759 u8 orig_vlan_control = qpc->pri_path.vlan_control; 3760 u8 orig_fvl_rx = qpc->pri_path.fvl_rx; 3761 u8 orig_pri_path_fl = qpc->pri_path.fl; 3762 u8 orig_vlan_index = qpc->pri_path.vlan_index; 3763 u8 orig_feup = qpc->pri_path.feup; 3764 3765 err = adjust_qp_sched_queue(dev, slave, qpc, inbox); 3766 if (err) 3767 return err; 3768 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_INIT2RTR, slave); 3769 if (err) 3770 return err; 3771 3772 if (roce_verify_mac(dev, slave, qpc, inbox)) 3773 return -EINVAL; 3774 3775 update_pkey_index(dev, slave, inbox); 3776 update_gid(dev, inbox, (u8)slave); 3777 adjust_proxy_tun_qkey(dev, vhcr, qpc); 3778 orig_sched_queue = qpc->pri_path.sched_queue; 3779 3780 err = get_res(dev, slave, qpn, RES_QP, &qp); 3781 if (err) 3782 return err; 3783 if (qp->com.from_state != RES_QP_HW) { 3784 err = -EBUSY; 3785 goto out; 3786 } 3787 3788 err = update_vport_qp_param(dev, inbox, slave, qpn); 3789 if (err) 3790 goto out; 3791 3792 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3793 out: 3794 /* if no error, save sched queue value passed in by VF. This is 3795 * essentially the QOS value provided by the VF. This will be useful 3796 * if we allow dynamic changes from VST back to VGT 3797 */ 3798 if (!err) { 3799 qp->sched_queue = orig_sched_queue; 3800 qp->param3 = orig_param3; 3801 qp->vlan_control = orig_vlan_control; 3802 qp->fvl_rx = orig_fvl_rx; 3803 qp->pri_path_fl = orig_pri_path_fl; 3804 qp->vlan_index = orig_vlan_index; 3805 qp->feup = orig_feup; 3806 } 3807 put_res(dev, slave, qpn, RES_QP); 3808 return err; 3809 } 3810 3811 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 3812 struct mlx4_vhcr *vhcr, 3813 struct mlx4_cmd_mailbox *inbox, 3814 struct mlx4_cmd_mailbox *outbox, 3815 struct mlx4_cmd_info *cmd) 3816 { 3817 int err; 3818 struct mlx4_qp_context *context = inbox->buf + 8; 3819 3820 err = adjust_qp_sched_queue(dev, slave, context, inbox); 3821 if (err) 3822 return err; 3823 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTR2RTS, slave); 3824 if (err) 3825 return err; 3826 3827 update_pkey_index(dev, slave, inbox); 3828 update_gid(dev, inbox, (u8)slave); 3829 adjust_proxy_tun_qkey(dev, vhcr, context); 3830 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3831 } 3832 3833 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 3834 struct mlx4_vhcr *vhcr, 3835 struct mlx4_cmd_mailbox *inbox, 3836 struct mlx4_cmd_mailbox *outbox, 3837 struct mlx4_cmd_info *cmd) 3838 { 3839 int err; 3840 struct mlx4_qp_context *context = inbox->buf + 8; 3841 3842 err = adjust_qp_sched_queue(dev, slave, context, inbox); 3843 if (err) 3844 return err; 3845 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTS2RTS, slave); 3846 if (err) 3847 return err; 3848 3849 update_pkey_index(dev, slave, inbox); 3850 update_gid(dev, inbox, (u8)slave); 3851 adjust_proxy_tun_qkey(dev, vhcr, context); 3852 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3853 } 3854 3855 3856 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 3857 struct mlx4_vhcr *vhcr, 3858 struct mlx4_cmd_mailbox *inbox, 3859 struct mlx4_cmd_mailbox *outbox, 3860 struct mlx4_cmd_info *cmd) 3861 { 3862 struct mlx4_qp_context *context = inbox->buf + 8; 3863 int err = adjust_qp_sched_queue(dev, slave, context, inbox); 3864 if (err) 3865 return err; 3866 adjust_proxy_tun_qkey(dev, vhcr, context); 3867 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3868 } 3869 3870 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 3871 struct mlx4_vhcr *vhcr, 3872 struct mlx4_cmd_mailbox *inbox, 3873 struct mlx4_cmd_mailbox *outbox, 3874 struct mlx4_cmd_info *cmd) 3875 { 3876 int err; 3877 struct mlx4_qp_context *context = inbox->buf + 8; 3878 3879 err = adjust_qp_sched_queue(dev, slave, context, inbox); 3880 if (err) 3881 return err; 3882 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2SQD, slave); 3883 if (err) 3884 return err; 3885 3886 adjust_proxy_tun_qkey(dev, vhcr, context); 3887 update_gid(dev, inbox, (u8)slave); 3888 update_pkey_index(dev, slave, inbox); 3889 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3890 } 3891 3892 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 3893 struct mlx4_vhcr *vhcr, 3894 struct mlx4_cmd_mailbox *inbox, 3895 struct mlx4_cmd_mailbox *outbox, 3896 struct mlx4_cmd_info *cmd) 3897 { 3898 int err; 3899 struct mlx4_qp_context *context = inbox->buf + 8; 3900 3901 err = adjust_qp_sched_queue(dev, slave, context, inbox); 3902 if (err) 3903 return err; 3904 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2RTS, slave); 3905 if (err) 3906 return err; 3907 3908 adjust_proxy_tun_qkey(dev, vhcr, context); 3909 update_gid(dev, inbox, (u8)slave); 3910 update_pkey_index(dev, slave, inbox); 3911 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3912 } 3913 3914 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, 3915 struct mlx4_vhcr *vhcr, 3916 struct mlx4_cmd_mailbox *inbox, 3917 struct mlx4_cmd_mailbox *outbox, 3918 struct mlx4_cmd_info *cmd) 3919 { 3920 int err; 3921 int qpn = vhcr->in_modifier & 0x7fffff; 3922 struct res_qp *qp; 3923 3924 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0); 3925 if (err) 3926 return err; 3927 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 3928 if (err) 3929 goto ex_abort; 3930 3931 atomic_dec(&qp->mtt->ref_count); 3932 atomic_dec(&qp->rcq->ref_count); 3933 atomic_dec(&qp->scq->ref_count); 3934 if (qp->srq) 3935 atomic_dec(&qp->srq->ref_count); 3936 res_end_move(dev, slave, RES_QP, qpn); 3937 return 0; 3938 3939 ex_abort: 3940 res_abort_move(dev, slave, RES_QP, qpn); 3941 3942 return err; 3943 } 3944 3945 static struct res_gid *find_gid(struct mlx4_dev *dev, int slave, 3946 struct res_qp *rqp, u8 *gid) 3947 { 3948 struct res_gid *res; 3949 3950 list_for_each_entry(res, &rqp->mcg_list, list) { 3951 if (!memcmp(res->gid, gid, 16)) 3952 return res; 3953 } 3954 return NULL; 3955 } 3956 3957 static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp, 3958 u8 *gid, enum mlx4_protocol prot, 3959 enum mlx4_steer_type steer, u64 reg_id) 3960 { 3961 struct res_gid *res; 3962 int err; 3963 3964 res = kzalloc(sizeof *res, GFP_KERNEL); 3965 if (!res) 3966 return -ENOMEM; 3967 3968 spin_lock_irq(&rqp->mcg_spl); 3969 if (find_gid(dev, slave, rqp, gid)) { 3970 kfree(res); 3971 err = -EEXIST; 3972 } else { 3973 memcpy(res->gid, gid, 16); 3974 res->prot = prot; 3975 res->steer = steer; 3976 res->reg_id = reg_id; 3977 list_add_tail(&res->list, &rqp->mcg_list); 3978 err = 0; 3979 } 3980 spin_unlock_irq(&rqp->mcg_spl); 3981 3982 return err; 3983 } 3984 3985 static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp, 3986 u8 *gid, enum mlx4_protocol prot, 3987 enum mlx4_steer_type steer, u64 *reg_id) 3988 { 3989 struct res_gid *res; 3990 int err; 3991 3992 spin_lock_irq(&rqp->mcg_spl); 3993 res = find_gid(dev, slave, rqp, gid); 3994 if (!res || res->prot != prot || res->steer != steer) 3995 err = -EINVAL; 3996 else { 3997 *reg_id = res->reg_id; 3998 list_del(&res->list); 3999 kfree(res); 4000 err = 0; 4001 } 4002 spin_unlock_irq(&rqp->mcg_spl); 4003 4004 return err; 4005 } 4006 4007 static int qp_attach(struct mlx4_dev *dev, int slave, struct mlx4_qp *qp, 4008 u8 gid[16], int block_loopback, enum mlx4_protocol prot, 4009 enum mlx4_steer_type type, u64 *reg_id) 4010 { 4011 switch (dev->caps.steering_mode) { 4012 case MLX4_STEERING_MODE_DEVICE_MANAGED: { 4013 int port = mlx4_slave_convert_port(dev, slave, gid[5]); 4014 if (port < 0) 4015 return port; 4016 return mlx4_trans_to_dmfs_attach(dev, qp, gid, port, 4017 block_loopback, prot, 4018 reg_id); 4019 } 4020 case MLX4_STEERING_MODE_B0: 4021 if (prot == MLX4_PROT_ETH) { 4022 int port = mlx4_slave_convert_port(dev, slave, gid[5]); 4023 if (port < 0) 4024 return port; 4025 gid[5] = port; 4026 } 4027 return mlx4_qp_attach_common(dev, qp, gid, 4028 block_loopback, prot, type); 4029 default: 4030 return -EINVAL; 4031 } 4032 } 4033 4034 static int qp_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, 4035 u8 gid[16], enum mlx4_protocol prot, 4036 enum mlx4_steer_type type, u64 reg_id) 4037 { 4038 switch (dev->caps.steering_mode) { 4039 case MLX4_STEERING_MODE_DEVICE_MANAGED: 4040 return mlx4_flow_detach(dev, reg_id); 4041 case MLX4_STEERING_MODE_B0: 4042 return mlx4_qp_detach_common(dev, qp, gid, prot, type); 4043 default: 4044 return -EINVAL; 4045 } 4046 } 4047 4048 static int mlx4_adjust_port(struct mlx4_dev *dev, int slave, 4049 u8 *gid, enum mlx4_protocol prot) 4050 { 4051 int real_port; 4052 4053 if (prot != MLX4_PROT_ETH) 4054 return 0; 4055 4056 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0 || 4057 dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 4058 real_port = mlx4_slave_convert_port(dev, slave, gid[5]); 4059 if (real_port < 0) 4060 return -EINVAL; 4061 gid[5] = real_port; 4062 } 4063 4064 return 0; 4065 } 4066 4067 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 4068 struct mlx4_vhcr *vhcr, 4069 struct mlx4_cmd_mailbox *inbox, 4070 struct mlx4_cmd_mailbox *outbox, 4071 struct mlx4_cmd_info *cmd) 4072 { 4073 struct mlx4_qp qp; /* dummy for calling attach/detach */ 4074 u8 *gid = inbox->buf; 4075 enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7; 4076 int err; 4077 int qpn; 4078 struct res_qp *rqp; 4079 u64 reg_id = 0; 4080 int attach = vhcr->op_modifier; 4081 int block_loopback = vhcr->in_modifier >> 31; 4082 u8 steer_type_mask = 2; 4083 enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1; 4084 4085 qpn = vhcr->in_modifier & 0xffffff; 4086 err = get_res(dev, slave, qpn, RES_QP, &rqp); 4087 if (err) 4088 return err; 4089 4090 qp.qpn = qpn; 4091 if (attach) { 4092 err = qp_attach(dev, slave, &qp, gid, block_loopback, prot, 4093 type, ®_id); 4094 if (err) { 4095 pr_err("Fail to attach rule to qp 0x%x\n", qpn); 4096 goto ex_put; 4097 } 4098 err = add_mcg_res(dev, slave, rqp, gid, prot, type, reg_id); 4099 if (err) 4100 goto ex_detach; 4101 } else { 4102 err = mlx4_adjust_port(dev, slave, gid, prot); 4103 if (err) 4104 goto ex_put; 4105 4106 err = rem_mcg_res(dev, slave, rqp, gid, prot, type, ®_id); 4107 if (err) 4108 goto ex_put; 4109 4110 err = qp_detach(dev, &qp, gid, prot, type, reg_id); 4111 if (err) 4112 pr_err("Fail to detach rule from qp 0x%x reg_id = 0x%llx\n", 4113 qpn, reg_id); 4114 } 4115 put_res(dev, slave, qpn, RES_QP); 4116 return err; 4117 4118 ex_detach: 4119 qp_detach(dev, &qp, gid, prot, type, reg_id); 4120 ex_put: 4121 put_res(dev, slave, qpn, RES_QP); 4122 return err; 4123 } 4124 4125 /* 4126 * MAC validation for Flow Steering rules. 4127 * VF can attach rules only with a mac address which is assigned to it. 4128 */ 4129 static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header, 4130 struct list_head *rlist) 4131 { 4132 struct mac_res *res, *tmp; 4133 __be64 be_mac; 4134 4135 /* make sure it isn't multicast or broadcast mac*/ 4136 if (!is_multicast_ether_addr(eth_header->eth.dst_mac) && 4137 !is_broadcast_ether_addr(eth_header->eth.dst_mac)) { 4138 list_for_each_entry_safe(res, tmp, rlist, list) { 4139 be_mac = cpu_to_be64(res->mac << 16); 4140 if (ether_addr_equal((u8 *)&be_mac, eth_header->eth.dst_mac)) 4141 return 0; 4142 } 4143 pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n", 4144 eth_header->eth.dst_mac, slave); 4145 return -EINVAL; 4146 } 4147 return 0; 4148 } 4149 4150 static void handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl, 4151 struct _rule_hw *eth_header) 4152 { 4153 if (is_multicast_ether_addr(eth_header->eth.dst_mac) || 4154 is_broadcast_ether_addr(eth_header->eth.dst_mac)) { 4155 struct mlx4_net_trans_rule_hw_eth *eth = 4156 (struct mlx4_net_trans_rule_hw_eth *)eth_header; 4157 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1); 4158 bool last_rule = next_rule->size == 0 && next_rule->id == 0 && 4159 next_rule->rsvd == 0; 4160 4161 if (last_rule) 4162 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC); 4163 } 4164 } 4165 4166 /* 4167 * In case of missing eth header, append eth header with a MAC address 4168 * assigned to the VF. 4169 */ 4170 static int add_eth_header(struct mlx4_dev *dev, int slave, 4171 struct mlx4_cmd_mailbox *inbox, 4172 struct list_head *rlist, int header_id) 4173 { 4174 struct mac_res *res, *tmp; 4175 u8 port; 4176 struct mlx4_net_trans_rule_hw_ctrl *ctrl; 4177 struct mlx4_net_trans_rule_hw_eth *eth_header; 4178 struct mlx4_net_trans_rule_hw_ipv4 *ip_header; 4179 struct mlx4_net_trans_rule_hw_tcp_udp *l4_header; 4180 __be64 be_mac = 0; 4181 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16); 4182 4183 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf; 4184 port = ctrl->port; 4185 eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1); 4186 4187 /* Clear a space in the inbox for eth header */ 4188 switch (header_id) { 4189 case MLX4_NET_TRANS_RULE_ID_IPV4: 4190 ip_header = 4191 (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1); 4192 memmove(ip_header, eth_header, 4193 sizeof(*ip_header) + sizeof(*l4_header)); 4194 break; 4195 case MLX4_NET_TRANS_RULE_ID_TCP: 4196 case MLX4_NET_TRANS_RULE_ID_UDP: 4197 l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *) 4198 (eth_header + 1); 4199 memmove(l4_header, eth_header, sizeof(*l4_header)); 4200 break; 4201 default: 4202 return -EINVAL; 4203 } 4204 list_for_each_entry_safe(res, tmp, rlist, list) { 4205 if (port == res->port) { 4206 be_mac = cpu_to_be64(res->mac << 16); 4207 break; 4208 } 4209 } 4210 if (!be_mac) { 4211 pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d\n", 4212 port); 4213 return -EINVAL; 4214 } 4215 4216 memset(eth_header, 0, sizeof(*eth_header)); 4217 eth_header->size = sizeof(*eth_header) >> 2; 4218 eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]); 4219 memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN); 4220 memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN); 4221 4222 return 0; 4223 4224 } 4225 4226 #define MLX4_UPD_QP_PATH_MASK_SUPPORTED ( \ 4227 1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX |\ 4228 1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB) 4229 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave, 4230 struct mlx4_vhcr *vhcr, 4231 struct mlx4_cmd_mailbox *inbox, 4232 struct mlx4_cmd_mailbox *outbox, 4233 struct mlx4_cmd_info *cmd_info) 4234 { 4235 int err; 4236 u32 qpn = vhcr->in_modifier & 0xffffff; 4237 struct res_qp *rqp; 4238 u64 mac; 4239 unsigned port; 4240 u64 pri_addr_path_mask; 4241 struct mlx4_update_qp_context *cmd; 4242 int smac_index; 4243 4244 cmd = (struct mlx4_update_qp_context *)inbox->buf; 4245 4246 pri_addr_path_mask = be64_to_cpu(cmd->primary_addr_path_mask); 4247 if (cmd->qp_mask || cmd->secondary_addr_path_mask || 4248 (pri_addr_path_mask & ~MLX4_UPD_QP_PATH_MASK_SUPPORTED)) 4249 return -EPERM; 4250 4251 if ((pri_addr_path_mask & 4252 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB)) && 4253 !(dev->caps.flags2 & 4254 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB)) { 4255 mlx4_warn(dev, 4256 "Src check LB for slave %d isn't supported\n", 4257 slave); 4258 return -ENOTSUPP; 4259 } 4260 4261 /* Just change the smac for the QP */ 4262 err = get_res(dev, slave, qpn, RES_QP, &rqp); 4263 if (err) { 4264 mlx4_err(dev, "Updating qpn 0x%x for slave %d rejected\n", qpn, slave); 4265 return err; 4266 } 4267 4268 port = (rqp->sched_queue >> 6 & 1) + 1; 4269 4270 if (pri_addr_path_mask & (1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX)) { 4271 smac_index = cmd->qp_context.pri_path.grh_mylmc; 4272 err = mac_find_smac_ix_in_slave(dev, slave, port, 4273 smac_index, &mac); 4274 4275 if (err) { 4276 mlx4_err(dev, "Failed to update qpn 0x%x, MAC is invalid. smac_ix: %d\n", 4277 qpn, smac_index); 4278 goto err_mac; 4279 } 4280 } 4281 4282 err = mlx4_cmd(dev, inbox->dma, 4283 vhcr->in_modifier, 0, 4284 MLX4_CMD_UPDATE_QP, MLX4_CMD_TIME_CLASS_A, 4285 MLX4_CMD_NATIVE); 4286 if (err) { 4287 mlx4_err(dev, "Failed to update qpn on qpn 0x%x, command failed\n", qpn); 4288 goto err_mac; 4289 } 4290 4291 err_mac: 4292 put_res(dev, slave, qpn, RES_QP); 4293 return err; 4294 } 4295 4296 static u32 qp_attach_mbox_size(void *mbox) 4297 { 4298 u32 size = sizeof(struct mlx4_net_trans_rule_hw_ctrl); 4299 struct _rule_hw *rule_header; 4300 4301 rule_header = (struct _rule_hw *)(mbox + size); 4302 4303 while (rule_header->size) { 4304 size += rule_header->size * sizeof(u32); 4305 rule_header += 1; 4306 } 4307 return size; 4308 } 4309 4310 static int mlx4_do_mirror_rule(struct mlx4_dev *dev, struct res_fs_rule *fs_rule); 4311 4312 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 4313 struct mlx4_vhcr *vhcr, 4314 struct mlx4_cmd_mailbox *inbox, 4315 struct mlx4_cmd_mailbox *outbox, 4316 struct mlx4_cmd_info *cmd) 4317 { 4318 4319 struct mlx4_priv *priv = mlx4_priv(dev); 4320 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 4321 struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC]; 4322 int err; 4323 int qpn; 4324 struct res_qp *rqp; 4325 struct mlx4_net_trans_rule_hw_ctrl *ctrl; 4326 struct _rule_hw *rule_header; 4327 int header_id; 4328 struct res_fs_rule *rrule; 4329 u32 mbox_size; 4330 4331 if (dev->caps.steering_mode != 4332 MLX4_STEERING_MODE_DEVICE_MANAGED) 4333 return -EOPNOTSUPP; 4334 4335 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf; 4336 err = mlx4_slave_convert_port(dev, slave, ctrl->port); 4337 if (err <= 0) 4338 return -EINVAL; 4339 ctrl->port = err; 4340 qpn = be32_to_cpu(ctrl->qpn) & 0xffffff; 4341 err = get_res(dev, slave, qpn, RES_QP, &rqp); 4342 if (err) { 4343 pr_err("Steering rule with qpn 0x%x rejected\n", qpn); 4344 return err; 4345 } 4346 rule_header = (struct _rule_hw *)(ctrl + 1); 4347 header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id)); 4348 4349 if (header_id == MLX4_NET_TRANS_RULE_ID_ETH) 4350 handle_eth_header_mcast_prio(ctrl, rule_header); 4351 4352 if (slave == dev->caps.function) 4353 goto execute; 4354 4355 switch (header_id) { 4356 case MLX4_NET_TRANS_RULE_ID_ETH: 4357 if (validate_eth_header_mac(slave, rule_header, rlist)) { 4358 err = -EINVAL; 4359 goto err_put_qp; 4360 } 4361 break; 4362 case MLX4_NET_TRANS_RULE_ID_IB: 4363 break; 4364 case MLX4_NET_TRANS_RULE_ID_IPV4: 4365 case MLX4_NET_TRANS_RULE_ID_TCP: 4366 case MLX4_NET_TRANS_RULE_ID_UDP: 4367 pr_warn("Can't attach FS rule without L2 headers, adding L2 header\n"); 4368 if (add_eth_header(dev, slave, inbox, rlist, header_id)) { 4369 err = -EINVAL; 4370 goto err_put_qp; 4371 } 4372 vhcr->in_modifier += 4373 sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2; 4374 break; 4375 default: 4376 pr_err("Corrupted mailbox\n"); 4377 err = -EINVAL; 4378 goto err_put_qp; 4379 } 4380 4381 execute: 4382 err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param, 4383 vhcr->in_modifier, 0, 4384 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A, 4385 MLX4_CMD_NATIVE); 4386 if (err) 4387 goto err_put_qp; 4388 4389 4390 err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, qpn); 4391 if (err) { 4392 mlx4_err(dev, "Fail to add flow steering resources\n"); 4393 goto err_detach; 4394 } 4395 4396 err = get_res(dev, slave, vhcr->out_param, RES_FS_RULE, &rrule); 4397 if (err) 4398 goto err_detach; 4399 4400 mbox_size = qp_attach_mbox_size(inbox->buf); 4401 rrule->mirr_mbox = kmalloc(mbox_size, GFP_KERNEL); 4402 if (!rrule->mirr_mbox) { 4403 err = -ENOMEM; 4404 goto err_put_rule; 4405 } 4406 rrule->mirr_mbox_size = mbox_size; 4407 rrule->mirr_rule_id = 0; 4408 memcpy(rrule->mirr_mbox, inbox->buf, mbox_size); 4409 4410 /* set different port */ 4411 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)rrule->mirr_mbox; 4412 if (ctrl->port == 1) 4413 ctrl->port = 2; 4414 else 4415 ctrl->port = 1; 4416 4417 if (mlx4_is_bonded(dev)) 4418 mlx4_do_mirror_rule(dev, rrule); 4419 4420 atomic_inc(&rqp->ref_count); 4421 4422 err_put_rule: 4423 put_res(dev, slave, vhcr->out_param, RES_FS_RULE); 4424 err_detach: 4425 /* detach rule on error */ 4426 if (err) 4427 mlx4_cmd(dev, vhcr->out_param, 0, 0, 4428 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A, 4429 MLX4_CMD_NATIVE); 4430 err_put_qp: 4431 put_res(dev, slave, qpn, RES_QP); 4432 return err; 4433 } 4434 4435 static int mlx4_undo_mirror_rule(struct mlx4_dev *dev, struct res_fs_rule *fs_rule) 4436 { 4437 int err; 4438 4439 err = rem_res_range(dev, fs_rule->com.owner, fs_rule->com.res_id, 1, RES_FS_RULE, 0); 4440 if (err) { 4441 mlx4_err(dev, "Fail to remove flow steering resources\n"); 4442 return err; 4443 } 4444 4445 mlx4_cmd(dev, fs_rule->com.res_id, 0, 0, MLX4_QP_FLOW_STEERING_DETACH, 4446 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 4447 return 0; 4448 } 4449 4450 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave, 4451 struct mlx4_vhcr *vhcr, 4452 struct mlx4_cmd_mailbox *inbox, 4453 struct mlx4_cmd_mailbox *outbox, 4454 struct mlx4_cmd_info *cmd) 4455 { 4456 int err; 4457 struct res_qp *rqp; 4458 struct res_fs_rule *rrule; 4459 u64 mirr_reg_id; 4460 4461 if (dev->caps.steering_mode != 4462 MLX4_STEERING_MODE_DEVICE_MANAGED) 4463 return -EOPNOTSUPP; 4464 4465 err = get_res(dev, slave, vhcr->in_param, RES_FS_RULE, &rrule); 4466 if (err) 4467 return err; 4468 4469 if (!rrule->mirr_mbox) { 4470 mlx4_err(dev, "Mirror rules cannot be removed explicitly\n"); 4471 put_res(dev, slave, vhcr->in_param, RES_FS_RULE); 4472 return -EINVAL; 4473 } 4474 mirr_reg_id = rrule->mirr_rule_id; 4475 kfree(rrule->mirr_mbox); 4476 4477 /* Release the rule form busy state before removal */ 4478 put_res(dev, slave, vhcr->in_param, RES_FS_RULE); 4479 err = get_res(dev, slave, rrule->qpn, RES_QP, &rqp); 4480 if (err) 4481 return err; 4482 4483 if (mirr_reg_id && mlx4_is_bonded(dev)) { 4484 err = get_res(dev, slave, mirr_reg_id, RES_FS_RULE, &rrule); 4485 if (err) { 4486 mlx4_err(dev, "Fail to get resource of mirror rule\n"); 4487 } else { 4488 put_res(dev, slave, mirr_reg_id, RES_FS_RULE); 4489 mlx4_undo_mirror_rule(dev, rrule); 4490 } 4491 } 4492 err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0); 4493 if (err) { 4494 mlx4_err(dev, "Fail to remove flow steering resources\n"); 4495 goto out; 4496 } 4497 4498 err = mlx4_cmd(dev, vhcr->in_param, 0, 0, 4499 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A, 4500 MLX4_CMD_NATIVE); 4501 if (!err) 4502 atomic_dec(&rqp->ref_count); 4503 out: 4504 put_res(dev, slave, rrule->qpn, RES_QP); 4505 return err; 4506 } 4507 4508 enum { 4509 BUSY_MAX_RETRIES = 10 4510 }; 4511 4512 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, 4513 struct mlx4_vhcr *vhcr, 4514 struct mlx4_cmd_mailbox *inbox, 4515 struct mlx4_cmd_mailbox *outbox, 4516 struct mlx4_cmd_info *cmd) 4517 { 4518 int err; 4519 int index = vhcr->in_modifier & 0xffff; 4520 4521 err = get_res(dev, slave, index, RES_COUNTER, NULL); 4522 if (err) 4523 return err; 4524 4525 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd); 4526 put_res(dev, slave, index, RES_COUNTER); 4527 return err; 4528 } 4529 4530 static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp) 4531 { 4532 struct res_gid *rgid; 4533 struct res_gid *tmp; 4534 struct mlx4_qp qp; /* dummy for calling attach/detach */ 4535 4536 list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) { 4537 switch (dev->caps.steering_mode) { 4538 case MLX4_STEERING_MODE_DEVICE_MANAGED: 4539 mlx4_flow_detach(dev, rgid->reg_id); 4540 break; 4541 case MLX4_STEERING_MODE_B0: 4542 qp.qpn = rqp->local_qpn; 4543 (void) mlx4_qp_detach_common(dev, &qp, rgid->gid, 4544 rgid->prot, rgid->steer); 4545 break; 4546 } 4547 list_del(&rgid->list); 4548 kfree(rgid); 4549 } 4550 } 4551 4552 static int _move_all_busy(struct mlx4_dev *dev, int slave, 4553 enum mlx4_resource type, int print) 4554 { 4555 struct mlx4_priv *priv = mlx4_priv(dev); 4556 struct mlx4_resource_tracker *tracker = 4557 &priv->mfunc.master.res_tracker; 4558 struct list_head *rlist = &tracker->slave_list[slave].res_list[type]; 4559 struct res_common *r; 4560 struct res_common *tmp; 4561 int busy; 4562 4563 busy = 0; 4564 spin_lock_irq(mlx4_tlock(dev)); 4565 list_for_each_entry_safe(r, tmp, rlist, list) { 4566 if (r->owner == slave) { 4567 if (!r->removing) { 4568 if (r->state == RES_ANY_BUSY) { 4569 if (print) 4570 mlx4_dbg(dev, 4571 "%s id 0x%llx is busy\n", 4572 resource_str(type), 4573 r->res_id); 4574 ++busy; 4575 } else { 4576 r->from_state = r->state; 4577 r->state = RES_ANY_BUSY; 4578 r->removing = 1; 4579 } 4580 } 4581 } 4582 } 4583 spin_unlock_irq(mlx4_tlock(dev)); 4584 4585 return busy; 4586 } 4587 4588 static int move_all_busy(struct mlx4_dev *dev, int slave, 4589 enum mlx4_resource type) 4590 { 4591 unsigned long begin; 4592 int busy; 4593 4594 begin = jiffies; 4595 do { 4596 busy = _move_all_busy(dev, slave, type, 0); 4597 if (time_after(jiffies, begin + 5 * HZ)) 4598 break; 4599 if (busy) 4600 cond_resched(); 4601 } while (busy); 4602 4603 if (busy) 4604 busy = _move_all_busy(dev, slave, type, 1); 4605 4606 return busy; 4607 } 4608 static void rem_slave_qps(struct mlx4_dev *dev, int slave) 4609 { 4610 struct mlx4_priv *priv = mlx4_priv(dev); 4611 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 4612 struct list_head *qp_list = 4613 &tracker->slave_list[slave].res_list[RES_QP]; 4614 struct res_qp *qp; 4615 struct res_qp *tmp; 4616 int state; 4617 u64 in_param; 4618 int qpn; 4619 int err; 4620 4621 err = move_all_busy(dev, slave, RES_QP); 4622 if (err) 4623 mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy for slave %d\n", 4624 slave); 4625 4626 spin_lock_irq(mlx4_tlock(dev)); 4627 list_for_each_entry_safe(qp, tmp, qp_list, com.list) { 4628 spin_unlock_irq(mlx4_tlock(dev)); 4629 if (qp->com.owner == slave) { 4630 qpn = qp->com.res_id; 4631 detach_qp(dev, slave, qp); 4632 state = qp->com.from_state; 4633 while (state != 0) { 4634 switch (state) { 4635 case RES_QP_RESERVED: 4636 spin_lock_irq(mlx4_tlock(dev)); 4637 rb_erase(&qp->com.node, 4638 &tracker->res_tree[RES_QP]); 4639 list_del(&qp->com.list); 4640 spin_unlock_irq(mlx4_tlock(dev)); 4641 if (!valid_reserved(dev, slave, qpn)) { 4642 __mlx4_qp_release_range(dev, qpn, 1); 4643 mlx4_release_resource(dev, slave, 4644 RES_QP, 1, 0); 4645 } 4646 kfree(qp); 4647 state = 0; 4648 break; 4649 case RES_QP_MAPPED: 4650 if (!valid_reserved(dev, slave, qpn)) 4651 __mlx4_qp_free_icm(dev, qpn); 4652 state = RES_QP_RESERVED; 4653 break; 4654 case RES_QP_HW: 4655 in_param = slave; 4656 err = mlx4_cmd(dev, in_param, 4657 qp->local_qpn, 2, 4658 MLX4_CMD_2RST_QP, 4659 MLX4_CMD_TIME_CLASS_A, 4660 MLX4_CMD_NATIVE); 4661 if (err) 4662 mlx4_dbg(dev, "rem_slave_qps: failed to move slave %d qpn %d to reset\n", 4663 slave, qp->local_qpn); 4664 atomic_dec(&qp->rcq->ref_count); 4665 atomic_dec(&qp->scq->ref_count); 4666 atomic_dec(&qp->mtt->ref_count); 4667 if (qp->srq) 4668 atomic_dec(&qp->srq->ref_count); 4669 state = RES_QP_MAPPED; 4670 break; 4671 default: 4672 state = 0; 4673 } 4674 } 4675 } 4676 spin_lock_irq(mlx4_tlock(dev)); 4677 } 4678 spin_unlock_irq(mlx4_tlock(dev)); 4679 } 4680 4681 static void rem_slave_srqs(struct mlx4_dev *dev, int slave) 4682 { 4683 struct mlx4_priv *priv = mlx4_priv(dev); 4684 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 4685 struct list_head *srq_list = 4686 &tracker->slave_list[slave].res_list[RES_SRQ]; 4687 struct res_srq *srq; 4688 struct res_srq *tmp; 4689 int state; 4690 u64 in_param; 4691 LIST_HEAD(tlist); 4692 int srqn; 4693 int err; 4694 4695 err = move_all_busy(dev, slave, RES_SRQ); 4696 if (err) 4697 mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs - too busy for slave %d\n", 4698 slave); 4699 4700 spin_lock_irq(mlx4_tlock(dev)); 4701 list_for_each_entry_safe(srq, tmp, srq_list, com.list) { 4702 spin_unlock_irq(mlx4_tlock(dev)); 4703 if (srq->com.owner == slave) { 4704 srqn = srq->com.res_id; 4705 state = srq->com.from_state; 4706 while (state != 0) { 4707 switch (state) { 4708 case RES_SRQ_ALLOCATED: 4709 __mlx4_srq_free_icm(dev, srqn); 4710 spin_lock_irq(mlx4_tlock(dev)); 4711 rb_erase(&srq->com.node, 4712 &tracker->res_tree[RES_SRQ]); 4713 list_del(&srq->com.list); 4714 spin_unlock_irq(mlx4_tlock(dev)); 4715 mlx4_release_resource(dev, slave, 4716 RES_SRQ, 1, 0); 4717 kfree(srq); 4718 state = 0; 4719 break; 4720 4721 case RES_SRQ_HW: 4722 in_param = slave; 4723 err = mlx4_cmd(dev, in_param, srqn, 1, 4724 MLX4_CMD_HW2SW_SRQ, 4725 MLX4_CMD_TIME_CLASS_A, 4726 MLX4_CMD_NATIVE); 4727 if (err) 4728 mlx4_dbg(dev, "rem_slave_srqs: failed to move slave %d srq %d to SW ownership\n", 4729 slave, srqn); 4730 4731 atomic_dec(&srq->mtt->ref_count); 4732 if (srq->cq) 4733 atomic_dec(&srq->cq->ref_count); 4734 state = RES_SRQ_ALLOCATED; 4735 break; 4736 4737 default: 4738 state = 0; 4739 } 4740 } 4741 } 4742 spin_lock_irq(mlx4_tlock(dev)); 4743 } 4744 spin_unlock_irq(mlx4_tlock(dev)); 4745 } 4746 4747 static void rem_slave_cqs(struct mlx4_dev *dev, int slave) 4748 { 4749 struct mlx4_priv *priv = mlx4_priv(dev); 4750 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 4751 struct list_head *cq_list = 4752 &tracker->slave_list[slave].res_list[RES_CQ]; 4753 struct res_cq *cq; 4754 struct res_cq *tmp; 4755 int state; 4756 u64 in_param; 4757 LIST_HEAD(tlist); 4758 int cqn; 4759 int err; 4760 4761 err = move_all_busy(dev, slave, RES_CQ); 4762 if (err) 4763 mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs - too busy for slave %d\n", 4764 slave); 4765 4766 spin_lock_irq(mlx4_tlock(dev)); 4767 list_for_each_entry_safe(cq, tmp, cq_list, com.list) { 4768 spin_unlock_irq(mlx4_tlock(dev)); 4769 if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) { 4770 cqn = cq->com.res_id; 4771 state = cq->com.from_state; 4772 while (state != 0) { 4773 switch (state) { 4774 case RES_CQ_ALLOCATED: 4775 __mlx4_cq_free_icm(dev, cqn); 4776 spin_lock_irq(mlx4_tlock(dev)); 4777 rb_erase(&cq->com.node, 4778 &tracker->res_tree[RES_CQ]); 4779 list_del(&cq->com.list); 4780 spin_unlock_irq(mlx4_tlock(dev)); 4781 mlx4_release_resource(dev, slave, 4782 RES_CQ, 1, 0); 4783 kfree(cq); 4784 state = 0; 4785 break; 4786 4787 case RES_CQ_HW: 4788 in_param = slave; 4789 err = mlx4_cmd(dev, in_param, cqn, 1, 4790 MLX4_CMD_HW2SW_CQ, 4791 MLX4_CMD_TIME_CLASS_A, 4792 MLX4_CMD_NATIVE); 4793 if (err) 4794 mlx4_dbg(dev, "rem_slave_cqs: failed to move slave %d cq %d to SW ownership\n", 4795 slave, cqn); 4796 atomic_dec(&cq->mtt->ref_count); 4797 state = RES_CQ_ALLOCATED; 4798 break; 4799 4800 default: 4801 state = 0; 4802 } 4803 } 4804 } 4805 spin_lock_irq(mlx4_tlock(dev)); 4806 } 4807 spin_unlock_irq(mlx4_tlock(dev)); 4808 } 4809 4810 static void rem_slave_mrs(struct mlx4_dev *dev, int slave) 4811 { 4812 struct mlx4_priv *priv = mlx4_priv(dev); 4813 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 4814 struct list_head *mpt_list = 4815 &tracker->slave_list[slave].res_list[RES_MPT]; 4816 struct res_mpt *mpt; 4817 struct res_mpt *tmp; 4818 int state; 4819 u64 in_param; 4820 LIST_HEAD(tlist); 4821 int mptn; 4822 int err; 4823 4824 err = move_all_busy(dev, slave, RES_MPT); 4825 if (err) 4826 mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts - too busy for slave %d\n", 4827 slave); 4828 4829 spin_lock_irq(mlx4_tlock(dev)); 4830 list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) { 4831 spin_unlock_irq(mlx4_tlock(dev)); 4832 if (mpt->com.owner == slave) { 4833 mptn = mpt->com.res_id; 4834 state = mpt->com.from_state; 4835 while (state != 0) { 4836 switch (state) { 4837 case RES_MPT_RESERVED: 4838 __mlx4_mpt_release(dev, mpt->key); 4839 spin_lock_irq(mlx4_tlock(dev)); 4840 rb_erase(&mpt->com.node, 4841 &tracker->res_tree[RES_MPT]); 4842 list_del(&mpt->com.list); 4843 spin_unlock_irq(mlx4_tlock(dev)); 4844 mlx4_release_resource(dev, slave, 4845 RES_MPT, 1, 0); 4846 kfree(mpt); 4847 state = 0; 4848 break; 4849 4850 case RES_MPT_MAPPED: 4851 __mlx4_mpt_free_icm(dev, mpt->key); 4852 state = RES_MPT_RESERVED; 4853 break; 4854 4855 case RES_MPT_HW: 4856 in_param = slave; 4857 err = mlx4_cmd(dev, in_param, mptn, 0, 4858 MLX4_CMD_HW2SW_MPT, 4859 MLX4_CMD_TIME_CLASS_A, 4860 MLX4_CMD_NATIVE); 4861 if (err) 4862 mlx4_dbg(dev, "rem_slave_mrs: failed to move slave %d mpt %d to SW ownership\n", 4863 slave, mptn); 4864 if (mpt->mtt) 4865 atomic_dec(&mpt->mtt->ref_count); 4866 state = RES_MPT_MAPPED; 4867 break; 4868 default: 4869 state = 0; 4870 } 4871 } 4872 } 4873 spin_lock_irq(mlx4_tlock(dev)); 4874 } 4875 spin_unlock_irq(mlx4_tlock(dev)); 4876 } 4877 4878 static void rem_slave_mtts(struct mlx4_dev *dev, int slave) 4879 { 4880 struct mlx4_priv *priv = mlx4_priv(dev); 4881 struct mlx4_resource_tracker *tracker = 4882 &priv->mfunc.master.res_tracker; 4883 struct list_head *mtt_list = 4884 &tracker->slave_list[slave].res_list[RES_MTT]; 4885 struct res_mtt *mtt; 4886 struct res_mtt *tmp; 4887 int state; 4888 LIST_HEAD(tlist); 4889 int base; 4890 int err; 4891 4892 err = move_all_busy(dev, slave, RES_MTT); 4893 if (err) 4894 mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts - too busy for slave %d\n", 4895 slave); 4896 4897 spin_lock_irq(mlx4_tlock(dev)); 4898 list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) { 4899 spin_unlock_irq(mlx4_tlock(dev)); 4900 if (mtt->com.owner == slave) { 4901 base = mtt->com.res_id; 4902 state = mtt->com.from_state; 4903 while (state != 0) { 4904 switch (state) { 4905 case RES_MTT_ALLOCATED: 4906 __mlx4_free_mtt_range(dev, base, 4907 mtt->order); 4908 spin_lock_irq(mlx4_tlock(dev)); 4909 rb_erase(&mtt->com.node, 4910 &tracker->res_tree[RES_MTT]); 4911 list_del(&mtt->com.list); 4912 spin_unlock_irq(mlx4_tlock(dev)); 4913 mlx4_release_resource(dev, slave, RES_MTT, 4914 1 << mtt->order, 0); 4915 kfree(mtt); 4916 state = 0; 4917 break; 4918 4919 default: 4920 state = 0; 4921 } 4922 } 4923 } 4924 spin_lock_irq(mlx4_tlock(dev)); 4925 } 4926 spin_unlock_irq(mlx4_tlock(dev)); 4927 } 4928 4929 static int mlx4_do_mirror_rule(struct mlx4_dev *dev, struct res_fs_rule *fs_rule) 4930 { 4931 struct mlx4_cmd_mailbox *mailbox; 4932 int err; 4933 struct res_fs_rule *mirr_rule; 4934 u64 reg_id; 4935 4936 mailbox = mlx4_alloc_cmd_mailbox(dev); 4937 if (IS_ERR(mailbox)) 4938 return PTR_ERR(mailbox); 4939 4940 if (!fs_rule->mirr_mbox) { 4941 mlx4_err(dev, "rule mirroring mailbox is null\n"); 4942 return -EINVAL; 4943 } 4944 memcpy(mailbox->buf, fs_rule->mirr_mbox, fs_rule->mirr_mbox_size); 4945 err = mlx4_cmd_imm(dev, mailbox->dma, ®_id, fs_rule->mirr_mbox_size >> 2, 0, 4946 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A, 4947 MLX4_CMD_NATIVE); 4948 mlx4_free_cmd_mailbox(dev, mailbox); 4949 4950 if (err) 4951 goto err; 4952 4953 err = add_res_range(dev, fs_rule->com.owner, reg_id, 1, RES_FS_RULE, fs_rule->qpn); 4954 if (err) 4955 goto err_detach; 4956 4957 err = get_res(dev, fs_rule->com.owner, reg_id, RES_FS_RULE, &mirr_rule); 4958 if (err) 4959 goto err_rem; 4960 4961 fs_rule->mirr_rule_id = reg_id; 4962 mirr_rule->mirr_rule_id = 0; 4963 mirr_rule->mirr_mbox_size = 0; 4964 mirr_rule->mirr_mbox = NULL; 4965 put_res(dev, fs_rule->com.owner, reg_id, RES_FS_RULE); 4966 4967 return 0; 4968 err_rem: 4969 rem_res_range(dev, fs_rule->com.owner, reg_id, 1, RES_FS_RULE, 0); 4970 err_detach: 4971 mlx4_cmd(dev, reg_id, 0, 0, MLX4_QP_FLOW_STEERING_DETACH, 4972 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 4973 err: 4974 return err; 4975 } 4976 4977 static int mlx4_mirror_fs_rules(struct mlx4_dev *dev, bool bond) 4978 { 4979 struct mlx4_priv *priv = mlx4_priv(dev); 4980 struct mlx4_resource_tracker *tracker = 4981 &priv->mfunc.master.res_tracker; 4982 struct rb_root *root = &tracker->res_tree[RES_FS_RULE]; 4983 struct rb_node *p; 4984 struct res_fs_rule *fs_rule; 4985 int err = 0; 4986 LIST_HEAD(mirr_list); 4987 4988 for (p = rb_first(root); p; p = rb_next(p)) { 4989 fs_rule = rb_entry(p, struct res_fs_rule, com.node); 4990 if ((bond && fs_rule->mirr_mbox_size) || 4991 (!bond && !fs_rule->mirr_mbox_size)) 4992 list_add_tail(&fs_rule->mirr_list, &mirr_list); 4993 } 4994 4995 list_for_each_entry(fs_rule, &mirr_list, mirr_list) { 4996 if (bond) 4997 err += mlx4_do_mirror_rule(dev, fs_rule); 4998 else 4999 err += mlx4_undo_mirror_rule(dev, fs_rule); 5000 } 5001 return err; 5002 } 5003 5004 int mlx4_bond_fs_rules(struct mlx4_dev *dev) 5005 { 5006 return mlx4_mirror_fs_rules(dev, true); 5007 } 5008 5009 int mlx4_unbond_fs_rules(struct mlx4_dev *dev) 5010 { 5011 return mlx4_mirror_fs_rules(dev, false); 5012 } 5013 5014 static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave) 5015 { 5016 struct mlx4_priv *priv = mlx4_priv(dev); 5017 struct mlx4_resource_tracker *tracker = 5018 &priv->mfunc.master.res_tracker; 5019 struct list_head *fs_rule_list = 5020 &tracker->slave_list[slave].res_list[RES_FS_RULE]; 5021 struct res_fs_rule *fs_rule; 5022 struct res_fs_rule *tmp; 5023 int state; 5024 u64 base; 5025 int err; 5026 5027 err = move_all_busy(dev, slave, RES_FS_RULE); 5028 if (err) 5029 mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n", 5030 slave); 5031 5032 spin_lock_irq(mlx4_tlock(dev)); 5033 list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) { 5034 spin_unlock_irq(mlx4_tlock(dev)); 5035 if (fs_rule->com.owner == slave) { 5036 base = fs_rule->com.res_id; 5037 state = fs_rule->com.from_state; 5038 while (state != 0) { 5039 switch (state) { 5040 case RES_FS_RULE_ALLOCATED: 5041 /* detach rule */ 5042 err = mlx4_cmd(dev, base, 0, 0, 5043 MLX4_QP_FLOW_STEERING_DETACH, 5044 MLX4_CMD_TIME_CLASS_A, 5045 MLX4_CMD_NATIVE); 5046 5047 spin_lock_irq(mlx4_tlock(dev)); 5048 rb_erase(&fs_rule->com.node, 5049 &tracker->res_tree[RES_FS_RULE]); 5050 list_del(&fs_rule->com.list); 5051 spin_unlock_irq(mlx4_tlock(dev)); 5052 kfree(fs_rule); 5053 state = 0; 5054 break; 5055 5056 default: 5057 state = 0; 5058 } 5059 } 5060 } 5061 spin_lock_irq(mlx4_tlock(dev)); 5062 } 5063 spin_unlock_irq(mlx4_tlock(dev)); 5064 } 5065 5066 static void rem_slave_eqs(struct mlx4_dev *dev, int slave) 5067 { 5068 struct mlx4_priv *priv = mlx4_priv(dev); 5069 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 5070 struct list_head *eq_list = 5071 &tracker->slave_list[slave].res_list[RES_EQ]; 5072 struct res_eq *eq; 5073 struct res_eq *tmp; 5074 int err; 5075 int state; 5076 LIST_HEAD(tlist); 5077 int eqn; 5078 5079 err = move_all_busy(dev, slave, RES_EQ); 5080 if (err) 5081 mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs - too busy for slave %d\n", 5082 slave); 5083 5084 spin_lock_irq(mlx4_tlock(dev)); 5085 list_for_each_entry_safe(eq, tmp, eq_list, com.list) { 5086 spin_unlock_irq(mlx4_tlock(dev)); 5087 if (eq->com.owner == slave) { 5088 eqn = eq->com.res_id; 5089 state = eq->com.from_state; 5090 while (state != 0) { 5091 switch (state) { 5092 case RES_EQ_RESERVED: 5093 spin_lock_irq(mlx4_tlock(dev)); 5094 rb_erase(&eq->com.node, 5095 &tracker->res_tree[RES_EQ]); 5096 list_del(&eq->com.list); 5097 spin_unlock_irq(mlx4_tlock(dev)); 5098 kfree(eq); 5099 state = 0; 5100 break; 5101 5102 case RES_EQ_HW: 5103 err = mlx4_cmd(dev, slave, eqn & 0x3ff, 5104 1, MLX4_CMD_HW2SW_EQ, 5105 MLX4_CMD_TIME_CLASS_A, 5106 MLX4_CMD_NATIVE); 5107 if (err) 5108 mlx4_dbg(dev, "rem_slave_eqs: failed to move slave %d eqs %d to SW ownership\n", 5109 slave, eqn & 0x3ff); 5110 atomic_dec(&eq->mtt->ref_count); 5111 state = RES_EQ_RESERVED; 5112 break; 5113 5114 default: 5115 state = 0; 5116 } 5117 } 5118 } 5119 spin_lock_irq(mlx4_tlock(dev)); 5120 } 5121 spin_unlock_irq(mlx4_tlock(dev)); 5122 } 5123 5124 static void rem_slave_counters(struct mlx4_dev *dev, int slave) 5125 { 5126 struct mlx4_priv *priv = mlx4_priv(dev); 5127 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 5128 struct list_head *counter_list = 5129 &tracker->slave_list[slave].res_list[RES_COUNTER]; 5130 struct res_counter *counter; 5131 struct res_counter *tmp; 5132 int err; 5133 int *counters_arr = NULL; 5134 int i, j; 5135 5136 err = move_all_busy(dev, slave, RES_COUNTER); 5137 if (err) 5138 mlx4_warn(dev, "rem_slave_counters: Could not move all counters - too busy for slave %d\n", 5139 slave); 5140 5141 counters_arr = kmalloc_array(dev->caps.max_counters, 5142 sizeof(*counters_arr), GFP_KERNEL); 5143 if (!counters_arr) 5144 return; 5145 5146 do { 5147 i = 0; 5148 j = 0; 5149 spin_lock_irq(mlx4_tlock(dev)); 5150 list_for_each_entry_safe(counter, tmp, counter_list, com.list) { 5151 if (counter->com.owner == slave) { 5152 counters_arr[i++] = counter->com.res_id; 5153 rb_erase(&counter->com.node, 5154 &tracker->res_tree[RES_COUNTER]); 5155 list_del(&counter->com.list); 5156 kfree(counter); 5157 } 5158 } 5159 spin_unlock_irq(mlx4_tlock(dev)); 5160 5161 while (j < i) { 5162 __mlx4_counter_free(dev, counters_arr[j++]); 5163 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0); 5164 } 5165 } while (i); 5166 5167 kfree(counters_arr); 5168 } 5169 5170 static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave) 5171 { 5172 struct mlx4_priv *priv = mlx4_priv(dev); 5173 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker; 5174 struct list_head *xrcdn_list = 5175 &tracker->slave_list[slave].res_list[RES_XRCD]; 5176 struct res_xrcdn *xrcd; 5177 struct res_xrcdn *tmp; 5178 int err; 5179 int xrcdn; 5180 5181 err = move_all_busy(dev, slave, RES_XRCD); 5182 if (err) 5183 mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns - too busy for slave %d\n", 5184 slave); 5185 5186 spin_lock_irq(mlx4_tlock(dev)); 5187 list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) { 5188 if (xrcd->com.owner == slave) { 5189 xrcdn = xrcd->com.res_id; 5190 rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]); 5191 list_del(&xrcd->com.list); 5192 kfree(xrcd); 5193 __mlx4_xrcd_free(dev, xrcdn); 5194 } 5195 } 5196 spin_unlock_irq(mlx4_tlock(dev)); 5197 } 5198 5199 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave) 5200 { 5201 struct mlx4_priv *priv = mlx4_priv(dev); 5202 mlx4_reset_roce_gids(dev, slave); 5203 mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex); 5204 rem_slave_vlans(dev, slave); 5205 rem_slave_macs(dev, slave); 5206 rem_slave_fs_rule(dev, slave); 5207 rem_slave_qps(dev, slave); 5208 rem_slave_srqs(dev, slave); 5209 rem_slave_cqs(dev, slave); 5210 rem_slave_mrs(dev, slave); 5211 rem_slave_eqs(dev, slave); 5212 rem_slave_mtts(dev, slave); 5213 rem_slave_counters(dev, slave); 5214 rem_slave_xrcdns(dev, slave); 5215 mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex); 5216 } 5217 5218 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work) 5219 { 5220 struct mlx4_vf_immed_vlan_work *work = 5221 container_of(_work, struct mlx4_vf_immed_vlan_work, work); 5222 struct mlx4_cmd_mailbox *mailbox; 5223 struct mlx4_update_qp_context *upd_context; 5224 struct mlx4_dev *dev = &work->priv->dev; 5225 struct mlx4_resource_tracker *tracker = 5226 &work->priv->mfunc.master.res_tracker; 5227 struct list_head *qp_list = 5228 &tracker->slave_list[work->slave].res_list[RES_QP]; 5229 struct res_qp *qp; 5230 struct res_qp *tmp; 5231 u64 qp_path_mask_vlan_ctrl = 5232 ((1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED) | 5233 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P) | 5234 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED) | 5235 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED) | 5236 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P) | 5237 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED)); 5238 5239 u64 qp_path_mask = ((1ULL << MLX4_UPD_QP_PATH_MASK_VLAN_INDEX) | 5240 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL) | 5241 (1ULL << MLX4_UPD_QP_PATH_MASK_CV) | 5242 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN) | 5243 (1ULL << MLX4_UPD_QP_PATH_MASK_FEUP) | 5244 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL_RX) | 5245 (1ULL << MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE)); 5246 5247 int err; 5248 int port, errors = 0; 5249 u8 vlan_control; 5250 5251 if (mlx4_is_slave(dev)) { 5252 mlx4_warn(dev, "Trying to update-qp in slave %d\n", 5253 work->slave); 5254 goto out; 5255 } 5256 5257 mailbox = mlx4_alloc_cmd_mailbox(dev); 5258 if (IS_ERR(mailbox)) 5259 goto out; 5260 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE) /* block all */ 5261 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED | 5262 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED | 5263 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED | 5264 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED | 5265 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED | 5266 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED; 5267 else if (!work->vlan_id) 5268 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED | 5269 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED; 5270 else 5271 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED | 5272 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED | 5273 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED; 5274 5275 upd_context = mailbox->buf; 5276 upd_context->qp_mask = cpu_to_be64(1ULL << MLX4_UPD_QP_MASK_VSD); 5277 5278 spin_lock_irq(mlx4_tlock(dev)); 5279 list_for_each_entry_safe(qp, tmp, qp_list, com.list) { 5280 spin_unlock_irq(mlx4_tlock(dev)); 5281 if (qp->com.owner == work->slave) { 5282 if (qp->com.from_state != RES_QP_HW || 5283 !qp->sched_queue || /* no INIT2RTR trans yet */ 5284 mlx4_is_qp_reserved(dev, qp->local_qpn) || 5285 qp->qpc_flags & (1 << MLX4_RSS_QPC_FLAG_OFFSET)) { 5286 spin_lock_irq(mlx4_tlock(dev)); 5287 continue; 5288 } 5289 port = (qp->sched_queue >> 6 & 1) + 1; 5290 if (port != work->port) { 5291 spin_lock_irq(mlx4_tlock(dev)); 5292 continue; 5293 } 5294 if (MLX4_QP_ST_RC == ((qp->qpc_flags >> 16) & 0xff)) 5295 upd_context->primary_addr_path_mask = cpu_to_be64(qp_path_mask); 5296 else 5297 upd_context->primary_addr_path_mask = 5298 cpu_to_be64(qp_path_mask | qp_path_mask_vlan_ctrl); 5299 if (work->vlan_id == MLX4_VGT) { 5300 upd_context->qp_context.param3 = qp->param3; 5301 upd_context->qp_context.pri_path.vlan_control = qp->vlan_control; 5302 upd_context->qp_context.pri_path.fvl_rx = qp->fvl_rx; 5303 upd_context->qp_context.pri_path.vlan_index = qp->vlan_index; 5304 upd_context->qp_context.pri_path.fl = qp->pri_path_fl; 5305 upd_context->qp_context.pri_path.feup = qp->feup; 5306 upd_context->qp_context.pri_path.sched_queue = 5307 qp->sched_queue; 5308 } else { 5309 upd_context->qp_context.param3 = qp->param3 & ~cpu_to_be32(MLX4_STRIP_VLAN); 5310 upd_context->qp_context.pri_path.vlan_control = vlan_control; 5311 upd_context->qp_context.pri_path.vlan_index = work->vlan_ix; 5312 upd_context->qp_context.pri_path.fvl_rx = 5313 qp->fvl_rx | MLX4_FVL_RX_FORCE_ETH_VLAN; 5314 upd_context->qp_context.pri_path.fl = 5315 qp->pri_path_fl | MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN; 5316 upd_context->qp_context.pri_path.feup = 5317 qp->feup | MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN; 5318 upd_context->qp_context.pri_path.sched_queue = 5319 qp->sched_queue & 0xC7; 5320 upd_context->qp_context.pri_path.sched_queue |= 5321 ((work->qos & 0x7) << 3); 5322 upd_context->qp_mask |= 5323 cpu_to_be64(1ULL << 5324 MLX4_UPD_QP_MASK_QOS_VPP); 5325 upd_context->qp_context.qos_vport = 5326 work->qos_vport; 5327 } 5328 5329 err = mlx4_cmd(dev, mailbox->dma, 5330 qp->local_qpn & 0xffffff, 5331 0, MLX4_CMD_UPDATE_QP, 5332 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 5333 if (err) { 5334 mlx4_info(dev, "UPDATE_QP failed for slave %d, port %d, qpn %d (%d)\n", 5335 work->slave, port, qp->local_qpn, err); 5336 errors++; 5337 } 5338 } 5339 spin_lock_irq(mlx4_tlock(dev)); 5340 } 5341 spin_unlock_irq(mlx4_tlock(dev)); 5342 mlx4_free_cmd_mailbox(dev, mailbox); 5343 5344 if (errors) 5345 mlx4_err(dev, "%d UPDATE_QP failures for slave %d, port %d\n", 5346 errors, work->slave, work->port); 5347 5348 /* unregister previous vlan_id if needed and we had no errors 5349 * while updating the QPs 5350 */ 5351 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN && !errors && 5352 NO_INDX != work->orig_vlan_ix) 5353 __mlx4_unregister_vlan(&work->priv->dev, work->port, 5354 work->orig_vlan_id); 5355 out: 5356 kfree(work); 5357 return; 5358 } 5359