1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36 #include <linux/module.h> 37 #include <linux/init.h> 38 #include <linux/errno.h> 39 #include <linux/pci.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/slab.h> 42 #include <linux/io-mapping.h> 43 #include <linux/delay.h> 44 #include <linux/kmod.h> 45 46 #include <linux/mlx4/device.h> 47 #include <linux/mlx4/doorbell.h> 48 49 #include "mlx4.h" 50 #include "fw.h" 51 #include "icm.h" 52 53 MODULE_AUTHOR("Roland Dreier"); 54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); 55 MODULE_LICENSE("Dual BSD/GPL"); 56 MODULE_VERSION(DRV_VERSION); 57 58 struct workqueue_struct *mlx4_wq; 59 60 #ifdef CONFIG_MLX4_DEBUG 61 62 int mlx4_debug_level = 0; 63 module_param_named(debug_level, mlx4_debug_level, int, 0644); 64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); 65 66 #endif /* CONFIG_MLX4_DEBUG */ 67 68 #ifdef CONFIG_PCI_MSI 69 70 static int msi_x = 1; 71 module_param(msi_x, int, 0444); 72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero"); 73 74 #else /* CONFIG_PCI_MSI */ 75 76 #define msi_x (0) 77 78 #endif /* CONFIG_PCI_MSI */ 79 80 static uint8_t num_vfs[3] = {0, 0, 0}; 81 static int num_vfs_argc; 82 module_param_array(num_vfs, byte , &num_vfs_argc, 0444); 83 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n" 84 "num_vfs=port1,port2,port1+2"); 85 86 static uint8_t probe_vf[3] = {0, 0, 0}; 87 static int probe_vfs_argc; 88 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444); 89 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n" 90 "probe_vf=port1,port2,port1+2"); 91 92 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 93 module_param_named(log_num_mgm_entry_size, 94 mlx4_log_num_mgm_entry_size, int, 0444); 95 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" 96 " of qp per mcg, for example:" 97 " 10 gives 248.range: 7 <=" 98 " log_num_mgm_entry_size <= 12." 99 " To activate device managed" 100 " flow steering when available, set to -1"); 101 102 static bool enable_64b_cqe_eqe = true; 103 module_param(enable_64b_cqe_eqe, bool, 0444); 104 MODULE_PARM_DESC(enable_64b_cqe_eqe, 105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)"); 106 107 #define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \ 108 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \ 109 MLX4_FUNC_CAP_DMFS_A0_STATIC) 110 111 static char mlx4_version[] = 112 DRV_NAME ": Mellanox ConnectX core driver v" 113 DRV_VERSION " (" DRV_RELDATE ")\n"; 114 115 static struct mlx4_profile default_profile = { 116 .num_qp = 1 << 18, 117 .num_srq = 1 << 16, 118 .rdmarc_per_qp = 1 << 4, 119 .num_cq = 1 << 16, 120 .num_mcg = 1 << 13, 121 .num_mpt = 1 << 19, 122 .num_mtt = 1 << 20, /* It is really num mtt segements */ 123 }; 124 125 static struct mlx4_profile low_mem_profile = { 126 .num_qp = 1 << 17, 127 .num_srq = 1 << 6, 128 .rdmarc_per_qp = 1 << 4, 129 .num_cq = 1 << 8, 130 .num_mcg = 1 << 8, 131 .num_mpt = 1 << 9, 132 .num_mtt = 1 << 7, 133 }; 134 135 static int log_num_mac = 7; 136 module_param_named(log_num_mac, log_num_mac, int, 0444); 137 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); 138 139 static int log_num_vlan; 140 module_param_named(log_num_vlan, log_num_vlan, int, 0444); 141 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); 142 /* Log2 max number of VLANs per ETH port (0-7) */ 143 #define MLX4_LOG_NUM_VLANS 7 144 #define MLX4_MIN_LOG_NUM_VLANS 0 145 #define MLX4_MIN_LOG_NUM_MAC 1 146 147 static bool use_prio; 148 module_param_named(use_prio, use_prio, bool, 0444); 149 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)"); 150 151 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG); 152 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); 153 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)"); 154 155 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; 156 static int arr_argc = 2; 157 module_param_array(port_type_array, int, &arr_argc, 0444); 158 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " 159 "1 for IB, 2 for Ethernet"); 160 161 struct mlx4_port_config { 162 struct list_head list; 163 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 164 struct pci_dev *pdev; 165 }; 166 167 static atomic_t pf_loading = ATOMIC_INIT(0); 168 169 int mlx4_check_port_params(struct mlx4_dev *dev, 170 enum mlx4_port_type *port_type) 171 { 172 int i; 173 174 for (i = 0; i < dev->caps.num_ports - 1; i++) { 175 if (port_type[i] != port_type[i + 1]) { 176 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { 177 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n"); 178 return -EINVAL; 179 } 180 } 181 } 182 183 for (i = 0; i < dev->caps.num_ports; i++) { 184 if (!(port_type[i] & dev->caps.supported_type[i+1])) { 185 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n", 186 i + 1); 187 return -EINVAL; 188 } 189 } 190 return 0; 191 } 192 193 static void mlx4_set_port_mask(struct mlx4_dev *dev) 194 { 195 int i; 196 197 for (i = 1; i <= dev->caps.num_ports; ++i) 198 dev->caps.port_mask[i] = dev->caps.port_type[i]; 199 } 200 201 enum { 202 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0, 203 }; 204 205 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 206 { 207 int err = 0; 208 struct mlx4_func func; 209 210 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 211 err = mlx4_QUERY_FUNC(dev, &func, 0); 212 if (err) { 213 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 214 return err; 215 } 216 dev_cap->max_eqs = func.max_eq; 217 dev_cap->reserved_eqs = func.rsvd_eqs; 218 dev_cap->reserved_uars = func.rsvd_uars; 219 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS; 220 } 221 return err; 222 } 223 224 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev) 225 { 226 struct mlx4_caps *dev_cap = &dev->caps; 227 228 /* FW not supporting or cancelled by user */ 229 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) || 230 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) 231 return; 232 233 /* Must have 64B CQE_EQE enabled by FW to use bigger stride 234 * When FW has NCSI it may decide not to report 64B CQE/EQEs 235 */ 236 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) || 237 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) { 238 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 239 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 240 return; 241 } 242 243 if (cache_line_size() == 128 || cache_line_size() == 256) { 244 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n"); 245 /* Changing the real data inside CQE size to 32B */ 246 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 247 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 248 249 if (mlx4_is_master(dev)) 250 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE; 251 } else { 252 mlx4_dbg(dev, "Disabling CQE stride cacheLine unsupported\n"); 253 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 254 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 255 } 256 } 257 258 static int _mlx4_dev_port(struct mlx4_dev *dev, int port, 259 struct mlx4_port_cap *port_cap) 260 { 261 dev->caps.vl_cap[port] = port_cap->max_vl; 262 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu; 263 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids; 264 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys; 265 /* set gid and pkey table operating lengths by default 266 * to non-sriov values 267 */ 268 dev->caps.gid_table_len[port] = port_cap->max_gids; 269 dev->caps.pkey_table_len[port] = port_cap->max_pkeys; 270 dev->caps.port_width_cap[port] = port_cap->max_port_width; 271 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu; 272 dev->caps.def_mac[port] = port_cap->def_mac; 273 dev->caps.supported_type[port] = port_cap->supported_port_types; 274 dev->caps.suggested_type[port] = port_cap->suggested_type; 275 dev->caps.default_sense[port] = port_cap->default_sense; 276 dev->caps.trans_type[port] = port_cap->trans_type; 277 dev->caps.vendor_oui[port] = port_cap->vendor_oui; 278 dev->caps.wavelength[port] = port_cap->wavelength; 279 dev->caps.trans_code[port] = port_cap->trans_code; 280 281 return 0; 282 } 283 284 static int mlx4_dev_port(struct mlx4_dev *dev, int port, 285 struct mlx4_port_cap *port_cap) 286 { 287 int err = 0; 288 289 err = mlx4_QUERY_PORT(dev, port, port_cap); 290 291 if (err) 292 mlx4_err(dev, "QUERY_PORT command failed.\n"); 293 294 return err; 295 } 296 297 #define MLX4_A0_STEERING_TABLE_SIZE 256 298 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 299 { 300 int err; 301 int i; 302 303 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 304 if (err) { 305 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 306 return err; 307 } 308 309 if (dev_cap->min_page_sz > PAGE_SIZE) { 310 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 311 dev_cap->min_page_sz, PAGE_SIZE); 312 return -ENODEV; 313 } 314 if (dev_cap->num_ports > MLX4_MAX_PORTS) { 315 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 316 dev_cap->num_ports, MLX4_MAX_PORTS); 317 return -ENODEV; 318 } 319 320 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) { 321 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 322 dev_cap->uar_size, 323 (unsigned long long) pci_resource_len(dev->pdev, 2)); 324 return -ENODEV; 325 } 326 327 dev->caps.num_ports = dev_cap->num_ports; 328 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs; 329 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ? 330 dev->caps.num_sys_eqs : 331 MLX4_MAX_EQ_NUM; 332 for (i = 1; i <= dev->caps.num_ports; ++i) { 333 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i); 334 if (err) { 335 mlx4_err(dev, "QUERY_PORT command failed, aborting\n"); 336 return err; 337 } 338 } 339 340 dev->caps.uar_page_size = PAGE_SIZE; 341 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; 342 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; 343 dev->caps.bf_reg_size = dev_cap->bf_reg_size; 344 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; 345 dev->caps.max_sq_sg = dev_cap->max_sq_sg; 346 dev->caps.max_rq_sg = dev_cap->max_rq_sg; 347 dev->caps.max_wqes = dev_cap->max_qp_sz; 348 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; 349 dev->caps.max_srq_wqes = dev_cap->max_srq_sz; 350 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; 351 dev->caps.reserved_srqs = dev_cap->reserved_srqs; 352 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; 353 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; 354 /* 355 * Subtract 1 from the limit because we need to allocate a 356 * spare CQE so the HCA HW can tell the difference between an 357 * empty CQ and a full CQ. 358 */ 359 dev->caps.max_cqes = dev_cap->max_cq_sz - 1; 360 dev->caps.reserved_cqs = dev_cap->reserved_cqs; 361 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 362 dev->caps.reserved_mtts = dev_cap->reserved_mtts; 363 dev->caps.reserved_mrws = dev_cap->reserved_mrws; 364 365 /* The first 128 UARs are used for EQ doorbells */ 366 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars); 367 dev->caps.reserved_pds = dev_cap->reserved_pds; 368 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 369 dev_cap->reserved_xrcds : 0; 370 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 371 dev_cap->max_xrcds : 0; 372 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; 373 374 dev->caps.max_msg_sz = dev_cap->max_msg_sz; 375 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); 376 dev->caps.flags = dev_cap->flags; 377 dev->caps.flags2 = dev_cap->flags2; 378 dev->caps.bmme_flags = dev_cap->bmme_flags; 379 dev->caps.reserved_lkey = dev_cap->reserved_lkey; 380 dev->caps.stat_rate_support = dev_cap->stat_rate_support; 381 dev->caps.max_gso_sz = dev_cap->max_gso_sz; 382 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; 383 384 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ 385 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) 386 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 387 /* Don't do sense port on multifunction devices (for now at least) */ 388 if (mlx4_is_mfunc(dev)) 389 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 390 391 if (mlx4_low_memory_profile()) { 392 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC; 393 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS; 394 } else { 395 dev->caps.log_num_macs = log_num_mac; 396 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; 397 } 398 399 for (i = 1; i <= dev->caps.num_ports; ++i) { 400 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; 401 if (dev->caps.supported_type[i]) { 402 /* if only ETH is supported - assign ETH */ 403 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) 404 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; 405 /* if only IB is supported, assign IB */ 406 else if (dev->caps.supported_type[i] == 407 MLX4_PORT_TYPE_IB) 408 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; 409 else { 410 /* if IB and ETH are supported, we set the port 411 * type according to user selection of port type; 412 * if user selected none, take the FW hint */ 413 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) 414 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? 415 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; 416 else 417 dev->caps.port_type[i] = port_type_array[i - 1]; 418 } 419 } 420 /* 421 * Link sensing is allowed on the port if 3 conditions are true: 422 * 1. Both protocols are supported on the port. 423 * 2. Different types are supported on the port 424 * 3. FW declared that it supports link sensing 425 */ 426 mlx4_priv(dev)->sense.sense_allowed[i] = 427 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && 428 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 429 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); 430 431 /* 432 * If "default_sense" bit is set, we move the port to "AUTO" mode 433 * and perform sense_port FW command to try and set the correct 434 * port type from beginning 435 */ 436 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { 437 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; 438 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; 439 mlx4_SENSE_PORT(dev, i, &sensed_port); 440 if (sensed_port != MLX4_PORT_TYPE_NONE) 441 dev->caps.port_type[i] = sensed_port; 442 } else { 443 dev->caps.possible_type[i] = dev->caps.port_type[i]; 444 } 445 446 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) { 447 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs; 448 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n", 449 i, 1 << dev->caps.log_num_macs); 450 } 451 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) { 452 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans; 453 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n", 454 i, 1 << dev->caps.log_num_vlans); 455 } 456 } 457 458 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters); 459 460 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; 461 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = 462 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = 463 (1 << dev->caps.log_num_macs) * 464 (1 << dev->caps.log_num_vlans) * 465 dev->caps.num_ports; 466 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; 467 468 if (dev_cap->dmfs_high_rate_qpn_base > 0 && 469 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) 470 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base; 471 else 472 dev->caps.dmfs_high_rate_qpn_base = 473 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 474 475 if (dev_cap->dmfs_high_rate_qpn_range > 0 && 476 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) { 477 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range; 478 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT; 479 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0; 480 } else { 481 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED; 482 dev->caps.dmfs_high_rate_qpn_base = 483 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 484 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE; 485 } 486 487 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] = 488 dev->caps.dmfs_high_rate_qpn_range; 489 490 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + 491 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + 492 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + 493 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; 494 495 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; 496 497 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) { 498 if (dev_cap->flags & 499 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { 500 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); 501 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 502 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 503 } 504 505 if (dev_cap->flags2 & 506 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE | 507 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) { 508 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n"); 509 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 510 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 511 } 512 } 513 514 if ((dev->caps.flags & 515 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && 516 mlx4_is_master(dev)) 517 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; 518 519 if (!mlx4_is_slave(dev)) { 520 mlx4_enable_cqe_eqe_stride(dev); 521 dev->caps.alloc_res_qp_mask = 522 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) | 523 MLX4_RESERVE_A0_QP; 524 } else { 525 dev->caps.alloc_res_qp_mask = 0; 526 } 527 528 return 0; 529 } 530 531 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev, 532 enum pci_bus_speed *speed, 533 enum pcie_link_width *width) 534 { 535 u32 lnkcap1, lnkcap2; 536 int err1, err2; 537 538 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */ 539 540 *speed = PCI_SPEED_UNKNOWN; 541 *width = PCIE_LNK_WIDTH_UNKNOWN; 542 543 err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1); 544 err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2); 545 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */ 546 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 547 *speed = PCIE_SPEED_8_0GT; 548 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 549 *speed = PCIE_SPEED_5_0GT; 550 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 551 *speed = PCIE_SPEED_2_5GT; 552 } 553 if (!err1) { 554 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT; 555 if (!lnkcap2) { /* pre-r3.0 */ 556 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB) 557 *speed = PCIE_SPEED_5_0GT; 558 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB) 559 *speed = PCIE_SPEED_2_5GT; 560 } 561 } 562 563 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) { 564 return err1 ? err1 : 565 err2 ? err2 : -EINVAL; 566 } 567 return 0; 568 } 569 570 static void mlx4_check_pcie_caps(struct mlx4_dev *dev) 571 { 572 enum pcie_link_width width, width_cap; 573 enum pci_bus_speed speed, speed_cap; 574 int err; 575 576 #define PCIE_SPEED_STR(speed) \ 577 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \ 578 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \ 579 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \ 580 "Unknown") 581 582 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap); 583 if (err) { 584 mlx4_warn(dev, 585 "Unable to determine PCIe device BW capabilities\n"); 586 return; 587 } 588 589 err = pcie_get_minimum_link(dev->pdev, &speed, &width); 590 if (err || speed == PCI_SPEED_UNKNOWN || 591 width == PCIE_LNK_WIDTH_UNKNOWN) { 592 mlx4_warn(dev, 593 "Unable to determine PCI device chain minimum BW\n"); 594 return; 595 } 596 597 if (width != width_cap || speed != speed_cap) 598 mlx4_warn(dev, 599 "PCIe BW is different than device's capability\n"); 600 601 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n", 602 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap)); 603 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n", 604 width, width_cap); 605 return; 606 } 607 608 /*The function checks if there are live vf, return the num of them*/ 609 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) 610 { 611 struct mlx4_priv *priv = mlx4_priv(dev); 612 struct mlx4_slave_state *s_state; 613 int i; 614 int ret = 0; 615 616 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { 617 s_state = &priv->mfunc.master.slave_state[i]; 618 if (s_state->active && s_state->last_cmd != 619 MLX4_COMM_CMD_RESET) { 620 mlx4_warn(dev, "%s: slave: %d is still active\n", 621 __func__, i); 622 ret++; 623 } 624 } 625 return ret; 626 } 627 628 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) 629 { 630 u32 qk = MLX4_RESERVED_QKEY_BASE; 631 632 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || 633 qpn < dev->phys_caps.base_proxy_sqpn) 634 return -EINVAL; 635 636 if (qpn >= dev->phys_caps.base_tunnel_sqpn) 637 /* tunnel qp */ 638 qk += qpn - dev->phys_caps.base_tunnel_sqpn; 639 else 640 qk += qpn - dev->phys_caps.base_proxy_sqpn; 641 *qkey = qk; 642 return 0; 643 } 644 EXPORT_SYMBOL(mlx4_get_parav_qkey); 645 646 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) 647 { 648 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 649 650 if (!mlx4_is_master(dev)) 651 return; 652 653 priv->virt2phys_pkey[slave][port - 1][i] = val; 654 } 655 EXPORT_SYMBOL(mlx4_sync_pkey_table); 656 657 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) 658 { 659 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 660 661 if (!mlx4_is_master(dev)) 662 return; 663 664 priv->slave_node_guids[slave] = guid; 665 } 666 EXPORT_SYMBOL(mlx4_put_slave_node_guid); 667 668 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) 669 { 670 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 671 672 if (!mlx4_is_master(dev)) 673 return 0; 674 675 return priv->slave_node_guids[slave]; 676 } 677 EXPORT_SYMBOL(mlx4_get_slave_node_guid); 678 679 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) 680 { 681 struct mlx4_priv *priv = mlx4_priv(dev); 682 struct mlx4_slave_state *s_slave; 683 684 if (!mlx4_is_master(dev)) 685 return 0; 686 687 s_slave = &priv->mfunc.master.slave_state[slave]; 688 return !!s_slave->active; 689 } 690 EXPORT_SYMBOL(mlx4_is_slave_active); 691 692 static void slave_adjust_steering_mode(struct mlx4_dev *dev, 693 struct mlx4_dev_cap *dev_cap, 694 struct mlx4_init_hca_param *hca_param) 695 { 696 dev->caps.steering_mode = hca_param->steering_mode; 697 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 698 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 699 dev->caps.fs_log_max_ucast_qp_range_size = 700 dev_cap->fs_log_max_ucast_qp_range_size; 701 } else 702 dev->caps.num_qp_per_mgm = 703 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); 704 705 mlx4_dbg(dev, "Steering mode is: %s\n", 706 mlx4_steering_mode_str(dev->caps.steering_mode)); 707 } 708 709 static int mlx4_slave_cap(struct mlx4_dev *dev) 710 { 711 int err; 712 u32 page_size; 713 struct mlx4_dev_cap dev_cap; 714 struct mlx4_func_cap func_cap; 715 struct mlx4_init_hca_param hca_param; 716 u8 i; 717 718 memset(&hca_param, 0, sizeof(hca_param)); 719 err = mlx4_QUERY_HCA(dev, &hca_param); 720 if (err) { 721 mlx4_err(dev, "QUERY_HCA command failed, aborting\n"); 722 return err; 723 } 724 725 /* fail if the hca has an unknown global capability 726 * at this time global_caps should be always zeroed 727 */ 728 if (hca_param.global_caps) { 729 mlx4_err(dev, "Unknown hca global capabilities\n"); 730 return -ENOSYS; 731 } 732 733 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz; 734 735 dev->caps.hca_core_clock = hca_param.hca_core_clock; 736 737 memset(&dev_cap, 0, sizeof(dev_cap)); 738 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp; 739 err = mlx4_dev_cap(dev, &dev_cap); 740 if (err) { 741 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 742 return err; 743 } 744 745 err = mlx4_QUERY_FW(dev); 746 if (err) 747 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n"); 748 749 page_size = ~dev->caps.page_size_cap + 1; 750 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); 751 if (page_size > PAGE_SIZE) { 752 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 753 page_size, PAGE_SIZE); 754 return -ENODEV; 755 } 756 757 /* slave gets uar page size from QUERY_HCA fw command */ 758 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12); 759 760 /* TODO: relax this assumption */ 761 if (dev->caps.uar_page_size != PAGE_SIZE) { 762 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n", 763 dev->caps.uar_page_size, PAGE_SIZE); 764 return -ENODEV; 765 } 766 767 memset(&func_cap, 0, sizeof(func_cap)); 768 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap); 769 if (err) { 770 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n", 771 err); 772 return err; 773 } 774 775 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != 776 PF_CONTEXT_BEHAVIOUR_MASK) { 777 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n", 778 func_cap.pf_context_behaviour, PF_CONTEXT_BEHAVIOUR_MASK); 779 return -ENOSYS; 780 } 781 782 dev->caps.num_ports = func_cap.num_ports; 783 dev->quotas.qp = func_cap.qp_quota; 784 dev->quotas.srq = func_cap.srq_quota; 785 dev->quotas.cq = func_cap.cq_quota; 786 dev->quotas.mpt = func_cap.mpt_quota; 787 dev->quotas.mtt = func_cap.mtt_quota; 788 dev->caps.num_qps = 1 << hca_param.log_num_qps; 789 dev->caps.num_srqs = 1 << hca_param.log_num_srqs; 790 dev->caps.num_cqs = 1 << hca_param.log_num_cqs; 791 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz; 792 dev->caps.num_eqs = func_cap.max_eq; 793 dev->caps.reserved_eqs = func_cap.reserved_eq; 794 dev->caps.num_pds = MLX4_NUM_PDS; 795 dev->caps.num_mgms = 0; 796 dev->caps.num_amgms = 0; 797 798 if (dev->caps.num_ports > MLX4_MAX_PORTS) { 799 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 800 dev->caps.num_ports, MLX4_MAX_PORTS); 801 return -ENODEV; 802 } 803 804 dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL); 805 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 806 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 807 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 808 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 809 810 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy || 811 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy || 812 !dev->caps.qp0_qkey) { 813 err = -ENOMEM; 814 goto err_mem; 815 } 816 817 for (i = 1; i <= dev->caps.num_ports; ++i) { 818 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap); 819 if (err) { 820 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n", 821 i, err); 822 goto err_mem; 823 } 824 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey; 825 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn; 826 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn; 827 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn; 828 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn; 829 dev->caps.port_mask[i] = dev->caps.port_type[i]; 830 dev->caps.phys_port_id[i] = func_cap.phys_port_id; 831 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i, 832 &dev->caps.gid_table_len[i], 833 &dev->caps.pkey_table_len[i])) 834 goto err_mem; 835 } 836 837 if (dev->caps.uar_page_size * (dev->caps.num_uars - 838 dev->caps.reserved_uars) > 839 pci_resource_len(dev->pdev, 2)) { 840 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 841 dev->caps.uar_page_size * dev->caps.num_uars, 842 (unsigned long long) pci_resource_len(dev->pdev, 2)); 843 goto err_mem; 844 } 845 846 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { 847 dev->caps.eqe_size = 64; 848 dev->caps.eqe_factor = 1; 849 } else { 850 dev->caps.eqe_size = 32; 851 dev->caps.eqe_factor = 0; 852 } 853 854 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { 855 dev->caps.cqe_size = 64; 856 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 857 } else { 858 dev->caps.cqe_size = 32; 859 } 860 861 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) { 862 dev->caps.eqe_size = hca_param.eqe_size; 863 dev->caps.eqe_factor = 0; 864 } 865 866 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) { 867 dev->caps.cqe_size = hca_param.cqe_size; 868 /* User still need to know when CQE > 32B */ 869 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 870 } 871 872 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 873 mlx4_warn(dev, "Timestamping is not supported in slave mode\n"); 874 875 slave_adjust_steering_mode(dev, &dev_cap, &hca_param); 876 877 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP && 878 dev->caps.bf_reg_size) 879 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP; 880 881 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP) 882 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP; 883 884 return 0; 885 886 err_mem: 887 kfree(dev->caps.qp0_qkey); 888 kfree(dev->caps.qp0_tunnel); 889 kfree(dev->caps.qp0_proxy); 890 kfree(dev->caps.qp1_tunnel); 891 kfree(dev->caps.qp1_proxy); 892 dev->caps.qp0_qkey = NULL; 893 dev->caps.qp0_tunnel = NULL; 894 dev->caps.qp0_proxy = NULL; 895 dev->caps.qp1_tunnel = NULL; 896 dev->caps.qp1_proxy = NULL; 897 898 return err; 899 } 900 901 static void mlx4_request_modules(struct mlx4_dev *dev) 902 { 903 int port; 904 int has_ib_port = false; 905 int has_eth_port = false; 906 #define EN_DRV_NAME "mlx4_en" 907 #define IB_DRV_NAME "mlx4_ib" 908 909 for (port = 1; port <= dev->caps.num_ports; port++) { 910 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) 911 has_ib_port = true; 912 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 913 has_eth_port = true; 914 } 915 916 if (has_eth_port) 917 request_module_nowait(EN_DRV_NAME); 918 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 919 request_module_nowait(IB_DRV_NAME); 920 } 921 922 /* 923 * Change the port configuration of the device. 924 * Every user of this function must hold the port mutex. 925 */ 926 int mlx4_change_port_types(struct mlx4_dev *dev, 927 enum mlx4_port_type *port_types) 928 { 929 int err = 0; 930 int change = 0; 931 int port; 932 933 for (port = 0; port < dev->caps.num_ports; port++) { 934 /* Change the port type only if the new type is different 935 * from the current, and not set to Auto */ 936 if (port_types[port] != dev->caps.port_type[port + 1]) 937 change = 1; 938 } 939 if (change) { 940 mlx4_unregister_device(dev); 941 for (port = 1; port <= dev->caps.num_ports; port++) { 942 mlx4_CLOSE_PORT(dev, port); 943 dev->caps.port_type[port] = port_types[port - 1]; 944 err = mlx4_SET_PORT(dev, port, -1); 945 if (err) { 946 mlx4_err(dev, "Failed to set port %d, aborting\n", 947 port); 948 goto out; 949 } 950 } 951 mlx4_set_port_mask(dev); 952 err = mlx4_register_device(dev); 953 if (err) { 954 mlx4_err(dev, "Failed to register device\n"); 955 goto out; 956 } 957 mlx4_request_modules(dev); 958 } 959 960 out: 961 return err; 962 } 963 964 static ssize_t show_port_type(struct device *dev, 965 struct device_attribute *attr, 966 char *buf) 967 { 968 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 969 port_attr); 970 struct mlx4_dev *mdev = info->dev; 971 char type[8]; 972 973 sprintf(type, "%s", 974 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? 975 "ib" : "eth"); 976 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) 977 sprintf(buf, "auto (%s)\n", type); 978 else 979 sprintf(buf, "%s\n", type); 980 981 return strlen(buf); 982 } 983 984 static ssize_t set_port_type(struct device *dev, 985 struct device_attribute *attr, 986 const char *buf, size_t count) 987 { 988 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 989 port_attr); 990 struct mlx4_dev *mdev = info->dev; 991 struct mlx4_priv *priv = mlx4_priv(mdev); 992 enum mlx4_port_type types[MLX4_MAX_PORTS]; 993 enum mlx4_port_type new_types[MLX4_MAX_PORTS]; 994 static DEFINE_MUTEX(set_port_type_mutex); 995 int i; 996 int err = 0; 997 998 mutex_lock(&set_port_type_mutex); 999 1000 if (!strcmp(buf, "ib\n")) 1001 info->tmp_type = MLX4_PORT_TYPE_IB; 1002 else if (!strcmp(buf, "eth\n")) 1003 info->tmp_type = MLX4_PORT_TYPE_ETH; 1004 else if (!strcmp(buf, "auto\n")) 1005 info->tmp_type = MLX4_PORT_TYPE_AUTO; 1006 else { 1007 mlx4_err(mdev, "%s is not supported port type\n", buf); 1008 err = -EINVAL; 1009 goto err_out; 1010 } 1011 1012 mlx4_stop_sense(mdev); 1013 mutex_lock(&priv->port_mutex); 1014 /* Possible type is always the one that was delivered */ 1015 mdev->caps.possible_type[info->port] = info->tmp_type; 1016 1017 for (i = 0; i < mdev->caps.num_ports; i++) { 1018 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : 1019 mdev->caps.possible_type[i+1]; 1020 if (types[i] == MLX4_PORT_TYPE_AUTO) 1021 types[i] = mdev->caps.port_type[i+1]; 1022 } 1023 1024 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 1025 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { 1026 for (i = 1; i <= mdev->caps.num_ports; i++) { 1027 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { 1028 mdev->caps.possible_type[i] = mdev->caps.port_type[i]; 1029 err = -EINVAL; 1030 } 1031 } 1032 } 1033 if (err) { 1034 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n"); 1035 goto out; 1036 } 1037 1038 mlx4_do_sense_ports(mdev, new_types, types); 1039 1040 err = mlx4_check_port_params(mdev, new_types); 1041 if (err) 1042 goto out; 1043 1044 /* We are about to apply the changes after the configuration 1045 * was verified, no need to remember the temporary types 1046 * any more */ 1047 for (i = 0; i < mdev->caps.num_ports; i++) 1048 priv->port[i + 1].tmp_type = 0; 1049 1050 err = mlx4_change_port_types(mdev, new_types); 1051 1052 out: 1053 mlx4_start_sense(mdev); 1054 mutex_unlock(&priv->port_mutex); 1055 err_out: 1056 mutex_unlock(&set_port_type_mutex); 1057 1058 return err ? err : count; 1059 } 1060 1061 enum ibta_mtu { 1062 IB_MTU_256 = 1, 1063 IB_MTU_512 = 2, 1064 IB_MTU_1024 = 3, 1065 IB_MTU_2048 = 4, 1066 IB_MTU_4096 = 5 1067 }; 1068 1069 static inline int int_to_ibta_mtu(int mtu) 1070 { 1071 switch (mtu) { 1072 case 256: return IB_MTU_256; 1073 case 512: return IB_MTU_512; 1074 case 1024: return IB_MTU_1024; 1075 case 2048: return IB_MTU_2048; 1076 case 4096: return IB_MTU_4096; 1077 default: return -1; 1078 } 1079 } 1080 1081 static inline int ibta_mtu_to_int(enum ibta_mtu mtu) 1082 { 1083 switch (mtu) { 1084 case IB_MTU_256: return 256; 1085 case IB_MTU_512: return 512; 1086 case IB_MTU_1024: return 1024; 1087 case IB_MTU_2048: return 2048; 1088 case IB_MTU_4096: return 4096; 1089 default: return -1; 1090 } 1091 } 1092 1093 static ssize_t show_port_ib_mtu(struct device *dev, 1094 struct device_attribute *attr, 1095 char *buf) 1096 { 1097 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1098 port_mtu_attr); 1099 struct mlx4_dev *mdev = info->dev; 1100 1101 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) 1102 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1103 1104 sprintf(buf, "%d\n", 1105 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); 1106 return strlen(buf); 1107 } 1108 1109 static ssize_t set_port_ib_mtu(struct device *dev, 1110 struct device_attribute *attr, 1111 const char *buf, size_t count) 1112 { 1113 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1114 port_mtu_attr); 1115 struct mlx4_dev *mdev = info->dev; 1116 struct mlx4_priv *priv = mlx4_priv(mdev); 1117 int err, port, mtu, ibta_mtu = -1; 1118 1119 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { 1120 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1121 return -EINVAL; 1122 } 1123 1124 err = kstrtoint(buf, 0, &mtu); 1125 if (!err) 1126 ibta_mtu = int_to_ibta_mtu(mtu); 1127 1128 if (err || ibta_mtu < 0) { 1129 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); 1130 return -EINVAL; 1131 } 1132 1133 mdev->caps.port_ib_mtu[info->port] = ibta_mtu; 1134 1135 mlx4_stop_sense(mdev); 1136 mutex_lock(&priv->port_mutex); 1137 mlx4_unregister_device(mdev); 1138 for (port = 1; port <= mdev->caps.num_ports; port++) { 1139 mlx4_CLOSE_PORT(mdev, port); 1140 err = mlx4_SET_PORT(mdev, port, -1); 1141 if (err) { 1142 mlx4_err(mdev, "Failed to set port %d, aborting\n", 1143 port); 1144 goto err_set_port; 1145 } 1146 } 1147 err = mlx4_register_device(mdev); 1148 err_set_port: 1149 mutex_unlock(&priv->port_mutex); 1150 mlx4_start_sense(mdev); 1151 return err ? err : count; 1152 } 1153 1154 static int mlx4_load_fw(struct mlx4_dev *dev) 1155 { 1156 struct mlx4_priv *priv = mlx4_priv(dev); 1157 int err; 1158 1159 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, 1160 GFP_HIGHUSER | __GFP_NOWARN, 0); 1161 if (!priv->fw.fw_icm) { 1162 mlx4_err(dev, "Couldn't allocate FW area, aborting\n"); 1163 return -ENOMEM; 1164 } 1165 1166 err = mlx4_MAP_FA(dev, priv->fw.fw_icm); 1167 if (err) { 1168 mlx4_err(dev, "MAP_FA command failed, aborting\n"); 1169 goto err_free; 1170 } 1171 1172 err = mlx4_RUN_FW(dev); 1173 if (err) { 1174 mlx4_err(dev, "RUN_FW command failed, aborting\n"); 1175 goto err_unmap_fa; 1176 } 1177 1178 return 0; 1179 1180 err_unmap_fa: 1181 mlx4_UNMAP_FA(dev); 1182 1183 err_free: 1184 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 1185 return err; 1186 } 1187 1188 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, 1189 int cmpt_entry_sz) 1190 { 1191 struct mlx4_priv *priv = mlx4_priv(dev); 1192 int err; 1193 int num_eqs; 1194 1195 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, 1196 cmpt_base + 1197 ((u64) (MLX4_CMPT_TYPE_QP * 1198 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1199 cmpt_entry_sz, dev->caps.num_qps, 1200 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1201 0, 0); 1202 if (err) 1203 goto err; 1204 1205 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, 1206 cmpt_base + 1207 ((u64) (MLX4_CMPT_TYPE_SRQ * 1208 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1209 cmpt_entry_sz, dev->caps.num_srqs, 1210 dev->caps.reserved_srqs, 0, 0); 1211 if (err) 1212 goto err_qp; 1213 1214 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, 1215 cmpt_base + 1216 ((u64) (MLX4_CMPT_TYPE_CQ * 1217 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1218 cmpt_entry_sz, dev->caps.num_cqs, 1219 dev->caps.reserved_cqs, 0, 0); 1220 if (err) 1221 goto err_srq; 1222 1223 num_eqs = dev->phys_caps.num_phys_eqs; 1224 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, 1225 cmpt_base + 1226 ((u64) (MLX4_CMPT_TYPE_EQ * 1227 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1228 cmpt_entry_sz, num_eqs, num_eqs, 0, 0); 1229 if (err) 1230 goto err_cq; 1231 1232 return 0; 1233 1234 err_cq: 1235 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1236 1237 err_srq: 1238 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1239 1240 err_qp: 1241 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1242 1243 err: 1244 return err; 1245 } 1246 1247 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 1248 struct mlx4_init_hca_param *init_hca, u64 icm_size) 1249 { 1250 struct mlx4_priv *priv = mlx4_priv(dev); 1251 u64 aux_pages; 1252 int num_eqs; 1253 int err; 1254 1255 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); 1256 if (err) { 1257 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n"); 1258 return err; 1259 } 1260 1261 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n", 1262 (unsigned long long) icm_size >> 10, 1263 (unsigned long long) aux_pages << 2); 1264 1265 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, 1266 GFP_HIGHUSER | __GFP_NOWARN, 0); 1267 if (!priv->fw.aux_icm) { 1268 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n"); 1269 return -ENOMEM; 1270 } 1271 1272 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); 1273 if (err) { 1274 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n"); 1275 goto err_free_aux; 1276 } 1277 1278 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); 1279 if (err) { 1280 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n"); 1281 goto err_unmap_aux; 1282 } 1283 1284 1285 num_eqs = dev->phys_caps.num_phys_eqs; 1286 err = mlx4_init_icm_table(dev, &priv->eq_table.table, 1287 init_hca->eqc_base, dev_cap->eqc_entry_sz, 1288 num_eqs, num_eqs, 0, 0); 1289 if (err) { 1290 mlx4_err(dev, "Failed to map EQ context memory, aborting\n"); 1291 goto err_unmap_cmpt; 1292 } 1293 1294 /* 1295 * Reserved MTT entries must be aligned up to a cacheline 1296 * boundary, since the FW will write to them, while the driver 1297 * writes to all other MTT entries. (The variable 1298 * dev->caps.mtt_entry_sz below is really the MTT segment 1299 * size, not the raw entry size) 1300 */ 1301 dev->caps.reserved_mtts = 1302 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, 1303 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; 1304 1305 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, 1306 init_hca->mtt_base, 1307 dev->caps.mtt_entry_sz, 1308 dev->caps.num_mtts, 1309 dev->caps.reserved_mtts, 1, 0); 1310 if (err) { 1311 mlx4_err(dev, "Failed to map MTT context memory, aborting\n"); 1312 goto err_unmap_eq; 1313 } 1314 1315 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, 1316 init_hca->dmpt_base, 1317 dev_cap->dmpt_entry_sz, 1318 dev->caps.num_mpts, 1319 dev->caps.reserved_mrws, 1, 1); 1320 if (err) { 1321 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n"); 1322 goto err_unmap_mtt; 1323 } 1324 1325 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, 1326 init_hca->qpc_base, 1327 dev_cap->qpc_entry_sz, 1328 dev->caps.num_qps, 1329 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1330 0, 0); 1331 if (err) { 1332 mlx4_err(dev, "Failed to map QP context memory, aborting\n"); 1333 goto err_unmap_dmpt; 1334 } 1335 1336 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, 1337 init_hca->auxc_base, 1338 dev_cap->aux_entry_sz, 1339 dev->caps.num_qps, 1340 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1341 0, 0); 1342 if (err) { 1343 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n"); 1344 goto err_unmap_qp; 1345 } 1346 1347 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, 1348 init_hca->altc_base, 1349 dev_cap->altc_entry_sz, 1350 dev->caps.num_qps, 1351 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1352 0, 0); 1353 if (err) { 1354 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n"); 1355 goto err_unmap_auxc; 1356 } 1357 1358 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, 1359 init_hca->rdmarc_base, 1360 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, 1361 dev->caps.num_qps, 1362 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1363 0, 0); 1364 if (err) { 1365 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); 1366 goto err_unmap_altc; 1367 } 1368 1369 err = mlx4_init_icm_table(dev, &priv->cq_table.table, 1370 init_hca->cqc_base, 1371 dev_cap->cqc_entry_sz, 1372 dev->caps.num_cqs, 1373 dev->caps.reserved_cqs, 0, 0); 1374 if (err) { 1375 mlx4_err(dev, "Failed to map CQ context memory, aborting\n"); 1376 goto err_unmap_rdmarc; 1377 } 1378 1379 err = mlx4_init_icm_table(dev, &priv->srq_table.table, 1380 init_hca->srqc_base, 1381 dev_cap->srq_entry_sz, 1382 dev->caps.num_srqs, 1383 dev->caps.reserved_srqs, 0, 0); 1384 if (err) { 1385 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n"); 1386 goto err_unmap_cq; 1387 } 1388 1389 /* 1390 * For flow steering device managed mode it is required to use 1391 * mlx4_init_icm_table. For B0 steering mode it's not strictly 1392 * required, but for simplicity just map the whole multicast 1393 * group table now. The table isn't very big and it's a lot 1394 * easier than trying to track ref counts. 1395 */ 1396 err = mlx4_init_icm_table(dev, &priv->mcg_table.table, 1397 init_hca->mc_base, 1398 mlx4_get_mgm_entry_size(dev), 1399 dev->caps.num_mgms + dev->caps.num_amgms, 1400 dev->caps.num_mgms + dev->caps.num_amgms, 1401 0, 0); 1402 if (err) { 1403 mlx4_err(dev, "Failed to map MCG context memory, aborting\n"); 1404 goto err_unmap_srq; 1405 } 1406 1407 return 0; 1408 1409 err_unmap_srq: 1410 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1411 1412 err_unmap_cq: 1413 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1414 1415 err_unmap_rdmarc: 1416 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1417 1418 err_unmap_altc: 1419 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1420 1421 err_unmap_auxc: 1422 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1423 1424 err_unmap_qp: 1425 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1426 1427 err_unmap_dmpt: 1428 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1429 1430 err_unmap_mtt: 1431 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1432 1433 err_unmap_eq: 1434 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1435 1436 err_unmap_cmpt: 1437 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1438 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1439 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1440 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1441 1442 err_unmap_aux: 1443 mlx4_UNMAP_ICM_AUX(dev); 1444 1445 err_free_aux: 1446 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1447 1448 return err; 1449 } 1450 1451 static void mlx4_free_icms(struct mlx4_dev *dev) 1452 { 1453 struct mlx4_priv *priv = mlx4_priv(dev); 1454 1455 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); 1456 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1457 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1458 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1459 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1460 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1461 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1462 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1463 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1464 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1465 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1466 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1467 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1468 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1469 1470 mlx4_UNMAP_ICM_AUX(dev); 1471 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1472 } 1473 1474 static void mlx4_slave_exit(struct mlx4_dev *dev) 1475 { 1476 struct mlx4_priv *priv = mlx4_priv(dev); 1477 1478 mutex_lock(&priv->cmd.slave_cmd_mutex); 1479 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME)) 1480 mlx4_warn(dev, "Failed to close slave function\n"); 1481 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1482 } 1483 1484 static int map_bf_area(struct mlx4_dev *dev) 1485 { 1486 struct mlx4_priv *priv = mlx4_priv(dev); 1487 resource_size_t bf_start; 1488 resource_size_t bf_len; 1489 int err = 0; 1490 1491 if (!dev->caps.bf_reg_size) 1492 return -ENXIO; 1493 1494 bf_start = pci_resource_start(dev->pdev, 2) + 1495 (dev->caps.num_uars << PAGE_SHIFT); 1496 bf_len = pci_resource_len(dev->pdev, 2) - 1497 (dev->caps.num_uars << PAGE_SHIFT); 1498 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); 1499 if (!priv->bf_mapping) 1500 err = -ENOMEM; 1501 1502 return err; 1503 } 1504 1505 static void unmap_bf_area(struct mlx4_dev *dev) 1506 { 1507 if (mlx4_priv(dev)->bf_mapping) 1508 io_mapping_free(mlx4_priv(dev)->bf_mapping); 1509 } 1510 1511 cycle_t mlx4_read_clock(struct mlx4_dev *dev) 1512 { 1513 u32 clockhi, clocklo, clockhi1; 1514 cycle_t cycles; 1515 int i; 1516 struct mlx4_priv *priv = mlx4_priv(dev); 1517 1518 for (i = 0; i < 10; i++) { 1519 clockhi = swab32(readl(priv->clock_mapping)); 1520 clocklo = swab32(readl(priv->clock_mapping + 4)); 1521 clockhi1 = swab32(readl(priv->clock_mapping)); 1522 if (clockhi == clockhi1) 1523 break; 1524 } 1525 1526 cycles = (u64) clockhi << 32 | (u64) clocklo; 1527 1528 return cycles; 1529 } 1530 EXPORT_SYMBOL_GPL(mlx4_read_clock); 1531 1532 1533 static int map_internal_clock(struct mlx4_dev *dev) 1534 { 1535 struct mlx4_priv *priv = mlx4_priv(dev); 1536 1537 priv->clock_mapping = 1538 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) + 1539 priv->fw.clock_offset, MLX4_CLOCK_SIZE); 1540 1541 if (!priv->clock_mapping) 1542 return -ENOMEM; 1543 1544 return 0; 1545 } 1546 1547 static void unmap_internal_clock(struct mlx4_dev *dev) 1548 { 1549 struct mlx4_priv *priv = mlx4_priv(dev); 1550 1551 if (priv->clock_mapping) 1552 iounmap(priv->clock_mapping); 1553 } 1554 1555 static void mlx4_close_hca(struct mlx4_dev *dev) 1556 { 1557 unmap_internal_clock(dev); 1558 unmap_bf_area(dev); 1559 if (mlx4_is_slave(dev)) 1560 mlx4_slave_exit(dev); 1561 else { 1562 mlx4_CLOSE_HCA(dev, 0); 1563 mlx4_free_icms(dev); 1564 } 1565 } 1566 1567 static void mlx4_close_fw(struct mlx4_dev *dev) 1568 { 1569 if (!mlx4_is_slave(dev)) { 1570 mlx4_UNMAP_FA(dev); 1571 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); 1572 } 1573 } 1574 1575 static int mlx4_init_slave(struct mlx4_dev *dev) 1576 { 1577 struct mlx4_priv *priv = mlx4_priv(dev); 1578 u64 dma = (u64) priv->mfunc.vhcr_dma; 1579 int ret_from_reset = 0; 1580 u32 slave_read; 1581 u32 cmd_channel_ver; 1582 1583 if (atomic_read(&pf_loading)) { 1584 mlx4_warn(dev, "PF is not ready - Deferring probe\n"); 1585 return -EPROBE_DEFER; 1586 } 1587 1588 mutex_lock(&priv->cmd.slave_cmd_mutex); 1589 priv->cmd.max_cmds = 1; 1590 mlx4_warn(dev, "Sending reset\n"); 1591 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 1592 MLX4_COMM_TIME); 1593 /* if we are in the middle of flr the slave will try 1594 * NUM_OF_RESET_RETRIES times before leaving.*/ 1595 if (ret_from_reset) { 1596 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { 1597 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n"); 1598 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1599 return -EPROBE_DEFER; 1600 } else 1601 goto err; 1602 } 1603 1604 /* check the driver version - the slave I/F revision 1605 * must match the master's */ 1606 slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); 1607 cmd_channel_ver = mlx4_comm_get_version(); 1608 1609 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != 1610 MLX4_COMM_GET_IF_REV(slave_read)) { 1611 mlx4_err(dev, "slave driver version is not supported by the master\n"); 1612 goto err; 1613 } 1614 1615 mlx4_warn(dev, "Sending vhcr0\n"); 1616 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, 1617 MLX4_COMM_TIME)) 1618 goto err; 1619 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, 1620 MLX4_COMM_TIME)) 1621 goto err; 1622 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, 1623 MLX4_COMM_TIME)) 1624 goto err; 1625 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME)) 1626 goto err; 1627 1628 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1629 return 0; 1630 1631 err: 1632 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0); 1633 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1634 return -EIO; 1635 } 1636 1637 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) 1638 { 1639 int i; 1640 1641 for (i = 1; i <= dev->caps.num_ports; i++) { 1642 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 1643 dev->caps.gid_table_len[i] = 1644 mlx4_get_slave_num_gids(dev, 0, i); 1645 else 1646 dev->caps.gid_table_len[i] = 1; 1647 dev->caps.pkey_table_len[i] = 1648 dev->phys_caps.pkey_phys_table_len[i] - 1; 1649 } 1650 } 1651 1652 static int choose_log_fs_mgm_entry_size(int qp_per_entry) 1653 { 1654 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; 1655 1656 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; 1657 i++) { 1658 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) 1659 break; 1660 } 1661 1662 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; 1663 } 1664 1665 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode) 1666 { 1667 switch (dmfs_high_steer_mode) { 1668 case MLX4_STEERING_DMFS_A0_DEFAULT: 1669 return "default performance"; 1670 1671 case MLX4_STEERING_DMFS_A0_DYNAMIC: 1672 return "dynamic hybrid mode"; 1673 1674 case MLX4_STEERING_DMFS_A0_STATIC: 1675 return "performance optimized for limited rule configuration (static)"; 1676 1677 case MLX4_STEERING_DMFS_A0_DISABLE: 1678 return "disabled performance optimized steering"; 1679 1680 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED: 1681 return "performance optimized steering not supported"; 1682 1683 default: 1684 return "Unrecognized mode"; 1685 } 1686 } 1687 1688 #define MLX4_DMFS_A0_STEERING (1UL << 2) 1689 1690 static void choose_steering_mode(struct mlx4_dev *dev, 1691 struct mlx4_dev_cap *dev_cap) 1692 { 1693 if (mlx4_log_num_mgm_entry_size <= 0) { 1694 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) { 1695 if (dev->caps.dmfs_high_steer_mode == 1696 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 1697 mlx4_err(dev, "DMFS high rate mode not supported\n"); 1698 else 1699 dev->caps.dmfs_high_steer_mode = 1700 MLX4_STEERING_DMFS_A0_STATIC; 1701 } 1702 } 1703 1704 if (mlx4_log_num_mgm_entry_size <= 0 && 1705 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && 1706 (!mlx4_is_mfunc(dev) || 1707 (dev_cap->fs_max_num_qp_per_entry >= (dev->num_vfs + 1))) && 1708 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= 1709 MLX4_MIN_MGM_LOG_ENTRY_SIZE) { 1710 dev->oper_log_mgm_entry_size = 1711 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); 1712 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 1713 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 1714 dev->caps.fs_log_max_ucast_qp_range_size = 1715 dev_cap->fs_log_max_ucast_qp_range_size; 1716 } else { 1717 if (dev->caps.dmfs_high_steer_mode != 1718 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 1719 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE; 1720 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && 1721 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 1722 dev->caps.steering_mode = MLX4_STEERING_MODE_B0; 1723 else { 1724 dev->caps.steering_mode = MLX4_STEERING_MODE_A0; 1725 1726 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || 1727 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 1728 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n"); 1729 } 1730 dev->oper_log_mgm_entry_size = 1731 mlx4_log_num_mgm_entry_size > 0 ? 1732 mlx4_log_num_mgm_entry_size : 1733 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 1734 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); 1735 } 1736 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n", 1737 mlx4_steering_mode_str(dev->caps.steering_mode), 1738 dev->oper_log_mgm_entry_size, 1739 mlx4_log_num_mgm_entry_size); 1740 } 1741 1742 static void choose_tunnel_offload_mode(struct mlx4_dev *dev, 1743 struct mlx4_dev_cap *dev_cap) 1744 { 1745 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED && 1746 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS && 1747 dev->caps.dmfs_high_steer_mode != MLX4_STEERING_DMFS_A0_STATIC) 1748 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN; 1749 else 1750 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE; 1751 1752 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode 1753 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none"); 1754 } 1755 1756 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev) 1757 { 1758 int i; 1759 struct mlx4_port_cap port_cap; 1760 1761 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 1762 return -EINVAL; 1763 1764 for (i = 1; i <= dev->caps.num_ports; i++) { 1765 if (mlx4_dev_port(dev, i, &port_cap)) { 1766 mlx4_err(dev, 1767 "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n"); 1768 } else if ((dev->caps.dmfs_high_steer_mode != 1769 MLX4_STEERING_DMFS_A0_DEFAULT) && 1770 (port_cap.dmfs_optimized_state == 1771 !!(dev->caps.dmfs_high_steer_mode == 1772 MLX4_STEERING_DMFS_A0_DISABLE))) { 1773 mlx4_err(dev, 1774 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n", 1775 dmfs_high_rate_steering_mode_str( 1776 dev->caps.dmfs_high_steer_mode), 1777 (port_cap.dmfs_optimized_state ? 1778 "enabled" : "disabled")); 1779 } 1780 } 1781 1782 return 0; 1783 } 1784 1785 static int mlx4_init_fw(struct mlx4_dev *dev) 1786 { 1787 struct mlx4_mod_stat_cfg mlx4_cfg; 1788 int err = 0; 1789 1790 if (!mlx4_is_slave(dev)) { 1791 err = mlx4_QUERY_FW(dev); 1792 if (err) { 1793 if (err == -EACCES) 1794 mlx4_info(dev, "non-primary physical function, skipping\n"); 1795 else 1796 mlx4_err(dev, "QUERY_FW command failed, aborting\n"); 1797 return err; 1798 } 1799 1800 err = mlx4_load_fw(dev); 1801 if (err) { 1802 mlx4_err(dev, "Failed to start FW, aborting\n"); 1803 return err; 1804 } 1805 1806 mlx4_cfg.log_pg_sz_m = 1; 1807 mlx4_cfg.log_pg_sz = 0; 1808 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); 1809 if (err) 1810 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); 1811 } 1812 1813 return err; 1814 } 1815 1816 static int mlx4_init_hca(struct mlx4_dev *dev) 1817 { 1818 struct mlx4_priv *priv = mlx4_priv(dev); 1819 struct mlx4_adapter adapter; 1820 struct mlx4_dev_cap dev_cap; 1821 struct mlx4_profile profile; 1822 struct mlx4_init_hca_param init_hca; 1823 u64 icm_size; 1824 struct mlx4_config_dev_params params; 1825 int err; 1826 1827 if (!mlx4_is_slave(dev)) { 1828 err = mlx4_dev_cap(dev, &dev_cap); 1829 if (err) { 1830 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 1831 goto err_stop_fw; 1832 } 1833 1834 choose_steering_mode(dev, &dev_cap); 1835 choose_tunnel_offload_mode(dev, &dev_cap); 1836 1837 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC && 1838 mlx4_is_master(dev)) 1839 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC; 1840 1841 err = mlx4_get_phys_port_id(dev); 1842 if (err) 1843 mlx4_err(dev, "Fail to get physical port id\n"); 1844 1845 if (mlx4_is_master(dev)) 1846 mlx4_parav_master_pf_caps(dev); 1847 1848 if (mlx4_low_memory_profile()) { 1849 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n"); 1850 profile = low_mem_profile; 1851 } else { 1852 profile = default_profile; 1853 } 1854 if (dev->caps.steering_mode == 1855 MLX4_STEERING_MODE_DEVICE_MANAGED) 1856 profile.num_mcg = MLX4_FS_NUM_MCG; 1857 1858 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, 1859 &init_hca); 1860 if ((long long) icm_size < 0) { 1861 err = icm_size; 1862 goto err_stop_fw; 1863 } 1864 1865 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; 1866 1867 init_hca.log_uar_sz = ilog2(dev->caps.num_uars); 1868 init_hca.uar_page_sz = PAGE_SHIFT - 12; 1869 init_hca.mw_enabled = 0; 1870 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 1871 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) 1872 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE; 1873 1874 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size); 1875 if (err) 1876 goto err_stop_fw; 1877 1878 err = mlx4_INIT_HCA(dev, &init_hca); 1879 if (err) { 1880 mlx4_err(dev, "INIT_HCA command failed, aborting\n"); 1881 goto err_free_icm; 1882 } 1883 1884 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 1885 err = mlx4_query_func(dev, &dev_cap); 1886 if (err < 0) { 1887 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n"); 1888 goto err_stop_fw; 1889 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) { 1890 dev->caps.num_eqs = dev_cap.max_eqs; 1891 dev->caps.reserved_eqs = dev_cap.reserved_eqs; 1892 dev->caps.reserved_uars = dev_cap.reserved_uars; 1893 } 1894 } 1895 1896 /* 1897 * If TS is supported by FW 1898 * read HCA frequency by QUERY_HCA command 1899 */ 1900 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 1901 memset(&init_hca, 0, sizeof(init_hca)); 1902 err = mlx4_QUERY_HCA(dev, &init_hca); 1903 if (err) { 1904 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n"); 1905 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 1906 } else { 1907 dev->caps.hca_core_clock = 1908 init_hca.hca_core_clock; 1909 } 1910 1911 /* In case we got HCA frequency 0 - disable timestamping 1912 * to avoid dividing by zero 1913 */ 1914 if (!dev->caps.hca_core_clock) { 1915 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 1916 mlx4_err(dev, 1917 "HCA frequency is 0 - timestamping is not supported\n"); 1918 } else if (map_internal_clock(dev)) { 1919 /* 1920 * Map internal clock, 1921 * in case of failure disable timestamping 1922 */ 1923 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 1924 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n"); 1925 } 1926 } 1927 1928 if (dev->caps.dmfs_high_steer_mode != 1929 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) { 1930 if (mlx4_validate_optimized_steering(dev)) 1931 mlx4_warn(dev, "Optimized steering validation failed\n"); 1932 1933 if (dev->caps.dmfs_high_steer_mode == 1934 MLX4_STEERING_DMFS_A0_DISABLE) { 1935 dev->caps.dmfs_high_rate_qpn_base = 1936 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 1937 dev->caps.dmfs_high_rate_qpn_range = 1938 MLX4_A0_STEERING_TABLE_SIZE; 1939 } 1940 1941 mlx4_dbg(dev, "DMFS high rate steer mode is: %s\n", 1942 dmfs_high_rate_steering_mode_str( 1943 dev->caps.dmfs_high_steer_mode)); 1944 } 1945 } else { 1946 err = mlx4_init_slave(dev); 1947 if (err) { 1948 if (err != -EPROBE_DEFER) 1949 mlx4_err(dev, "Failed to initialize slave\n"); 1950 return err; 1951 } 1952 1953 err = mlx4_slave_cap(dev); 1954 if (err) { 1955 mlx4_err(dev, "Failed to obtain slave caps\n"); 1956 goto err_close; 1957 } 1958 } 1959 1960 if (map_bf_area(dev)) 1961 mlx4_dbg(dev, "Failed to map blue flame area\n"); 1962 1963 /*Only the master set the ports, all the rest got it from it.*/ 1964 if (!mlx4_is_slave(dev)) 1965 mlx4_set_port_mask(dev); 1966 1967 err = mlx4_QUERY_ADAPTER(dev, &adapter); 1968 if (err) { 1969 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n"); 1970 goto unmap_bf; 1971 } 1972 1973 /* Query CONFIG_DEV parameters */ 1974 err = mlx4_config_dev_retrieval(dev, ¶ms); 1975 if (err && err != -ENOTSUPP) { 1976 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n"); 1977 } else if (!err) { 1978 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1; 1979 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2; 1980 } 1981 priv->eq_table.inta_pin = adapter.inta_pin; 1982 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id); 1983 1984 return 0; 1985 1986 unmap_bf: 1987 unmap_internal_clock(dev); 1988 unmap_bf_area(dev); 1989 1990 if (mlx4_is_slave(dev)) { 1991 kfree(dev->caps.qp0_qkey); 1992 kfree(dev->caps.qp0_tunnel); 1993 kfree(dev->caps.qp0_proxy); 1994 kfree(dev->caps.qp1_tunnel); 1995 kfree(dev->caps.qp1_proxy); 1996 } 1997 1998 err_close: 1999 if (mlx4_is_slave(dev)) 2000 mlx4_slave_exit(dev); 2001 else 2002 mlx4_CLOSE_HCA(dev, 0); 2003 2004 err_free_icm: 2005 if (!mlx4_is_slave(dev)) 2006 mlx4_free_icms(dev); 2007 2008 err_stop_fw: 2009 if (!mlx4_is_slave(dev)) { 2010 mlx4_UNMAP_FA(dev); 2011 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 2012 } 2013 return err; 2014 } 2015 2016 static int mlx4_init_counters_table(struct mlx4_dev *dev) 2017 { 2018 struct mlx4_priv *priv = mlx4_priv(dev); 2019 int nent; 2020 2021 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2022 return -ENOENT; 2023 2024 nent = dev->caps.max_counters; 2025 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0); 2026 } 2027 2028 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) 2029 { 2030 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); 2031 } 2032 2033 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 2034 { 2035 struct mlx4_priv *priv = mlx4_priv(dev); 2036 2037 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2038 return -ENOENT; 2039 2040 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); 2041 if (*idx == -1) 2042 return -ENOMEM; 2043 2044 return 0; 2045 } 2046 2047 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 2048 { 2049 u64 out_param; 2050 int err; 2051 2052 if (mlx4_is_mfunc(dev)) { 2053 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER, 2054 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, 2055 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2056 if (!err) 2057 *idx = get_param_l(&out_param); 2058 2059 return err; 2060 } 2061 return __mlx4_counter_alloc(dev, idx); 2062 } 2063 EXPORT_SYMBOL_GPL(mlx4_counter_alloc); 2064 2065 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2066 { 2067 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR); 2068 return; 2069 } 2070 2071 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2072 { 2073 u64 in_param = 0; 2074 2075 if (mlx4_is_mfunc(dev)) { 2076 set_param_l(&in_param, idx); 2077 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE, 2078 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, 2079 MLX4_CMD_WRAPPED); 2080 return; 2081 } 2082 __mlx4_counter_free(dev, idx); 2083 } 2084 EXPORT_SYMBOL_GPL(mlx4_counter_free); 2085 2086 static int mlx4_setup_hca(struct mlx4_dev *dev) 2087 { 2088 struct mlx4_priv *priv = mlx4_priv(dev); 2089 int err; 2090 int port; 2091 __be32 ib_port_default_caps; 2092 2093 err = mlx4_init_uar_table(dev); 2094 if (err) { 2095 mlx4_err(dev, "Failed to initialize user access region table, aborting\n"); 2096 return err; 2097 } 2098 2099 err = mlx4_uar_alloc(dev, &priv->driver_uar); 2100 if (err) { 2101 mlx4_err(dev, "Failed to allocate driver access region, aborting\n"); 2102 goto err_uar_table_free; 2103 } 2104 2105 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); 2106 if (!priv->kar) { 2107 mlx4_err(dev, "Couldn't map kernel access region, aborting\n"); 2108 err = -ENOMEM; 2109 goto err_uar_free; 2110 } 2111 2112 err = mlx4_init_pd_table(dev); 2113 if (err) { 2114 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n"); 2115 goto err_kar_unmap; 2116 } 2117 2118 err = mlx4_init_xrcd_table(dev); 2119 if (err) { 2120 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n"); 2121 goto err_pd_table_free; 2122 } 2123 2124 err = mlx4_init_mr_table(dev); 2125 if (err) { 2126 mlx4_err(dev, "Failed to initialize memory region table, aborting\n"); 2127 goto err_xrcd_table_free; 2128 } 2129 2130 if (!mlx4_is_slave(dev)) { 2131 err = mlx4_init_mcg_table(dev); 2132 if (err) { 2133 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n"); 2134 goto err_mr_table_free; 2135 } 2136 err = mlx4_config_mad_demux(dev); 2137 if (err) { 2138 mlx4_err(dev, "Failed in config_mad_demux, aborting\n"); 2139 goto err_mcg_table_free; 2140 } 2141 } 2142 2143 err = mlx4_init_eq_table(dev); 2144 if (err) { 2145 mlx4_err(dev, "Failed to initialize event queue table, aborting\n"); 2146 goto err_mcg_table_free; 2147 } 2148 2149 err = mlx4_cmd_use_events(dev); 2150 if (err) { 2151 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n"); 2152 goto err_eq_table_free; 2153 } 2154 2155 err = mlx4_NOP(dev); 2156 if (err) { 2157 if (dev->flags & MLX4_FLAG_MSI_X) { 2158 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n", 2159 priv->eq_table.eq[dev->caps.num_comp_vectors].irq); 2160 mlx4_warn(dev, "Trying again without MSI-X\n"); 2161 } else { 2162 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n", 2163 priv->eq_table.eq[dev->caps.num_comp_vectors].irq); 2164 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); 2165 } 2166 2167 goto err_cmd_poll; 2168 } 2169 2170 mlx4_dbg(dev, "NOP command IRQ test passed\n"); 2171 2172 err = mlx4_init_cq_table(dev); 2173 if (err) { 2174 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n"); 2175 goto err_cmd_poll; 2176 } 2177 2178 err = mlx4_init_srq_table(dev); 2179 if (err) { 2180 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n"); 2181 goto err_cq_table_free; 2182 } 2183 2184 err = mlx4_init_qp_table(dev); 2185 if (err) { 2186 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n"); 2187 goto err_srq_table_free; 2188 } 2189 2190 err = mlx4_init_counters_table(dev); 2191 if (err && err != -ENOENT) { 2192 mlx4_err(dev, "Failed to initialize counters table, aborting\n"); 2193 goto err_qp_table_free; 2194 } 2195 2196 if (!mlx4_is_slave(dev)) { 2197 for (port = 1; port <= dev->caps.num_ports; port++) { 2198 ib_port_default_caps = 0; 2199 err = mlx4_get_port_ib_caps(dev, port, 2200 &ib_port_default_caps); 2201 if (err) 2202 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n", 2203 port, err); 2204 dev->caps.ib_port_def_cap[port] = ib_port_default_caps; 2205 2206 /* initialize per-slave default ib port capabilities */ 2207 if (mlx4_is_master(dev)) { 2208 int i; 2209 for (i = 0; i < dev->num_slaves; i++) { 2210 if (i == mlx4_master_func_num(dev)) 2211 continue; 2212 priv->mfunc.master.slave_state[i].ib_cap_mask[port] = 2213 ib_port_default_caps; 2214 } 2215 } 2216 2217 if (mlx4_is_mfunc(dev)) 2218 dev->caps.port_ib_mtu[port] = IB_MTU_2048; 2219 else 2220 dev->caps.port_ib_mtu[port] = IB_MTU_4096; 2221 2222 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? 2223 dev->caps.pkey_table_len[port] : -1); 2224 if (err) { 2225 mlx4_err(dev, "Failed to set port %d, aborting\n", 2226 port); 2227 goto err_counters_table_free; 2228 } 2229 } 2230 } 2231 2232 return 0; 2233 2234 err_counters_table_free: 2235 mlx4_cleanup_counters_table(dev); 2236 2237 err_qp_table_free: 2238 mlx4_cleanup_qp_table(dev); 2239 2240 err_srq_table_free: 2241 mlx4_cleanup_srq_table(dev); 2242 2243 err_cq_table_free: 2244 mlx4_cleanup_cq_table(dev); 2245 2246 err_cmd_poll: 2247 mlx4_cmd_use_polling(dev); 2248 2249 err_eq_table_free: 2250 mlx4_cleanup_eq_table(dev); 2251 2252 err_mcg_table_free: 2253 if (!mlx4_is_slave(dev)) 2254 mlx4_cleanup_mcg_table(dev); 2255 2256 err_mr_table_free: 2257 mlx4_cleanup_mr_table(dev); 2258 2259 err_xrcd_table_free: 2260 mlx4_cleanup_xrcd_table(dev); 2261 2262 err_pd_table_free: 2263 mlx4_cleanup_pd_table(dev); 2264 2265 err_kar_unmap: 2266 iounmap(priv->kar); 2267 2268 err_uar_free: 2269 mlx4_uar_free(dev, &priv->driver_uar); 2270 2271 err_uar_table_free: 2272 mlx4_cleanup_uar_table(dev); 2273 return err; 2274 } 2275 2276 static void mlx4_enable_msi_x(struct mlx4_dev *dev) 2277 { 2278 struct mlx4_priv *priv = mlx4_priv(dev); 2279 struct msix_entry *entries; 2280 int i; 2281 2282 if (msi_x) { 2283 int nreq = dev->caps.num_ports * num_online_cpus() + MSIX_LEGACY_SZ; 2284 2285 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs, 2286 nreq); 2287 2288 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); 2289 if (!entries) 2290 goto no_msi; 2291 2292 for (i = 0; i < nreq; ++i) 2293 entries[i].entry = i; 2294 2295 nreq = pci_enable_msix_range(dev->pdev, entries, 2, nreq); 2296 2297 if (nreq < 0) { 2298 kfree(entries); 2299 goto no_msi; 2300 } else if (nreq < MSIX_LEGACY_SZ + 2301 dev->caps.num_ports * MIN_MSIX_P_PORT) { 2302 /*Working in legacy mode , all EQ's shared*/ 2303 dev->caps.comp_pool = 0; 2304 dev->caps.num_comp_vectors = nreq - 1; 2305 } else { 2306 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ; 2307 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1; 2308 } 2309 for (i = 0; i < nreq; ++i) 2310 priv->eq_table.eq[i].irq = entries[i].vector; 2311 2312 dev->flags |= MLX4_FLAG_MSI_X; 2313 2314 kfree(entries); 2315 return; 2316 } 2317 2318 no_msi: 2319 dev->caps.num_comp_vectors = 1; 2320 dev->caps.comp_pool = 0; 2321 2322 for (i = 0; i < 2; ++i) 2323 priv->eq_table.eq[i].irq = dev->pdev->irq; 2324 } 2325 2326 static int mlx4_init_port_info(struct mlx4_dev *dev, int port) 2327 { 2328 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; 2329 int err = 0; 2330 2331 info->dev = dev; 2332 info->port = port; 2333 if (!mlx4_is_slave(dev)) { 2334 mlx4_init_mac_table(dev, &info->mac_table); 2335 mlx4_init_vlan_table(dev, &info->vlan_table); 2336 mlx4_init_roce_gid_table(dev, &info->gid_table); 2337 info->base_qpn = mlx4_get_base_qpn(dev, port); 2338 } 2339 2340 sprintf(info->dev_name, "mlx4_port%d", port); 2341 info->port_attr.attr.name = info->dev_name; 2342 if (mlx4_is_mfunc(dev)) 2343 info->port_attr.attr.mode = S_IRUGO; 2344 else { 2345 info->port_attr.attr.mode = S_IRUGO | S_IWUSR; 2346 info->port_attr.store = set_port_type; 2347 } 2348 info->port_attr.show = show_port_type; 2349 sysfs_attr_init(&info->port_attr.attr); 2350 2351 err = device_create_file(&dev->pdev->dev, &info->port_attr); 2352 if (err) { 2353 mlx4_err(dev, "Failed to create file for port %d\n", port); 2354 info->port = -1; 2355 } 2356 2357 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); 2358 info->port_mtu_attr.attr.name = info->dev_mtu_name; 2359 if (mlx4_is_mfunc(dev)) 2360 info->port_mtu_attr.attr.mode = S_IRUGO; 2361 else { 2362 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR; 2363 info->port_mtu_attr.store = set_port_ib_mtu; 2364 } 2365 info->port_mtu_attr.show = show_port_ib_mtu; 2366 sysfs_attr_init(&info->port_mtu_attr.attr); 2367 2368 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr); 2369 if (err) { 2370 mlx4_err(dev, "Failed to create mtu file for port %d\n", port); 2371 device_remove_file(&info->dev->pdev->dev, &info->port_attr); 2372 info->port = -1; 2373 } 2374 2375 return err; 2376 } 2377 2378 static void mlx4_cleanup_port_info(struct mlx4_port_info *info) 2379 { 2380 if (info->port < 0) 2381 return; 2382 2383 device_remove_file(&info->dev->pdev->dev, &info->port_attr); 2384 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr); 2385 } 2386 2387 static int mlx4_init_steering(struct mlx4_dev *dev) 2388 { 2389 struct mlx4_priv *priv = mlx4_priv(dev); 2390 int num_entries = dev->caps.num_ports; 2391 int i, j; 2392 2393 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL); 2394 if (!priv->steer) 2395 return -ENOMEM; 2396 2397 for (i = 0; i < num_entries; i++) 2398 for (j = 0; j < MLX4_NUM_STEERS; j++) { 2399 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); 2400 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); 2401 } 2402 return 0; 2403 } 2404 2405 static void mlx4_clear_steering(struct mlx4_dev *dev) 2406 { 2407 struct mlx4_priv *priv = mlx4_priv(dev); 2408 struct mlx4_steer_index *entry, *tmp_entry; 2409 struct mlx4_promisc_qp *pqp, *tmp_pqp; 2410 int num_entries = dev->caps.num_ports; 2411 int i, j; 2412 2413 for (i = 0; i < num_entries; i++) { 2414 for (j = 0; j < MLX4_NUM_STEERS; j++) { 2415 list_for_each_entry_safe(pqp, tmp_pqp, 2416 &priv->steer[i].promisc_qps[j], 2417 list) { 2418 list_del(&pqp->list); 2419 kfree(pqp); 2420 } 2421 list_for_each_entry_safe(entry, tmp_entry, 2422 &priv->steer[i].steer_entries[j], 2423 list) { 2424 list_del(&entry->list); 2425 list_for_each_entry_safe(pqp, tmp_pqp, 2426 &entry->duplicates, 2427 list) { 2428 list_del(&pqp->list); 2429 kfree(pqp); 2430 } 2431 kfree(entry); 2432 } 2433 } 2434 } 2435 kfree(priv->steer); 2436 } 2437 2438 static int extended_func_num(struct pci_dev *pdev) 2439 { 2440 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); 2441 } 2442 2443 #define MLX4_OWNER_BASE 0x8069c 2444 #define MLX4_OWNER_SIZE 4 2445 2446 static int mlx4_get_ownership(struct mlx4_dev *dev) 2447 { 2448 void __iomem *owner; 2449 u32 ret; 2450 2451 if (pci_channel_offline(dev->pdev)) 2452 return -EIO; 2453 2454 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, 2455 MLX4_OWNER_SIZE); 2456 if (!owner) { 2457 mlx4_err(dev, "Failed to obtain ownership bit\n"); 2458 return -ENOMEM; 2459 } 2460 2461 ret = readl(owner); 2462 iounmap(owner); 2463 return (int) !!ret; 2464 } 2465 2466 static void mlx4_free_ownership(struct mlx4_dev *dev) 2467 { 2468 void __iomem *owner; 2469 2470 if (pci_channel_offline(dev->pdev)) 2471 return; 2472 2473 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, 2474 MLX4_OWNER_SIZE); 2475 if (!owner) { 2476 mlx4_err(dev, "Failed to obtain ownership bit\n"); 2477 return; 2478 } 2479 writel(0, owner); 2480 msleep(1000); 2481 iounmap(owner); 2482 } 2483 2484 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\ 2485 !!((flags) & MLX4_FLAG_MASTER)) 2486 2487 static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev, 2488 u8 total_vfs, int existing_vfs) 2489 { 2490 u64 dev_flags = dev->flags; 2491 2492 dev->dev_vfs = kzalloc( 2493 total_vfs * sizeof(*dev->dev_vfs), 2494 GFP_KERNEL); 2495 if (NULL == dev->dev_vfs) { 2496 mlx4_err(dev, "Failed to allocate memory for VFs\n"); 2497 goto disable_sriov; 2498 } else if (!(dev->flags & MLX4_FLAG_SRIOV)) { 2499 int err = 0; 2500 2501 atomic_inc(&pf_loading); 2502 if (existing_vfs) { 2503 if (existing_vfs != total_vfs) 2504 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n", 2505 existing_vfs, total_vfs); 2506 } else { 2507 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs); 2508 err = pci_enable_sriov(pdev, total_vfs); 2509 } 2510 if (err) { 2511 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n", 2512 err); 2513 atomic_dec(&pf_loading); 2514 goto disable_sriov; 2515 } else { 2516 mlx4_warn(dev, "Running in master mode\n"); 2517 dev_flags |= MLX4_FLAG_SRIOV | 2518 MLX4_FLAG_MASTER; 2519 dev_flags &= ~MLX4_FLAG_SLAVE; 2520 dev->num_vfs = total_vfs; 2521 } 2522 } 2523 return dev_flags; 2524 2525 disable_sriov: 2526 dev->num_vfs = 0; 2527 kfree(dev->dev_vfs); 2528 return dev_flags & ~MLX4_FLAG_MASTER; 2529 } 2530 2531 enum { 2532 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1, 2533 }; 2534 2535 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 2536 int *nvfs) 2537 { 2538 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2]; 2539 /* Checking for 64 VFs as a limitation of CX2 */ 2540 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) && 2541 requested_vfs >= 64) { 2542 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n", 2543 requested_vfs); 2544 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64; 2545 } 2546 return 0; 2547 } 2548 2549 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data, 2550 int total_vfs, int *nvfs, struct mlx4_priv *priv) 2551 { 2552 struct mlx4_dev *dev; 2553 unsigned sum = 0; 2554 int err; 2555 int port; 2556 int i; 2557 struct mlx4_dev_cap *dev_cap = NULL; 2558 int existing_vfs = 0; 2559 2560 dev = &priv->dev; 2561 2562 INIT_LIST_HEAD(&priv->ctx_list); 2563 spin_lock_init(&priv->ctx_lock); 2564 2565 mutex_init(&priv->port_mutex); 2566 2567 INIT_LIST_HEAD(&priv->pgdir_list); 2568 mutex_init(&priv->pgdir_mutex); 2569 2570 INIT_LIST_HEAD(&priv->bf_list); 2571 mutex_init(&priv->bf_mutex); 2572 2573 dev->rev_id = pdev->revision; 2574 dev->numa_node = dev_to_node(&pdev->dev); 2575 2576 /* Detect if this device is a virtual function */ 2577 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 2578 mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); 2579 dev->flags |= MLX4_FLAG_SLAVE; 2580 } else { 2581 /* We reset the device and enable SRIOV only for physical 2582 * devices. Try to claim ownership on the device; 2583 * if already taken, skip -- do not allow multiple PFs */ 2584 err = mlx4_get_ownership(dev); 2585 if (err) { 2586 if (err < 0) 2587 return err; 2588 else { 2589 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n"); 2590 return -EINVAL; 2591 } 2592 } 2593 2594 atomic_set(&priv->opreq_count, 0); 2595 INIT_WORK(&priv->opreq_task, mlx4_opreq_action); 2596 2597 /* 2598 * Now reset the HCA before we touch the PCI capabilities or 2599 * attempt a firmware command, since a boot ROM may have left 2600 * the HCA in an undefined state. 2601 */ 2602 err = mlx4_reset(dev); 2603 if (err) { 2604 mlx4_err(dev, "Failed to reset HCA, aborting\n"); 2605 goto err_sriov; 2606 } 2607 2608 if (total_vfs) { 2609 existing_vfs = pci_num_vf(pdev); 2610 dev->flags = MLX4_FLAG_MASTER; 2611 dev->num_vfs = total_vfs; 2612 } 2613 } 2614 2615 slave_start: 2616 err = mlx4_cmd_init(dev); 2617 if (err) { 2618 mlx4_err(dev, "Failed to init command interface, aborting\n"); 2619 goto err_sriov; 2620 } 2621 2622 /* In slave functions, the communication channel must be initialized 2623 * before posting commands. Also, init num_slaves before calling 2624 * mlx4_init_hca */ 2625 if (mlx4_is_mfunc(dev)) { 2626 if (mlx4_is_master(dev)) { 2627 dev->num_slaves = MLX4_MAX_NUM_SLAVES; 2628 2629 } else { 2630 dev->num_slaves = 0; 2631 err = mlx4_multi_func_init(dev); 2632 if (err) { 2633 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n"); 2634 goto err_cmd; 2635 } 2636 } 2637 } 2638 2639 err = mlx4_init_fw(dev); 2640 if (err) { 2641 mlx4_err(dev, "Failed to init fw, aborting.\n"); 2642 goto err_mfunc; 2643 } 2644 2645 if (mlx4_is_master(dev)) { 2646 if (!dev_cap) { 2647 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 2648 2649 if (!dev_cap) { 2650 err = -ENOMEM; 2651 goto err_fw; 2652 } 2653 2654 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 2655 if (err) { 2656 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 2657 goto err_fw; 2658 } 2659 2660 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 2661 goto err_fw; 2662 2663 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 2664 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs, 2665 existing_vfs); 2666 2667 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 2668 dev->flags = dev_flags; 2669 if (!SRIOV_VALID_STATE(dev->flags)) { 2670 mlx4_err(dev, "Invalid SRIOV state\n"); 2671 goto err_sriov; 2672 } 2673 err = mlx4_reset(dev); 2674 if (err) { 2675 mlx4_err(dev, "Failed to reset HCA, aborting.\n"); 2676 goto err_sriov; 2677 } 2678 goto slave_start; 2679 } 2680 } else { 2681 /* Legacy mode FW requires SRIOV to be enabled before 2682 * doing QUERY_DEV_CAP, since max_eq's value is different if 2683 * SRIOV is enabled. 2684 */ 2685 memset(dev_cap, 0, sizeof(*dev_cap)); 2686 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 2687 if (err) { 2688 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 2689 goto err_fw; 2690 } 2691 2692 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 2693 goto err_fw; 2694 } 2695 } 2696 2697 err = mlx4_init_hca(dev); 2698 if (err) { 2699 if (err == -EACCES) { 2700 /* Not primary Physical function 2701 * Running in slave mode */ 2702 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 2703 /* We're not a PF */ 2704 if (dev->flags & MLX4_FLAG_SRIOV) { 2705 if (!existing_vfs) 2706 pci_disable_sriov(pdev); 2707 if (mlx4_is_master(dev)) 2708 atomic_dec(&pf_loading); 2709 dev->flags &= ~MLX4_FLAG_SRIOV; 2710 } 2711 if (!mlx4_is_slave(dev)) 2712 mlx4_free_ownership(dev); 2713 dev->flags |= MLX4_FLAG_SLAVE; 2714 dev->flags &= ~MLX4_FLAG_MASTER; 2715 goto slave_start; 2716 } else 2717 goto err_fw; 2718 } 2719 2720 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 2721 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs, existing_vfs); 2722 2723 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) { 2724 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR); 2725 dev->flags = dev_flags; 2726 err = mlx4_cmd_init(dev); 2727 if (err) { 2728 /* Only VHCR is cleaned up, so could still 2729 * send FW commands 2730 */ 2731 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n"); 2732 goto err_close; 2733 } 2734 } else { 2735 dev->flags = dev_flags; 2736 } 2737 2738 if (!SRIOV_VALID_STATE(dev->flags)) { 2739 mlx4_err(dev, "Invalid SRIOV state\n"); 2740 goto err_close; 2741 } 2742 } 2743 2744 /* check if the device is functioning at its maximum possible speed. 2745 * No return code for this call, just warn the user in case of PCI 2746 * express device capabilities are under-satisfied by the bus. 2747 */ 2748 if (!mlx4_is_slave(dev)) 2749 mlx4_check_pcie_caps(dev); 2750 2751 /* In master functions, the communication channel must be initialized 2752 * after obtaining its address from fw */ 2753 if (mlx4_is_master(dev)) { 2754 int ib_ports = 0; 2755 2756 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2757 ib_ports++; 2758 2759 if (ib_ports && 2760 (num_vfs_argc > 1 || probe_vfs_argc > 1)) { 2761 mlx4_err(dev, 2762 "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n"); 2763 err = -EINVAL; 2764 goto err_close; 2765 } 2766 if (dev->caps.num_ports < 2 && 2767 num_vfs_argc > 1) { 2768 err = -EINVAL; 2769 mlx4_err(dev, 2770 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n", 2771 dev->caps.num_ports); 2772 goto err_close; 2773 } 2774 memcpy(dev->nvfs, nvfs, sizeof(dev->nvfs)); 2775 2776 for (i = 0; i < sizeof(dev->nvfs)/sizeof(dev->nvfs[0]); i++) { 2777 unsigned j; 2778 2779 for (j = 0; j < dev->nvfs[i]; ++sum, ++j) { 2780 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1; 2781 dev->dev_vfs[sum].n_ports = i < 2 ? 1 : 2782 dev->caps.num_ports; 2783 } 2784 } 2785 2786 /* In master functions, the communication channel 2787 * must be initialized after obtaining its address from fw 2788 */ 2789 err = mlx4_multi_func_init(dev); 2790 if (err) { 2791 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n"); 2792 goto err_close; 2793 } 2794 } 2795 2796 err = mlx4_alloc_eq_table(dev); 2797 if (err) 2798 goto err_master_mfunc; 2799 2800 priv->msix_ctl.pool_bm = 0; 2801 mutex_init(&priv->msix_ctl.pool_lock); 2802 2803 mlx4_enable_msi_x(dev); 2804 if ((mlx4_is_mfunc(dev)) && 2805 !(dev->flags & MLX4_FLAG_MSI_X)) { 2806 err = -ENOSYS; 2807 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n"); 2808 goto err_free_eq; 2809 } 2810 2811 if (!mlx4_is_slave(dev)) { 2812 err = mlx4_init_steering(dev); 2813 if (err) 2814 goto err_disable_msix; 2815 } 2816 2817 err = mlx4_setup_hca(dev); 2818 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && 2819 !mlx4_is_mfunc(dev)) { 2820 dev->flags &= ~MLX4_FLAG_MSI_X; 2821 dev->caps.num_comp_vectors = 1; 2822 dev->caps.comp_pool = 0; 2823 pci_disable_msix(pdev); 2824 err = mlx4_setup_hca(dev); 2825 } 2826 2827 if (err) 2828 goto err_steer; 2829 2830 mlx4_init_quotas(dev); 2831 2832 for (port = 1; port <= dev->caps.num_ports; port++) { 2833 err = mlx4_init_port_info(dev, port); 2834 if (err) 2835 goto err_port; 2836 } 2837 2838 err = mlx4_register_device(dev); 2839 if (err) 2840 goto err_port; 2841 2842 mlx4_request_modules(dev); 2843 2844 mlx4_sense_init(dev); 2845 mlx4_start_sense(dev); 2846 2847 priv->removed = 0; 2848 2849 if (mlx4_is_master(dev) && dev->num_vfs) 2850 atomic_dec(&pf_loading); 2851 2852 return 0; 2853 2854 err_port: 2855 for (--port; port >= 1; --port) 2856 mlx4_cleanup_port_info(&priv->port[port]); 2857 2858 mlx4_cleanup_counters_table(dev); 2859 mlx4_cleanup_qp_table(dev); 2860 mlx4_cleanup_srq_table(dev); 2861 mlx4_cleanup_cq_table(dev); 2862 mlx4_cmd_use_polling(dev); 2863 mlx4_cleanup_eq_table(dev); 2864 mlx4_cleanup_mcg_table(dev); 2865 mlx4_cleanup_mr_table(dev); 2866 mlx4_cleanup_xrcd_table(dev); 2867 mlx4_cleanup_pd_table(dev); 2868 mlx4_cleanup_uar_table(dev); 2869 2870 err_steer: 2871 if (!mlx4_is_slave(dev)) 2872 mlx4_clear_steering(dev); 2873 2874 err_disable_msix: 2875 if (dev->flags & MLX4_FLAG_MSI_X) 2876 pci_disable_msix(pdev); 2877 2878 err_free_eq: 2879 mlx4_free_eq_table(dev); 2880 2881 err_master_mfunc: 2882 if (mlx4_is_master(dev)) 2883 mlx4_multi_func_cleanup(dev); 2884 2885 if (mlx4_is_slave(dev)) { 2886 kfree(dev->caps.qp0_qkey); 2887 kfree(dev->caps.qp0_tunnel); 2888 kfree(dev->caps.qp0_proxy); 2889 kfree(dev->caps.qp1_tunnel); 2890 kfree(dev->caps.qp1_proxy); 2891 } 2892 2893 err_close: 2894 mlx4_close_hca(dev); 2895 2896 err_fw: 2897 mlx4_close_fw(dev); 2898 2899 err_mfunc: 2900 if (mlx4_is_slave(dev)) 2901 mlx4_multi_func_cleanup(dev); 2902 2903 err_cmd: 2904 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 2905 2906 err_sriov: 2907 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) 2908 pci_disable_sriov(pdev); 2909 2910 if (mlx4_is_master(dev) && dev->num_vfs) 2911 atomic_dec(&pf_loading); 2912 2913 kfree(priv->dev.dev_vfs); 2914 2915 if (!mlx4_is_slave(dev)) 2916 mlx4_free_ownership(dev); 2917 2918 kfree(dev_cap); 2919 return err; 2920 } 2921 2922 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data, 2923 struct mlx4_priv *priv) 2924 { 2925 int err; 2926 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 2927 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 2928 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = { 2929 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} }; 2930 unsigned total_vfs = 0; 2931 unsigned int i; 2932 2933 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); 2934 2935 err = pci_enable_device(pdev); 2936 if (err) { 2937 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 2938 return err; 2939 } 2940 2941 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS 2942 * per port, we must limit the number of VFs to 63 (since their are 2943 * 128 MACs) 2944 */ 2945 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc; 2946 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) { 2947 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i]; 2948 if (nvfs[i] < 0) { 2949 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n"); 2950 err = -EINVAL; 2951 goto err_disable_pdev; 2952 } 2953 } 2954 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc; 2955 i++) { 2956 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i]; 2957 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) { 2958 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n"); 2959 err = -EINVAL; 2960 goto err_disable_pdev; 2961 } 2962 } 2963 if (total_vfs >= MLX4_MAX_NUM_VF) { 2964 dev_err(&pdev->dev, 2965 "Requested more VF's (%d) than allowed (%d)\n", 2966 total_vfs, MLX4_MAX_NUM_VF - 1); 2967 err = -EINVAL; 2968 goto err_disable_pdev; 2969 } 2970 2971 for (i = 0; i < MLX4_MAX_PORTS; i++) { 2972 if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) { 2973 dev_err(&pdev->dev, 2974 "Requested more VF's (%d) for port (%d) than allowed (%d)\n", 2975 nvfs[i] + nvfs[2], i + 1, 2976 MLX4_MAX_NUM_VF_P_PORT - 1); 2977 err = -EINVAL; 2978 goto err_disable_pdev; 2979 } 2980 } 2981 2982 /* Check for BARs. */ 2983 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) && 2984 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 2985 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n", 2986 pci_dev_data, pci_resource_flags(pdev, 0)); 2987 err = -ENODEV; 2988 goto err_disable_pdev; 2989 } 2990 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 2991 dev_err(&pdev->dev, "Missing UAR, aborting\n"); 2992 err = -ENODEV; 2993 goto err_disable_pdev; 2994 } 2995 2996 err = pci_request_regions(pdev, DRV_NAME); 2997 if (err) { 2998 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 2999 goto err_disable_pdev; 3000 } 3001 3002 pci_set_master(pdev); 3003 3004 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 3005 if (err) { 3006 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 3007 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3008 if (err) { 3009 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 3010 goto err_release_regions; 3011 } 3012 } 3013 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 3014 if (err) { 3015 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 3016 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 3017 if (err) { 3018 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n"); 3019 goto err_release_regions; 3020 } 3021 } 3022 3023 /* Allow large DMA segments, up to the firmware limit of 1 GB */ 3024 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); 3025 /* Detect if this device is a virtual function */ 3026 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3027 /* When acting as pf, we normally skip vfs unless explicitly 3028 * requested to probe them. 3029 */ 3030 if (total_vfs) { 3031 unsigned vfs_offset = 0; 3032 3033 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && 3034 vfs_offset + nvfs[i] < extended_func_num(pdev); 3035 vfs_offset += nvfs[i], i++) 3036 ; 3037 if (i == sizeof(nvfs)/sizeof(nvfs[0])) { 3038 err = -ENODEV; 3039 goto err_release_regions; 3040 } 3041 if ((extended_func_num(pdev) - vfs_offset) 3042 > prb_vf[i]) { 3043 dev_warn(&pdev->dev, "Skipping virtual function:%d\n", 3044 extended_func_num(pdev)); 3045 err = -ENODEV; 3046 goto err_release_regions; 3047 } 3048 } 3049 } 3050 3051 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv); 3052 if (err) 3053 goto err_release_regions; 3054 return 0; 3055 3056 err_release_regions: 3057 pci_release_regions(pdev); 3058 3059 err_disable_pdev: 3060 pci_disable_device(pdev); 3061 pci_set_drvdata(pdev, NULL); 3062 return err; 3063 } 3064 3065 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 3066 { 3067 struct mlx4_priv *priv; 3068 struct mlx4_dev *dev; 3069 int ret; 3070 3071 printk_once(KERN_INFO "%s", mlx4_version); 3072 3073 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 3074 if (!priv) 3075 return -ENOMEM; 3076 3077 dev = &priv->dev; 3078 dev->pdev = pdev; 3079 pci_set_drvdata(pdev, dev); 3080 priv->pci_dev_data = id->driver_data; 3081 3082 ret = __mlx4_init_one(pdev, id->driver_data, priv); 3083 if (ret) 3084 kfree(priv); 3085 3086 return ret; 3087 } 3088 3089 static void mlx4_unload_one(struct pci_dev *pdev) 3090 { 3091 struct mlx4_dev *dev = pci_get_drvdata(pdev); 3092 struct mlx4_priv *priv = mlx4_priv(dev); 3093 int pci_dev_data; 3094 int p; 3095 int active_vfs = 0; 3096 3097 if (priv->removed) 3098 return; 3099 3100 pci_dev_data = priv->pci_dev_data; 3101 3102 /* Disabling SR-IOV is not allowed while there are active vf's */ 3103 if (mlx4_is_master(dev)) { 3104 active_vfs = mlx4_how_many_lives_vf(dev); 3105 if (active_vfs) { 3106 pr_warn("Removing PF when there are active VF's !!\n"); 3107 pr_warn("Will not disable SR-IOV.\n"); 3108 } 3109 } 3110 mlx4_stop_sense(dev); 3111 mlx4_unregister_device(dev); 3112 3113 for (p = 1; p <= dev->caps.num_ports; p++) { 3114 mlx4_cleanup_port_info(&priv->port[p]); 3115 mlx4_CLOSE_PORT(dev, p); 3116 } 3117 3118 if (mlx4_is_master(dev)) 3119 mlx4_free_resource_tracker(dev, 3120 RES_TR_FREE_SLAVES_ONLY); 3121 3122 mlx4_cleanup_counters_table(dev); 3123 mlx4_cleanup_qp_table(dev); 3124 mlx4_cleanup_srq_table(dev); 3125 mlx4_cleanup_cq_table(dev); 3126 mlx4_cmd_use_polling(dev); 3127 mlx4_cleanup_eq_table(dev); 3128 mlx4_cleanup_mcg_table(dev); 3129 mlx4_cleanup_mr_table(dev); 3130 mlx4_cleanup_xrcd_table(dev); 3131 mlx4_cleanup_pd_table(dev); 3132 3133 if (mlx4_is_master(dev)) 3134 mlx4_free_resource_tracker(dev, 3135 RES_TR_FREE_STRUCTS_ONLY); 3136 3137 iounmap(priv->kar); 3138 mlx4_uar_free(dev, &priv->driver_uar); 3139 mlx4_cleanup_uar_table(dev); 3140 if (!mlx4_is_slave(dev)) 3141 mlx4_clear_steering(dev); 3142 mlx4_free_eq_table(dev); 3143 if (mlx4_is_master(dev)) 3144 mlx4_multi_func_cleanup(dev); 3145 mlx4_close_hca(dev); 3146 mlx4_close_fw(dev); 3147 if (mlx4_is_slave(dev)) 3148 mlx4_multi_func_cleanup(dev); 3149 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3150 3151 if (dev->flags & MLX4_FLAG_MSI_X) 3152 pci_disable_msix(pdev); 3153 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) { 3154 mlx4_warn(dev, "Disabling SR-IOV\n"); 3155 pci_disable_sriov(pdev); 3156 dev->flags &= ~MLX4_FLAG_SRIOV; 3157 dev->num_vfs = 0; 3158 } 3159 3160 if (!mlx4_is_slave(dev)) 3161 mlx4_free_ownership(dev); 3162 3163 kfree(dev->caps.qp0_qkey); 3164 kfree(dev->caps.qp0_tunnel); 3165 kfree(dev->caps.qp0_proxy); 3166 kfree(dev->caps.qp1_tunnel); 3167 kfree(dev->caps.qp1_proxy); 3168 kfree(dev->dev_vfs); 3169 3170 memset(priv, 0, sizeof(*priv)); 3171 priv->pci_dev_data = pci_dev_data; 3172 priv->removed = 1; 3173 } 3174 3175 static void mlx4_remove_one(struct pci_dev *pdev) 3176 { 3177 struct mlx4_dev *dev = pci_get_drvdata(pdev); 3178 struct mlx4_priv *priv = mlx4_priv(dev); 3179 3180 mlx4_unload_one(pdev); 3181 pci_release_regions(pdev); 3182 pci_disable_device(pdev); 3183 kfree(priv); 3184 pci_set_drvdata(pdev, NULL); 3185 } 3186 3187 int mlx4_restart_one(struct pci_dev *pdev) 3188 { 3189 struct mlx4_dev *dev = pci_get_drvdata(pdev); 3190 struct mlx4_priv *priv = mlx4_priv(dev); 3191 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3192 int pci_dev_data, err, total_vfs; 3193 3194 pci_dev_data = priv->pci_dev_data; 3195 total_vfs = dev->num_vfs; 3196 memcpy(nvfs, dev->nvfs, sizeof(dev->nvfs)); 3197 3198 mlx4_unload_one(pdev); 3199 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv); 3200 if (err) { 3201 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n", 3202 __func__, pci_name(pdev), err); 3203 return err; 3204 } 3205 3206 return err; 3207 } 3208 3209 static const struct pci_device_id mlx4_pci_table[] = { 3210 /* MT25408 "Hermon" SDR */ 3211 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3212 /* MT25408 "Hermon" DDR */ 3213 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3214 /* MT25408 "Hermon" QDR */ 3215 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3216 /* MT25408 "Hermon" DDR PCIe gen2 */ 3217 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3218 /* MT25408 "Hermon" QDR PCIe gen2 */ 3219 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3220 /* MT25408 "Hermon" EN 10GigE */ 3221 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3222 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */ 3223 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3224 /* MT25458 ConnectX EN 10GBASE-T 10GigE */ 3225 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3226 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */ 3227 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3228 /* MT26468 ConnectX EN 10GigE PCIe gen2*/ 3229 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3230 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */ 3231 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3232 /* MT26478 ConnectX2 40GigE PCIe gen2 */ 3233 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3234 /* MT25400 Family [ConnectX-2 Virtual Function] */ 3235 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF }, 3236 /* MT27500 Family [ConnectX-3] */ 3237 { PCI_VDEVICE(MELLANOX, 0x1003), 0 }, 3238 /* MT27500 Family [ConnectX-3 Virtual Function] */ 3239 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF }, 3240 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */ 3241 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */ 3242 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */ 3243 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */ 3244 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */ 3245 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */ 3246 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */ 3247 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */ 3248 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */ 3249 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */ 3250 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */ 3251 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */ 3252 { 0, } 3253 }; 3254 3255 MODULE_DEVICE_TABLE(pci, mlx4_pci_table); 3256 3257 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, 3258 pci_channel_state_t state) 3259 { 3260 mlx4_unload_one(pdev); 3261 3262 return state == pci_channel_io_perm_failure ? 3263 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 3264 } 3265 3266 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) 3267 { 3268 struct mlx4_dev *dev = pci_get_drvdata(pdev); 3269 struct mlx4_priv *priv = mlx4_priv(dev); 3270 int ret; 3271 3272 ret = __mlx4_init_one(pdev, priv->pci_dev_data, priv); 3273 3274 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 3275 } 3276 3277 static const struct pci_error_handlers mlx4_err_handler = { 3278 .error_detected = mlx4_pci_err_detected, 3279 .slot_reset = mlx4_pci_slot_reset, 3280 }; 3281 3282 static struct pci_driver mlx4_driver = { 3283 .name = DRV_NAME, 3284 .id_table = mlx4_pci_table, 3285 .probe = mlx4_init_one, 3286 .shutdown = mlx4_unload_one, 3287 .remove = mlx4_remove_one, 3288 .err_handler = &mlx4_err_handler, 3289 }; 3290 3291 static int __init mlx4_verify_params(void) 3292 { 3293 if ((log_num_mac < 0) || (log_num_mac > 7)) { 3294 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac); 3295 return -1; 3296 } 3297 3298 if (log_num_vlan != 0) 3299 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n", 3300 MLX4_LOG_NUM_VLANS); 3301 3302 if (use_prio != 0) 3303 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n"); 3304 3305 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) { 3306 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n", 3307 log_mtts_per_seg); 3308 return -1; 3309 } 3310 3311 /* Check if module param for ports type has legal combination */ 3312 if (port_type_array[0] == false && port_type_array[1] == true) { 3313 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); 3314 port_type_array[0] = true; 3315 } 3316 3317 if (mlx4_log_num_mgm_entry_size < -7 || 3318 (mlx4_log_num_mgm_entry_size > 0 && 3319 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || 3320 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) { 3321 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n", 3322 mlx4_log_num_mgm_entry_size, 3323 MLX4_MIN_MGM_LOG_ENTRY_SIZE, 3324 MLX4_MAX_MGM_LOG_ENTRY_SIZE); 3325 return -1; 3326 } 3327 3328 return 0; 3329 } 3330 3331 static int __init mlx4_init(void) 3332 { 3333 int ret; 3334 3335 if (mlx4_verify_params()) 3336 return -EINVAL; 3337 3338 mlx4_catas_init(); 3339 3340 mlx4_wq = create_singlethread_workqueue("mlx4"); 3341 if (!mlx4_wq) 3342 return -ENOMEM; 3343 3344 ret = pci_register_driver(&mlx4_driver); 3345 if (ret < 0) 3346 destroy_workqueue(mlx4_wq); 3347 return ret < 0 ? ret : 0; 3348 } 3349 3350 static void __exit mlx4_cleanup(void) 3351 { 3352 pci_unregister_driver(&mlx4_driver); 3353 destroy_workqueue(mlx4_wq); 3354 } 3355 3356 module_init(mlx4_init); 3357 module_exit(mlx4_cleanup); 3358