1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/etherdevice.h> 36 #include <linux/mlx4/cmd.h> 37 #include <linux/module.h> 38 #include <linux/cache.h> 39 40 #include "fw.h" 41 #include "icm.h" 42 43 enum { 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2, 45 MLX4_COMMAND_INTERFACE_MAX_REV = 3, 46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, 47 }; 48 49 extern void __buggy_use_of_MLX4_GET(void); 50 extern void __buggy_use_of_MLX4_PUT(void); 51 52 static bool enable_qos = true; 53 module_param(enable_qos, bool, 0444); 54 MODULE_PARM_DESC(enable_qos, "Enable Enhanced QoS support (default: on)"); 55 56 #define MLX4_GET(dest, source, offset) \ 57 do { \ 58 void *__p = (char *) (source) + (offset); \ 59 u64 val; \ 60 switch (sizeof (dest)) { \ 61 case 1: (dest) = *(u8 *) __p; break; \ 62 case 2: (dest) = be16_to_cpup(__p); break; \ 63 case 4: (dest) = be32_to_cpup(__p); break; \ 64 case 8: val = get_unaligned((u64 *)__p); \ 65 (dest) = be64_to_cpu(val); break; \ 66 default: __buggy_use_of_MLX4_GET(); \ 67 } \ 68 } while (0) 69 70 #define MLX4_PUT(dest, source, offset) \ 71 do { \ 72 void *__d = ((char *) (dest) + (offset)); \ 73 switch (sizeof(source)) { \ 74 case 1: *(u8 *) __d = (source); break; \ 75 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ 76 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ 77 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ 78 default: __buggy_use_of_MLX4_PUT(); \ 79 } \ 80 } while (0) 81 82 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) 83 { 84 static const char *fname[] = { 85 [ 0] = "RC transport", 86 [ 1] = "UC transport", 87 [ 2] = "UD transport", 88 [ 3] = "XRC transport", 89 [ 6] = "SRQ support", 90 [ 7] = "IPoIB checksum offload", 91 [ 8] = "P_Key violation counter", 92 [ 9] = "Q_Key violation counter", 93 [12] = "Dual Port Different Protocol (DPDP) support", 94 [15] = "Big LSO headers", 95 [16] = "MW support", 96 [17] = "APM support", 97 [18] = "Atomic ops support", 98 [19] = "Raw multicast support", 99 [20] = "Address vector port checking support", 100 [21] = "UD multicast support", 101 [30] = "IBoE support", 102 [32] = "Unicast loopback support", 103 [34] = "FCS header control", 104 [37] = "Wake On LAN (port1) support", 105 [38] = "Wake On LAN (port2) support", 106 [40] = "UDP RSS support", 107 [41] = "Unicast VEP steering support", 108 [42] = "Multicast VEP steering support", 109 [48] = "Counters support", 110 [52] = "RSS IP fragments support", 111 [53] = "Port ETS Scheduler support", 112 [55] = "Port link type sensing support", 113 [59] = "Port management change event support", 114 [61] = "64 byte EQE support", 115 [62] = "64 byte CQE support", 116 }; 117 int i; 118 119 mlx4_dbg(dev, "DEV_CAP flags:\n"); 120 for (i = 0; i < ARRAY_SIZE(fname); ++i) 121 if (fname[i] && (flags & (1LL << i))) 122 mlx4_dbg(dev, " %s\n", fname[i]); 123 } 124 125 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) 126 { 127 static const char * const fname[] = { 128 [0] = "RSS support", 129 [1] = "RSS Toeplitz Hash Function support", 130 [2] = "RSS XOR Hash Function support", 131 [3] = "Device managed flow steering support", 132 [4] = "Automatic MAC reassignment support", 133 [5] = "Time stamping support", 134 [6] = "VST (control vlan insertion/stripping) support", 135 [7] = "FSM (MAC anti-spoofing) support", 136 [8] = "Dynamic QP updates support", 137 [9] = "Device managed flow steering IPoIB support", 138 [10] = "TCP/IP offloads/flow-steering for VXLAN support", 139 [11] = "MAD DEMUX (Secure-Host) support", 140 [12] = "Large cache line (>64B) CQE stride support", 141 [13] = "Large cache line (>64B) EQE stride support", 142 [14] = "Ethernet protocol control support", 143 [15] = "Ethernet Backplane autoneg support", 144 [16] = "CONFIG DEV support", 145 [17] = "Asymmetric EQs support", 146 [18] = "More than 80 VFs support", 147 [19] = "Performance optimized for limited rule configuration flow steering support", 148 [20] = "Recoverable error events support", 149 [21] = "Port Remap support", 150 [22] = "QCN support", 151 [23] = "QP rate limiting support", 152 [24] = "Ethernet Flow control statistics support", 153 [25] = "Granular QoS per VF support", 154 [26] = "Port ETS Scheduler support", 155 [27] = "Port beacon support", 156 [28] = "RX-ALL support", 157 [29] = "802.1ad offload support", 158 [31] = "Modifying loopback source checks using UPDATE_QP support", 159 [32] = "Loopback source checks support", 160 [33] = "RoCEv2 support", 161 [34] = "DMFS Sniffer support (UC & MC)", 162 [35] = "QinQ VST mode support", 163 }; 164 int i; 165 166 for (i = 0; i < ARRAY_SIZE(fname); ++i) 167 if (fname[i] && (flags & (1LL << i))) 168 mlx4_dbg(dev, " %s\n", fname[i]); 169 } 170 171 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) 172 { 173 struct mlx4_cmd_mailbox *mailbox; 174 u32 *inbox; 175 int err = 0; 176 177 #define MOD_STAT_CFG_IN_SIZE 0x100 178 179 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 180 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 181 182 mailbox = mlx4_alloc_cmd_mailbox(dev); 183 if (IS_ERR(mailbox)) 184 return PTR_ERR(mailbox); 185 inbox = mailbox->buf; 186 187 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); 188 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); 189 190 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, 191 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 192 193 mlx4_free_cmd_mailbox(dev, mailbox); 194 return err; 195 } 196 197 int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave) 198 { 199 struct mlx4_cmd_mailbox *mailbox; 200 u32 *outbox; 201 u8 in_modifier; 202 u8 field; 203 u16 field16; 204 int err; 205 206 #define QUERY_FUNC_BUS_OFFSET 0x00 207 #define QUERY_FUNC_DEVICE_OFFSET 0x01 208 #define QUERY_FUNC_FUNCTION_OFFSET 0x01 209 #define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03 210 #define QUERY_FUNC_RSVD_EQS_OFFSET 0x04 211 #define QUERY_FUNC_MAX_EQ_OFFSET 0x06 212 #define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b 213 214 mailbox = mlx4_alloc_cmd_mailbox(dev); 215 if (IS_ERR(mailbox)) 216 return PTR_ERR(mailbox); 217 outbox = mailbox->buf; 218 219 in_modifier = slave; 220 221 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0, 222 MLX4_CMD_QUERY_FUNC, 223 MLX4_CMD_TIME_CLASS_A, 224 MLX4_CMD_NATIVE); 225 if (err) 226 goto out; 227 228 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET); 229 func->bus = field & 0xf; 230 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET); 231 func->device = field & 0xf1; 232 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET); 233 func->function = field & 0x7; 234 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET); 235 func->physical_function = field & 0xf; 236 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET); 237 func->rsvd_eqs = field16 & 0xffff; 238 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET); 239 func->max_eq = field16 & 0xffff; 240 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET); 241 func->rsvd_uars = field & 0x0f; 242 243 mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n", 244 func->bus, func->device, func->function, func->physical_function, 245 func->max_eq, func->rsvd_eqs, func->rsvd_uars); 246 247 out: 248 mlx4_free_cmd_mailbox(dev, mailbox); 249 return err; 250 } 251 252 static int mlx4_activate_vst_qinq(struct mlx4_priv *priv, int slave, int port) 253 { 254 struct mlx4_vport_oper_state *vp_oper; 255 struct mlx4_vport_state *vp_admin; 256 int err; 257 258 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; 259 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; 260 261 if (vp_admin->default_vlan != vp_oper->state.default_vlan) { 262 err = __mlx4_register_vlan(&priv->dev, port, 263 vp_admin->default_vlan, 264 &vp_oper->vlan_idx); 265 if (err) { 266 vp_oper->vlan_idx = NO_INDX; 267 mlx4_warn(&priv->dev, 268 "No vlan resources slave %d, port %d\n", 269 slave, port); 270 return err; 271 } 272 mlx4_dbg(&priv->dev, "alloc vlan %d idx %d slave %d port %d\n", 273 (int)(vp_oper->state.default_vlan), 274 vp_oper->vlan_idx, slave, port); 275 } 276 vp_oper->state.vlan_proto = vp_admin->vlan_proto; 277 vp_oper->state.default_vlan = vp_admin->default_vlan; 278 vp_oper->state.default_qos = vp_admin->default_qos; 279 280 return 0; 281 } 282 283 static int mlx4_handle_vst_qinq(struct mlx4_priv *priv, int slave, int port) 284 { 285 struct mlx4_vport_oper_state *vp_oper; 286 struct mlx4_slave_state *slave_state; 287 struct mlx4_vport_state *vp_admin; 288 int err; 289 290 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; 291 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; 292 slave_state = &priv->mfunc.master.slave_state[slave]; 293 294 if ((vp_admin->vlan_proto != htons(ETH_P_8021AD)) || 295 (!slave_state->active)) 296 return 0; 297 298 if (vp_oper->state.vlan_proto == vp_admin->vlan_proto && 299 vp_oper->state.default_vlan == vp_admin->default_vlan && 300 vp_oper->state.default_qos == vp_admin->default_qos) 301 return 0; 302 303 if (!slave_state->vst_qinq_supported) { 304 /* Warn and revert the request to set vst QinQ mode */ 305 vp_admin->vlan_proto = vp_oper->state.vlan_proto; 306 vp_admin->default_vlan = vp_oper->state.default_vlan; 307 vp_admin->default_qos = vp_oper->state.default_qos; 308 309 mlx4_warn(&priv->dev, 310 "Slave %d does not support VST QinQ mode\n", slave); 311 return 0; 312 } 313 314 err = mlx4_activate_vst_qinq(priv, slave, port); 315 return err; 316 } 317 318 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, 319 struct mlx4_vhcr *vhcr, 320 struct mlx4_cmd_mailbox *inbox, 321 struct mlx4_cmd_mailbox *outbox, 322 struct mlx4_cmd_info *cmd) 323 { 324 struct mlx4_priv *priv = mlx4_priv(dev); 325 u8 field, port; 326 u32 size, proxy_qp, qkey; 327 int err = 0; 328 struct mlx4_func func; 329 330 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 331 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 332 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 333 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 334 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10 335 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14 336 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18 337 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20 338 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24 339 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28 340 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c 341 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 342 #define QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET 0x48 343 344 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50 345 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54 346 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58 347 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60 348 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64 349 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68 350 351 #define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c 352 353 #define QUERY_FUNC_CAP_FMR_FLAG 0x80 354 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 355 #define QUERY_FUNC_CAP_FLAG_ETH 0x80 356 #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10 357 #define QUERY_FUNC_CAP_FLAG_RESD_LKEY 0x08 358 #define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04 359 360 #define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31) 361 #define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30) 362 363 /* when opcode modifier = 1 */ 364 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 365 #define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4 366 #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8 367 #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc 368 369 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 370 #define QUERY_FUNC_CAP_QP0_PROXY 0x14 371 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 372 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c 373 #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28 374 375 #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40 376 #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80 377 #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10 378 #define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08 379 380 #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80 381 #define QUERY_FUNC_CAP_PHV_BIT 0x40 382 #define QUERY_FUNC_CAP_VLAN_OFFLOAD_DISABLE 0x20 383 384 #define QUERY_FUNC_CAP_SUPPORTS_VST_QINQ BIT(30) 385 #define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS BIT(31) 386 387 if (vhcr->op_modifier == 1) { 388 struct mlx4_active_ports actv_ports = 389 mlx4_get_active_ports(dev, slave); 390 int converted_port = mlx4_slave_convert_port( 391 dev, slave, vhcr->in_modifier); 392 struct mlx4_vport_oper_state *vp_oper; 393 394 if (converted_port < 0) 395 return -EINVAL; 396 397 vhcr->in_modifier = converted_port; 398 /* phys-port = logical-port */ 399 field = vhcr->in_modifier - 400 find_first_bit(actv_ports.ports, dev->caps.num_ports); 401 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 402 403 port = vhcr->in_modifier; 404 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1; 405 406 /* Set nic_info bit to mark new fields support */ 407 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO; 408 409 if (mlx4_vf_smi_enabled(dev, slave, port) && 410 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) { 411 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0; 412 MLX4_PUT(outbox->buf, qkey, 413 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); 414 } 415 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET); 416 417 /* size is now the QP number */ 418 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1; 419 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); 420 421 size += 2; 422 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); 423 424 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY); 425 proxy_qp += 2; 426 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY); 427 428 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier], 429 QUERY_FUNC_CAP_PHYS_PORT_ID); 430 431 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; 432 err = mlx4_handle_vst_qinq(priv, slave, port); 433 if (err) 434 return err; 435 436 field = 0; 437 if (dev->caps.phv_bit[port]) 438 field |= QUERY_FUNC_CAP_PHV_BIT; 439 if (vp_oper->state.vlan_proto == htons(ETH_P_8021AD)) 440 field |= QUERY_FUNC_CAP_VLAN_OFFLOAD_DISABLE; 441 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS0_OFFSET); 442 443 } else if (vhcr->op_modifier == 0) { 444 struct mlx4_active_ports actv_ports = 445 mlx4_get_active_ports(dev, slave); 446 struct mlx4_slave_state *slave_state = 447 &priv->mfunc.master.slave_state[slave]; 448 449 /* enable rdma and ethernet interfaces, new quota locations, 450 * and reserved lkey 451 */ 452 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA | 453 QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX | 454 QUERY_FUNC_CAP_FLAG_RESD_LKEY); 455 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); 456 457 field = min( 458 bitmap_weight(actv_ports.ports, dev->caps.num_ports), 459 dev->caps.num_ports); 460 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 461 462 size = dev->caps.function_caps; /* set PF behaviours */ 463 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 464 465 field = 0; /* protected FMR support not available as yet */ 466 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); 467 468 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave]; 469 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 470 size = dev->caps.num_qps; 471 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 472 473 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave]; 474 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 475 size = dev->caps.num_srqs; 476 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 477 478 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave]; 479 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 480 size = dev->caps.num_cqs; 481 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 482 483 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) || 484 mlx4_QUERY_FUNC(dev, &func, slave)) { 485 size = vhcr->in_modifier & 486 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? 487 dev->caps.num_eqs : 488 rounddown_pow_of_two(dev->caps.num_eqs); 489 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 490 size = dev->caps.reserved_eqs; 491 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 492 } else { 493 size = vhcr->in_modifier & 494 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? 495 func.max_eq : 496 rounddown_pow_of_two(func.max_eq); 497 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 498 size = func.rsvd_eqs; 499 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 500 } 501 502 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave]; 503 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 504 size = dev->caps.num_mpts; 505 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 506 507 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave]; 508 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 509 size = dev->caps.num_mtts; 510 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 511 512 size = dev->caps.num_mgms + dev->caps.num_amgms; 513 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 514 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 515 516 size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG | 517 QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG; 518 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); 519 520 size = dev->caps.reserved_lkey + ((slave << 8) & 0xFF00); 521 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); 522 523 if (vhcr->in_modifier & QUERY_FUNC_CAP_SUPPORTS_VST_QINQ) 524 slave_state->vst_qinq_supported = true; 525 526 } else 527 err = -EINVAL; 528 529 return err; 530 } 531 532 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port, 533 struct mlx4_func_cap *func_cap) 534 { 535 struct mlx4_cmd_mailbox *mailbox; 536 u32 *outbox; 537 u8 field, op_modifier; 538 u32 size, qkey; 539 int err = 0, quotas = 0; 540 u32 in_modifier; 541 u32 slave_caps; 542 543 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ 544 slave_caps = QUERY_FUNC_CAP_SUPPORTS_VST_QINQ | 545 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS; 546 in_modifier = op_modifier ? gen_or_port : slave_caps; 547 548 mailbox = mlx4_alloc_cmd_mailbox(dev); 549 if (IS_ERR(mailbox)) 550 return PTR_ERR(mailbox); 551 552 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier, 553 MLX4_CMD_QUERY_FUNC_CAP, 554 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 555 if (err) 556 goto out; 557 558 outbox = mailbox->buf; 559 560 if (!op_modifier) { 561 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); 562 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { 563 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); 564 err = -EPROTONOSUPPORT; 565 goto out; 566 } 567 func_cap->flags = field; 568 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS); 569 570 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 571 func_cap->num_ports = field; 572 573 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 574 func_cap->pf_context_behaviour = size; 575 576 if (quotas) { 577 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 578 func_cap->qp_quota = size & 0xFFFFFF; 579 580 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 581 func_cap->srq_quota = size & 0xFFFFFF; 582 583 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 584 func_cap->cq_quota = size & 0xFFFFFF; 585 586 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 587 func_cap->mpt_quota = size & 0xFFFFFF; 588 589 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 590 func_cap->mtt_quota = size & 0xFFFFFF; 591 592 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 593 func_cap->mcg_quota = size & 0xFFFFFF; 594 595 } else { 596 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 597 func_cap->qp_quota = size & 0xFFFFFF; 598 599 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 600 func_cap->srq_quota = size & 0xFFFFFF; 601 602 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 603 func_cap->cq_quota = size & 0xFFFFFF; 604 605 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 606 func_cap->mpt_quota = size & 0xFFFFFF; 607 608 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 609 func_cap->mtt_quota = size & 0xFFFFFF; 610 611 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 612 func_cap->mcg_quota = size & 0xFFFFFF; 613 } 614 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 615 func_cap->max_eq = size & 0xFFFFFF; 616 617 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 618 func_cap->reserved_eq = size & 0xFFFFFF; 619 620 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_RESD_LKEY) { 621 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); 622 func_cap->reserved_lkey = size; 623 } else { 624 func_cap->reserved_lkey = 0; 625 } 626 627 func_cap->extra_flags = 0; 628 629 /* Mailbox data from 0x6c and onward should only be treated if 630 * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags 631 */ 632 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) { 633 MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); 634 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG) 635 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP; 636 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG) 637 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP; 638 } 639 640 goto out; 641 } 642 643 /* logical port query */ 644 if (gen_or_port > dev->caps.num_ports) { 645 err = -EINVAL; 646 goto out; 647 } 648 649 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET); 650 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { 651 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) { 652 mlx4_err(dev, "VLAN is enforced on this port\n"); 653 err = -EPROTONOSUPPORT; 654 goto out; 655 } 656 657 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) { 658 mlx4_err(dev, "Force mac is enabled on this port\n"); 659 err = -EPROTONOSUPPORT; 660 goto out; 661 } 662 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { 663 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); 664 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) { 665 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n"); 666 err = -EPROTONOSUPPORT; 667 goto out; 668 } 669 } 670 671 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 672 func_cap->physical_port = field; 673 if (func_cap->physical_port != gen_or_port) { 674 err = -ENOSYS; 675 goto out; 676 } 677 678 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) { 679 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); 680 func_cap->qp0_qkey = qkey; 681 } else { 682 func_cap->qp0_qkey = 0; 683 } 684 685 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); 686 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; 687 688 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); 689 func_cap->qp0_proxy_qpn = size & 0xFFFFFF; 690 691 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); 692 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; 693 694 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); 695 func_cap->qp1_proxy_qpn = size & 0xFFFFFF; 696 697 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO) 698 MLX4_GET(func_cap->phys_port_id, outbox, 699 QUERY_FUNC_CAP_PHYS_PORT_ID); 700 701 MLX4_GET(func_cap->flags0, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); 702 703 /* All other resources are allocated by the master, but we still report 704 * 'num' and 'reserved' capabilities as follows: 705 * - num remains the maximum resource index 706 * - 'num - reserved' is the total available objects of a resource, but 707 * resource indices may be less than 'reserved' 708 * TODO: set per-resource quotas */ 709 710 out: 711 mlx4_free_cmd_mailbox(dev, mailbox); 712 713 return err; 714 } 715 716 static void disable_unsupported_roce_caps(void *buf); 717 718 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 719 { 720 struct mlx4_cmd_mailbox *mailbox; 721 u32 *outbox; 722 u8 field; 723 u32 field32, flags, ext_flags; 724 u16 size; 725 u16 stat_rate; 726 int err; 727 int i; 728 729 #define QUERY_DEV_CAP_OUT_SIZE 0x100 730 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 731 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 732 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 733 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 734 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 735 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 736 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 737 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 738 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 739 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a 740 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b 741 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d 742 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e 743 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f 744 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 745 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 746 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 747 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 748 #define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26 749 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 750 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 751 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b 752 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d 753 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e 754 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f 755 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 756 #define QUERY_DEV_CAP_PORT_BEACON_OFFSET 0x34 757 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 758 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 759 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 760 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 761 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b 762 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c 763 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e 764 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f 765 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 766 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 767 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 768 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 769 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b 770 #define QUERY_DEV_CAP_BF_OFFSET 0x4c 771 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d 772 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e 773 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f 774 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 775 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 776 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 777 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 778 #define QUERY_DEV_CAP_SVLAN_BY_QP_OFFSET 0x5D 779 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 780 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 781 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 782 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 783 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 784 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 785 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 786 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 787 #define QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET 0x70 788 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70 789 #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74 790 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 791 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 792 #define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a 793 #define QUERY_DEV_CAP_ECN_QCN_VER_OFFSET 0x7b 794 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 795 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 796 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 797 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 798 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 799 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a 800 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c 801 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e 802 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 803 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 804 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 805 #define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94 806 #define QUERY_DEV_CAP_PHV_EN_OFFSET 0x96 807 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 808 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 809 #define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c 810 #define QUERY_DEV_CAP_DIAG_RPRT_PER_PORT 0x9c 811 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d 812 #define QUERY_DEV_CAP_VXLAN 0x9e 813 #define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0 814 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET 0xa8 815 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET 0xac 816 #define QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET 0xcc 817 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET 0xd0 818 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET 0xd2 819 820 821 dev_cap->flags2 = 0; 822 mailbox = mlx4_alloc_cmd_mailbox(dev); 823 if (IS_ERR(mailbox)) 824 return PTR_ERR(mailbox); 825 outbox = mailbox->buf; 826 827 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 828 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 829 if (err) 830 goto out; 831 832 if (mlx4_is_mfunc(dev)) 833 disable_unsupported_roce_caps(outbox); 834 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); 835 dev_cap->reserved_qps = 1 << (field & 0xf); 836 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); 837 dev_cap->max_qps = 1 << (field & 0x1f); 838 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); 839 dev_cap->reserved_srqs = 1 << (field >> 4); 840 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); 841 dev_cap->max_srqs = 1 << (field & 0x1f); 842 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); 843 dev_cap->max_cq_sz = 1 << field; 844 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); 845 dev_cap->reserved_cqs = 1 << (field & 0xf); 846 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); 847 dev_cap->max_cqs = 1 << (field & 0x1f); 848 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); 849 dev_cap->max_mpts = 1 << (field & 0x3f); 850 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); 851 dev_cap->reserved_eqs = 1 << (field & 0xf); 852 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); 853 dev_cap->max_eqs = 1 << (field & 0xf); 854 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); 855 dev_cap->reserved_mtts = 1 << (field >> 4); 856 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); 857 dev_cap->reserved_mrws = 1 << (field & 0xf); 858 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET); 859 dev_cap->num_sys_eqs = size & 0xfff; 860 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); 861 dev_cap->max_requester_per_qp = 1 << (field & 0x3f); 862 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); 863 dev_cap->max_responder_per_qp = 1 << (field & 0x3f); 864 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); 865 field &= 0x1f; 866 if (!field) 867 dev_cap->max_gso_sz = 0; 868 else 869 dev_cap->max_gso_sz = 1 << field; 870 871 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); 872 if (field & 0x20) 873 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; 874 if (field & 0x10) 875 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; 876 field &= 0xf; 877 if (field) { 878 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; 879 dev_cap->max_rss_tbl_sz = 1 << field; 880 } else 881 dev_cap->max_rss_tbl_sz = 0; 882 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); 883 dev_cap->max_rdma_global = 1 << (field & 0x3f); 884 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); 885 dev_cap->local_ca_ack_delay = field & 0x1f; 886 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 887 dev_cap->num_ports = field & 0xf; 888 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); 889 dev_cap->max_msg_sz = 1 << (field & 0x1f); 890 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET); 891 if (field & 0x10) 892 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN; 893 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 894 if (field & 0x80) 895 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; 896 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; 897 if (field & 0x20) 898 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER; 899 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 900 if (field & 0x80) 901 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON; 902 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 903 if (field & 0x80) 904 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB; 905 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); 906 dev_cap->fs_max_num_qp_per_entry = field; 907 MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 908 if (field & 0x1) 909 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN; 910 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); 911 dev_cap->stat_rate_support = stat_rate; 912 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 913 if (field & 0x80) 914 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS; 915 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 916 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); 917 dev_cap->flags = flags | (u64)ext_flags << 32; 918 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); 919 dev_cap->reserved_uars = field >> 4; 920 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); 921 dev_cap->uar_size = 1 << ((field & 0x3f) + 20); 922 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); 923 dev_cap->min_page_sz = 1 << field; 924 925 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); 926 if (field & 0x80) { 927 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); 928 dev_cap->bf_reg_size = 1 << (field & 0x1f); 929 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); 930 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) 931 field = 3; 932 dev_cap->bf_regs_per_page = 1 << (field & 0x3f); 933 } else { 934 dev_cap->bf_reg_size = 0; 935 } 936 937 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); 938 dev_cap->max_sq_sg = field; 939 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); 940 dev_cap->max_sq_desc_sz = size; 941 942 MLX4_GET(field, outbox, QUERY_DEV_CAP_SVLAN_BY_QP_OFFSET); 943 if (field & 0x1) 944 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP; 945 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); 946 dev_cap->max_qp_per_mcg = 1 << field; 947 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); 948 dev_cap->reserved_mgms = field & 0xf; 949 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); 950 dev_cap->max_mcgs = 1 << field; 951 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); 952 dev_cap->reserved_pds = field >> 4; 953 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); 954 dev_cap->max_pds = 1 << (field & 0x3f); 955 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); 956 dev_cap->reserved_xrcds = field >> 4; 957 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); 958 dev_cap->max_xrcds = 1 << (field & 0x1f); 959 960 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); 961 dev_cap->rdmarc_entry_sz = size; 962 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); 963 dev_cap->qpc_entry_sz = size; 964 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); 965 dev_cap->aux_entry_sz = size; 966 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); 967 dev_cap->altc_entry_sz = size; 968 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); 969 dev_cap->eqc_entry_sz = size; 970 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); 971 dev_cap->cqc_entry_sz = size; 972 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); 973 dev_cap->srq_entry_sz = size; 974 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); 975 dev_cap->cmpt_entry_sz = size; 976 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); 977 dev_cap->mtt_entry_sz = size; 978 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); 979 dev_cap->dmpt_entry_sz = size; 980 981 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); 982 dev_cap->max_srq_sz = 1 << field; 983 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); 984 dev_cap->max_qp_sz = 1 << field; 985 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); 986 dev_cap->resize_srq = field & 1; 987 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); 988 dev_cap->max_rq_sg = field; 989 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); 990 dev_cap->max_rq_desc_sz = size; 991 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 992 if (field & (1 << 4)) 993 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP; 994 if (field & (1 << 5)) 995 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL; 996 if (field & (1 << 6)) 997 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 998 if (field & (1 << 7)) 999 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 1000 MLX4_GET(dev_cap->bmme_flags, outbox, 1001 QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1002 if (dev_cap->bmme_flags & MLX4_FLAG_ROCE_V1_V2) 1003 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ROCE_V1_V2; 1004 if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP) 1005 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP; 1006 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 1007 if (field & 0x20) 1008 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV; 1009 if (field & (1 << 2)) 1010 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 1011 MLX4_GET(field, outbox, QUERY_DEV_CAP_PHV_EN_OFFSET); 1012 if (field & 0x80) 1013 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PHV_EN; 1014 if (field & 0x40) 1015 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN; 1016 1017 MLX4_GET(dev_cap->reserved_lkey, outbox, 1018 QUERY_DEV_CAP_RSVD_LKEY_OFFSET); 1019 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET); 1020 if (field32 & (1 << 0)) 1021 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP; 1022 if (field32 & (1 << 7)) 1023 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT; 1024 MLX4_GET(field32, outbox, QUERY_DEV_CAP_DIAG_RPRT_PER_PORT); 1025 if (field32 & (1 << 17)) 1026 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT; 1027 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); 1028 if (field & 1<<6) 1029 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN; 1030 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN); 1031 if (field & 1<<3) 1032 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS; 1033 if (field & (1 << 5)) 1034 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; 1035 MLX4_GET(dev_cap->max_icm_sz, outbox, 1036 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); 1037 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) 1038 MLX4_GET(dev_cap->max_counters, outbox, 1039 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); 1040 1041 MLX4_GET(field32, outbox, 1042 QUERY_DEV_CAP_MAD_DEMUX_OFFSET); 1043 if (field32 & (1 << 0)) 1044 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX; 1045 1046 MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox, 1047 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET); 1048 dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK; 1049 MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox, 1050 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET); 1051 dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK; 1052 1053 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); 1054 dev_cap->rl_caps.num_rates = size; 1055 if (dev_cap->rl_caps.num_rates) { 1056 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT; 1057 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET); 1058 dev_cap->rl_caps.max_val = size & 0xfff; 1059 dev_cap->rl_caps.max_unit = size >> 14; 1060 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET); 1061 dev_cap->rl_caps.min_val = size & 0xfff; 1062 dev_cap->rl_caps.min_unit = size >> 14; 1063 } 1064 1065 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1066 if (field32 & (1 << 16)) 1067 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP; 1068 if (field32 & (1 << 18)) 1069 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB; 1070 if (field32 & (1 << 19)) 1071 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_LB_SRC_CHK; 1072 if (field32 & (1 << 26)) 1073 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL; 1074 if (field32 & (1 << 20)) 1075 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM; 1076 if (field32 & (1 << 21)) 1077 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS; 1078 1079 for (i = 1; i <= dev_cap->num_ports; i++) { 1080 err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i); 1081 if (err) 1082 goto out; 1083 } 1084 1085 /* 1086 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then 1087 * we can't use any EQs whose doorbell falls on that page, 1088 * even if the EQ itself isn't reserved. 1089 */ 1090 if (dev_cap->num_sys_eqs == 0) 1091 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, 1092 dev_cap->reserved_eqs); 1093 else 1094 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS; 1095 1096 out: 1097 mlx4_free_cmd_mailbox(dev, mailbox); 1098 return err; 1099 } 1100 1101 void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 1102 { 1103 if (dev_cap->bf_reg_size > 0) 1104 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", 1105 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); 1106 else 1107 mlx4_dbg(dev, "BlueFlame not available\n"); 1108 1109 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", 1110 dev_cap->bmme_flags, dev_cap->reserved_lkey); 1111 mlx4_dbg(dev, "Max ICM size %lld MB\n", 1112 (unsigned long long) dev_cap->max_icm_sz >> 20); 1113 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", 1114 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); 1115 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", 1116 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); 1117 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", 1118 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); 1119 mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n", 1120 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs, 1121 dev_cap->eqc_entry_sz); 1122 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", 1123 dev_cap->reserved_mrws, dev_cap->reserved_mtts); 1124 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", 1125 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); 1126 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", 1127 dev_cap->max_pds, dev_cap->reserved_mgms); 1128 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", 1129 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); 1130 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", 1131 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu, 1132 dev_cap->port_cap[1].max_port_width); 1133 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", 1134 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); 1135 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", 1136 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); 1137 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); 1138 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); 1139 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); 1140 mlx4_dbg(dev, "DMFS high rate steer QPn base: %d\n", 1141 dev_cap->dmfs_high_rate_qpn_base); 1142 mlx4_dbg(dev, "DMFS high rate steer QPn range: %d\n", 1143 dev_cap->dmfs_high_rate_qpn_range); 1144 1145 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) { 1146 struct mlx4_rate_limit_caps *rl_caps = &dev_cap->rl_caps; 1147 1148 mlx4_dbg(dev, "QP Rate-Limit: #rates %d, unit/val max %d/%d, min %d/%d\n", 1149 rl_caps->num_rates, rl_caps->max_unit, rl_caps->max_val, 1150 rl_caps->min_unit, rl_caps->min_val); 1151 } 1152 1153 dump_dev_cap_flags(dev, dev_cap->flags); 1154 dump_dev_cap_flags2(dev, dev_cap->flags2); 1155 } 1156 1157 int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap) 1158 { 1159 struct mlx4_cmd_mailbox *mailbox; 1160 u32 *outbox; 1161 u8 field; 1162 u32 field32; 1163 int err; 1164 1165 mailbox = mlx4_alloc_cmd_mailbox(dev); 1166 if (IS_ERR(mailbox)) 1167 return PTR_ERR(mailbox); 1168 outbox = mailbox->buf; 1169 1170 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1171 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 1172 MLX4_CMD_TIME_CLASS_A, 1173 MLX4_CMD_NATIVE); 1174 1175 if (err) 1176 goto out; 1177 1178 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 1179 port_cap->max_vl = field >> 4; 1180 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); 1181 port_cap->ib_mtu = field >> 4; 1182 port_cap->max_port_width = field & 0xf; 1183 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); 1184 port_cap->max_gids = 1 << (field & 0xf); 1185 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); 1186 port_cap->max_pkeys = 1 << (field & 0xf); 1187 } else { 1188 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 1189 #define QUERY_PORT_MTU_OFFSET 0x01 1190 #define QUERY_PORT_ETH_MTU_OFFSET 0x02 1191 #define QUERY_PORT_WIDTH_OFFSET 0x06 1192 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 1193 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a 1194 #define QUERY_PORT_MAX_VL_OFFSET 0x0b 1195 #define QUERY_PORT_MAC_OFFSET 0x10 1196 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 1197 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c 1198 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 1199 1200 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, MLX4_CMD_QUERY_PORT, 1201 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1202 if (err) 1203 goto out; 1204 1205 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1206 port_cap->link_state = (field & 0x80) >> 7; 1207 port_cap->supported_port_types = field & 3; 1208 port_cap->suggested_type = (field >> 3) & 1; 1209 port_cap->default_sense = (field >> 4) & 1; 1210 port_cap->dmfs_optimized_state = (field >> 5) & 1; 1211 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); 1212 port_cap->ib_mtu = field & 0xf; 1213 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); 1214 port_cap->max_port_width = field & 0xf; 1215 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); 1216 port_cap->max_gids = 1 << (field >> 4); 1217 port_cap->max_pkeys = 1 << (field & 0xf); 1218 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); 1219 port_cap->max_vl = field & 0xf; 1220 port_cap->max_tc_eth = field >> 4; 1221 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); 1222 port_cap->log_max_macs = field & 0xf; 1223 port_cap->log_max_vlans = field >> 4; 1224 MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET); 1225 MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET); 1226 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); 1227 port_cap->trans_type = field32 >> 24; 1228 port_cap->vendor_oui = field32 & 0xffffff; 1229 MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET); 1230 MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET); 1231 } 1232 1233 out: 1234 mlx4_free_cmd_mailbox(dev, mailbox); 1235 return err; 1236 } 1237 1238 #define DEV_CAP_EXT_2_FLAG_PFC_COUNTERS (1 << 28) 1239 #define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26) 1240 #define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21) 1241 #define DEV_CAP_EXT_2_FLAG_FSM (1 << 20) 1242 1243 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1244 struct mlx4_vhcr *vhcr, 1245 struct mlx4_cmd_mailbox *inbox, 1246 struct mlx4_cmd_mailbox *outbox, 1247 struct mlx4_cmd_info *cmd) 1248 { 1249 u64 flags; 1250 int err = 0; 1251 u8 field; 1252 u16 field16; 1253 u32 bmme_flags, field32; 1254 int real_port; 1255 int slave_port; 1256 int first_port; 1257 struct mlx4_active_ports actv_ports; 1258 1259 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 1260 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1261 if (err) 1262 return err; 1263 1264 disable_unsupported_roce_caps(outbox->buf); 1265 /* add port mng change event capability and disable mw type 1 1266 * unconditionally to slaves 1267 */ 1268 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1269 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; 1270 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; 1271 actv_ports = mlx4_get_active_ports(dev, slave); 1272 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 1273 for (slave_port = 0, real_port = first_port; 1274 real_port < first_port + 1275 bitmap_weight(actv_ports.ports, dev->caps.num_ports); 1276 ++real_port, ++slave_port) { 1277 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port)) 1278 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port; 1279 else 1280 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); 1281 } 1282 for (; slave_port < dev->caps.num_ports; ++slave_port) 1283 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); 1284 1285 /* Not exposing RSS IP fragments to guests */ 1286 flags &= ~MLX4_DEV_CAP_FLAG_RSS_IP_FRAG; 1287 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1288 1289 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET); 1290 field &= ~0x0F; 1291 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F; 1292 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET); 1293 1294 /* For guests, disable timestamp */ 1295 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 1296 field &= 0x7f; 1297 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 1298 1299 /* For guests, disable vxlan tunneling and QoS support */ 1300 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN); 1301 field &= 0xd7; 1302 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN); 1303 1304 /* For guests, disable port BEACON */ 1305 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 1306 field &= 0x7f; 1307 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 1308 1309 /* For guests, report Blueflame disabled */ 1310 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); 1311 field &= 0x7f; 1312 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); 1313 1314 /* For guests, disable mw type 2 and port remap*/ 1315 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1316 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; 1317 bmme_flags &= ~MLX4_FLAG_PORT_REMAP; 1318 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1319 1320 /* turn off device-managed steering capability if not enabled */ 1321 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 1322 MLX4_GET(field, outbox->buf, 1323 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 1324 field &= 0x7f; 1325 MLX4_PUT(outbox->buf, field, 1326 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 1327 } 1328 1329 /* turn off ipoib managed steering for guests */ 1330 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 1331 field &= ~0x80; 1332 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 1333 1334 /* turn off host side virt features (VST, FSM, etc) for guests */ 1335 MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1336 field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS | 1337 DEV_CAP_EXT_2_FLAG_FSM | DEV_CAP_EXT_2_FLAG_PFC_COUNTERS); 1338 MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1339 1340 /* turn off QCN for guests */ 1341 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 1342 field &= 0xfe; 1343 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 1344 1345 /* turn off QP max-rate limiting for guests */ 1346 field16 = 0; 1347 MLX4_PUT(outbox->buf, field16, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); 1348 1349 /* turn off QoS per VF support for guests */ 1350 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 1351 field &= 0xef; 1352 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 1353 1354 /* turn off ignore FCS feature for guests */ 1355 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 1356 field &= 0xfb; 1357 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 1358 1359 return 0; 1360 } 1361 1362 static void disable_unsupported_roce_caps(void *buf) 1363 { 1364 u32 flags; 1365 1366 MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1367 flags &= ~(1UL << 31); 1368 MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1369 MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1370 flags &= ~(1UL << 24); 1371 MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1372 MLX4_GET(flags, buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1373 flags &= ~(MLX4_FLAG_ROCE_V1_V2); 1374 MLX4_PUT(buf, flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1375 } 1376 1377 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1378 struct mlx4_vhcr *vhcr, 1379 struct mlx4_cmd_mailbox *inbox, 1380 struct mlx4_cmd_mailbox *outbox, 1381 struct mlx4_cmd_info *cmd) 1382 { 1383 struct mlx4_priv *priv = mlx4_priv(dev); 1384 u64 def_mac; 1385 u8 port_type; 1386 u16 short_field; 1387 int err; 1388 int admin_link_state; 1389 int port = mlx4_slave_convert_port(dev, slave, 1390 vhcr->in_modifier & 0xFF); 1391 1392 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 1393 #define MLX4_PORT_LINK_UP_MASK 0x80 1394 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c 1395 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e 1396 1397 if (port < 0) 1398 return -EINVAL; 1399 1400 /* Protect against untrusted guests: enforce that this is the 1401 * QUERY_PORT general query. 1402 */ 1403 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF) 1404 return -EINVAL; 1405 1406 vhcr->in_modifier = port; 1407 1408 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, 1409 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 1410 MLX4_CMD_NATIVE); 1411 1412 if (!err && dev->caps.function != slave) { 1413 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac; 1414 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); 1415 1416 /* get port type - currently only eth is enabled */ 1417 MLX4_GET(port_type, outbox->buf, 1418 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1419 1420 /* No link sensing allowed */ 1421 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; 1422 /* set port type to currently operating port type */ 1423 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); 1424 1425 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state; 1426 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state) 1427 port_type |= MLX4_PORT_LINK_UP_MASK; 1428 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state) 1429 port_type &= ~MLX4_PORT_LINK_UP_MASK; 1430 else if (IFLA_VF_LINK_STATE_AUTO == admin_link_state && mlx4_is_bonded(dev)) { 1431 int other_port = (port == 1) ? 2 : 1; 1432 struct mlx4_port_cap port_cap; 1433 1434 err = mlx4_QUERY_PORT(dev, other_port, &port_cap); 1435 if (err) 1436 goto out; 1437 port_type |= (port_cap.link_state << 7); 1438 } 1439 1440 MLX4_PUT(outbox->buf, port_type, 1441 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1442 1443 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH) 1444 short_field = mlx4_get_slave_num_gids(dev, slave, port); 1445 else 1446 short_field = 1; /* slave max gids */ 1447 MLX4_PUT(outbox->buf, short_field, 1448 QUERY_PORT_CUR_MAX_GID_OFFSET); 1449 1450 short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; 1451 MLX4_PUT(outbox->buf, short_field, 1452 QUERY_PORT_CUR_MAX_PKEY_OFFSET); 1453 } 1454 out: 1455 return err; 1456 } 1457 1458 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 1459 int *gid_tbl_len, int *pkey_tbl_len) 1460 { 1461 struct mlx4_cmd_mailbox *mailbox; 1462 u32 *outbox; 1463 u16 field; 1464 int err; 1465 1466 mailbox = mlx4_alloc_cmd_mailbox(dev); 1467 if (IS_ERR(mailbox)) 1468 return PTR_ERR(mailbox); 1469 1470 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, 1471 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 1472 MLX4_CMD_WRAPPED); 1473 if (err) 1474 goto out; 1475 1476 outbox = mailbox->buf; 1477 1478 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); 1479 *gid_tbl_len = field; 1480 1481 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); 1482 *pkey_tbl_len = field; 1483 1484 out: 1485 mlx4_free_cmd_mailbox(dev, mailbox); 1486 return err; 1487 } 1488 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); 1489 1490 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) 1491 { 1492 struct mlx4_cmd_mailbox *mailbox; 1493 struct mlx4_icm_iter iter; 1494 __be64 *pages; 1495 int lg; 1496 int nent = 0; 1497 int i; 1498 int err = 0; 1499 int ts = 0, tc = 0; 1500 1501 mailbox = mlx4_alloc_cmd_mailbox(dev); 1502 if (IS_ERR(mailbox)) 1503 return PTR_ERR(mailbox); 1504 pages = mailbox->buf; 1505 1506 for (mlx4_icm_first(icm, &iter); 1507 !mlx4_icm_last(&iter); 1508 mlx4_icm_next(&iter)) { 1509 /* 1510 * We have to pass pages that are aligned to their 1511 * size, so find the least significant 1 in the 1512 * address or size and use that as our log2 size. 1513 */ 1514 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; 1515 if (lg < MLX4_ICM_PAGE_SHIFT) { 1516 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n", 1517 MLX4_ICM_PAGE_SIZE, 1518 (unsigned long long) mlx4_icm_addr(&iter), 1519 mlx4_icm_size(&iter)); 1520 err = -EINVAL; 1521 goto out; 1522 } 1523 1524 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { 1525 if (virt != -1) { 1526 pages[nent * 2] = cpu_to_be64(virt); 1527 virt += 1 << lg; 1528 } 1529 1530 pages[nent * 2 + 1] = 1531 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | 1532 (lg - MLX4_ICM_PAGE_SHIFT)); 1533 ts += 1 << (lg - 10); 1534 ++tc; 1535 1536 if (++nent == MLX4_MAILBOX_SIZE / 16) { 1537 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1538 MLX4_CMD_TIME_CLASS_B, 1539 MLX4_CMD_NATIVE); 1540 if (err) 1541 goto out; 1542 nent = 0; 1543 } 1544 } 1545 } 1546 1547 if (nent) 1548 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1549 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1550 if (err) 1551 goto out; 1552 1553 switch (op) { 1554 case MLX4_CMD_MAP_FA: 1555 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts); 1556 break; 1557 case MLX4_CMD_MAP_ICM_AUX: 1558 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts); 1559 break; 1560 case MLX4_CMD_MAP_ICM: 1561 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n", 1562 tc, ts, (unsigned long long) virt - (ts << 10)); 1563 break; 1564 } 1565 1566 out: 1567 mlx4_free_cmd_mailbox(dev, mailbox); 1568 return err; 1569 } 1570 1571 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) 1572 { 1573 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); 1574 } 1575 1576 int mlx4_UNMAP_FA(struct mlx4_dev *dev) 1577 { 1578 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, 1579 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1580 } 1581 1582 1583 int mlx4_RUN_FW(struct mlx4_dev *dev) 1584 { 1585 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, 1586 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1587 } 1588 1589 int mlx4_QUERY_FW(struct mlx4_dev *dev) 1590 { 1591 struct mlx4_fw *fw = &mlx4_priv(dev)->fw; 1592 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 1593 struct mlx4_cmd_mailbox *mailbox; 1594 u32 *outbox; 1595 int err = 0; 1596 u64 fw_ver; 1597 u16 cmd_if_rev; 1598 u8 lg; 1599 1600 #define QUERY_FW_OUT_SIZE 0x100 1601 #define QUERY_FW_VER_OFFSET 0x00 1602 #define QUERY_FW_PPF_ID 0x09 1603 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a 1604 #define QUERY_FW_MAX_CMD_OFFSET 0x0f 1605 #define QUERY_FW_ERR_START_OFFSET 0x30 1606 #define QUERY_FW_ERR_SIZE_OFFSET 0x38 1607 #define QUERY_FW_ERR_BAR_OFFSET 0x3c 1608 1609 #define QUERY_FW_SIZE_OFFSET 0x00 1610 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 1611 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 1612 1613 #define QUERY_FW_COMM_BASE_OFFSET 0x40 1614 #define QUERY_FW_COMM_BAR_OFFSET 0x48 1615 1616 #define QUERY_FW_CLOCK_OFFSET 0x50 1617 #define QUERY_FW_CLOCK_BAR 0x58 1618 1619 mailbox = mlx4_alloc_cmd_mailbox(dev); 1620 if (IS_ERR(mailbox)) 1621 return PTR_ERR(mailbox); 1622 outbox = mailbox->buf; 1623 1624 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1625 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1626 if (err) 1627 goto out; 1628 1629 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); 1630 /* 1631 * FW subminor version is at more significant bits than minor 1632 * version, so swap here. 1633 */ 1634 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | 1635 ((fw_ver & 0xffff0000ull) >> 16) | 1636 ((fw_ver & 0x0000ffffull) << 16); 1637 1638 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); 1639 dev->caps.function = lg; 1640 1641 if (mlx4_is_slave(dev)) 1642 goto out; 1643 1644 1645 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); 1646 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || 1647 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { 1648 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n", 1649 cmd_if_rev); 1650 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", 1651 (int) (dev->caps.fw_ver >> 32), 1652 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1653 (int) dev->caps.fw_ver & 0xffff); 1654 mlx4_err(dev, "This driver version supports only revisions %d to %d\n", 1655 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); 1656 err = -ENODEV; 1657 goto out; 1658 } 1659 1660 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) 1661 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; 1662 1663 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); 1664 cmd->max_cmds = 1 << lg; 1665 1666 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", 1667 (int) (dev->caps.fw_ver >> 32), 1668 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1669 (int) dev->caps.fw_ver & 0xffff, 1670 cmd_if_rev, cmd->max_cmds); 1671 1672 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); 1673 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); 1674 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); 1675 fw->catas_bar = (fw->catas_bar >> 6) * 2; 1676 1677 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", 1678 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); 1679 1680 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); 1681 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); 1682 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); 1683 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; 1684 1685 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); 1686 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); 1687 fw->comm_bar = (fw->comm_bar >> 6) * 2; 1688 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", 1689 fw->comm_bar, fw->comm_base); 1690 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); 1691 1692 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET); 1693 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR); 1694 fw->clock_bar = (fw->clock_bar >> 6) * 2; 1695 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n", 1696 fw->clock_bar, fw->clock_offset); 1697 1698 /* 1699 * Round up number of system pages needed in case 1700 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 1701 */ 1702 fw->fw_pages = 1703 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 1704 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 1705 1706 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", 1707 (unsigned long long) fw->clr_int_base, fw->clr_int_bar); 1708 1709 out: 1710 mlx4_free_cmd_mailbox(dev, mailbox); 1711 return err; 1712 } 1713 1714 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1715 struct mlx4_vhcr *vhcr, 1716 struct mlx4_cmd_mailbox *inbox, 1717 struct mlx4_cmd_mailbox *outbox, 1718 struct mlx4_cmd_info *cmd) 1719 { 1720 u8 *outbuf; 1721 int err; 1722 1723 outbuf = outbox->buf; 1724 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1725 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1726 if (err) 1727 return err; 1728 1729 /* for slaves, set pci PPF ID to invalid and zero out everything 1730 * else except FW version */ 1731 outbuf[0] = outbuf[1] = 0; 1732 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); 1733 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; 1734 1735 return 0; 1736 } 1737 1738 static void get_board_id(void *vsd, char *board_id) 1739 { 1740 int i; 1741 1742 #define VSD_OFFSET_SIG1 0x00 1743 #define VSD_OFFSET_SIG2 0xde 1744 #define VSD_OFFSET_MLX_BOARD_ID 0xd0 1745 #define VSD_OFFSET_TS_BOARD_ID 0x20 1746 1747 #define VSD_SIGNATURE_TOPSPIN 0x5ad 1748 1749 memset(board_id, 0, MLX4_BOARD_ID_LEN); 1750 1751 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && 1752 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { 1753 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); 1754 } else { 1755 /* 1756 * The board ID is a string but the firmware byte 1757 * swaps each 4-byte word before passing it back to 1758 * us. Therefore we need to swab it before printing. 1759 */ 1760 u32 *bid_u32 = (u32 *)board_id; 1761 1762 for (i = 0; i < 4; ++i) { 1763 u32 *addr; 1764 u32 val; 1765 1766 addr = (u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4); 1767 val = get_unaligned(addr); 1768 val = swab32(val); 1769 put_unaligned(val, &bid_u32[i]); 1770 } 1771 } 1772 } 1773 1774 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) 1775 { 1776 struct mlx4_cmd_mailbox *mailbox; 1777 u32 *outbox; 1778 int err; 1779 1780 #define QUERY_ADAPTER_OUT_SIZE 0x100 1781 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 1782 #define QUERY_ADAPTER_VSD_OFFSET 0x20 1783 1784 mailbox = mlx4_alloc_cmd_mailbox(dev); 1785 if (IS_ERR(mailbox)) 1786 return PTR_ERR(mailbox); 1787 outbox = mailbox->buf; 1788 1789 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, 1790 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1791 if (err) 1792 goto out; 1793 1794 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); 1795 1796 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, 1797 adapter->board_id); 1798 1799 out: 1800 mlx4_free_cmd_mailbox(dev, mailbox); 1801 return err; 1802 } 1803 1804 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) 1805 { 1806 struct mlx4_cmd_mailbox *mailbox; 1807 __be32 *inbox; 1808 int err; 1809 static const u8 a0_dmfs_hw_steering[] = { 1810 [MLX4_STEERING_DMFS_A0_DEFAULT] = 0, 1811 [MLX4_STEERING_DMFS_A0_DYNAMIC] = 1, 1812 [MLX4_STEERING_DMFS_A0_STATIC] = 2, 1813 [MLX4_STEERING_DMFS_A0_DISABLE] = 3 1814 }; 1815 1816 #define INIT_HCA_IN_SIZE 0x200 1817 #define INIT_HCA_VERSION_OFFSET 0x000 1818 #define INIT_HCA_VERSION 2 1819 #define INIT_HCA_VXLAN_OFFSET 0x0c 1820 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e 1821 #define INIT_HCA_FLAGS_OFFSET 0x014 1822 #define INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET 0x018 1823 #define INIT_HCA_QPC_OFFSET 0x020 1824 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) 1825 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) 1826 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) 1827 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) 1828 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) 1829 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) 1830 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) 1831 #define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b) 1832 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) 1833 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) 1834 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) 1835 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) 1836 #define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a) 1837 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) 1838 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) 1839 #define INIT_HCA_MCAST_OFFSET 0x0c0 1840 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) 1841 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) 1842 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) 1843 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) 1844 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) 1845 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 1846 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 1847 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) 1848 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) 1849 #define INIT_HCA_FS_A0_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x18) 1850 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) 1851 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) 1852 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) 1853 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) 1854 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) 1855 #define INIT_HCA_TPT_OFFSET 0x0f0 1856 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) 1857 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) 1858 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) 1859 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) 1860 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) 1861 #define INIT_HCA_UAR_OFFSET 0x120 1862 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) 1863 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) 1864 1865 mailbox = mlx4_alloc_cmd_mailbox(dev); 1866 if (IS_ERR(mailbox)) 1867 return PTR_ERR(mailbox); 1868 inbox = mailbox->buf; 1869 1870 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; 1871 1872 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = 1873 (ilog2(cache_line_size()) - 4) << 5; 1874 1875 #if defined(__LITTLE_ENDIAN) 1876 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); 1877 #elif defined(__BIG_ENDIAN) 1878 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); 1879 #else 1880 #error Host endianness not defined 1881 #endif 1882 /* Check port for UD address vector: */ 1883 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); 1884 1885 /* Enable IPoIB checksumming if we can: */ 1886 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 1887 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); 1888 1889 /* Enable QoS support if module parameter set */ 1890 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG && enable_qos) 1891 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); 1892 1893 /* enable counters */ 1894 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) 1895 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); 1896 1897 /* Enable RSS spread to fragmented IP packets when supported */ 1898 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_RSS_IP_FRAG) 1899 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 13); 1900 1901 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 1902 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { 1903 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); 1904 dev->caps.eqe_size = 64; 1905 dev->caps.eqe_factor = 1; 1906 } else { 1907 dev->caps.eqe_size = 32; 1908 dev->caps.eqe_factor = 0; 1909 } 1910 1911 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { 1912 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); 1913 dev->caps.cqe_size = 64; 1914 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1915 } else { 1916 dev->caps.cqe_size = 32; 1917 } 1918 1919 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ 1920 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) && 1921 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) { 1922 dev->caps.eqe_size = cache_line_size(); 1923 dev->caps.cqe_size = cache_line_size(); 1924 dev->caps.eqe_factor = 0; 1925 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 | 1926 (ilog2(dev->caps.eqe_size) - 5)), 1927 INIT_HCA_EQE_CQE_STRIDE_OFFSET); 1928 1929 /* User still need to know to support CQE > 32B */ 1930 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1931 } 1932 1933 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) 1934 *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31); 1935 1936 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1937 1938 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 1939 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); 1940 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); 1941 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); 1942 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); 1943 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); 1944 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); 1945 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); 1946 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); 1947 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); 1948 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET); 1949 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); 1950 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); 1951 1952 /* steering attributes */ 1953 if (dev->caps.steering_mode == 1954 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1955 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= 1956 cpu_to_be32(1 << 1957 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); 1958 1959 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); 1960 MLX4_PUT(inbox, param->log_mc_entry_sz, 1961 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 1962 MLX4_PUT(inbox, param->log_mc_table_sz, 1963 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 1964 /* Enable Ethernet flow steering 1965 * with udp unicast and tcp unicast 1966 */ 1967 if (dev->caps.dmfs_high_steer_mode != 1968 MLX4_STEERING_DMFS_A0_STATIC) 1969 MLX4_PUT(inbox, 1970 (u8)(MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1971 INIT_HCA_FS_ETH_BITS_OFFSET); 1972 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1973 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); 1974 /* Enable IPoIB flow steering 1975 * with udp unicast and tcp unicast 1976 */ 1977 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1978 INIT_HCA_FS_IB_BITS_OFFSET); 1979 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1980 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); 1981 1982 if (dev->caps.dmfs_high_steer_mode != 1983 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 1984 MLX4_PUT(inbox, 1985 ((u8)(a0_dmfs_hw_steering[dev->caps.dmfs_high_steer_mode] 1986 << 6)), 1987 INIT_HCA_FS_A0_OFFSET); 1988 } else { 1989 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); 1990 MLX4_PUT(inbox, param->log_mc_entry_sz, 1991 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1992 MLX4_PUT(inbox, param->log_mc_hash_sz, 1993 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1994 MLX4_PUT(inbox, param->log_mc_table_sz, 1995 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1996 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) 1997 MLX4_PUT(inbox, (u8) (1 << 3), 1998 INIT_HCA_UC_STEERING_OFFSET); 1999 } 2000 2001 /* TPT attributes */ 2002 2003 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); 2004 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); 2005 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); 2006 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); 2007 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); 2008 2009 /* UAR attributes */ 2010 2011 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); 2012 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); 2013 2014 /* set parser VXLAN attributes */ 2015 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) { 2016 u8 parser_params = 0; 2017 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET); 2018 } 2019 2020 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 2021 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 2022 2023 if (err) 2024 mlx4_err(dev, "INIT_HCA returns %d\n", err); 2025 2026 mlx4_free_cmd_mailbox(dev, mailbox); 2027 return err; 2028 } 2029 2030 int mlx4_QUERY_HCA(struct mlx4_dev *dev, 2031 struct mlx4_init_hca_param *param) 2032 { 2033 struct mlx4_cmd_mailbox *mailbox; 2034 __be32 *outbox; 2035 u32 dword_field; 2036 int err; 2037 u8 byte_field; 2038 static const u8 a0_dmfs_query_hw_steering[] = { 2039 [0] = MLX4_STEERING_DMFS_A0_DEFAULT, 2040 [1] = MLX4_STEERING_DMFS_A0_DYNAMIC, 2041 [2] = MLX4_STEERING_DMFS_A0_STATIC, 2042 [3] = MLX4_STEERING_DMFS_A0_DISABLE 2043 }; 2044 2045 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 2046 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c 2047 2048 mailbox = mlx4_alloc_cmd_mailbox(dev); 2049 if (IS_ERR(mailbox)) 2050 return PTR_ERR(mailbox); 2051 outbox = mailbox->buf; 2052 2053 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 2054 MLX4_CMD_QUERY_HCA, 2055 MLX4_CMD_TIME_CLASS_B, 2056 !mlx4_is_slave(dev)); 2057 if (err) 2058 goto out; 2059 2060 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); 2061 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 2062 2063 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 2064 2065 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); 2066 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); 2067 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); 2068 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); 2069 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); 2070 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); 2071 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); 2072 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); 2073 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); 2074 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); 2075 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET); 2076 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); 2077 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); 2078 2079 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); 2080 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { 2081 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 2082 } else { 2083 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); 2084 if (byte_field & 0x8) 2085 param->steering_mode = MLX4_STEERING_MODE_B0; 2086 else 2087 param->steering_mode = MLX4_STEERING_MODE_A0; 2088 } 2089 2090 if (dword_field & (1 << 13)) 2091 param->rss_ip_frags = 1; 2092 2093 /* steering attributes */ 2094 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 2095 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); 2096 MLX4_GET(param->log_mc_entry_sz, outbox, 2097 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 2098 MLX4_GET(param->log_mc_table_sz, outbox, 2099 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 2100 MLX4_GET(byte_field, outbox, 2101 INIT_HCA_FS_A0_OFFSET); 2102 param->dmfs_high_steer_mode = 2103 a0_dmfs_query_hw_steering[(byte_field >> 6) & 3]; 2104 } else { 2105 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); 2106 MLX4_GET(param->log_mc_entry_sz, outbox, 2107 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 2108 MLX4_GET(param->log_mc_hash_sz, outbox, 2109 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 2110 MLX4_GET(param->log_mc_table_sz, outbox, 2111 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 2112 } 2113 2114 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 2115 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); 2116 if (byte_field & 0x20) /* 64-bytes eqe enabled */ 2117 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; 2118 if (byte_field & 0x40) /* 64-bytes cqe enabled */ 2119 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; 2120 2121 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ 2122 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET); 2123 if (byte_field) { 2124 param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED; 2125 param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED; 2126 param->cqe_size = 1 << ((byte_field & 2127 MLX4_CQE_SIZE_MASK_STRIDE) + 5); 2128 param->eqe_size = 1 << (((byte_field & 2129 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5); 2130 } 2131 2132 /* TPT attributes */ 2133 2134 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); 2135 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); 2136 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); 2137 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); 2138 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); 2139 2140 /* UAR attributes */ 2141 2142 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); 2143 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); 2144 2145 /* phv_check enable */ 2146 MLX4_GET(byte_field, outbox, INIT_HCA_CACHELINE_SZ_OFFSET); 2147 if (byte_field & 0x2) 2148 param->phv_check_en = 1; 2149 out: 2150 mlx4_free_cmd_mailbox(dev, mailbox); 2151 2152 return err; 2153 } 2154 2155 static int mlx4_hca_core_clock_update(struct mlx4_dev *dev) 2156 { 2157 struct mlx4_cmd_mailbox *mailbox; 2158 __be32 *outbox; 2159 int err; 2160 2161 mailbox = mlx4_alloc_cmd_mailbox(dev); 2162 if (IS_ERR(mailbox)) { 2163 mlx4_warn(dev, "hca_core_clock mailbox allocation failed\n"); 2164 return PTR_ERR(mailbox); 2165 } 2166 outbox = mailbox->buf; 2167 2168 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 2169 MLX4_CMD_QUERY_HCA, 2170 MLX4_CMD_TIME_CLASS_B, 2171 !mlx4_is_slave(dev)); 2172 if (err) { 2173 mlx4_warn(dev, "hca_core_clock update failed\n"); 2174 goto out; 2175 } 2176 2177 MLX4_GET(dev->caps.hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 2178 2179 out: 2180 mlx4_free_cmd_mailbox(dev, mailbox); 2181 2182 return err; 2183 } 2184 2185 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 2186 * and real QP0 are active, so that the paravirtualized QP0 is ready 2187 * to operate */ 2188 static int check_qp0_state(struct mlx4_dev *dev, int function, int port) 2189 { 2190 struct mlx4_priv *priv = mlx4_priv(dev); 2191 /* irrelevant if not infiniband */ 2192 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && 2193 priv->mfunc.master.qp0_state[port].qp0_active) 2194 return 1; 2195 return 0; 2196 } 2197 2198 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 2199 struct mlx4_vhcr *vhcr, 2200 struct mlx4_cmd_mailbox *inbox, 2201 struct mlx4_cmd_mailbox *outbox, 2202 struct mlx4_cmd_info *cmd) 2203 { 2204 struct mlx4_priv *priv = mlx4_priv(dev); 2205 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); 2206 int err; 2207 2208 if (port < 0) 2209 return -EINVAL; 2210 2211 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) 2212 return 0; 2213 2214 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 2215 /* Enable port only if it was previously disabled */ 2216 if (!priv->mfunc.master.init_port_ref[port]) { 2217 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2218 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2219 if (err) 2220 return err; 2221 } 2222 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2223 } else { 2224 if (slave == mlx4_master_func_num(dev)) { 2225 if (check_qp0_state(dev, slave, port) && 2226 !priv->mfunc.master.qp0_state[port].port_active) { 2227 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2228 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2229 if (err) 2230 return err; 2231 priv->mfunc.master.qp0_state[port].port_active = 1; 2232 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2233 } 2234 } else 2235 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2236 } 2237 ++priv->mfunc.master.init_port_ref[port]; 2238 return 0; 2239 } 2240 2241 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) 2242 { 2243 struct mlx4_cmd_mailbox *mailbox; 2244 u32 *inbox; 2245 int err; 2246 u32 flags; 2247 u16 field; 2248 2249 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 2250 #define INIT_PORT_IN_SIZE 256 2251 #define INIT_PORT_FLAGS_OFFSET 0x00 2252 #define INIT_PORT_FLAG_SIG (1 << 18) 2253 #define INIT_PORT_FLAG_NG (1 << 17) 2254 #define INIT_PORT_FLAG_G0 (1 << 16) 2255 #define INIT_PORT_VL_SHIFT 4 2256 #define INIT_PORT_PORT_WIDTH_SHIFT 8 2257 #define INIT_PORT_MTU_OFFSET 0x04 2258 #define INIT_PORT_MAX_GID_OFFSET 0x06 2259 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a 2260 #define INIT_PORT_GUID0_OFFSET 0x10 2261 #define INIT_PORT_NODE_GUID_OFFSET 0x18 2262 #define INIT_PORT_SI_GUID_OFFSET 0x20 2263 2264 mailbox = mlx4_alloc_cmd_mailbox(dev); 2265 if (IS_ERR(mailbox)) 2266 return PTR_ERR(mailbox); 2267 inbox = mailbox->buf; 2268 2269 flags = 0; 2270 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; 2271 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; 2272 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); 2273 2274 field = 128 << dev->caps.ib_mtu_cap[port]; 2275 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); 2276 field = dev->caps.gid_table_len[port]; 2277 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); 2278 field = dev->caps.pkey_table_len[port]; 2279 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); 2280 2281 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, 2282 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2283 2284 mlx4_free_cmd_mailbox(dev, mailbox); 2285 } else 2286 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2287 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2288 2289 if (!err) 2290 mlx4_hca_core_clock_update(dev); 2291 2292 return err; 2293 } 2294 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); 2295 2296 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 2297 struct mlx4_vhcr *vhcr, 2298 struct mlx4_cmd_mailbox *inbox, 2299 struct mlx4_cmd_mailbox *outbox, 2300 struct mlx4_cmd_info *cmd) 2301 { 2302 struct mlx4_priv *priv = mlx4_priv(dev); 2303 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); 2304 int err; 2305 2306 if (port < 0) 2307 return -EINVAL; 2308 2309 if (!(priv->mfunc.master.slave_state[slave].init_port_mask & 2310 (1 << port))) 2311 return 0; 2312 2313 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 2314 if (priv->mfunc.master.init_port_ref[port] == 1) { 2315 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2316 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2317 if (err) 2318 return err; 2319 } 2320 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2321 } else { 2322 /* infiniband port */ 2323 if (slave == mlx4_master_func_num(dev)) { 2324 if (!priv->mfunc.master.qp0_state[port].qp0_active && 2325 priv->mfunc.master.qp0_state[port].port_active) { 2326 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2327 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2328 if (err) 2329 return err; 2330 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2331 priv->mfunc.master.qp0_state[port].port_active = 0; 2332 } 2333 } else 2334 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2335 } 2336 --priv->mfunc.master.init_port_ref[port]; 2337 return 0; 2338 } 2339 2340 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) 2341 { 2342 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2343 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2344 } 2345 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); 2346 2347 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) 2348 { 2349 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 2350 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 2351 } 2352 2353 struct mlx4_config_dev { 2354 __be32 update_flags; 2355 __be32 rsvd1[3]; 2356 __be16 vxlan_udp_dport; 2357 __be16 rsvd2; 2358 __be16 roce_v2_entropy; 2359 __be16 roce_v2_udp_dport; 2360 __be32 roce_flags; 2361 __be32 rsvd4[25]; 2362 __be16 rsvd5; 2363 u8 rsvd6; 2364 u8 rx_checksum_val; 2365 }; 2366 2367 #define MLX4_VXLAN_UDP_DPORT (1 << 0) 2368 #define MLX4_ROCE_V2_UDP_DPORT BIT(3) 2369 #define MLX4_DISABLE_RX_PORT BIT(18) 2370 2371 static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) 2372 { 2373 int err; 2374 struct mlx4_cmd_mailbox *mailbox; 2375 2376 mailbox = mlx4_alloc_cmd_mailbox(dev); 2377 if (IS_ERR(mailbox)) 2378 return PTR_ERR(mailbox); 2379 2380 memcpy(mailbox->buf, config_dev, sizeof(*config_dev)); 2381 2382 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV, 2383 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2384 2385 mlx4_free_cmd_mailbox(dev, mailbox); 2386 return err; 2387 } 2388 2389 static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) 2390 { 2391 int err; 2392 struct mlx4_cmd_mailbox *mailbox; 2393 2394 mailbox = mlx4_alloc_cmd_mailbox(dev); 2395 if (IS_ERR(mailbox)) 2396 return PTR_ERR(mailbox); 2397 2398 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV, 2399 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2400 2401 if (!err) 2402 memcpy(config_dev, mailbox->buf, sizeof(*config_dev)); 2403 2404 mlx4_free_cmd_mailbox(dev, mailbox); 2405 return err; 2406 } 2407 2408 /* Conversion between the HW values and the actual functionality. 2409 * The value represented by the array index, 2410 * and the functionality determined by the flags. 2411 */ 2412 static const u8 config_dev_csum_flags[] = { 2413 [0] = 0, 2414 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP, 2415 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP | 2416 MLX4_RX_CSUM_MODE_L4, 2417 [3] = MLX4_RX_CSUM_MODE_L4 | 2418 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP | 2419 MLX4_RX_CSUM_MODE_MULTI_VLAN 2420 }; 2421 2422 int mlx4_config_dev_retrieval(struct mlx4_dev *dev, 2423 struct mlx4_config_dev_params *params) 2424 { 2425 struct mlx4_config_dev config_dev = {0}; 2426 int err; 2427 u8 csum_mask; 2428 2429 #define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7 2430 #define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0 2431 #define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4 2432 2433 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV)) 2434 return -ENOTSUPP; 2435 2436 err = mlx4_CONFIG_DEV_get(dev, &config_dev); 2437 if (err) 2438 return err; 2439 2440 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) & 2441 CONFIG_DEV_RX_CSUM_MODE_MASK; 2442 2443 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) 2444 return -EINVAL; 2445 params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask]; 2446 2447 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) & 2448 CONFIG_DEV_RX_CSUM_MODE_MASK; 2449 2450 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) 2451 return -EINVAL; 2452 params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask]; 2453 2454 params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport); 2455 2456 return 0; 2457 } 2458 EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval); 2459 2460 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port) 2461 { 2462 struct mlx4_config_dev config_dev; 2463 2464 memset(&config_dev, 0, sizeof(config_dev)); 2465 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT); 2466 config_dev.vxlan_udp_dport = udp_port; 2467 2468 return mlx4_CONFIG_DEV_set(dev, &config_dev); 2469 } 2470 EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port); 2471 2472 #define CONFIG_DISABLE_RX_PORT BIT(15) 2473 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis) 2474 { 2475 struct mlx4_config_dev config_dev; 2476 2477 memset(&config_dev, 0, sizeof(config_dev)); 2478 config_dev.update_flags = cpu_to_be32(MLX4_DISABLE_RX_PORT); 2479 if (dis) 2480 config_dev.roce_flags = 2481 cpu_to_be32(CONFIG_DISABLE_RX_PORT); 2482 2483 return mlx4_CONFIG_DEV_set(dev, &config_dev); 2484 } 2485 2486 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port) 2487 { 2488 struct mlx4_config_dev config_dev; 2489 2490 memset(&config_dev, 0, sizeof(config_dev)); 2491 config_dev.update_flags = cpu_to_be32(MLX4_ROCE_V2_UDP_DPORT); 2492 config_dev.roce_v2_udp_dport = cpu_to_be16(udp_port); 2493 2494 return mlx4_CONFIG_DEV_set(dev, &config_dev); 2495 } 2496 EXPORT_SYMBOL_GPL(mlx4_config_roce_v2_port); 2497 2498 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2) 2499 { 2500 struct mlx4_cmd_mailbox *mailbox; 2501 struct { 2502 __be32 v_port1; 2503 __be32 v_port2; 2504 } *v2p; 2505 int err; 2506 2507 mailbox = mlx4_alloc_cmd_mailbox(dev); 2508 if (IS_ERR(mailbox)) 2509 return -ENOMEM; 2510 2511 v2p = mailbox->buf; 2512 v2p->v_port1 = cpu_to_be32(port1); 2513 v2p->v_port2 = cpu_to_be32(port2); 2514 2515 err = mlx4_cmd(dev, mailbox->dma, 0, 2516 MLX4_SET_PORT_VIRT2PHY, MLX4_CMD_VIRT_PORT_MAP, 2517 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2518 2519 mlx4_free_cmd_mailbox(dev, mailbox); 2520 return err; 2521 } 2522 2523 2524 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) 2525 { 2526 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, 2527 MLX4_CMD_SET_ICM_SIZE, 2528 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2529 if (ret) 2530 return ret; 2531 2532 /* 2533 * Round up number of system pages needed in case 2534 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 2535 */ 2536 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 2537 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 2538 2539 return 0; 2540 } 2541 2542 int mlx4_NOP(struct mlx4_dev *dev) 2543 { 2544 /* Input modifier of 0x1f means "finish as soon as possible." */ 2545 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, MLX4_CMD_TIME_CLASS_A, 2546 MLX4_CMD_NATIVE); 2547 } 2548 2549 int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier, 2550 const u32 offset[], 2551 u32 value[], size_t array_len, u8 port) 2552 { 2553 struct mlx4_cmd_mailbox *mailbox; 2554 u32 *outbox; 2555 size_t i; 2556 int ret; 2557 2558 mailbox = mlx4_alloc_cmd_mailbox(dev); 2559 if (IS_ERR(mailbox)) 2560 return PTR_ERR(mailbox); 2561 2562 outbox = mailbox->buf; 2563 2564 ret = mlx4_cmd_box(dev, 0, mailbox->dma, port, op_modifier, 2565 MLX4_CMD_DIAG_RPRT, MLX4_CMD_TIME_CLASS_A, 2566 MLX4_CMD_NATIVE); 2567 if (ret) 2568 goto out; 2569 2570 for (i = 0; i < array_len; i++) { 2571 if (offset[i] > MLX4_MAILBOX_SIZE) { 2572 ret = -EINVAL; 2573 goto out; 2574 } 2575 2576 MLX4_GET(value[i], outbox, offset[i]); 2577 } 2578 2579 out: 2580 mlx4_free_cmd_mailbox(dev, mailbox); 2581 return ret; 2582 } 2583 EXPORT_SYMBOL(mlx4_query_diag_counters); 2584 2585 int mlx4_get_phys_port_id(struct mlx4_dev *dev) 2586 { 2587 u8 port; 2588 u32 *outbox; 2589 struct mlx4_cmd_mailbox *mailbox; 2590 u32 in_mod; 2591 u32 guid_hi, guid_lo; 2592 int err, ret = 0; 2593 #define MOD_STAT_CFG_PORT_OFFSET 8 2594 #define MOD_STAT_CFG_GUID_H 0X14 2595 #define MOD_STAT_CFG_GUID_L 0X1c 2596 2597 mailbox = mlx4_alloc_cmd_mailbox(dev); 2598 if (IS_ERR(mailbox)) 2599 return PTR_ERR(mailbox); 2600 outbox = mailbox->buf; 2601 2602 for (port = 1; port <= dev->caps.num_ports; port++) { 2603 in_mod = port << MOD_STAT_CFG_PORT_OFFSET; 2604 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2, 2605 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 2606 MLX4_CMD_NATIVE); 2607 if (err) { 2608 mlx4_err(dev, "Fail to get port %d uplink guid\n", 2609 port); 2610 ret = err; 2611 } else { 2612 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H); 2613 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L); 2614 dev->caps.phys_port_id[port] = (u64)guid_lo | 2615 (u64)guid_hi << 32; 2616 } 2617 } 2618 mlx4_free_cmd_mailbox(dev, mailbox); 2619 return ret; 2620 } 2621 2622 #define MLX4_WOL_SETUP_MODE (5 << 28) 2623 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) 2624 { 2625 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 2626 2627 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, 2628 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 2629 MLX4_CMD_NATIVE); 2630 } 2631 EXPORT_SYMBOL_GPL(mlx4_wol_read); 2632 2633 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) 2634 { 2635 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 2636 2637 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, 2638 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2639 } 2640 EXPORT_SYMBOL_GPL(mlx4_wol_write); 2641 2642 enum { 2643 ADD_TO_MCG = 0x26, 2644 }; 2645 2646 2647 void mlx4_opreq_action(struct work_struct *work) 2648 { 2649 struct mlx4_priv *priv = container_of(work, struct mlx4_priv, 2650 opreq_task); 2651 struct mlx4_dev *dev = &priv->dev; 2652 int num_tasks = atomic_read(&priv->opreq_count); 2653 struct mlx4_cmd_mailbox *mailbox; 2654 struct mlx4_mgm *mgm; 2655 u32 *outbox; 2656 u32 modifier; 2657 u16 token; 2658 u16 type; 2659 int err; 2660 u32 num_qps; 2661 struct mlx4_qp qp; 2662 int i; 2663 u8 rem_mcg; 2664 u8 prot; 2665 2666 #define GET_OP_REQ_MODIFIER_OFFSET 0x08 2667 #define GET_OP_REQ_TOKEN_OFFSET 0x14 2668 #define GET_OP_REQ_TYPE_OFFSET 0x1a 2669 #define GET_OP_REQ_DATA_OFFSET 0x20 2670 2671 mailbox = mlx4_alloc_cmd_mailbox(dev); 2672 if (IS_ERR(mailbox)) { 2673 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n"); 2674 return; 2675 } 2676 outbox = mailbox->buf; 2677 2678 while (num_tasks) { 2679 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 2680 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 2681 MLX4_CMD_NATIVE); 2682 if (err) { 2683 mlx4_err(dev, "Failed to retrieve required operation: %d\n", 2684 err); 2685 return; 2686 } 2687 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET); 2688 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET); 2689 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET); 2690 type &= 0xfff; 2691 2692 switch (type) { 2693 case ADD_TO_MCG: 2694 if (dev->caps.steering_mode == 2695 MLX4_STEERING_MODE_DEVICE_MANAGED) { 2696 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n"); 2697 err = EPERM; 2698 break; 2699 } 2700 mgm = (struct mlx4_mgm *)((u8 *)(outbox) + 2701 GET_OP_REQ_DATA_OFFSET); 2702 num_qps = be32_to_cpu(mgm->members_count) & 2703 MGM_QPN_MASK; 2704 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1; 2705 prot = ((u8 *)(&mgm->members_count))[0] >> 6; 2706 2707 for (i = 0; i < num_qps; i++) { 2708 qp.qpn = be32_to_cpu(mgm->qp[i]); 2709 if (rem_mcg) 2710 err = mlx4_multicast_detach(dev, &qp, 2711 mgm->gid, 2712 prot, 0); 2713 else 2714 err = mlx4_multicast_attach(dev, &qp, 2715 mgm->gid, 2716 mgm->gid[5] 2717 , 0, prot, 2718 NULL); 2719 if (err) 2720 break; 2721 } 2722 break; 2723 default: 2724 mlx4_warn(dev, "Bad type for required operation\n"); 2725 err = EINVAL; 2726 break; 2727 } 2728 err = mlx4_cmd(dev, 0, ((u32) err | 2729 (__force u32)cpu_to_be32(token) << 16), 2730 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 2731 MLX4_CMD_NATIVE); 2732 if (err) { 2733 mlx4_err(dev, "Failed to acknowledge required request: %d\n", 2734 err); 2735 goto out; 2736 } 2737 memset(outbox, 0, 0xffc); 2738 num_tasks = atomic_dec_return(&priv->opreq_count); 2739 } 2740 2741 out: 2742 mlx4_free_cmd_mailbox(dev, mailbox); 2743 } 2744 2745 static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev, 2746 struct mlx4_cmd_mailbox *mailbox) 2747 { 2748 #define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10 2749 #define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20 2750 #define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40 2751 #define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70 2752 2753 u32 set_attr_mask, getresp_attr_mask; 2754 u32 trap_attr_mask, traprepress_attr_mask; 2755 2756 MLX4_GET(set_attr_mask, mailbox->buf, 2757 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET); 2758 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n", 2759 set_attr_mask); 2760 2761 MLX4_GET(getresp_attr_mask, mailbox->buf, 2762 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET); 2763 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n", 2764 getresp_attr_mask); 2765 2766 MLX4_GET(trap_attr_mask, mailbox->buf, 2767 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET); 2768 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n", 2769 trap_attr_mask); 2770 2771 MLX4_GET(traprepress_attr_mask, mailbox->buf, 2772 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET); 2773 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n", 2774 traprepress_attr_mask); 2775 2776 if (set_attr_mask && getresp_attr_mask && trap_attr_mask && 2777 traprepress_attr_mask) 2778 return 1; 2779 2780 return 0; 2781 } 2782 2783 int mlx4_config_mad_demux(struct mlx4_dev *dev) 2784 { 2785 struct mlx4_cmd_mailbox *mailbox; 2786 int secure_host_active; 2787 int err; 2788 2789 /* Check if mad_demux is supported */ 2790 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX)) 2791 return 0; 2792 2793 mailbox = mlx4_alloc_cmd_mailbox(dev); 2794 if (IS_ERR(mailbox)) { 2795 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX"); 2796 return -ENOMEM; 2797 } 2798 2799 /* Query mad_demux to find out which MADs are handled by internal sma */ 2800 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */, 2801 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX, 2802 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2803 if (err) { 2804 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n", 2805 err); 2806 goto out; 2807 } 2808 2809 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox); 2810 2811 /* Config mad_demux to handle all MADs returned by the query above */ 2812 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */, 2813 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX, 2814 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2815 if (err) { 2816 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err); 2817 goto out; 2818 } 2819 2820 if (secure_host_active) 2821 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n"); 2822 out: 2823 mlx4_free_cmd_mailbox(dev, mailbox); 2824 return err; 2825 } 2826 2827 /* Access Reg commands */ 2828 enum mlx4_access_reg_masks { 2829 MLX4_ACCESS_REG_STATUS_MASK = 0x7f, 2830 MLX4_ACCESS_REG_METHOD_MASK = 0x7f, 2831 MLX4_ACCESS_REG_LEN_MASK = 0x7ff 2832 }; 2833 2834 struct mlx4_access_reg { 2835 __be16 constant1; 2836 u8 status; 2837 u8 resrvd1; 2838 __be16 reg_id; 2839 u8 method; 2840 u8 constant2; 2841 __be32 resrvd2[2]; 2842 __be16 len_const; 2843 __be16 resrvd3; 2844 #define MLX4_ACCESS_REG_HEADER_SIZE (20) 2845 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE]; 2846 } __attribute__((__packed__)); 2847 2848 /** 2849 * mlx4_ACCESS_REG - Generic access reg command. 2850 * @dev: mlx4_dev. 2851 * @reg_id: register ID to access. 2852 * @method: Access method Read/Write. 2853 * @reg_len: register length to Read/Write in bytes. 2854 * @reg_data: reg_data pointer to Read/Write From/To. 2855 * 2856 * Access ConnectX registers FW command. 2857 * Returns 0 on success and copies outbox mlx4_access_reg data 2858 * field into reg_data or a negative error code. 2859 */ 2860 static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id, 2861 enum mlx4_access_reg_method method, 2862 u16 reg_len, void *reg_data) 2863 { 2864 struct mlx4_cmd_mailbox *inbox, *outbox; 2865 struct mlx4_access_reg *inbuf, *outbuf; 2866 int err; 2867 2868 inbox = mlx4_alloc_cmd_mailbox(dev); 2869 if (IS_ERR(inbox)) 2870 return PTR_ERR(inbox); 2871 2872 outbox = mlx4_alloc_cmd_mailbox(dev); 2873 if (IS_ERR(outbox)) { 2874 mlx4_free_cmd_mailbox(dev, inbox); 2875 return PTR_ERR(outbox); 2876 } 2877 2878 inbuf = inbox->buf; 2879 outbuf = outbox->buf; 2880 2881 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4); 2882 inbuf->constant2 = 0x1; 2883 inbuf->reg_id = cpu_to_be16(reg_id); 2884 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK; 2885 2886 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data))); 2887 inbuf->len_const = 2888 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) | 2889 ((0x3) << 12)); 2890 2891 memcpy(inbuf->reg_data, reg_data, reg_len); 2892 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0, 2893 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, 2894 MLX4_CMD_WRAPPED); 2895 if (err) 2896 goto out; 2897 2898 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) { 2899 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK; 2900 mlx4_err(dev, 2901 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n", 2902 reg_id, err); 2903 goto out; 2904 } 2905 2906 memcpy(reg_data, outbuf->reg_data, reg_len); 2907 out: 2908 mlx4_free_cmd_mailbox(dev, inbox); 2909 mlx4_free_cmd_mailbox(dev, outbox); 2910 return err; 2911 } 2912 2913 /* ConnectX registers IDs */ 2914 enum mlx4_reg_id { 2915 MLX4_REG_ID_PTYS = 0x5004, 2916 }; 2917 2918 /** 2919 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed) 2920 * register 2921 * @dev: mlx4_dev. 2922 * @method: Access method Read/Write. 2923 * @ptys_reg: PTYS register data pointer. 2924 * 2925 * Access ConnectX PTYS register, to Read/Write Port Type/Speed 2926 * configuration 2927 * Returns 0 on success or a negative error code. 2928 */ 2929 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 2930 enum mlx4_access_reg_method method, 2931 struct mlx4_ptys_reg *ptys_reg) 2932 { 2933 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS, 2934 method, sizeof(*ptys_reg), ptys_reg); 2935 } 2936 EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG); 2937 2938 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave, 2939 struct mlx4_vhcr *vhcr, 2940 struct mlx4_cmd_mailbox *inbox, 2941 struct mlx4_cmd_mailbox *outbox, 2942 struct mlx4_cmd_info *cmd) 2943 { 2944 struct mlx4_access_reg *inbuf = inbox->buf; 2945 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK; 2946 u16 reg_id = be16_to_cpu(inbuf->reg_id); 2947 2948 if (slave != mlx4_master_func_num(dev) && 2949 method == MLX4_ACCESS_REG_WRITE) 2950 return -EPERM; 2951 2952 if (reg_id == MLX4_REG_ID_PTYS) { 2953 struct mlx4_ptys_reg *ptys_reg = 2954 (struct mlx4_ptys_reg *)inbuf->reg_data; 2955 2956 ptys_reg->local_port = 2957 mlx4_slave_convert_port(dev, slave, 2958 ptys_reg->local_port); 2959 } 2960 2961 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier, 2962 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, 2963 MLX4_CMD_NATIVE); 2964 } 2965 2966 static int mlx4_SET_PORT_phv_bit(struct mlx4_dev *dev, u8 port, u8 phv_bit) 2967 { 2968 #define SET_PORT_GEN_PHV_VALID 0x10 2969 #define SET_PORT_GEN_PHV_EN 0x80 2970 2971 struct mlx4_cmd_mailbox *mailbox; 2972 struct mlx4_set_port_general_context *context; 2973 u32 in_mod; 2974 int err; 2975 2976 mailbox = mlx4_alloc_cmd_mailbox(dev); 2977 if (IS_ERR(mailbox)) 2978 return PTR_ERR(mailbox); 2979 context = mailbox->buf; 2980 2981 context->v_ignore_fcs |= SET_PORT_GEN_PHV_VALID; 2982 if (phv_bit) 2983 context->phv_en |= SET_PORT_GEN_PHV_EN; 2984 2985 in_mod = MLX4_SET_PORT_GENERAL << 8 | port; 2986 err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE, 2987 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 2988 MLX4_CMD_NATIVE); 2989 2990 mlx4_free_cmd_mailbox(dev, mailbox); 2991 return err; 2992 } 2993 2994 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv) 2995 { 2996 int err; 2997 struct mlx4_func_cap func_cap; 2998 2999 memset(&func_cap, 0, sizeof(func_cap)); 3000 err = mlx4_QUERY_FUNC_CAP(dev, port, &func_cap); 3001 if (!err) 3002 *phv = func_cap.flags0 & QUERY_FUNC_CAP_PHV_BIT; 3003 return err; 3004 } 3005 EXPORT_SYMBOL(get_phv_bit); 3006 3007 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val) 3008 { 3009 int ret; 3010 3011 if (mlx4_is_slave(dev)) 3012 return -EPERM; 3013 3014 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN && 3015 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) { 3016 ret = mlx4_SET_PORT_phv_bit(dev, port, new_val); 3017 if (!ret) 3018 dev->caps.phv_bit[port] = new_val; 3019 return ret; 3020 } 3021 3022 return -EOPNOTSUPP; 3023 } 3024 EXPORT_SYMBOL(set_phv_bit); 3025 3026 int mlx4_get_is_vlan_offload_disabled(struct mlx4_dev *dev, u8 port, 3027 bool *vlan_offload_disabled) 3028 { 3029 struct mlx4_func_cap func_cap; 3030 int err; 3031 3032 memset(&func_cap, 0, sizeof(func_cap)); 3033 err = mlx4_QUERY_FUNC_CAP(dev, port, &func_cap); 3034 if (!err) 3035 *vlan_offload_disabled = 3036 !!(func_cap.flags0 & 3037 QUERY_FUNC_CAP_VLAN_OFFLOAD_DISABLE); 3038 return err; 3039 } 3040 EXPORT_SYMBOL(mlx4_get_is_vlan_offload_disabled); 3041 3042 void mlx4_replace_zero_macs(struct mlx4_dev *dev) 3043 { 3044 int i; 3045 u8 mac_addr[ETH_ALEN]; 3046 3047 dev->port_random_macs = 0; 3048 for (i = 1; i <= dev->caps.num_ports; ++i) 3049 if (!dev->caps.def_mac[i] && 3050 dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) { 3051 eth_random_addr(mac_addr); 3052 dev->port_random_macs |= 1 << i; 3053 dev->caps.def_mac[i] = mlx4_mac_to_u64(mac_addr); 3054 } 3055 } 3056 EXPORT_SYMBOL_GPL(mlx4_replace_zero_macs); 3057