1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/types.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/netdevice.h> 33 #include <linux/vmalloc.h> 34 #include <linux/string.h> 35 #include <linux/in.h> 36 #include <linux/interrupt.h> 37 #include <linux/ip.h> 38 #include <linux/tcp.h> 39 #include <linux/sctp.h> 40 #include <linux/pkt_sched.h> 41 #include <linux/ipv6.h> 42 #include <linux/slab.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <linux/etherdevice.h> 46 #include <linux/ethtool.h> 47 #include <linux/if.h> 48 #include <linux/if_vlan.h> 49 #include <linux/if_macvlan.h> 50 #include <linux/if_bridge.h> 51 #include <linux/prefetch.h> 52 #include <scsi/fc/fc_fcoe.h> 53 54 #ifdef CONFIG_OF 55 #include <linux/of_net.h> 56 #endif 57 58 #ifdef CONFIG_SPARC 59 #include <asm/idprom.h> 60 #include <asm/prom.h> 61 #endif 62 63 #include "ixgbe.h" 64 #include "ixgbe_common.h" 65 #include "ixgbe_dcb_82599.h" 66 #include "ixgbe_sriov.h" 67 68 char ixgbe_driver_name[] = "ixgbe"; 69 static const char ixgbe_driver_string[] = 70 "Intel(R) 10 Gigabit PCI Express Network Driver"; 71 #ifdef IXGBE_FCOE 72 char ixgbe_default_device_descr[] = 73 "Intel(R) 10 Gigabit Network Connection"; 74 #else 75 static char ixgbe_default_device_descr[] = 76 "Intel(R) 10 Gigabit Network Connection"; 77 #endif 78 #define DRV_VERSION "4.0.1-k" 79 const char ixgbe_driver_version[] = DRV_VERSION; 80 static const char ixgbe_copyright[] = 81 "Copyright (c) 1999-2014 Intel Corporation."; 82 83 static const struct ixgbe_info *ixgbe_info_tbl[] = { 84 [board_82598] = &ixgbe_82598_info, 85 [board_82599] = &ixgbe_82599_info, 86 [board_X540] = &ixgbe_X540_info, 87 [board_X550] = &ixgbe_X550_info, 88 [board_X550EM_x] = &ixgbe_X550EM_x_info, 89 }; 90 91 /* ixgbe_pci_tbl - PCI Device ID Table 92 * 93 * Wildcard entries (PCI_ANY_ID) should come last 94 * Last entry must be all 0s 95 * 96 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 97 * Class, Class Mask, private data (not used) } 98 */ 99 static const struct pci_device_id ixgbe_pci_tbl[] = { 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 133 /* required last entry */ 134 {0, } 135 }; 136 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 137 138 #ifdef CONFIG_IXGBE_DCA 139 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 140 void *p); 141 static struct notifier_block dca_notifier = { 142 .notifier_call = ixgbe_notify_dca, 143 .next = NULL, 144 .priority = 0 145 }; 146 #endif 147 148 #ifdef CONFIG_PCI_IOV 149 static unsigned int max_vfs; 150 module_param(max_vfs, uint, 0); 151 MODULE_PARM_DESC(max_vfs, 152 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 153 #endif /* CONFIG_PCI_IOV */ 154 155 static unsigned int allow_unsupported_sfp; 156 module_param(allow_unsupported_sfp, uint, 0); 157 MODULE_PARM_DESC(allow_unsupported_sfp, 158 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 159 160 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 161 static int debug = -1; 162 module_param(debug, int, 0); 163 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 164 165 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 166 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 167 MODULE_LICENSE("GPL"); 168 MODULE_VERSION(DRV_VERSION); 169 170 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 171 172 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 173 u32 reg, u16 *value) 174 { 175 struct pci_dev *parent_dev; 176 struct pci_bus *parent_bus; 177 178 parent_bus = adapter->pdev->bus->parent; 179 if (!parent_bus) 180 return -1; 181 182 parent_dev = parent_bus->self; 183 if (!parent_dev) 184 return -1; 185 186 if (!pci_is_pcie(parent_dev)) 187 return -1; 188 189 pcie_capability_read_word(parent_dev, reg, value); 190 if (*value == IXGBE_FAILED_READ_CFG_WORD && 191 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 192 return -1; 193 return 0; 194 } 195 196 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 197 { 198 struct ixgbe_hw *hw = &adapter->hw; 199 u16 link_status = 0; 200 int err; 201 202 hw->bus.type = ixgbe_bus_type_pci_express; 203 204 /* Get the negotiated link width and speed from PCI config space of the 205 * parent, as this device is behind a switch 206 */ 207 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 208 209 /* assume caller will handle error case */ 210 if (err) 211 return err; 212 213 hw->bus.width = ixgbe_convert_bus_width(link_status); 214 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 215 216 return 0; 217 } 218 219 /** 220 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 221 * @hw: hw specific details 222 * 223 * This function is used by probe to determine whether a device's PCI-Express 224 * bandwidth details should be gathered from the parent bus instead of from the 225 * device. Used to ensure that various locations all have the correct device ID 226 * checks. 227 */ 228 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 229 { 230 switch (hw->device_id) { 231 case IXGBE_DEV_ID_82599_SFP_SF_QP: 232 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 233 return true; 234 default: 235 return false; 236 } 237 } 238 239 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 240 int expected_gts) 241 { 242 int max_gts = 0; 243 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; 244 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; 245 struct pci_dev *pdev; 246 247 /* determine whether to use the the parent device 248 */ 249 if (ixgbe_pcie_from_parent(&adapter->hw)) 250 pdev = adapter->pdev->bus->parent->self; 251 else 252 pdev = adapter->pdev; 253 254 if (pcie_get_minimum_link(pdev, &speed, &width) || 255 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { 256 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 257 return; 258 } 259 260 switch (speed) { 261 case PCIE_SPEED_2_5GT: 262 /* 8b/10b encoding reduces max throughput by 20% */ 263 max_gts = 2 * width; 264 break; 265 case PCIE_SPEED_5_0GT: 266 /* 8b/10b encoding reduces max throughput by 20% */ 267 max_gts = 4 * width; 268 break; 269 case PCIE_SPEED_8_0GT: 270 /* 128b/130b encoding reduces throughput by less than 2% */ 271 max_gts = 8 * width; 272 break; 273 default: 274 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 275 return; 276 } 277 278 e_dev_info("PCI Express bandwidth of %dGT/s available\n", 279 max_gts); 280 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n", 281 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : 282 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : 283 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : 284 "Unknown"), 285 width, 286 (speed == PCIE_SPEED_2_5GT ? "20%" : 287 speed == PCIE_SPEED_5_0GT ? "20%" : 288 speed == PCIE_SPEED_8_0GT ? "<2%" : 289 "Unknown")); 290 291 if (max_gts < expected_gts) { 292 e_dev_warn("This is not sufficient for optimal performance of this card.\n"); 293 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n", 294 expected_gts); 295 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n"); 296 } 297 } 298 299 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 300 { 301 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 302 !test_bit(__IXGBE_REMOVING, &adapter->state) && 303 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 304 schedule_work(&adapter->service_task); 305 } 306 307 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 308 { 309 struct ixgbe_adapter *adapter = hw->back; 310 311 if (!hw->hw_addr) 312 return; 313 hw->hw_addr = NULL; 314 e_dev_err("Adapter removed\n"); 315 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 316 ixgbe_service_event_schedule(adapter); 317 } 318 319 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 320 { 321 u32 value; 322 323 /* The following check not only optimizes a bit by not 324 * performing a read on the status register when the 325 * register just read was a status register read that 326 * returned IXGBE_FAILED_READ_REG. It also blocks any 327 * potential recursion. 328 */ 329 if (reg == IXGBE_STATUS) { 330 ixgbe_remove_adapter(hw); 331 return; 332 } 333 value = ixgbe_read_reg(hw, IXGBE_STATUS); 334 if (value == IXGBE_FAILED_READ_REG) 335 ixgbe_remove_adapter(hw); 336 } 337 338 /** 339 * ixgbe_read_reg - Read from device register 340 * @hw: hw specific details 341 * @reg: offset of register to read 342 * 343 * Returns : value read or IXGBE_FAILED_READ_REG if removed 344 * 345 * This function is used to read device registers. It checks for device 346 * removal by confirming any read that returns all ones by checking the 347 * status register value for all ones. This function avoids reading from 348 * the hardware if a removal was previously detected in which case it 349 * returns IXGBE_FAILED_READ_REG (all ones). 350 */ 351 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 352 { 353 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr); 354 u32 value; 355 356 if (ixgbe_removed(reg_addr)) 357 return IXGBE_FAILED_READ_REG; 358 value = readl(reg_addr + reg); 359 if (unlikely(value == IXGBE_FAILED_READ_REG)) 360 ixgbe_check_remove(hw, reg); 361 return value; 362 } 363 364 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 365 { 366 u16 value; 367 368 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 369 if (value == IXGBE_FAILED_READ_CFG_WORD) { 370 ixgbe_remove_adapter(hw); 371 return true; 372 } 373 return false; 374 } 375 376 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 377 { 378 struct ixgbe_adapter *adapter = hw->back; 379 u16 value; 380 381 if (ixgbe_removed(hw->hw_addr)) 382 return IXGBE_FAILED_READ_CFG_WORD; 383 pci_read_config_word(adapter->pdev, reg, &value); 384 if (value == IXGBE_FAILED_READ_CFG_WORD && 385 ixgbe_check_cfg_remove(hw, adapter->pdev)) 386 return IXGBE_FAILED_READ_CFG_WORD; 387 return value; 388 } 389 390 #ifdef CONFIG_PCI_IOV 391 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 392 { 393 struct ixgbe_adapter *adapter = hw->back; 394 u32 value; 395 396 if (ixgbe_removed(hw->hw_addr)) 397 return IXGBE_FAILED_READ_CFG_DWORD; 398 pci_read_config_dword(adapter->pdev, reg, &value); 399 if (value == IXGBE_FAILED_READ_CFG_DWORD && 400 ixgbe_check_cfg_remove(hw, adapter->pdev)) 401 return IXGBE_FAILED_READ_CFG_DWORD; 402 return value; 403 } 404 #endif /* CONFIG_PCI_IOV */ 405 406 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 407 { 408 struct ixgbe_adapter *adapter = hw->back; 409 410 if (ixgbe_removed(hw->hw_addr)) 411 return; 412 pci_write_config_word(adapter->pdev, reg, value); 413 } 414 415 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 416 { 417 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 418 419 /* flush memory to make sure state is correct before next watchdog */ 420 smp_mb__before_atomic(); 421 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 422 } 423 424 struct ixgbe_reg_info { 425 u32 ofs; 426 char *name; 427 }; 428 429 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 430 431 /* General Registers */ 432 {IXGBE_CTRL, "CTRL"}, 433 {IXGBE_STATUS, "STATUS"}, 434 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 435 436 /* Interrupt Registers */ 437 {IXGBE_EICR, "EICR"}, 438 439 /* RX Registers */ 440 {IXGBE_SRRCTL(0), "SRRCTL"}, 441 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 442 {IXGBE_RDLEN(0), "RDLEN"}, 443 {IXGBE_RDH(0), "RDH"}, 444 {IXGBE_RDT(0), "RDT"}, 445 {IXGBE_RXDCTL(0), "RXDCTL"}, 446 {IXGBE_RDBAL(0), "RDBAL"}, 447 {IXGBE_RDBAH(0), "RDBAH"}, 448 449 /* TX Registers */ 450 {IXGBE_TDBAL(0), "TDBAL"}, 451 {IXGBE_TDBAH(0), "TDBAH"}, 452 {IXGBE_TDLEN(0), "TDLEN"}, 453 {IXGBE_TDH(0), "TDH"}, 454 {IXGBE_TDT(0), "TDT"}, 455 {IXGBE_TXDCTL(0), "TXDCTL"}, 456 457 /* List Terminator */ 458 { .name = NULL } 459 }; 460 461 462 /* 463 * ixgbe_regdump - register printout routine 464 */ 465 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 466 { 467 int i = 0, j = 0; 468 char rname[16]; 469 u32 regs[64]; 470 471 switch (reginfo->ofs) { 472 case IXGBE_SRRCTL(0): 473 for (i = 0; i < 64; i++) 474 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 475 break; 476 case IXGBE_DCA_RXCTRL(0): 477 for (i = 0; i < 64; i++) 478 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 479 break; 480 case IXGBE_RDLEN(0): 481 for (i = 0; i < 64; i++) 482 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 483 break; 484 case IXGBE_RDH(0): 485 for (i = 0; i < 64; i++) 486 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 487 break; 488 case IXGBE_RDT(0): 489 for (i = 0; i < 64; i++) 490 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 491 break; 492 case IXGBE_RXDCTL(0): 493 for (i = 0; i < 64; i++) 494 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 495 break; 496 case IXGBE_RDBAL(0): 497 for (i = 0; i < 64; i++) 498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 499 break; 500 case IXGBE_RDBAH(0): 501 for (i = 0; i < 64; i++) 502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 503 break; 504 case IXGBE_TDBAL(0): 505 for (i = 0; i < 64; i++) 506 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 507 break; 508 case IXGBE_TDBAH(0): 509 for (i = 0; i < 64; i++) 510 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 511 break; 512 case IXGBE_TDLEN(0): 513 for (i = 0; i < 64; i++) 514 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 515 break; 516 case IXGBE_TDH(0): 517 for (i = 0; i < 64; i++) 518 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 519 break; 520 case IXGBE_TDT(0): 521 for (i = 0; i < 64; i++) 522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 523 break; 524 case IXGBE_TXDCTL(0): 525 for (i = 0; i < 64; i++) 526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 527 break; 528 default: 529 pr_info("%-15s %08x\n", reginfo->name, 530 IXGBE_READ_REG(hw, reginfo->ofs)); 531 return; 532 } 533 534 for (i = 0; i < 8; i++) { 535 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); 536 pr_err("%-15s", rname); 537 for (j = 0; j < 8; j++) 538 pr_cont(" %08x", regs[i*8+j]); 539 pr_cont("\n"); 540 } 541 542 } 543 544 /* 545 * ixgbe_dump - Print registers, tx-rings and rx-rings 546 */ 547 static void ixgbe_dump(struct ixgbe_adapter *adapter) 548 { 549 struct net_device *netdev = adapter->netdev; 550 struct ixgbe_hw *hw = &adapter->hw; 551 struct ixgbe_reg_info *reginfo; 552 int n = 0; 553 struct ixgbe_ring *tx_ring; 554 struct ixgbe_tx_buffer *tx_buffer; 555 union ixgbe_adv_tx_desc *tx_desc; 556 struct my_u0 { u64 a; u64 b; } *u0; 557 struct ixgbe_ring *rx_ring; 558 union ixgbe_adv_rx_desc *rx_desc; 559 struct ixgbe_rx_buffer *rx_buffer_info; 560 u32 staterr; 561 int i = 0; 562 563 if (!netif_msg_hw(adapter)) 564 return; 565 566 /* Print netdevice Info */ 567 if (netdev) { 568 dev_info(&adapter->pdev->dev, "Net device Info\n"); 569 pr_info("Device Name state " 570 "trans_start last_rx\n"); 571 pr_info("%-15s %016lX %016lX %016lX\n", 572 netdev->name, 573 netdev->state, 574 netdev->trans_start, 575 netdev->last_rx); 576 } 577 578 /* Print Registers */ 579 dev_info(&adapter->pdev->dev, "Register Dump\n"); 580 pr_info(" Register Name Value\n"); 581 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 582 reginfo->name; reginfo++) { 583 ixgbe_regdump(hw, reginfo); 584 } 585 586 /* Print TX Ring Summary */ 587 if (!netdev || !netif_running(netdev)) 588 return; 589 590 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 591 pr_info(" %s %s %s %s\n", 592 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 593 "leng", "ntw", "timestamp"); 594 for (n = 0; n < adapter->num_tx_queues; n++) { 595 tx_ring = adapter->tx_ring[n]; 596 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 597 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 598 n, tx_ring->next_to_use, tx_ring->next_to_clean, 599 (u64)dma_unmap_addr(tx_buffer, dma), 600 dma_unmap_len(tx_buffer, len), 601 tx_buffer->next_to_watch, 602 (u64)tx_buffer->time_stamp); 603 } 604 605 /* Print TX Rings */ 606 if (!netif_msg_tx_done(adapter)) 607 goto rx_ring_summary; 608 609 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 610 611 /* Transmit Descriptor Formats 612 * 613 * 82598 Advanced Transmit Descriptor 614 * +--------------------------------------------------------------+ 615 * 0 | Buffer Address [63:0] | 616 * +--------------------------------------------------------------+ 617 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 618 * +--------------------------------------------------------------+ 619 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 620 * 621 * 82598 Advanced Transmit Descriptor (Write-Back Format) 622 * +--------------------------------------------------------------+ 623 * 0 | RSV [63:0] | 624 * +--------------------------------------------------------------+ 625 * 8 | RSV | STA | NXTSEQ | 626 * +--------------------------------------------------------------+ 627 * 63 36 35 32 31 0 628 * 629 * 82599+ Advanced Transmit Descriptor 630 * +--------------------------------------------------------------+ 631 * 0 | Buffer Address [63:0] | 632 * +--------------------------------------------------------------+ 633 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 634 * +--------------------------------------------------------------+ 635 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 636 * 637 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 638 * +--------------------------------------------------------------+ 639 * 0 | RSV [63:0] | 640 * +--------------------------------------------------------------+ 641 * 8 | RSV | STA | RSV | 642 * +--------------------------------------------------------------+ 643 * 63 36 35 32 31 0 644 */ 645 646 for (n = 0; n < adapter->num_tx_queues; n++) { 647 tx_ring = adapter->tx_ring[n]; 648 pr_info("------------------------------------\n"); 649 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 650 pr_info("------------------------------------\n"); 651 pr_info("%s%s %s %s %s %s\n", 652 "T [desc] [address 63:0 ] ", 653 "[PlPOIdStDDt Ln] [bi->dma ] ", 654 "leng", "ntw", "timestamp", "bi->skb"); 655 656 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 657 tx_desc = IXGBE_TX_DESC(tx_ring, i); 658 tx_buffer = &tx_ring->tx_buffer_info[i]; 659 u0 = (struct my_u0 *)tx_desc; 660 if (dma_unmap_len(tx_buffer, len) > 0) { 661 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p", 662 i, 663 le64_to_cpu(u0->a), 664 le64_to_cpu(u0->b), 665 (u64)dma_unmap_addr(tx_buffer, dma), 666 dma_unmap_len(tx_buffer, len), 667 tx_buffer->next_to_watch, 668 (u64)tx_buffer->time_stamp, 669 tx_buffer->skb); 670 if (i == tx_ring->next_to_use && 671 i == tx_ring->next_to_clean) 672 pr_cont(" NTC/U\n"); 673 else if (i == tx_ring->next_to_use) 674 pr_cont(" NTU\n"); 675 else if (i == tx_ring->next_to_clean) 676 pr_cont(" NTC\n"); 677 else 678 pr_cont("\n"); 679 680 if (netif_msg_pktdata(adapter) && 681 tx_buffer->skb) 682 print_hex_dump(KERN_INFO, "", 683 DUMP_PREFIX_ADDRESS, 16, 1, 684 tx_buffer->skb->data, 685 dma_unmap_len(tx_buffer, len), 686 true); 687 } 688 } 689 } 690 691 /* Print RX Rings Summary */ 692 rx_ring_summary: 693 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 694 pr_info("Queue [NTU] [NTC]\n"); 695 for (n = 0; n < adapter->num_rx_queues; n++) { 696 rx_ring = adapter->rx_ring[n]; 697 pr_info("%5d %5X %5X\n", 698 n, rx_ring->next_to_use, rx_ring->next_to_clean); 699 } 700 701 /* Print RX Rings */ 702 if (!netif_msg_rx_status(adapter)) 703 return; 704 705 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 706 707 /* Receive Descriptor Formats 708 * 709 * 82598 Advanced Receive Descriptor (Read) Format 710 * 63 1 0 711 * +-----------------------------------------------------+ 712 * 0 | Packet Buffer Address [63:1] |A0/NSE| 713 * +----------------------------------------------+------+ 714 * 8 | Header Buffer Address [63:1] | DD | 715 * +-----------------------------------------------------+ 716 * 717 * 718 * 82598 Advanced Receive Descriptor (Write-Back) Format 719 * 720 * 63 48 47 32 31 30 21 20 16 15 4 3 0 721 * +------------------------------------------------------+ 722 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 723 * | Packet | IP | | | | Type | Type | 724 * | Checksum | Ident | | | | | | 725 * +------------------------------------------------------+ 726 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 727 * +------------------------------------------------------+ 728 * 63 48 47 32 31 20 19 0 729 * 730 * 82599+ Advanced Receive Descriptor (Read) Format 731 * 63 1 0 732 * +-----------------------------------------------------+ 733 * 0 | Packet Buffer Address [63:1] |A0/NSE| 734 * +----------------------------------------------+------+ 735 * 8 | Header Buffer Address [63:1] | DD | 736 * +-----------------------------------------------------+ 737 * 738 * 739 * 82599+ Advanced Receive Descriptor (Write-Back) Format 740 * 741 * 63 48 47 32 31 30 21 20 17 16 4 3 0 742 * +------------------------------------------------------+ 743 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 744 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 745 * |/ Flow Dir Flt ID | | | | | | 746 * +------------------------------------------------------+ 747 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 748 * +------------------------------------------------------+ 749 * 63 48 47 32 31 20 19 0 750 */ 751 752 for (n = 0; n < adapter->num_rx_queues; n++) { 753 rx_ring = adapter->rx_ring[n]; 754 pr_info("------------------------------------\n"); 755 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 756 pr_info("------------------------------------\n"); 757 pr_info("%s%s%s", 758 "R [desc] [ PktBuf A0] ", 759 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 760 "<-- Adv Rx Read format\n"); 761 pr_info("%s%s%s", 762 "RWB[desc] [PcsmIpSHl PtRs] ", 763 "[vl er S cks ln] ---------------- [bi->skb ] ", 764 "<-- Adv Rx Write-Back format\n"); 765 766 for (i = 0; i < rx_ring->count; i++) { 767 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 768 rx_desc = IXGBE_RX_DESC(rx_ring, i); 769 u0 = (struct my_u0 *)rx_desc; 770 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 771 if (staterr & IXGBE_RXD_STAT_DD) { 772 /* Descriptor Done */ 773 pr_info("RWB[0x%03X] %016llX " 774 "%016llX ---------------- %p", i, 775 le64_to_cpu(u0->a), 776 le64_to_cpu(u0->b), 777 rx_buffer_info->skb); 778 } else { 779 pr_info("R [0x%03X] %016llX " 780 "%016llX %016llX %p", i, 781 le64_to_cpu(u0->a), 782 le64_to_cpu(u0->b), 783 (u64)rx_buffer_info->dma, 784 rx_buffer_info->skb); 785 786 if (netif_msg_pktdata(adapter) && 787 rx_buffer_info->dma) { 788 print_hex_dump(KERN_INFO, "", 789 DUMP_PREFIX_ADDRESS, 16, 1, 790 page_address(rx_buffer_info->page) + 791 rx_buffer_info->page_offset, 792 ixgbe_rx_bufsz(rx_ring), true); 793 } 794 } 795 796 if (i == rx_ring->next_to_use) 797 pr_cont(" NTU\n"); 798 else if (i == rx_ring->next_to_clean) 799 pr_cont(" NTC\n"); 800 else 801 pr_cont("\n"); 802 803 } 804 } 805 } 806 807 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 808 { 809 u32 ctrl_ext; 810 811 /* Let firmware take over control of h/w */ 812 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 813 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 814 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 815 } 816 817 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 818 { 819 u32 ctrl_ext; 820 821 /* Let firmware know the driver has taken over */ 822 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 823 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 824 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 825 } 826 827 /** 828 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 829 * @adapter: pointer to adapter struct 830 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 831 * @queue: queue to map the corresponding interrupt to 832 * @msix_vector: the vector to map to the corresponding queue 833 * 834 */ 835 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 836 u8 queue, u8 msix_vector) 837 { 838 u32 ivar, index; 839 struct ixgbe_hw *hw = &adapter->hw; 840 switch (hw->mac.type) { 841 case ixgbe_mac_82598EB: 842 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 843 if (direction == -1) 844 direction = 0; 845 index = (((direction * 64) + queue) >> 2) & 0x1F; 846 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 847 ivar &= ~(0xFF << (8 * (queue & 0x3))); 848 ivar |= (msix_vector << (8 * (queue & 0x3))); 849 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 850 break; 851 case ixgbe_mac_82599EB: 852 case ixgbe_mac_X540: 853 case ixgbe_mac_X550: 854 case ixgbe_mac_X550EM_x: 855 if (direction == -1) { 856 /* other causes */ 857 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 858 index = ((queue & 1) * 8); 859 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 860 ivar &= ~(0xFF << index); 861 ivar |= (msix_vector << index); 862 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 863 break; 864 } else { 865 /* tx or rx causes */ 866 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 867 index = ((16 * (queue & 1)) + (8 * direction)); 868 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 869 ivar &= ~(0xFF << index); 870 ivar |= (msix_vector << index); 871 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 872 break; 873 } 874 default: 875 break; 876 } 877 } 878 879 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 880 u64 qmask) 881 { 882 u32 mask; 883 884 switch (adapter->hw.mac.type) { 885 case ixgbe_mac_82598EB: 886 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 887 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 888 break; 889 case ixgbe_mac_82599EB: 890 case ixgbe_mac_X540: 891 case ixgbe_mac_X550: 892 case ixgbe_mac_X550EM_x: 893 mask = (qmask & 0xFFFFFFFF); 894 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 895 mask = (qmask >> 32); 896 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 897 break; 898 default: 899 break; 900 } 901 } 902 903 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring, 904 struct ixgbe_tx_buffer *tx_buffer) 905 { 906 if (tx_buffer->skb) { 907 dev_kfree_skb_any(tx_buffer->skb); 908 if (dma_unmap_len(tx_buffer, len)) 909 dma_unmap_single(ring->dev, 910 dma_unmap_addr(tx_buffer, dma), 911 dma_unmap_len(tx_buffer, len), 912 DMA_TO_DEVICE); 913 } else if (dma_unmap_len(tx_buffer, len)) { 914 dma_unmap_page(ring->dev, 915 dma_unmap_addr(tx_buffer, dma), 916 dma_unmap_len(tx_buffer, len), 917 DMA_TO_DEVICE); 918 } 919 tx_buffer->next_to_watch = NULL; 920 tx_buffer->skb = NULL; 921 dma_unmap_len_set(tx_buffer, len, 0); 922 /* tx_buffer must be completely set up in the transmit path */ 923 } 924 925 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 926 { 927 struct ixgbe_hw *hw = &adapter->hw; 928 struct ixgbe_hw_stats *hwstats = &adapter->stats; 929 int i; 930 u32 data; 931 932 if ((hw->fc.current_mode != ixgbe_fc_full) && 933 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 934 return; 935 936 switch (hw->mac.type) { 937 case ixgbe_mac_82598EB: 938 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 939 break; 940 default: 941 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 942 } 943 hwstats->lxoffrxc += data; 944 945 /* refill credits (no tx hang) if we received xoff */ 946 if (!data) 947 return; 948 949 for (i = 0; i < adapter->num_tx_queues; i++) 950 clear_bit(__IXGBE_HANG_CHECK_ARMED, 951 &adapter->tx_ring[i]->state); 952 } 953 954 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 955 { 956 struct ixgbe_hw *hw = &adapter->hw; 957 struct ixgbe_hw_stats *hwstats = &adapter->stats; 958 u32 xoff[8] = {0}; 959 u8 tc; 960 int i; 961 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 962 963 if (adapter->ixgbe_ieee_pfc) 964 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 965 966 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 967 ixgbe_update_xoff_rx_lfc(adapter); 968 return; 969 } 970 971 /* update stats for each tc, only valid with PFC enabled */ 972 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 973 u32 pxoffrxc; 974 975 switch (hw->mac.type) { 976 case ixgbe_mac_82598EB: 977 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 978 break; 979 default: 980 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 981 } 982 hwstats->pxoffrxc[i] += pxoffrxc; 983 /* Get the TC for given UP */ 984 tc = netdev_get_prio_tc_map(adapter->netdev, i); 985 xoff[tc] += pxoffrxc; 986 } 987 988 /* disarm tx queues that have received xoff frames */ 989 for (i = 0; i < adapter->num_tx_queues; i++) { 990 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 991 992 tc = tx_ring->dcb_tc; 993 if (xoff[tc]) 994 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 995 } 996 } 997 998 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 999 { 1000 return ring->stats.packets; 1001 } 1002 1003 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1004 { 1005 struct ixgbe_adapter *adapter; 1006 struct ixgbe_hw *hw; 1007 u32 head, tail; 1008 1009 if (ring->l2_accel_priv) 1010 adapter = ring->l2_accel_priv->real_adapter; 1011 else 1012 adapter = netdev_priv(ring->netdev); 1013 1014 hw = &adapter->hw; 1015 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); 1016 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); 1017 1018 if (head != tail) 1019 return (head < tail) ? 1020 tail - head : (tail + ring->count - head); 1021 1022 return 0; 1023 } 1024 1025 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1026 { 1027 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1028 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1029 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1030 1031 clear_check_for_tx_hang(tx_ring); 1032 1033 /* 1034 * Check for a hung queue, but be thorough. This verifies 1035 * that a transmit has been completed since the previous 1036 * check AND there is at least one packet pending. The 1037 * ARMED bit is set to indicate a potential hang. The 1038 * bit is cleared if a pause frame is received to remove 1039 * false hang detection due to PFC or 802.3x frames. By 1040 * requiring this to fail twice we avoid races with 1041 * pfc clearing the ARMED bit and conditions where we 1042 * run the check_tx_hang logic with a transmit completion 1043 * pending but without time to complete it yet. 1044 */ 1045 if (tx_done_old == tx_done && tx_pending) 1046 /* make sure it is true for two checks in a row */ 1047 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1048 &tx_ring->state); 1049 /* update completed stats and continue */ 1050 tx_ring->tx_stats.tx_done_old = tx_done; 1051 /* reset the countdown */ 1052 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1053 1054 return false; 1055 } 1056 1057 /** 1058 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1059 * @adapter: driver private struct 1060 **/ 1061 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1062 { 1063 1064 /* Do the reset outside of interrupt context */ 1065 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1066 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 1067 e_warn(drv, "initiating reset due to tx timeout\n"); 1068 ixgbe_service_event_schedule(adapter); 1069 } 1070 } 1071 1072 /** 1073 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1074 * @q_vector: structure containing interrupt and ring information 1075 * @tx_ring: tx ring to clean 1076 **/ 1077 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1078 struct ixgbe_ring *tx_ring) 1079 { 1080 struct ixgbe_adapter *adapter = q_vector->adapter; 1081 struct ixgbe_tx_buffer *tx_buffer; 1082 union ixgbe_adv_tx_desc *tx_desc; 1083 unsigned int total_bytes = 0, total_packets = 0; 1084 unsigned int budget = q_vector->tx.work_limit; 1085 unsigned int i = tx_ring->next_to_clean; 1086 1087 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1088 return true; 1089 1090 tx_buffer = &tx_ring->tx_buffer_info[i]; 1091 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1092 i -= tx_ring->count; 1093 1094 do { 1095 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1096 1097 /* if next_to_watch is not set then there is no work pending */ 1098 if (!eop_desc) 1099 break; 1100 1101 /* prevent any other reads prior to eop_desc */ 1102 read_barrier_depends(); 1103 1104 /* if DD is not set pending work has not been completed */ 1105 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1106 break; 1107 1108 /* clear next_to_watch to prevent false hangs */ 1109 tx_buffer->next_to_watch = NULL; 1110 1111 /* update the statistics for this packet */ 1112 total_bytes += tx_buffer->bytecount; 1113 total_packets += tx_buffer->gso_segs; 1114 1115 /* free the skb */ 1116 dev_consume_skb_any(tx_buffer->skb); 1117 1118 /* unmap skb header data */ 1119 dma_unmap_single(tx_ring->dev, 1120 dma_unmap_addr(tx_buffer, dma), 1121 dma_unmap_len(tx_buffer, len), 1122 DMA_TO_DEVICE); 1123 1124 /* clear tx_buffer data */ 1125 tx_buffer->skb = NULL; 1126 dma_unmap_len_set(tx_buffer, len, 0); 1127 1128 /* unmap remaining buffers */ 1129 while (tx_desc != eop_desc) { 1130 tx_buffer++; 1131 tx_desc++; 1132 i++; 1133 if (unlikely(!i)) { 1134 i -= tx_ring->count; 1135 tx_buffer = tx_ring->tx_buffer_info; 1136 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1137 } 1138 1139 /* unmap any remaining paged data */ 1140 if (dma_unmap_len(tx_buffer, len)) { 1141 dma_unmap_page(tx_ring->dev, 1142 dma_unmap_addr(tx_buffer, dma), 1143 dma_unmap_len(tx_buffer, len), 1144 DMA_TO_DEVICE); 1145 dma_unmap_len_set(tx_buffer, len, 0); 1146 } 1147 } 1148 1149 /* move us one more past the eop_desc for start of next pkt */ 1150 tx_buffer++; 1151 tx_desc++; 1152 i++; 1153 if (unlikely(!i)) { 1154 i -= tx_ring->count; 1155 tx_buffer = tx_ring->tx_buffer_info; 1156 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1157 } 1158 1159 /* issue prefetch for next Tx descriptor */ 1160 prefetch(tx_desc); 1161 1162 /* update budget accounting */ 1163 budget--; 1164 } while (likely(budget)); 1165 1166 i += tx_ring->count; 1167 tx_ring->next_to_clean = i; 1168 u64_stats_update_begin(&tx_ring->syncp); 1169 tx_ring->stats.bytes += total_bytes; 1170 tx_ring->stats.packets += total_packets; 1171 u64_stats_update_end(&tx_ring->syncp); 1172 q_vector->tx.total_bytes += total_bytes; 1173 q_vector->tx.total_packets += total_packets; 1174 1175 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1176 /* schedule immediate reset if we believe we hung */ 1177 struct ixgbe_hw *hw = &adapter->hw; 1178 e_err(drv, "Detected Tx Unit Hang\n" 1179 " Tx Queue <%d>\n" 1180 " TDH, TDT <%x>, <%x>\n" 1181 " next_to_use <%x>\n" 1182 " next_to_clean <%x>\n" 1183 "tx_buffer_info[next_to_clean]\n" 1184 " time_stamp <%lx>\n" 1185 " jiffies <%lx>\n", 1186 tx_ring->queue_index, 1187 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1188 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1189 tx_ring->next_to_use, i, 1190 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1191 1192 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 1193 1194 e_info(probe, 1195 "tx hang %d detected on queue %d, resetting adapter\n", 1196 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1197 1198 /* schedule immediate reset if we believe we hung */ 1199 ixgbe_tx_timeout_reset(adapter); 1200 1201 /* the adapter is about to reset, no point in enabling stuff */ 1202 return true; 1203 } 1204 1205 netdev_tx_completed_queue(txring_txq(tx_ring), 1206 total_packets, total_bytes); 1207 1208 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1209 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1210 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1211 /* Make sure that anybody stopping the queue after this 1212 * sees the new next_to_clean. 1213 */ 1214 smp_mb(); 1215 if (__netif_subqueue_stopped(tx_ring->netdev, 1216 tx_ring->queue_index) 1217 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1218 netif_wake_subqueue(tx_ring->netdev, 1219 tx_ring->queue_index); 1220 ++tx_ring->tx_stats.restart_queue; 1221 } 1222 } 1223 1224 return !!budget; 1225 } 1226 1227 #ifdef CONFIG_IXGBE_DCA 1228 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1229 struct ixgbe_ring *tx_ring, 1230 int cpu) 1231 { 1232 struct ixgbe_hw *hw = &adapter->hw; 1233 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1234 u16 reg_offset; 1235 1236 switch (hw->mac.type) { 1237 case ixgbe_mac_82598EB: 1238 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1239 break; 1240 case ixgbe_mac_82599EB: 1241 case ixgbe_mac_X540: 1242 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1243 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1244 break; 1245 default: 1246 /* for unknown hardware do not write register */ 1247 return; 1248 } 1249 1250 /* 1251 * We can enable relaxed ordering for reads, but not writes when 1252 * DCA is enabled. This is due to a known issue in some chipsets 1253 * which will cause the DCA tag to be cleared. 1254 */ 1255 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1256 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1257 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1258 1259 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1260 } 1261 1262 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1263 struct ixgbe_ring *rx_ring, 1264 int cpu) 1265 { 1266 struct ixgbe_hw *hw = &adapter->hw; 1267 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1268 u8 reg_idx = rx_ring->reg_idx; 1269 1270 1271 switch (hw->mac.type) { 1272 case ixgbe_mac_82599EB: 1273 case ixgbe_mac_X540: 1274 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1275 break; 1276 default: 1277 break; 1278 } 1279 1280 /* 1281 * We can enable relaxed ordering for reads, but not writes when 1282 * DCA is enabled. This is due to a known issue in some chipsets 1283 * which will cause the DCA tag to be cleared. 1284 */ 1285 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1286 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1287 1288 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1289 } 1290 1291 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1292 { 1293 struct ixgbe_adapter *adapter = q_vector->adapter; 1294 struct ixgbe_ring *ring; 1295 int cpu = get_cpu(); 1296 1297 if (q_vector->cpu == cpu) 1298 goto out_no_update; 1299 1300 ixgbe_for_each_ring(ring, q_vector->tx) 1301 ixgbe_update_tx_dca(adapter, ring, cpu); 1302 1303 ixgbe_for_each_ring(ring, q_vector->rx) 1304 ixgbe_update_rx_dca(adapter, ring, cpu); 1305 1306 q_vector->cpu = cpu; 1307 out_no_update: 1308 put_cpu(); 1309 } 1310 1311 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1312 { 1313 int i; 1314 1315 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) 1316 return; 1317 1318 /* always use CB2 mode, difference is masked in the CB driver */ 1319 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); 1320 1321 for (i = 0; i < adapter->num_q_vectors; i++) { 1322 adapter->q_vector[i]->cpu = -1; 1323 ixgbe_update_dca(adapter->q_vector[i]); 1324 } 1325 } 1326 1327 static int __ixgbe_notify_dca(struct device *dev, void *data) 1328 { 1329 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1330 unsigned long event = *(unsigned long *)data; 1331 1332 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1333 return 0; 1334 1335 switch (event) { 1336 case DCA_PROVIDER_ADD: 1337 /* if we're already enabled, don't do it again */ 1338 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1339 break; 1340 if (dca_add_requester(dev) == 0) { 1341 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1342 ixgbe_setup_dca(adapter); 1343 break; 1344 } 1345 /* Fall Through since DCA is disabled. */ 1346 case DCA_PROVIDER_REMOVE: 1347 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1348 dca_remove_requester(dev); 1349 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1350 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); 1351 } 1352 break; 1353 } 1354 1355 return 0; 1356 } 1357 1358 #endif /* CONFIG_IXGBE_DCA */ 1359 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1360 union ixgbe_adv_rx_desc *rx_desc, 1361 struct sk_buff *skb) 1362 { 1363 if (ring->netdev->features & NETIF_F_RXHASH) 1364 skb_set_hash(skb, 1365 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1366 PKT_HASH_TYPE_L3); 1367 } 1368 1369 #ifdef IXGBE_FCOE 1370 /** 1371 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1372 * @ring: structure containing ring specific data 1373 * @rx_desc: advanced rx descriptor 1374 * 1375 * Returns : true if it is FCoE pkt 1376 */ 1377 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1378 union ixgbe_adv_rx_desc *rx_desc) 1379 { 1380 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1381 1382 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1383 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1384 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1385 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1386 } 1387 1388 #endif /* IXGBE_FCOE */ 1389 /** 1390 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1391 * @ring: structure containing ring specific data 1392 * @rx_desc: current Rx descriptor being processed 1393 * @skb: skb currently being received and modified 1394 **/ 1395 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1396 union ixgbe_adv_rx_desc *rx_desc, 1397 struct sk_buff *skb) 1398 { 1399 skb_checksum_none_assert(skb); 1400 1401 /* Rx csum disabled */ 1402 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1403 return; 1404 1405 /* if IP and error */ 1406 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1407 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1408 ring->rx_stats.csum_err++; 1409 return; 1410 } 1411 1412 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1413 return; 1414 1415 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1416 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1417 1418 /* 1419 * 82599 errata, UDP frames with a 0 checksum can be marked as 1420 * checksum errors. 1421 */ 1422 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1423 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1424 return; 1425 1426 ring->rx_stats.csum_err++; 1427 return; 1428 } 1429 1430 /* It must be a TCP or UDP packet with a valid checksum */ 1431 skb->ip_summed = CHECKSUM_UNNECESSARY; 1432 } 1433 1434 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1435 struct ixgbe_rx_buffer *bi) 1436 { 1437 struct page *page = bi->page; 1438 dma_addr_t dma; 1439 1440 /* since we are recycling buffers we should seldom need to alloc */ 1441 if (likely(page)) 1442 return true; 1443 1444 /* alloc new page for storage */ 1445 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1446 if (unlikely(!page)) { 1447 rx_ring->rx_stats.alloc_rx_page_failed++; 1448 return false; 1449 } 1450 1451 /* map page for use */ 1452 dma = dma_map_page(rx_ring->dev, page, 0, 1453 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 1454 1455 /* 1456 * if mapping failed free memory back to system since 1457 * there isn't much point in holding memory we can't use 1458 */ 1459 if (dma_mapping_error(rx_ring->dev, dma)) { 1460 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1461 1462 rx_ring->rx_stats.alloc_rx_page_failed++; 1463 return false; 1464 } 1465 1466 bi->dma = dma; 1467 bi->page = page; 1468 bi->page_offset = 0; 1469 1470 return true; 1471 } 1472 1473 /** 1474 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1475 * @rx_ring: ring to place buffers on 1476 * @cleaned_count: number of buffers to replace 1477 **/ 1478 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1479 { 1480 union ixgbe_adv_rx_desc *rx_desc; 1481 struct ixgbe_rx_buffer *bi; 1482 u16 i = rx_ring->next_to_use; 1483 1484 /* nothing to do */ 1485 if (!cleaned_count) 1486 return; 1487 1488 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1489 bi = &rx_ring->rx_buffer_info[i]; 1490 i -= rx_ring->count; 1491 1492 do { 1493 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1494 break; 1495 1496 /* 1497 * Refresh the desc even if buffer_addrs didn't change 1498 * because each write-back erases this info. 1499 */ 1500 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1501 1502 rx_desc++; 1503 bi++; 1504 i++; 1505 if (unlikely(!i)) { 1506 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1507 bi = rx_ring->rx_buffer_info; 1508 i -= rx_ring->count; 1509 } 1510 1511 /* clear the status bits for the next_to_use descriptor */ 1512 rx_desc->wb.upper.status_error = 0; 1513 1514 cleaned_count--; 1515 } while (cleaned_count); 1516 1517 i += rx_ring->count; 1518 1519 if (rx_ring->next_to_use != i) { 1520 rx_ring->next_to_use = i; 1521 1522 /* update next to alloc since we have filled the ring */ 1523 rx_ring->next_to_alloc = i; 1524 1525 /* Force memory writes to complete before letting h/w 1526 * know there are new descriptors to fetch. (Only 1527 * applicable for weak-ordered memory model archs, 1528 * such as IA-64). 1529 */ 1530 wmb(); 1531 writel(i, rx_ring->tail); 1532 } 1533 } 1534 1535 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1536 struct sk_buff *skb) 1537 { 1538 u16 hdr_len = skb_headlen(skb); 1539 1540 /* set gso_size to avoid messing up TCP MSS */ 1541 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1542 IXGBE_CB(skb)->append_cnt); 1543 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1544 } 1545 1546 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1547 struct sk_buff *skb) 1548 { 1549 /* if append_cnt is 0 then frame is not RSC */ 1550 if (!IXGBE_CB(skb)->append_cnt) 1551 return; 1552 1553 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1554 rx_ring->rx_stats.rsc_flush++; 1555 1556 ixgbe_set_rsc_gso_size(rx_ring, skb); 1557 1558 /* gso_size is computed using append_cnt so always clear it last */ 1559 IXGBE_CB(skb)->append_cnt = 0; 1560 } 1561 1562 /** 1563 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1564 * @rx_ring: rx descriptor ring packet is being transacted on 1565 * @rx_desc: pointer to the EOP Rx descriptor 1566 * @skb: pointer to current skb being populated 1567 * 1568 * This function checks the ring, descriptor, and packet information in 1569 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1570 * other fields within the skb. 1571 **/ 1572 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1573 union ixgbe_adv_rx_desc *rx_desc, 1574 struct sk_buff *skb) 1575 { 1576 struct net_device *dev = rx_ring->netdev; 1577 1578 ixgbe_update_rsc_stats(rx_ring, skb); 1579 1580 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1581 1582 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1583 1584 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) 1585 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb); 1586 1587 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1588 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1589 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1590 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1591 } 1592 1593 skb_record_rx_queue(skb, rx_ring->queue_index); 1594 1595 skb->protocol = eth_type_trans(skb, dev); 1596 } 1597 1598 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1599 struct sk_buff *skb) 1600 { 1601 struct ixgbe_adapter *adapter = q_vector->adapter; 1602 1603 if (ixgbe_qv_busy_polling(q_vector)) 1604 netif_receive_skb(skb); 1605 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) 1606 napi_gro_receive(&q_vector->napi, skb); 1607 else 1608 netif_rx(skb); 1609 } 1610 1611 /** 1612 * ixgbe_is_non_eop - process handling of non-EOP buffers 1613 * @rx_ring: Rx ring being processed 1614 * @rx_desc: Rx descriptor for current buffer 1615 * @skb: Current socket buffer containing buffer in progress 1616 * 1617 * This function updates next to clean. If the buffer is an EOP buffer 1618 * this function exits returning false, otherwise it will place the 1619 * sk_buff in the next buffer to be chained and return true indicating 1620 * that this is in fact a non-EOP buffer. 1621 **/ 1622 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1623 union ixgbe_adv_rx_desc *rx_desc, 1624 struct sk_buff *skb) 1625 { 1626 u32 ntc = rx_ring->next_to_clean + 1; 1627 1628 /* fetch, update, and store next to clean */ 1629 ntc = (ntc < rx_ring->count) ? ntc : 0; 1630 rx_ring->next_to_clean = ntc; 1631 1632 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1633 1634 /* update RSC append count if present */ 1635 if (ring_is_rsc_enabled(rx_ring)) { 1636 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1637 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1638 1639 if (unlikely(rsc_enabled)) { 1640 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1641 1642 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1643 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1644 1645 /* update ntc based on RSC value */ 1646 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1647 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1648 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1649 } 1650 } 1651 1652 /* if we are the last buffer then there is nothing else to do */ 1653 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1654 return false; 1655 1656 /* place skb in next buffer to be received */ 1657 rx_ring->rx_buffer_info[ntc].skb = skb; 1658 rx_ring->rx_stats.non_eop_descs++; 1659 1660 return true; 1661 } 1662 1663 /** 1664 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1665 * @rx_ring: rx descriptor ring packet is being transacted on 1666 * @skb: pointer to current skb being adjusted 1667 * 1668 * This function is an ixgbe specific version of __pskb_pull_tail. The 1669 * main difference between this version and the original function is that 1670 * this function can make several assumptions about the state of things 1671 * that allow for significant optimizations versus the standard function. 1672 * As a result we can do things like drop a frag and maintain an accurate 1673 * truesize for the skb. 1674 */ 1675 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1676 struct sk_buff *skb) 1677 { 1678 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1679 unsigned char *va; 1680 unsigned int pull_len; 1681 1682 /* 1683 * it is valid to use page_address instead of kmap since we are 1684 * working with pages allocated out of the lomem pool per 1685 * alloc_page(GFP_ATOMIC) 1686 */ 1687 va = skb_frag_address(frag); 1688 1689 /* 1690 * we need the header to contain the greater of either ETH_HLEN or 1691 * 60 bytes if the skb->len is less than 60 for skb_pad. 1692 */ 1693 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); 1694 1695 /* align pull length to size of long to optimize memcpy performance */ 1696 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1697 1698 /* update all of the pointers */ 1699 skb_frag_size_sub(frag, pull_len); 1700 frag->page_offset += pull_len; 1701 skb->data_len -= pull_len; 1702 skb->tail += pull_len; 1703 } 1704 1705 /** 1706 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1707 * @rx_ring: rx descriptor ring packet is being transacted on 1708 * @skb: pointer to current skb being updated 1709 * 1710 * This function provides a basic DMA sync up for the first fragment of an 1711 * skb. The reason for doing this is that the first fragment cannot be 1712 * unmapped until we have reached the end of packet descriptor for a buffer 1713 * chain. 1714 */ 1715 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1716 struct sk_buff *skb) 1717 { 1718 /* if the page was released unmap it, else just sync our portion */ 1719 if (unlikely(IXGBE_CB(skb)->page_released)) { 1720 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma, 1721 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 1722 IXGBE_CB(skb)->page_released = false; 1723 } else { 1724 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1725 1726 dma_sync_single_range_for_cpu(rx_ring->dev, 1727 IXGBE_CB(skb)->dma, 1728 frag->page_offset, 1729 ixgbe_rx_bufsz(rx_ring), 1730 DMA_FROM_DEVICE); 1731 } 1732 IXGBE_CB(skb)->dma = 0; 1733 } 1734 1735 /** 1736 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1737 * @rx_ring: rx descriptor ring packet is being transacted on 1738 * @rx_desc: pointer to the EOP Rx descriptor 1739 * @skb: pointer to current skb being fixed 1740 * 1741 * Check for corrupted packet headers caused by senders on the local L2 1742 * embedded NIC switch not setting up their Tx Descriptors right. These 1743 * should be very rare. 1744 * 1745 * Also address the case where we are pulling data in on pages only 1746 * and as such no data is present in the skb header. 1747 * 1748 * In addition if skb is not at least 60 bytes we need to pad it so that 1749 * it is large enough to qualify as a valid Ethernet frame. 1750 * 1751 * Returns true if an error was encountered and skb was freed. 1752 **/ 1753 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1754 union ixgbe_adv_rx_desc *rx_desc, 1755 struct sk_buff *skb) 1756 { 1757 struct net_device *netdev = rx_ring->netdev; 1758 1759 /* verify that the packet does not have any known errors */ 1760 if (unlikely(ixgbe_test_staterr(rx_desc, 1761 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1762 !(netdev->features & NETIF_F_RXALL))) { 1763 dev_kfree_skb_any(skb); 1764 return true; 1765 } 1766 1767 /* place header in linear portion of buffer */ 1768 if (skb_is_nonlinear(skb)) 1769 ixgbe_pull_tail(rx_ring, skb); 1770 1771 #ifdef IXGBE_FCOE 1772 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1773 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1774 return false; 1775 1776 #endif 1777 /* if eth_skb_pad returns an error the skb was freed */ 1778 if (eth_skb_pad(skb)) 1779 return true; 1780 1781 return false; 1782 } 1783 1784 /** 1785 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1786 * @rx_ring: rx descriptor ring to store buffers on 1787 * @old_buff: donor buffer to have page reused 1788 * 1789 * Synchronizes page for reuse by the adapter 1790 **/ 1791 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1792 struct ixgbe_rx_buffer *old_buff) 1793 { 1794 struct ixgbe_rx_buffer *new_buff; 1795 u16 nta = rx_ring->next_to_alloc; 1796 1797 new_buff = &rx_ring->rx_buffer_info[nta]; 1798 1799 /* update, and store next to alloc */ 1800 nta++; 1801 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1802 1803 /* transfer page from old buffer to new buffer */ 1804 *new_buff = *old_buff; 1805 1806 /* sync the buffer for use by the device */ 1807 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma, 1808 new_buff->page_offset, 1809 ixgbe_rx_bufsz(rx_ring), 1810 DMA_FROM_DEVICE); 1811 } 1812 1813 static inline bool ixgbe_page_is_reserved(struct page *page) 1814 { 1815 return (page_to_nid(page) != numa_mem_id()) || page->pfmemalloc; 1816 } 1817 1818 /** 1819 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 1820 * @rx_ring: rx descriptor ring to transact packets on 1821 * @rx_buffer: buffer containing page to add 1822 * @rx_desc: descriptor containing length of buffer written by hardware 1823 * @skb: sk_buff to place the data into 1824 * 1825 * This function will add the data contained in rx_buffer->page to the skb. 1826 * This is done either through a direct copy if the data in the buffer is 1827 * less than the skb header size, otherwise it will just attach the page as 1828 * a frag to the skb. 1829 * 1830 * The function will then update the page offset if necessary and return 1831 * true if the buffer can be reused by the adapter. 1832 **/ 1833 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 1834 struct ixgbe_rx_buffer *rx_buffer, 1835 union ixgbe_adv_rx_desc *rx_desc, 1836 struct sk_buff *skb) 1837 { 1838 struct page *page = rx_buffer->page; 1839 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 1840 #if (PAGE_SIZE < 8192) 1841 unsigned int truesize = ixgbe_rx_bufsz(rx_ring); 1842 #else 1843 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 1844 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) - 1845 ixgbe_rx_bufsz(rx_ring); 1846 #endif 1847 1848 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) { 1849 unsigned char *va = page_address(page) + rx_buffer->page_offset; 1850 1851 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 1852 1853 /* page is not reserved, we can reuse buffer as-is */ 1854 if (likely(!ixgbe_page_is_reserved(page))) 1855 return true; 1856 1857 /* this page cannot be reused so discard it */ 1858 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1859 return false; 1860 } 1861 1862 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 1863 rx_buffer->page_offset, size, truesize); 1864 1865 /* avoid re-using remote pages */ 1866 if (unlikely(ixgbe_page_is_reserved(page))) 1867 return false; 1868 1869 #if (PAGE_SIZE < 8192) 1870 /* if we are only owner of page we can reuse it */ 1871 if (unlikely(page_count(page) != 1)) 1872 return false; 1873 1874 /* flip page offset to other buffer */ 1875 rx_buffer->page_offset ^= truesize; 1876 #else 1877 /* move offset up to the next cache line */ 1878 rx_buffer->page_offset += truesize; 1879 1880 if (rx_buffer->page_offset > last_offset) 1881 return false; 1882 #endif 1883 1884 /* Even if we own the page, we are not allowed to use atomic_set() 1885 * This would break get_page_unless_zero() users. 1886 */ 1887 atomic_inc(&page->_count); 1888 1889 return true; 1890 } 1891 1892 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring, 1893 union ixgbe_adv_rx_desc *rx_desc) 1894 { 1895 struct ixgbe_rx_buffer *rx_buffer; 1896 struct sk_buff *skb; 1897 struct page *page; 1898 1899 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 1900 page = rx_buffer->page; 1901 prefetchw(page); 1902 1903 skb = rx_buffer->skb; 1904 1905 if (likely(!skb)) { 1906 void *page_addr = page_address(page) + 1907 rx_buffer->page_offset; 1908 1909 /* prefetch first cache line of first page */ 1910 prefetch(page_addr); 1911 #if L1_CACHE_BYTES < 128 1912 prefetch(page_addr + L1_CACHE_BYTES); 1913 #endif 1914 1915 /* allocate a skb to store the frags */ 1916 skb = napi_alloc_skb(&rx_ring->q_vector->napi, 1917 IXGBE_RX_HDR_SIZE); 1918 if (unlikely(!skb)) { 1919 rx_ring->rx_stats.alloc_rx_buff_failed++; 1920 return NULL; 1921 } 1922 1923 /* 1924 * we will be copying header into skb->data in 1925 * pskb_may_pull so it is in our interest to prefetch 1926 * it now to avoid a possible cache miss 1927 */ 1928 prefetchw(skb->data); 1929 1930 /* 1931 * Delay unmapping of the first packet. It carries the 1932 * header information, HW may still access the header 1933 * after the writeback. Only unmap it when EOP is 1934 * reached 1935 */ 1936 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1937 goto dma_sync; 1938 1939 IXGBE_CB(skb)->dma = rx_buffer->dma; 1940 } else { 1941 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 1942 ixgbe_dma_sync_frag(rx_ring, skb); 1943 1944 dma_sync: 1945 /* we are reusing so sync this buffer for CPU use */ 1946 dma_sync_single_range_for_cpu(rx_ring->dev, 1947 rx_buffer->dma, 1948 rx_buffer->page_offset, 1949 ixgbe_rx_bufsz(rx_ring), 1950 DMA_FROM_DEVICE); 1951 1952 rx_buffer->skb = NULL; 1953 } 1954 1955 /* pull page into skb */ 1956 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 1957 /* hand second half of page back to the ring */ 1958 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 1959 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) { 1960 /* the page has been released from the ring */ 1961 IXGBE_CB(skb)->page_released = true; 1962 } else { 1963 /* we are not reusing the buffer so unmap it */ 1964 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 1965 ixgbe_rx_pg_size(rx_ring), 1966 DMA_FROM_DEVICE); 1967 } 1968 1969 /* clear contents of buffer_info */ 1970 rx_buffer->page = NULL; 1971 1972 return skb; 1973 } 1974 1975 /** 1976 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 1977 * @q_vector: structure containing interrupt and ring information 1978 * @rx_ring: rx descriptor ring to transact packets on 1979 * @budget: Total limit on number of packets to process 1980 * 1981 * This function provides a "bounce buffer" approach to Rx interrupt 1982 * processing. The advantage to this is that on systems that have 1983 * expensive overhead for IOMMU access this provides a means of avoiding 1984 * it by maintaining the mapping of the page to the syste. 1985 * 1986 * Returns amount of work completed 1987 **/ 1988 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 1989 struct ixgbe_ring *rx_ring, 1990 const int budget) 1991 { 1992 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1993 #ifdef IXGBE_FCOE 1994 struct ixgbe_adapter *adapter = q_vector->adapter; 1995 int ddp_bytes; 1996 unsigned int mss = 0; 1997 #endif /* IXGBE_FCOE */ 1998 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 1999 2000 while (likely(total_rx_packets < budget)) { 2001 union ixgbe_adv_rx_desc *rx_desc; 2002 struct sk_buff *skb; 2003 2004 /* return some buffers to hardware, one at a time is too slow */ 2005 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2006 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2007 cleaned_count = 0; 2008 } 2009 2010 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2011 2012 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) 2013 break; 2014 2015 /* 2016 * This memory barrier is needed to keep us from reading 2017 * any other fields out of the rx_desc until we know the 2018 * RXD_STAT_DD bit is set 2019 */ 2020 rmb(); 2021 2022 /* retrieve a buffer from the ring */ 2023 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc); 2024 2025 /* exit if we failed to retrieve a buffer */ 2026 if (!skb) 2027 break; 2028 2029 cleaned_count++; 2030 2031 /* place incomplete frames back on ring for completion */ 2032 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2033 continue; 2034 2035 /* verify the packet layout is correct */ 2036 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2037 continue; 2038 2039 /* probably a little skewed due to removing CRC */ 2040 total_rx_bytes += skb->len; 2041 2042 /* populate checksum, timestamp, VLAN, and protocol */ 2043 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2044 2045 #ifdef IXGBE_FCOE 2046 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2047 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2048 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2049 /* include DDPed FCoE data */ 2050 if (ddp_bytes > 0) { 2051 if (!mss) { 2052 mss = rx_ring->netdev->mtu - 2053 sizeof(struct fcoe_hdr) - 2054 sizeof(struct fc_frame_header) - 2055 sizeof(struct fcoe_crc_eof); 2056 if (mss > 512) 2057 mss &= ~511; 2058 } 2059 total_rx_bytes += ddp_bytes; 2060 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2061 mss); 2062 } 2063 if (!ddp_bytes) { 2064 dev_kfree_skb_any(skb); 2065 continue; 2066 } 2067 } 2068 2069 #endif /* IXGBE_FCOE */ 2070 skb_mark_napi_id(skb, &q_vector->napi); 2071 ixgbe_rx_skb(q_vector, skb); 2072 2073 /* update budget accounting */ 2074 total_rx_packets++; 2075 } 2076 2077 u64_stats_update_begin(&rx_ring->syncp); 2078 rx_ring->stats.packets += total_rx_packets; 2079 rx_ring->stats.bytes += total_rx_bytes; 2080 u64_stats_update_end(&rx_ring->syncp); 2081 q_vector->rx.total_packets += total_rx_packets; 2082 q_vector->rx.total_bytes += total_rx_bytes; 2083 2084 return total_rx_packets; 2085 } 2086 2087 #ifdef CONFIG_NET_RX_BUSY_POLL 2088 /* must be called with local_bh_disable()d */ 2089 static int ixgbe_low_latency_recv(struct napi_struct *napi) 2090 { 2091 struct ixgbe_q_vector *q_vector = 2092 container_of(napi, struct ixgbe_q_vector, napi); 2093 struct ixgbe_adapter *adapter = q_vector->adapter; 2094 struct ixgbe_ring *ring; 2095 int found = 0; 2096 2097 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2098 return LL_FLUSH_FAILED; 2099 2100 if (!ixgbe_qv_lock_poll(q_vector)) 2101 return LL_FLUSH_BUSY; 2102 2103 ixgbe_for_each_ring(ring, q_vector->rx) { 2104 found = ixgbe_clean_rx_irq(q_vector, ring, 4); 2105 #ifdef BP_EXTENDED_STATS 2106 if (found) 2107 ring->stats.cleaned += found; 2108 else 2109 ring->stats.misses++; 2110 #endif 2111 if (found) 2112 break; 2113 } 2114 2115 ixgbe_qv_unlock_poll(q_vector); 2116 2117 return found; 2118 } 2119 #endif /* CONFIG_NET_RX_BUSY_POLL */ 2120 2121 /** 2122 * ixgbe_configure_msix - Configure MSI-X hardware 2123 * @adapter: board private structure 2124 * 2125 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2126 * interrupts. 2127 **/ 2128 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2129 { 2130 struct ixgbe_q_vector *q_vector; 2131 int v_idx; 2132 u32 mask; 2133 2134 /* Populate MSIX to EITR Select */ 2135 if (adapter->num_vfs > 32) { 2136 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; 2137 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2138 } 2139 2140 /* 2141 * Populate the IVAR table and set the ITR values to the 2142 * corresponding register. 2143 */ 2144 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2145 struct ixgbe_ring *ring; 2146 q_vector = adapter->q_vector[v_idx]; 2147 2148 ixgbe_for_each_ring(ring, q_vector->rx) 2149 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2150 2151 ixgbe_for_each_ring(ring, q_vector->tx) 2152 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2153 2154 ixgbe_write_eitr(q_vector); 2155 } 2156 2157 switch (adapter->hw.mac.type) { 2158 case ixgbe_mac_82598EB: 2159 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2160 v_idx); 2161 break; 2162 case ixgbe_mac_82599EB: 2163 case ixgbe_mac_X540: 2164 case ixgbe_mac_X550: 2165 case ixgbe_mac_X550EM_x: 2166 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2167 break; 2168 default: 2169 break; 2170 } 2171 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2172 2173 /* set up to autoclear timer, and the vectors */ 2174 mask = IXGBE_EIMS_ENABLE_MASK; 2175 mask &= ~(IXGBE_EIMS_OTHER | 2176 IXGBE_EIMS_MAILBOX | 2177 IXGBE_EIMS_LSC); 2178 2179 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2180 } 2181 2182 enum latency_range { 2183 lowest_latency = 0, 2184 low_latency = 1, 2185 bulk_latency = 2, 2186 latency_invalid = 255 2187 }; 2188 2189 /** 2190 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2191 * @q_vector: structure containing interrupt and ring information 2192 * @ring_container: structure containing ring performance data 2193 * 2194 * Stores a new ITR value based on packets and byte 2195 * counts during the last interrupt. The advantage of per interrupt 2196 * computation is faster updates and more accurate ITR for the current 2197 * traffic pattern. Constants in this function were computed 2198 * based on theoretical maximum wire speed and thresholds were set based 2199 * on testing data as well as attempting to minimize response time 2200 * while increasing bulk throughput. 2201 * this functionality is controlled by the InterruptThrottleRate module 2202 * parameter (see ixgbe_param.c) 2203 **/ 2204 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2205 struct ixgbe_ring_container *ring_container) 2206 { 2207 int bytes = ring_container->total_bytes; 2208 int packets = ring_container->total_packets; 2209 u32 timepassed_us; 2210 u64 bytes_perint; 2211 u8 itr_setting = ring_container->itr; 2212 2213 if (packets == 0) 2214 return; 2215 2216 /* simple throttlerate management 2217 * 0-10MB/s lowest (100000 ints/s) 2218 * 10-20MB/s low (20000 ints/s) 2219 * 20-1249MB/s bulk (8000 ints/s) 2220 */ 2221 /* what was last interrupt timeslice? */ 2222 timepassed_us = q_vector->itr >> 2; 2223 if (timepassed_us == 0) 2224 return; 2225 2226 bytes_perint = bytes / timepassed_us; /* bytes/usec */ 2227 2228 switch (itr_setting) { 2229 case lowest_latency: 2230 if (bytes_perint > 10) 2231 itr_setting = low_latency; 2232 break; 2233 case low_latency: 2234 if (bytes_perint > 20) 2235 itr_setting = bulk_latency; 2236 else if (bytes_perint <= 10) 2237 itr_setting = lowest_latency; 2238 break; 2239 case bulk_latency: 2240 if (bytes_perint <= 20) 2241 itr_setting = low_latency; 2242 break; 2243 } 2244 2245 /* clear work counters since we have the values we need */ 2246 ring_container->total_bytes = 0; 2247 ring_container->total_packets = 0; 2248 2249 /* write updated itr to ring container */ 2250 ring_container->itr = itr_setting; 2251 } 2252 2253 /** 2254 * ixgbe_write_eitr - write EITR register in hardware specific way 2255 * @q_vector: structure containing interrupt and ring information 2256 * 2257 * This function is made to be called by ethtool and by the driver 2258 * when it needs to update EITR registers at runtime. Hardware 2259 * specific quirks/differences are taken care of here. 2260 */ 2261 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2262 { 2263 struct ixgbe_adapter *adapter = q_vector->adapter; 2264 struct ixgbe_hw *hw = &adapter->hw; 2265 int v_idx = q_vector->v_idx; 2266 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2267 2268 switch (adapter->hw.mac.type) { 2269 case ixgbe_mac_82598EB: 2270 /* must write high and low 16 bits to reset counter */ 2271 itr_reg |= (itr_reg << 16); 2272 break; 2273 case ixgbe_mac_82599EB: 2274 case ixgbe_mac_X540: 2275 case ixgbe_mac_X550: 2276 case ixgbe_mac_X550EM_x: 2277 /* 2278 * set the WDIS bit to not clear the timer bits and cause an 2279 * immediate assertion of the interrupt 2280 */ 2281 itr_reg |= IXGBE_EITR_CNT_WDIS; 2282 break; 2283 default: 2284 break; 2285 } 2286 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2287 } 2288 2289 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2290 { 2291 u32 new_itr = q_vector->itr; 2292 u8 current_itr; 2293 2294 ixgbe_update_itr(q_vector, &q_vector->tx); 2295 ixgbe_update_itr(q_vector, &q_vector->rx); 2296 2297 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 2298 2299 switch (current_itr) { 2300 /* counts and packets in update_itr are dependent on these numbers */ 2301 case lowest_latency: 2302 new_itr = IXGBE_100K_ITR; 2303 break; 2304 case low_latency: 2305 new_itr = IXGBE_20K_ITR; 2306 break; 2307 case bulk_latency: 2308 new_itr = IXGBE_8K_ITR; 2309 break; 2310 default: 2311 break; 2312 } 2313 2314 if (new_itr != q_vector->itr) { 2315 /* do an exponential smoothing */ 2316 new_itr = (10 * new_itr * q_vector->itr) / 2317 ((9 * new_itr) + q_vector->itr); 2318 2319 /* save the algorithm value here */ 2320 q_vector->itr = new_itr; 2321 2322 ixgbe_write_eitr(q_vector); 2323 } 2324 } 2325 2326 /** 2327 * ixgbe_check_overtemp_subtask - check for over temperature 2328 * @adapter: pointer to adapter 2329 **/ 2330 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2331 { 2332 struct ixgbe_hw *hw = &adapter->hw; 2333 u32 eicr = adapter->interrupt_event; 2334 2335 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2336 return; 2337 2338 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && 2339 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2340 return; 2341 2342 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2343 2344 switch (hw->device_id) { 2345 case IXGBE_DEV_ID_82599_T3_LOM: 2346 /* 2347 * Since the warning interrupt is for both ports 2348 * we don't have to check if: 2349 * - This interrupt wasn't for our port. 2350 * - We may have missed the interrupt so always have to 2351 * check if we got a LSC 2352 */ 2353 if (!(eicr & IXGBE_EICR_GPI_SDP0) && 2354 !(eicr & IXGBE_EICR_LSC)) 2355 return; 2356 2357 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2358 u32 speed; 2359 bool link_up = false; 2360 2361 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2362 2363 if (link_up) 2364 return; 2365 } 2366 2367 /* Check if this is not due to overtemp */ 2368 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2369 return; 2370 2371 break; 2372 default: 2373 if (!(eicr & IXGBE_EICR_GPI_SDP0)) 2374 return; 2375 break; 2376 } 2377 e_crit(drv, 2378 "Network adapter has been stopped because it has over heated. " 2379 "Restart the computer. If the problem persists, " 2380 "power off the system and replace the adapter\n"); 2381 2382 adapter->interrupt_event = 0; 2383 } 2384 2385 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2386 { 2387 struct ixgbe_hw *hw = &adapter->hw; 2388 2389 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2390 (eicr & IXGBE_EICR_GPI_SDP1)) { 2391 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2392 /* write to clear the interrupt */ 2393 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); 2394 } 2395 } 2396 2397 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2398 { 2399 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2400 return; 2401 2402 switch (adapter->hw.mac.type) { 2403 case ixgbe_mac_82599EB: 2404 /* 2405 * Need to check link state so complete overtemp check 2406 * on service task 2407 */ 2408 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) && 2409 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2410 adapter->interrupt_event = eicr; 2411 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2412 ixgbe_service_event_schedule(adapter); 2413 return; 2414 } 2415 return; 2416 case ixgbe_mac_X540: 2417 if (!(eicr & IXGBE_EICR_TS)) 2418 return; 2419 break; 2420 default: 2421 return; 2422 } 2423 2424 e_crit(drv, 2425 "Network adapter has been stopped because it has over heated. " 2426 "Restart the computer. If the problem persists, " 2427 "power off the system and replace the adapter\n"); 2428 } 2429 2430 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2431 { 2432 struct ixgbe_hw *hw = &adapter->hw; 2433 2434 if (eicr & IXGBE_EICR_GPI_SDP2) { 2435 /* Clear the interrupt */ 2436 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); 2437 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2438 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2439 ixgbe_service_event_schedule(adapter); 2440 } 2441 } 2442 2443 if (eicr & IXGBE_EICR_GPI_SDP1) { 2444 /* Clear the interrupt */ 2445 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); 2446 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2447 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2448 ixgbe_service_event_schedule(adapter); 2449 } 2450 } 2451 } 2452 2453 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2454 { 2455 struct ixgbe_hw *hw = &adapter->hw; 2456 2457 adapter->lsc_int++; 2458 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2459 adapter->link_check_timeout = jiffies; 2460 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2461 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2462 IXGBE_WRITE_FLUSH(hw); 2463 ixgbe_service_event_schedule(adapter); 2464 } 2465 } 2466 2467 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2468 u64 qmask) 2469 { 2470 u32 mask; 2471 struct ixgbe_hw *hw = &adapter->hw; 2472 2473 switch (hw->mac.type) { 2474 case ixgbe_mac_82598EB: 2475 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2476 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2477 break; 2478 case ixgbe_mac_82599EB: 2479 case ixgbe_mac_X540: 2480 case ixgbe_mac_X550: 2481 case ixgbe_mac_X550EM_x: 2482 mask = (qmask & 0xFFFFFFFF); 2483 if (mask) 2484 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2485 mask = (qmask >> 32); 2486 if (mask) 2487 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2488 break; 2489 default: 2490 break; 2491 } 2492 /* skip the flush */ 2493 } 2494 2495 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 2496 u64 qmask) 2497 { 2498 u32 mask; 2499 struct ixgbe_hw *hw = &adapter->hw; 2500 2501 switch (hw->mac.type) { 2502 case ixgbe_mac_82598EB: 2503 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2504 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 2505 break; 2506 case ixgbe_mac_82599EB: 2507 case ixgbe_mac_X540: 2508 case ixgbe_mac_X550: 2509 case ixgbe_mac_X550EM_x: 2510 mask = (qmask & 0xFFFFFFFF); 2511 if (mask) 2512 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 2513 mask = (qmask >> 32); 2514 if (mask) 2515 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 2516 break; 2517 default: 2518 break; 2519 } 2520 /* skip the flush */ 2521 } 2522 2523 /** 2524 * ixgbe_irq_enable - Enable default interrupt generation settings 2525 * @adapter: board private structure 2526 **/ 2527 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2528 bool flush) 2529 { 2530 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2531 2532 /* don't reenable LSC while waiting for link */ 2533 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 2534 mask &= ~IXGBE_EIMS_LSC; 2535 2536 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 2537 switch (adapter->hw.mac.type) { 2538 case ixgbe_mac_82599EB: 2539 mask |= IXGBE_EIMS_GPI_SDP0; 2540 break; 2541 case ixgbe_mac_X540: 2542 case ixgbe_mac_X550: 2543 case ixgbe_mac_X550EM_x: 2544 mask |= IXGBE_EIMS_TS; 2545 break; 2546 default: 2547 break; 2548 } 2549 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 2550 mask |= IXGBE_EIMS_GPI_SDP1; 2551 switch (adapter->hw.mac.type) { 2552 case ixgbe_mac_82599EB: 2553 mask |= IXGBE_EIMS_GPI_SDP1; 2554 mask |= IXGBE_EIMS_GPI_SDP2; 2555 /* fall through */ 2556 case ixgbe_mac_X540: 2557 case ixgbe_mac_X550: 2558 case ixgbe_mac_X550EM_x: 2559 mask |= IXGBE_EIMS_ECC; 2560 mask |= IXGBE_EIMS_MAILBOX; 2561 break; 2562 default: 2563 break; 2564 } 2565 2566 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 2567 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 2568 mask |= IXGBE_EIMS_FLOW_DIR; 2569 2570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 2571 if (queues) 2572 ixgbe_irq_enable_queues(adapter, ~0); 2573 if (flush) 2574 IXGBE_WRITE_FLUSH(&adapter->hw); 2575 } 2576 2577 static irqreturn_t ixgbe_msix_other(int irq, void *data) 2578 { 2579 struct ixgbe_adapter *adapter = data; 2580 struct ixgbe_hw *hw = &adapter->hw; 2581 u32 eicr; 2582 2583 /* 2584 * Workaround for Silicon errata. Use clear-by-write instead 2585 * of clear-by-read. Reading with EICS will return the 2586 * interrupt causes without clearing, which later be done 2587 * with the write to EICR. 2588 */ 2589 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 2590 2591 /* The lower 16bits of the EICR register are for the queue interrupts 2592 * which should be masked here in order to not accidently clear them if 2593 * the bits are high when ixgbe_msix_other is called. There is a race 2594 * condition otherwise which results in possible performance loss 2595 * especially if the ixgbe_msix_other interrupt is triggering 2596 * consistently (as it would when PPS is turned on for the X540 device) 2597 */ 2598 eicr &= 0xFFFF0000; 2599 2600 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 2601 2602 if (eicr & IXGBE_EICR_LSC) 2603 ixgbe_check_lsc(adapter); 2604 2605 if (eicr & IXGBE_EICR_MAILBOX) 2606 ixgbe_msg_task(adapter); 2607 2608 switch (hw->mac.type) { 2609 case ixgbe_mac_82599EB: 2610 case ixgbe_mac_X540: 2611 case ixgbe_mac_X550: 2612 case ixgbe_mac_X550EM_x: 2613 if (eicr & IXGBE_EICR_ECC) { 2614 e_info(link, "Received ECC Err, initiating reset\n"); 2615 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 2616 ixgbe_service_event_schedule(adapter); 2617 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 2618 } 2619 /* Handle Flow Director Full threshold interrupt */ 2620 if (eicr & IXGBE_EICR_FLOW_DIR) { 2621 int reinit_count = 0; 2622 int i; 2623 for (i = 0; i < adapter->num_tx_queues; i++) { 2624 struct ixgbe_ring *ring = adapter->tx_ring[i]; 2625 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 2626 &ring->state)) 2627 reinit_count++; 2628 } 2629 if (reinit_count) { 2630 /* no more flow director interrupts until after init */ 2631 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 2632 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 2633 ixgbe_service_event_schedule(adapter); 2634 } 2635 } 2636 ixgbe_check_sfp_event(adapter, eicr); 2637 ixgbe_check_overtemp_event(adapter, eicr); 2638 break; 2639 default: 2640 break; 2641 } 2642 2643 ixgbe_check_fan_failure(adapter, eicr); 2644 2645 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 2646 ixgbe_ptp_check_pps_event(adapter, eicr); 2647 2648 /* re-enable the original interrupt state, no lsc, no queues */ 2649 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2650 ixgbe_irq_enable(adapter, false, false); 2651 2652 return IRQ_HANDLED; 2653 } 2654 2655 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 2656 { 2657 struct ixgbe_q_vector *q_vector = data; 2658 2659 /* EIAM disabled interrupts (on this vector) for us */ 2660 2661 if (q_vector->rx.ring || q_vector->tx.ring) 2662 napi_schedule(&q_vector->napi); 2663 2664 return IRQ_HANDLED; 2665 } 2666 2667 /** 2668 * ixgbe_poll - NAPI Rx polling callback 2669 * @napi: structure for representing this polling device 2670 * @budget: how many packets driver is allowed to clean 2671 * 2672 * This function is used for legacy and MSI, NAPI mode 2673 **/ 2674 int ixgbe_poll(struct napi_struct *napi, int budget) 2675 { 2676 struct ixgbe_q_vector *q_vector = 2677 container_of(napi, struct ixgbe_q_vector, napi); 2678 struct ixgbe_adapter *adapter = q_vector->adapter; 2679 struct ixgbe_ring *ring; 2680 int per_ring_budget; 2681 bool clean_complete = true; 2682 2683 #ifdef CONFIG_IXGBE_DCA 2684 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 2685 ixgbe_update_dca(q_vector); 2686 #endif 2687 2688 ixgbe_for_each_ring(ring, q_vector->tx) 2689 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring); 2690 2691 if (!ixgbe_qv_lock_napi(q_vector)) 2692 return budget; 2693 2694 /* attempt to distribute budget to each queue fairly, but don't allow 2695 * the budget to go below 1 because we'll exit polling */ 2696 if (q_vector->rx.count > 1) 2697 per_ring_budget = max(budget/q_vector->rx.count, 1); 2698 else 2699 per_ring_budget = budget; 2700 2701 ixgbe_for_each_ring(ring, q_vector->rx) 2702 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring, 2703 per_ring_budget) < per_ring_budget); 2704 2705 ixgbe_qv_unlock_napi(q_vector); 2706 /* If all work not completed, return budget and keep polling */ 2707 if (!clean_complete) 2708 return budget; 2709 2710 /* all work done, exit the polling mode */ 2711 napi_complete(napi); 2712 if (adapter->rx_itr_setting & 1) 2713 ixgbe_set_itr(q_vector); 2714 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2715 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); 2716 2717 return 0; 2718 } 2719 2720 /** 2721 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 2722 * @adapter: board private structure 2723 * 2724 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 2725 * interrupts from the kernel. 2726 **/ 2727 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 2728 { 2729 struct net_device *netdev = adapter->netdev; 2730 int vector, err; 2731 int ri = 0, ti = 0; 2732 2733 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 2734 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 2735 struct msix_entry *entry = &adapter->msix_entries[vector]; 2736 2737 if (q_vector->tx.ring && q_vector->rx.ring) { 2738 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2739 "%s-%s-%d", netdev->name, "TxRx", ri++); 2740 ti++; 2741 } else if (q_vector->rx.ring) { 2742 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2743 "%s-%s-%d", netdev->name, "rx", ri++); 2744 } else if (q_vector->tx.ring) { 2745 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2746 "%s-%s-%d", netdev->name, "tx", ti++); 2747 } else { 2748 /* skip this unused q_vector */ 2749 continue; 2750 } 2751 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 2752 q_vector->name, q_vector); 2753 if (err) { 2754 e_err(probe, "request_irq failed for MSIX interrupt " 2755 "Error: %d\n", err); 2756 goto free_queue_irqs; 2757 } 2758 /* If Flow Director is enabled, set interrupt affinity */ 2759 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 2760 /* assign the mask for this irq */ 2761 irq_set_affinity_hint(entry->vector, 2762 &q_vector->affinity_mask); 2763 } 2764 } 2765 2766 err = request_irq(adapter->msix_entries[vector].vector, 2767 ixgbe_msix_other, 0, netdev->name, adapter); 2768 if (err) { 2769 e_err(probe, "request_irq for msix_other failed: %d\n", err); 2770 goto free_queue_irqs; 2771 } 2772 2773 return 0; 2774 2775 free_queue_irqs: 2776 while (vector) { 2777 vector--; 2778 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 2779 NULL); 2780 free_irq(adapter->msix_entries[vector].vector, 2781 adapter->q_vector[vector]); 2782 } 2783 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 2784 pci_disable_msix(adapter->pdev); 2785 kfree(adapter->msix_entries); 2786 adapter->msix_entries = NULL; 2787 return err; 2788 } 2789 2790 /** 2791 * ixgbe_intr - legacy mode Interrupt Handler 2792 * @irq: interrupt number 2793 * @data: pointer to a network interface device structure 2794 **/ 2795 static irqreturn_t ixgbe_intr(int irq, void *data) 2796 { 2797 struct ixgbe_adapter *adapter = data; 2798 struct ixgbe_hw *hw = &adapter->hw; 2799 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 2800 u32 eicr; 2801 2802 /* 2803 * Workaround for silicon errata #26 on 82598. Mask the interrupt 2804 * before the read of EICR. 2805 */ 2806 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 2807 2808 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 2809 * therefore no explicit interrupt disable is necessary */ 2810 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 2811 if (!eicr) { 2812 /* 2813 * shared interrupt alert! 2814 * make sure interrupts are enabled because the read will 2815 * have disabled interrupts due to EIAM 2816 * finish the workaround of silicon errata on 82598. Unmask 2817 * the interrupt that we masked before the EICR read. 2818 */ 2819 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2820 ixgbe_irq_enable(adapter, true, true); 2821 return IRQ_NONE; /* Not our interrupt */ 2822 } 2823 2824 if (eicr & IXGBE_EICR_LSC) 2825 ixgbe_check_lsc(adapter); 2826 2827 switch (hw->mac.type) { 2828 case ixgbe_mac_82599EB: 2829 ixgbe_check_sfp_event(adapter, eicr); 2830 /* Fall through */ 2831 case ixgbe_mac_X540: 2832 case ixgbe_mac_X550: 2833 case ixgbe_mac_X550EM_x: 2834 if (eicr & IXGBE_EICR_ECC) { 2835 e_info(link, "Received ECC Err, initiating reset\n"); 2836 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 2837 ixgbe_service_event_schedule(adapter); 2838 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 2839 } 2840 ixgbe_check_overtemp_event(adapter, eicr); 2841 break; 2842 default: 2843 break; 2844 } 2845 2846 ixgbe_check_fan_failure(adapter, eicr); 2847 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 2848 ixgbe_ptp_check_pps_event(adapter, eicr); 2849 2850 /* would disable interrupts here but EIAM disabled it */ 2851 napi_schedule(&q_vector->napi); 2852 2853 /* 2854 * re-enable link(maybe) and non-queue interrupts, no flush. 2855 * ixgbe_poll will re-enable the queue interrupts 2856 */ 2857 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2858 ixgbe_irq_enable(adapter, false, false); 2859 2860 return IRQ_HANDLED; 2861 } 2862 2863 /** 2864 * ixgbe_request_irq - initialize interrupts 2865 * @adapter: board private structure 2866 * 2867 * Attempts to configure interrupts using the best available 2868 * capabilities of the hardware and kernel. 2869 **/ 2870 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 2871 { 2872 struct net_device *netdev = adapter->netdev; 2873 int err; 2874 2875 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 2876 err = ixgbe_request_msix_irqs(adapter); 2877 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 2878 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 2879 netdev->name, adapter); 2880 else 2881 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 2882 netdev->name, adapter); 2883 2884 if (err) 2885 e_err(probe, "request_irq failed, Error %d\n", err); 2886 2887 return err; 2888 } 2889 2890 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 2891 { 2892 int vector; 2893 2894 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 2895 free_irq(adapter->pdev->irq, adapter); 2896 return; 2897 } 2898 2899 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 2900 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 2901 struct msix_entry *entry = &adapter->msix_entries[vector]; 2902 2903 /* free only the irqs that were actually requested */ 2904 if (!q_vector->rx.ring && !q_vector->tx.ring) 2905 continue; 2906 2907 /* clear the affinity_mask in the IRQ descriptor */ 2908 irq_set_affinity_hint(entry->vector, NULL); 2909 2910 free_irq(entry->vector, q_vector); 2911 } 2912 2913 free_irq(adapter->msix_entries[vector++].vector, adapter); 2914 } 2915 2916 /** 2917 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 2918 * @adapter: board private structure 2919 **/ 2920 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 2921 { 2922 switch (adapter->hw.mac.type) { 2923 case ixgbe_mac_82598EB: 2924 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 2925 break; 2926 case ixgbe_mac_82599EB: 2927 case ixgbe_mac_X540: 2928 case ixgbe_mac_X550: 2929 case ixgbe_mac_X550EM_x: 2930 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 2931 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 2932 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 2933 break; 2934 default: 2935 break; 2936 } 2937 IXGBE_WRITE_FLUSH(&adapter->hw); 2938 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 2939 int vector; 2940 2941 for (vector = 0; vector < adapter->num_q_vectors; vector++) 2942 synchronize_irq(adapter->msix_entries[vector].vector); 2943 2944 synchronize_irq(adapter->msix_entries[vector++].vector); 2945 } else { 2946 synchronize_irq(adapter->pdev->irq); 2947 } 2948 } 2949 2950 /** 2951 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 2952 * 2953 **/ 2954 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 2955 { 2956 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 2957 2958 ixgbe_write_eitr(q_vector); 2959 2960 ixgbe_set_ivar(adapter, 0, 0, 0); 2961 ixgbe_set_ivar(adapter, 1, 0, 0); 2962 2963 e_info(hw, "Legacy interrupt IVAR setup done\n"); 2964 } 2965 2966 /** 2967 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 2968 * @adapter: board private structure 2969 * @ring: structure containing ring specific data 2970 * 2971 * Configure the Tx descriptor ring after a reset. 2972 **/ 2973 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 2974 struct ixgbe_ring *ring) 2975 { 2976 struct ixgbe_hw *hw = &adapter->hw; 2977 u64 tdba = ring->dma; 2978 int wait_loop = 10; 2979 u32 txdctl = IXGBE_TXDCTL_ENABLE; 2980 u8 reg_idx = ring->reg_idx; 2981 2982 /* disable queue to avoid issues while updating state */ 2983 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 2984 IXGBE_WRITE_FLUSH(hw); 2985 2986 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 2987 (tdba & DMA_BIT_MASK(32))); 2988 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 2989 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 2990 ring->count * sizeof(union ixgbe_adv_tx_desc)); 2991 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 2992 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 2993 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 2994 2995 /* 2996 * set WTHRESH to encourage burst writeback, it should not be set 2997 * higher than 1 when: 2998 * - ITR is 0 as it could cause false TX hangs 2999 * - ITR is set to > 100k int/sec and BQL is enabled 3000 * 3001 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3002 * to or less than the number of on chip descriptors, which is 3003 * currently 40. 3004 */ 3005 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3006 txdctl |= (1 << 16); /* WTHRESH = 1 */ 3007 else 3008 txdctl |= (8 << 16); /* WTHRESH = 8 */ 3009 3010 /* 3011 * Setting PTHRESH to 32 both improves performance 3012 * and avoids a TX hang with DFP enabled 3013 */ 3014 txdctl |= (1 << 8) | /* HTHRESH = 1 */ 3015 32; /* PTHRESH = 32 */ 3016 3017 /* reinitialize flowdirector state */ 3018 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3019 ring->atr_sample_rate = adapter->atr_sample_rate; 3020 ring->atr_count = 0; 3021 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3022 } else { 3023 ring->atr_sample_rate = 0; 3024 } 3025 3026 /* initialize XPS */ 3027 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3028 struct ixgbe_q_vector *q_vector = ring->q_vector; 3029 3030 if (q_vector) 3031 netif_set_xps_queue(ring->netdev, 3032 &q_vector->affinity_mask, 3033 ring->queue_index); 3034 } 3035 3036 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3037 3038 /* enable queue */ 3039 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3040 3041 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3042 if (hw->mac.type == ixgbe_mac_82598EB && 3043 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3044 return; 3045 3046 /* poll to verify queue is enabled */ 3047 do { 3048 usleep_range(1000, 2000); 3049 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3050 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3051 if (!wait_loop) 3052 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); 3053 } 3054 3055 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3056 { 3057 struct ixgbe_hw *hw = &adapter->hw; 3058 u32 rttdcs, mtqc; 3059 u8 tcs = netdev_get_num_tc(adapter->netdev); 3060 3061 if (hw->mac.type == ixgbe_mac_82598EB) 3062 return; 3063 3064 /* disable the arbiter while setting MTQC */ 3065 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3066 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3067 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3068 3069 /* set transmit pool layout */ 3070 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3071 mtqc = IXGBE_MTQC_VT_ENA; 3072 if (tcs > 4) 3073 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3074 else if (tcs > 1) 3075 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3076 else if (adapter->ring_feature[RING_F_RSS].indices == 4) 3077 mtqc |= IXGBE_MTQC_32VF; 3078 else 3079 mtqc |= IXGBE_MTQC_64VF; 3080 } else { 3081 if (tcs > 4) 3082 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3083 else if (tcs > 1) 3084 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3085 else 3086 mtqc = IXGBE_MTQC_64Q_1PB; 3087 } 3088 3089 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3090 3091 /* Enable Security TX Buffer IFG for multiple pb */ 3092 if (tcs) { 3093 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3094 sectx |= IXGBE_SECTX_DCB; 3095 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3096 } 3097 3098 /* re-enable the arbiter */ 3099 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3100 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3101 } 3102 3103 /** 3104 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3105 * @adapter: board private structure 3106 * 3107 * Configure the Tx unit of the MAC after a reset. 3108 **/ 3109 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3110 { 3111 struct ixgbe_hw *hw = &adapter->hw; 3112 u32 dmatxctl; 3113 u32 i; 3114 3115 ixgbe_setup_mtqc(adapter); 3116 3117 if (hw->mac.type != ixgbe_mac_82598EB) { 3118 /* DMATXCTL.EN must be before Tx queues are enabled */ 3119 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3120 dmatxctl |= IXGBE_DMATXCTL_TE; 3121 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3122 } 3123 3124 /* Setup the HW Tx Head and Tail descriptor pointers */ 3125 for (i = 0; i < adapter->num_tx_queues; i++) 3126 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3127 } 3128 3129 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3130 struct ixgbe_ring *ring) 3131 { 3132 struct ixgbe_hw *hw = &adapter->hw; 3133 u8 reg_idx = ring->reg_idx; 3134 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3135 3136 srrctl |= IXGBE_SRRCTL_DROP_EN; 3137 3138 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3139 } 3140 3141 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3142 struct ixgbe_ring *ring) 3143 { 3144 struct ixgbe_hw *hw = &adapter->hw; 3145 u8 reg_idx = ring->reg_idx; 3146 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3147 3148 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3149 3150 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3151 } 3152 3153 #ifdef CONFIG_IXGBE_DCB 3154 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3155 #else 3156 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3157 #endif 3158 { 3159 int i; 3160 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3161 3162 if (adapter->ixgbe_ieee_pfc) 3163 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3164 3165 /* 3166 * We should set the drop enable bit if: 3167 * SR-IOV is enabled 3168 * or 3169 * Number of Rx queues > 1 and flow control is disabled 3170 * 3171 * This allows us to avoid head of line blocking for security 3172 * and performance reasons. 3173 */ 3174 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3175 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3176 for (i = 0; i < adapter->num_rx_queues; i++) 3177 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3178 } else { 3179 for (i = 0; i < adapter->num_rx_queues; i++) 3180 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3181 } 3182 } 3183 3184 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3185 3186 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3187 struct ixgbe_ring *rx_ring) 3188 { 3189 struct ixgbe_hw *hw = &adapter->hw; 3190 u32 srrctl; 3191 u8 reg_idx = rx_ring->reg_idx; 3192 3193 if (hw->mac.type == ixgbe_mac_82598EB) { 3194 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3195 3196 /* 3197 * if VMDq is not active we must program one srrctl register 3198 * per RSS queue since we have enabled RDRXCTL.MVMEN 3199 */ 3200 reg_idx &= mask; 3201 } 3202 3203 /* configure header buffer length, needed for RSC */ 3204 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3205 3206 /* configure the packet buffer length */ 3207 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3208 3209 /* configure descriptor type */ 3210 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3211 3212 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3213 } 3214 3215 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter, const u32 *seed) 3216 { 3217 struct ixgbe_hw *hw = &adapter->hw; 3218 u32 reta = 0; 3219 int i, j; 3220 int reta_entries = 128; 3221 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3222 int indices_multi; 3223 3224 /* 3225 * Program table for at least 2 queues w/ SR-IOV so that VFs can 3226 * make full use of any rings they may have. We will use the 3227 * PSRTYPE register to control how many rings we use within the PF. 3228 */ 3229 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2)) 3230 rss_i = 2; 3231 3232 /* Fill out hash function seeds */ 3233 for (i = 0; i < 10; i++) 3234 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); 3235 3236 /* Fill out the redirection table as follows: 3237 * 82598: 128 (8 bit wide) entries containing pair of 4 bit RSS indices 3238 * 82599/X540: 128 (8 bit wide) entries containing 4 bit RSS index 3239 * X550: 512 (8 bit wide) entries containing 6 bit RSS index 3240 */ 3241 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3242 indices_multi = 0x11; 3243 else 3244 indices_multi = 0x1; 3245 3246 switch (adapter->hw.mac.type) { 3247 case ixgbe_mac_X550: 3248 case ixgbe_mac_X550EM_x: 3249 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 3250 reta_entries = 512; 3251 default: 3252 break; 3253 } 3254 3255 /* Fill out redirection table */ 3256 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3257 if (j == rss_i) 3258 j = 0; 3259 reta = (reta << 8) | (j * indices_multi); 3260 if ((i & 3) == 3) { 3261 if (i < 128) 3262 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3263 else 3264 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3265 reta); 3266 } 3267 } 3268 } 3269 3270 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter, const u32 *seed) 3271 { 3272 struct ixgbe_hw *hw = &adapter->hw; 3273 u32 vfreta = 0; 3274 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3275 unsigned int pf_pool = adapter->num_vfs; 3276 int i, j; 3277 3278 /* Fill out hash function seeds */ 3279 for (i = 0; i < 10; i++) 3280 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool), seed[i]); 3281 3282 /* Fill out the redirection table */ 3283 for (i = 0, j = 0; i < 64; i++, j++) { 3284 if (j == rss_i) 3285 j = 0; 3286 vfreta = (vfreta << 8) | j; 3287 if ((i & 3) == 3) 3288 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool), 3289 vfreta); 3290 } 3291 } 3292 3293 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3294 { 3295 struct ixgbe_hw *hw = &adapter->hw; 3296 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3297 u32 rss_key[10]; 3298 u32 rxcsum; 3299 3300 /* Disable indicating checksum in descriptor, enables RSS hash */ 3301 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3302 rxcsum |= IXGBE_RXCSUM_PCSD; 3303 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3304 3305 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3306 if (adapter->ring_feature[RING_F_RSS].mask) 3307 mrqc = IXGBE_MRQC_RSSEN; 3308 } else { 3309 u8 tcs = netdev_get_num_tc(adapter->netdev); 3310 3311 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3312 if (tcs > 4) 3313 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3314 else if (tcs > 1) 3315 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3316 else if (adapter->ring_feature[RING_F_RSS].indices == 4) 3317 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3318 else 3319 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3320 } else { 3321 if (tcs > 4) 3322 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3323 else if (tcs > 1) 3324 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3325 else 3326 mrqc = IXGBE_MRQC_RSSEN; 3327 } 3328 } 3329 3330 /* Perform hash on these packet types */ 3331 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3332 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3333 IXGBE_MRQC_RSS_FIELD_IPV6 | 3334 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3335 3336 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3337 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3338 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3339 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3340 3341 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3342 if ((hw->mac.type >= ixgbe_mac_X550) && 3343 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3344 unsigned int pf_pool = adapter->num_vfs; 3345 3346 /* Enable VF RSS mode */ 3347 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3348 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3349 3350 /* Setup RSS through the VF registers */ 3351 ixgbe_setup_vfreta(adapter, rss_key); 3352 vfmrqc = IXGBE_MRQC_RSSEN; 3353 vfmrqc |= rss_field; 3354 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc); 3355 } else { 3356 ixgbe_setup_reta(adapter, rss_key); 3357 mrqc |= rss_field; 3358 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3359 } 3360 } 3361 3362 /** 3363 * ixgbe_configure_rscctl - enable RSC for the indicated ring 3364 * @adapter: address of board private structure 3365 * @index: index of ring to set 3366 **/ 3367 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 3368 struct ixgbe_ring *ring) 3369 { 3370 struct ixgbe_hw *hw = &adapter->hw; 3371 u32 rscctrl; 3372 u8 reg_idx = ring->reg_idx; 3373 3374 if (!ring_is_rsc_enabled(ring)) 3375 return; 3376 3377 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 3378 rscctrl |= IXGBE_RSCCTL_RSCEN; 3379 /* 3380 * we must limit the number of descriptors so that the 3381 * total size of max desc * buf_len is not greater 3382 * than 65536 3383 */ 3384 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 3385 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 3386 } 3387 3388 #define IXGBE_MAX_RX_DESC_POLL 10 3389 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 3390 struct ixgbe_ring *ring) 3391 { 3392 struct ixgbe_hw *hw = &adapter->hw; 3393 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3394 u32 rxdctl; 3395 u8 reg_idx = ring->reg_idx; 3396 3397 if (ixgbe_removed(hw->hw_addr)) 3398 return; 3399 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3400 if (hw->mac.type == ixgbe_mac_82598EB && 3401 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3402 return; 3403 3404 do { 3405 usleep_range(1000, 2000); 3406 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3407 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 3408 3409 if (!wait_loop) { 3410 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 3411 "the polling period\n", reg_idx); 3412 } 3413 } 3414 3415 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 3416 struct ixgbe_ring *ring) 3417 { 3418 struct ixgbe_hw *hw = &adapter->hw; 3419 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3420 u32 rxdctl; 3421 u8 reg_idx = ring->reg_idx; 3422 3423 if (ixgbe_removed(hw->hw_addr)) 3424 return; 3425 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3426 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 3427 3428 /* write value back with RXDCTL.ENABLE bit cleared */ 3429 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3430 3431 if (hw->mac.type == ixgbe_mac_82598EB && 3432 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3433 return; 3434 3435 /* the hardware may take up to 100us to really disable the rx queue */ 3436 do { 3437 udelay(10); 3438 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3439 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); 3440 3441 if (!wait_loop) { 3442 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " 3443 "the polling period\n", reg_idx); 3444 } 3445 } 3446 3447 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 3448 struct ixgbe_ring *ring) 3449 { 3450 struct ixgbe_hw *hw = &adapter->hw; 3451 u64 rdba = ring->dma; 3452 u32 rxdctl; 3453 u8 reg_idx = ring->reg_idx; 3454 3455 /* disable queue to avoid issues while updating state */ 3456 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3457 ixgbe_disable_rx_queue(adapter, ring); 3458 3459 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 3460 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 3461 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 3462 ring->count * sizeof(union ixgbe_adv_rx_desc)); 3463 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 3464 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 3465 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 3466 3467 ixgbe_configure_srrctl(adapter, ring); 3468 ixgbe_configure_rscctl(adapter, ring); 3469 3470 if (hw->mac.type == ixgbe_mac_82598EB) { 3471 /* 3472 * enable cache line friendly hardware writes: 3473 * PTHRESH=32 descriptors (half the internal cache), 3474 * this also removes ugly rx_no_buffer_count increment 3475 * HTHRESH=4 descriptors (to minimize latency on fetch) 3476 * WTHRESH=8 burst writeback up to two cache lines 3477 */ 3478 rxdctl &= ~0x3FFFFF; 3479 rxdctl |= 0x080420; 3480 } 3481 3482 /* enable receive descriptor ring */ 3483 rxdctl |= IXGBE_RXDCTL_ENABLE; 3484 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3485 3486 ixgbe_rx_desc_queue_enable(adapter, ring); 3487 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 3488 } 3489 3490 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 3491 { 3492 struct ixgbe_hw *hw = &adapter->hw; 3493 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 3494 u16 pool; 3495 3496 /* PSRTYPE must be initialized in non 82598 adapters */ 3497 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 3498 IXGBE_PSRTYPE_UDPHDR | 3499 IXGBE_PSRTYPE_IPV4HDR | 3500 IXGBE_PSRTYPE_L2HDR | 3501 IXGBE_PSRTYPE_IPV6HDR; 3502 3503 if (hw->mac.type == ixgbe_mac_82598EB) 3504 return; 3505 3506 if (rss_i > 3) 3507 psrtype |= 2 << 29; 3508 else if (rss_i > 1) 3509 psrtype |= 1 << 29; 3510 3511 for_each_set_bit(pool, &adapter->fwd_bitmask, 32) 3512 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 3513 } 3514 3515 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 3516 { 3517 struct ixgbe_hw *hw = &adapter->hw; 3518 u32 reg_offset, vf_shift; 3519 u32 gcr_ext, vmdctl; 3520 int i; 3521 3522 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 3523 return; 3524 3525 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 3526 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 3527 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 3528 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 3529 vmdctl |= IXGBE_VT_CTL_REPLEN; 3530 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 3531 3532 vf_shift = VMDQ_P(0) % 32; 3533 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 3534 3535 /* Enable only the PF's pool for Tx/Rx */ 3536 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift); 3537 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 3538 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift); 3539 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 3540 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB) 3541 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 3542 3543 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 3544 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 3545 3546 /* 3547 * Set up VF register offsets for selected VT Mode, 3548 * i.e. 32 or 64 VFs for SR-IOV 3549 */ 3550 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 3551 case IXGBE_82599_VMDQ_8Q_MASK: 3552 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 3553 break; 3554 case IXGBE_82599_VMDQ_4Q_MASK: 3555 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 3556 break; 3557 default: 3558 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 3559 break; 3560 } 3561 3562 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 3563 3564 3565 /* Enable MAC Anti-Spoofing */ 3566 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0), 3567 adapter->num_vfs); 3568 /* For VFs that have spoof checking turned off */ 3569 for (i = 0; i < adapter->num_vfs; i++) { 3570 if (!adapter->vfinfo[i].spoofchk_enabled) 3571 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false); 3572 } 3573 } 3574 3575 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 3576 { 3577 struct ixgbe_hw *hw = &adapter->hw; 3578 struct net_device *netdev = adapter->netdev; 3579 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 3580 struct ixgbe_ring *rx_ring; 3581 int i; 3582 u32 mhadd, hlreg0; 3583 3584 #ifdef IXGBE_FCOE 3585 /* adjust max frame to be able to do baby jumbo for FCoE */ 3586 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 3587 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 3588 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 3589 3590 #endif /* IXGBE_FCOE */ 3591 3592 /* adjust max frame to be at least the size of a standard frame */ 3593 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 3594 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 3595 3596 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 3597 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 3598 mhadd &= ~IXGBE_MHADD_MFS_MASK; 3599 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 3600 3601 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 3602 } 3603 3604 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3605 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 3606 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 3607 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3608 3609 /* 3610 * Setup the HW Rx Head and Tail Descriptor Pointers and 3611 * the Base and Length of the Rx Descriptor Ring 3612 */ 3613 for (i = 0; i < adapter->num_rx_queues; i++) { 3614 rx_ring = adapter->rx_ring[i]; 3615 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 3616 set_ring_rsc_enabled(rx_ring); 3617 else 3618 clear_ring_rsc_enabled(rx_ring); 3619 } 3620 } 3621 3622 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 3623 { 3624 struct ixgbe_hw *hw = &adapter->hw; 3625 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 3626 3627 switch (hw->mac.type) { 3628 case ixgbe_mac_X550: 3629 case ixgbe_mac_X550EM_x: 3630 case ixgbe_mac_82598EB: 3631 /* 3632 * For VMDq support of different descriptor types or 3633 * buffer sizes through the use of multiple SRRCTL 3634 * registers, RDRXCTL.MVMEN must be set to 1 3635 * 3636 * also, the manual doesn't mention it clearly but DCA hints 3637 * will only use queue 0's tags unless this bit is set. Side 3638 * effects of setting this bit are only that SRRCTL must be 3639 * fully programmed [0..15] 3640 */ 3641 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 3642 break; 3643 case ixgbe_mac_82599EB: 3644 case ixgbe_mac_X540: 3645 /* Disable RSC for ACK packets */ 3646 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 3647 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 3648 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 3649 /* hardware requires some bits to be set by default */ 3650 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 3651 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 3652 break; 3653 default: 3654 /* We should do nothing since we don't know this hardware */ 3655 return; 3656 } 3657 3658 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 3659 } 3660 3661 /** 3662 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 3663 * @adapter: board private structure 3664 * 3665 * Configure the Rx unit of the MAC after a reset. 3666 **/ 3667 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 3668 { 3669 struct ixgbe_hw *hw = &adapter->hw; 3670 int i; 3671 u32 rxctrl, rfctl; 3672 3673 /* disable receives while setting up the descriptors */ 3674 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3675 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); 3676 3677 ixgbe_setup_psrtype(adapter); 3678 ixgbe_setup_rdrxctl(adapter); 3679 3680 /* RSC Setup */ 3681 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 3682 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 3683 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 3684 rfctl |= IXGBE_RFCTL_RSC_DIS; 3685 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 3686 3687 /* Program registers for the distribution of queues */ 3688 ixgbe_setup_mrqc(adapter); 3689 3690 /* set_rx_buffer_len must be called before ring initialization */ 3691 ixgbe_set_rx_buffer_len(adapter); 3692 3693 /* 3694 * Setup the HW Rx Head and Tail Descriptor Pointers and 3695 * the Base and Length of the Rx Descriptor Ring 3696 */ 3697 for (i = 0; i < adapter->num_rx_queues; i++) 3698 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 3699 3700 /* disable drop enable for 82598 parts */ 3701 if (hw->mac.type == ixgbe_mac_82598EB) 3702 rxctrl |= IXGBE_RXCTRL_DMBYPS; 3703 3704 /* enable all receives */ 3705 rxctrl |= IXGBE_RXCTRL_RXEN; 3706 hw->mac.ops.enable_rx_dma(hw, rxctrl); 3707 } 3708 3709 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 3710 __be16 proto, u16 vid) 3711 { 3712 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3713 struct ixgbe_hw *hw = &adapter->hw; 3714 3715 /* add VID to filter table */ 3716 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true); 3717 set_bit(vid, adapter->active_vlans); 3718 3719 return 0; 3720 } 3721 3722 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 3723 __be16 proto, u16 vid) 3724 { 3725 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3726 struct ixgbe_hw *hw = &adapter->hw; 3727 3728 /* remove VID from filter table */ 3729 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false); 3730 clear_bit(vid, adapter->active_vlans); 3731 3732 return 0; 3733 } 3734 3735 /** 3736 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 3737 * @adapter: driver data 3738 */ 3739 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 3740 { 3741 struct ixgbe_hw *hw = &adapter->hw; 3742 u32 vlnctrl; 3743 int i, j; 3744 3745 switch (hw->mac.type) { 3746 case ixgbe_mac_82598EB: 3747 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 3748 vlnctrl &= ~IXGBE_VLNCTRL_VME; 3749 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 3750 break; 3751 case ixgbe_mac_82599EB: 3752 case ixgbe_mac_X540: 3753 case ixgbe_mac_X550: 3754 case ixgbe_mac_X550EM_x: 3755 for (i = 0; i < adapter->num_rx_queues; i++) { 3756 struct ixgbe_ring *ring = adapter->rx_ring[i]; 3757 3758 if (ring->l2_accel_priv) 3759 continue; 3760 j = ring->reg_idx; 3761 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 3762 vlnctrl &= ~IXGBE_RXDCTL_VME; 3763 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 3764 } 3765 break; 3766 default: 3767 break; 3768 } 3769 } 3770 3771 /** 3772 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 3773 * @adapter: driver data 3774 */ 3775 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 3776 { 3777 struct ixgbe_hw *hw = &adapter->hw; 3778 u32 vlnctrl; 3779 int i, j; 3780 3781 switch (hw->mac.type) { 3782 case ixgbe_mac_82598EB: 3783 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 3784 vlnctrl |= IXGBE_VLNCTRL_VME; 3785 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 3786 break; 3787 case ixgbe_mac_82599EB: 3788 case ixgbe_mac_X540: 3789 case ixgbe_mac_X550: 3790 case ixgbe_mac_X550EM_x: 3791 for (i = 0; i < adapter->num_rx_queues; i++) { 3792 struct ixgbe_ring *ring = adapter->rx_ring[i]; 3793 3794 if (ring->l2_accel_priv) 3795 continue; 3796 j = ring->reg_idx; 3797 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 3798 vlnctrl |= IXGBE_RXDCTL_VME; 3799 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 3800 } 3801 break; 3802 default: 3803 break; 3804 } 3805 } 3806 3807 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 3808 { 3809 u16 vid; 3810 3811 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 3812 3813 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 3814 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 3815 } 3816 3817 /** 3818 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 3819 * @netdev: network interface device structure 3820 * 3821 * Writes multicast address list to the MTA hash table. 3822 * Returns: -ENOMEM on failure 3823 * 0 on no addresses written 3824 * X on writing X addresses to MTA 3825 **/ 3826 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 3827 { 3828 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3829 struct ixgbe_hw *hw = &adapter->hw; 3830 3831 if (!netif_running(netdev)) 3832 return 0; 3833 3834 if (hw->mac.ops.update_mc_addr_list) 3835 hw->mac.ops.update_mc_addr_list(hw, netdev); 3836 else 3837 return -ENOMEM; 3838 3839 #ifdef CONFIG_PCI_IOV 3840 ixgbe_restore_vf_multicasts(adapter); 3841 #endif 3842 3843 return netdev_mc_count(netdev); 3844 } 3845 3846 #ifdef CONFIG_PCI_IOV 3847 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 3848 { 3849 struct ixgbe_hw *hw = &adapter->hw; 3850 int i; 3851 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3852 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE) 3853 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr, 3854 adapter->mac_table[i].queue, 3855 IXGBE_RAH_AV); 3856 else 3857 hw->mac.ops.clear_rar(hw, i); 3858 3859 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED); 3860 } 3861 } 3862 #endif 3863 3864 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 3865 { 3866 struct ixgbe_hw *hw = &adapter->hw; 3867 int i; 3868 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3869 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) { 3870 if (adapter->mac_table[i].state & 3871 IXGBE_MAC_STATE_IN_USE) 3872 hw->mac.ops.set_rar(hw, i, 3873 adapter->mac_table[i].addr, 3874 adapter->mac_table[i].queue, 3875 IXGBE_RAH_AV); 3876 else 3877 hw->mac.ops.clear_rar(hw, i); 3878 3879 adapter->mac_table[i].state &= 3880 ~(IXGBE_MAC_STATE_MODIFIED); 3881 } 3882 } 3883 } 3884 3885 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 3886 { 3887 int i; 3888 struct ixgbe_hw *hw = &adapter->hw; 3889 3890 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3891 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED; 3892 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE; 3893 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 3894 adapter->mac_table[i].queue = 0; 3895 } 3896 ixgbe_sync_mac_table(adapter); 3897 } 3898 3899 static int ixgbe_available_rars(struct ixgbe_adapter *adapter) 3900 { 3901 struct ixgbe_hw *hw = &adapter->hw; 3902 int i, count = 0; 3903 3904 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3905 if (adapter->mac_table[i].state == 0) 3906 count++; 3907 } 3908 return count; 3909 } 3910 3911 /* this function destroys the first RAR entry */ 3912 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter, 3913 u8 *addr) 3914 { 3915 struct ixgbe_hw *hw = &adapter->hw; 3916 3917 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN); 3918 adapter->mac_table[0].queue = VMDQ_P(0); 3919 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT | 3920 IXGBE_MAC_STATE_IN_USE); 3921 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr, 3922 adapter->mac_table[0].queue, 3923 IXGBE_RAH_AV); 3924 } 3925 3926 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue) 3927 { 3928 struct ixgbe_hw *hw = &adapter->hw; 3929 int i; 3930 3931 if (is_zero_ether_addr(addr)) 3932 return -EINVAL; 3933 3934 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3935 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE) 3936 continue; 3937 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED | 3938 IXGBE_MAC_STATE_IN_USE); 3939 ether_addr_copy(adapter->mac_table[i].addr, addr); 3940 adapter->mac_table[i].queue = queue; 3941 ixgbe_sync_mac_table(adapter); 3942 return i; 3943 } 3944 return -ENOMEM; 3945 } 3946 3947 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue) 3948 { 3949 /* search table for addr, if found, set to 0 and sync */ 3950 int i; 3951 struct ixgbe_hw *hw = &adapter->hw; 3952 3953 if (is_zero_ether_addr(addr)) 3954 return -EINVAL; 3955 3956 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3957 if (ether_addr_equal(addr, adapter->mac_table[i].addr) && 3958 adapter->mac_table[i].queue == queue) { 3959 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED; 3960 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE; 3961 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 3962 adapter->mac_table[i].queue = 0; 3963 ixgbe_sync_mac_table(adapter); 3964 return 0; 3965 } 3966 } 3967 return -ENOMEM; 3968 } 3969 /** 3970 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table 3971 * @netdev: network interface device structure 3972 * 3973 * Writes unicast address list to the RAR table. 3974 * Returns: -ENOMEM on failure/insufficient address space 3975 * 0 on no addresses written 3976 * X on writing X addresses to the RAR table 3977 **/ 3978 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn) 3979 { 3980 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3981 int count = 0; 3982 3983 /* return ENOMEM indicating insufficient memory for addresses */ 3984 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter)) 3985 return -ENOMEM; 3986 3987 if (!netdev_uc_empty(netdev)) { 3988 struct netdev_hw_addr *ha; 3989 netdev_for_each_uc_addr(ha, netdev) { 3990 ixgbe_del_mac_filter(adapter, ha->addr, vfn); 3991 ixgbe_add_mac_filter(adapter, ha->addr, vfn); 3992 count++; 3993 } 3994 } 3995 return count; 3996 } 3997 3998 /** 3999 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4000 * @netdev: network interface device structure 4001 * 4002 * The set_rx_method entry point is called whenever the unicast/multicast 4003 * address list or the network interface flags are updated. This routine is 4004 * responsible for configuring the hardware for proper unicast, multicast and 4005 * promiscuous mode. 4006 **/ 4007 void ixgbe_set_rx_mode(struct net_device *netdev) 4008 { 4009 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4010 struct ixgbe_hw *hw = &adapter->hw; 4011 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4012 u32 vlnctrl; 4013 int count; 4014 4015 /* Check for Promiscuous and All Multicast modes */ 4016 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4017 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4018 4019 /* set all bits that we expect to always be set */ 4020 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4021 fctrl |= IXGBE_FCTRL_BAM; 4022 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4023 fctrl |= IXGBE_FCTRL_PMCF; 4024 4025 /* clear the bits we are changing the status of */ 4026 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4027 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); 4028 if (netdev->flags & IFF_PROMISC) { 4029 hw->addr_ctrl.user_set_promisc = true; 4030 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4031 vmolr |= IXGBE_VMOLR_MPE; 4032 /* Only disable hardware filter vlans in promiscuous mode 4033 * if SR-IOV and VMDQ are disabled - otherwise ensure 4034 * that hardware VLAN filters remain enabled. 4035 */ 4036 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED | 4037 IXGBE_FLAG_SRIOV_ENABLED)) 4038 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); 4039 } else { 4040 if (netdev->flags & IFF_ALLMULTI) { 4041 fctrl |= IXGBE_FCTRL_MPE; 4042 vmolr |= IXGBE_VMOLR_MPE; 4043 } 4044 vlnctrl |= IXGBE_VLNCTRL_VFE; 4045 hw->addr_ctrl.user_set_promisc = false; 4046 } 4047 4048 /* 4049 * Write addresses to available RAR registers, if there is not 4050 * sufficient space to store all the addresses then enable 4051 * unicast promiscuous mode 4052 */ 4053 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0)); 4054 if (count < 0) { 4055 fctrl |= IXGBE_FCTRL_UPE; 4056 vmolr |= IXGBE_VMOLR_ROPE; 4057 } 4058 4059 /* Write addresses to the MTA, if the attempt fails 4060 * then we should just turn on promiscuous mode so 4061 * that we can at least receive multicast traffic 4062 */ 4063 count = ixgbe_write_mc_addr_list(netdev); 4064 if (count < 0) { 4065 fctrl |= IXGBE_FCTRL_MPE; 4066 vmolr |= IXGBE_VMOLR_MPE; 4067 } else if (count) { 4068 vmolr |= IXGBE_VMOLR_ROMPE; 4069 } 4070 4071 if (hw->mac.type != ixgbe_mac_82598EB) { 4072 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4073 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4074 IXGBE_VMOLR_ROPE); 4075 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4076 } 4077 4078 /* This is useful for sniffing bad packets. */ 4079 if (adapter->netdev->features & NETIF_F_RXALL) { 4080 /* UPE and MPE will be handled by normal PROMISC logic 4081 * in e1000e_set_rx_mode */ 4082 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4083 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4084 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4085 4086 fctrl &= ~(IXGBE_FCTRL_DPF); 4087 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4088 } 4089 4090 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4091 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4092 4093 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 4094 ixgbe_vlan_strip_enable(adapter); 4095 else 4096 ixgbe_vlan_strip_disable(adapter); 4097 } 4098 4099 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4100 { 4101 int q_idx; 4102 4103 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) { 4104 ixgbe_qv_init_lock(adapter->q_vector[q_idx]); 4105 napi_enable(&adapter->q_vector[q_idx]->napi); 4106 } 4107 } 4108 4109 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 4110 { 4111 int q_idx; 4112 4113 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) { 4114 napi_disable(&adapter->q_vector[q_idx]->napi); 4115 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) { 4116 pr_info("QV %d locked\n", q_idx); 4117 usleep_range(1000, 20000); 4118 } 4119 } 4120 } 4121 4122 #ifdef CONFIG_IXGBE_DCB 4123 /** 4124 * ixgbe_configure_dcb - Configure DCB hardware 4125 * @adapter: ixgbe adapter struct 4126 * 4127 * This is called by the driver on open to configure the DCB hardware. 4128 * This is also called by the gennetlink interface when reconfiguring 4129 * the DCB state. 4130 */ 4131 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 4132 { 4133 struct ixgbe_hw *hw = &adapter->hw; 4134 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4135 4136 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 4137 if (hw->mac.type == ixgbe_mac_82598EB) 4138 netif_set_gso_max_size(adapter->netdev, 65536); 4139 return; 4140 } 4141 4142 if (hw->mac.type == ixgbe_mac_82598EB) 4143 netif_set_gso_max_size(adapter->netdev, 32768); 4144 4145 #ifdef IXGBE_FCOE 4146 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 4147 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 4148 #endif 4149 4150 /* reconfigure the hardware */ 4151 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 4152 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4153 DCB_TX_CONFIG); 4154 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4155 DCB_RX_CONFIG); 4156 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 4157 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 4158 ixgbe_dcb_hw_ets(&adapter->hw, 4159 adapter->ixgbe_ieee_ets, 4160 max_frame); 4161 ixgbe_dcb_hw_pfc_config(&adapter->hw, 4162 adapter->ixgbe_ieee_pfc->pfc_en, 4163 adapter->ixgbe_ieee_ets->prio_tc); 4164 } 4165 4166 /* Enable RSS Hash per TC */ 4167 if (hw->mac.type != ixgbe_mac_82598EB) { 4168 u32 msb = 0; 4169 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 4170 4171 while (rss_i) { 4172 msb++; 4173 rss_i >>= 1; 4174 } 4175 4176 /* write msb to all 8 TCs in one write */ 4177 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 4178 } 4179 } 4180 #endif 4181 4182 /* Additional bittime to account for IXGBE framing */ 4183 #define IXGBE_ETH_FRAMING 20 4184 4185 /** 4186 * ixgbe_hpbthresh - calculate high water mark for flow control 4187 * 4188 * @adapter: board private structure to calculate for 4189 * @pb: packet buffer to calculate 4190 */ 4191 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 4192 { 4193 struct ixgbe_hw *hw = &adapter->hw; 4194 struct net_device *dev = adapter->netdev; 4195 int link, tc, kb, marker; 4196 u32 dv_id, rx_pba; 4197 4198 /* Calculate max LAN frame size */ 4199 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 4200 4201 #ifdef IXGBE_FCOE 4202 /* FCoE traffic class uses FCOE jumbo frames */ 4203 if ((dev->features & NETIF_F_FCOE_MTU) && 4204 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 4205 (pb == ixgbe_fcoe_get_tc(adapter))) 4206 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4207 #endif 4208 4209 /* Calculate delay value for device */ 4210 switch (hw->mac.type) { 4211 case ixgbe_mac_X540: 4212 case ixgbe_mac_X550: 4213 case ixgbe_mac_X550EM_x: 4214 dv_id = IXGBE_DV_X540(link, tc); 4215 break; 4216 default: 4217 dv_id = IXGBE_DV(link, tc); 4218 break; 4219 } 4220 4221 /* Loopback switch introduces additional latency */ 4222 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4223 dv_id += IXGBE_B2BT(tc); 4224 4225 /* Delay value is calculated in bit times convert to KB */ 4226 kb = IXGBE_BT2KB(dv_id); 4227 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 4228 4229 marker = rx_pba - kb; 4230 4231 /* It is possible that the packet buffer is not large enough 4232 * to provide required headroom. In this case throw an error 4233 * to user and a do the best we can. 4234 */ 4235 if (marker < 0) { 4236 e_warn(drv, "Packet Buffer(%i) can not provide enough" 4237 "headroom to support flow control." 4238 "Decrease MTU or number of traffic classes\n", pb); 4239 marker = tc + 1; 4240 } 4241 4242 return marker; 4243 } 4244 4245 /** 4246 * ixgbe_lpbthresh - calculate low water mark for for flow control 4247 * 4248 * @adapter: board private structure to calculate for 4249 * @pb: packet buffer to calculate 4250 */ 4251 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 4252 { 4253 struct ixgbe_hw *hw = &adapter->hw; 4254 struct net_device *dev = adapter->netdev; 4255 int tc; 4256 u32 dv_id; 4257 4258 /* Calculate max LAN frame size */ 4259 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 4260 4261 #ifdef IXGBE_FCOE 4262 /* FCoE traffic class uses FCOE jumbo frames */ 4263 if ((dev->features & NETIF_F_FCOE_MTU) && 4264 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 4265 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 4266 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4267 #endif 4268 4269 /* Calculate delay value for device */ 4270 switch (hw->mac.type) { 4271 case ixgbe_mac_X540: 4272 case ixgbe_mac_X550: 4273 case ixgbe_mac_X550EM_x: 4274 dv_id = IXGBE_LOW_DV_X540(tc); 4275 break; 4276 default: 4277 dv_id = IXGBE_LOW_DV(tc); 4278 break; 4279 } 4280 4281 /* Delay value is calculated in bit times convert to KB */ 4282 return IXGBE_BT2KB(dv_id); 4283 } 4284 4285 /* 4286 * ixgbe_pbthresh_setup - calculate and setup high low water marks 4287 */ 4288 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 4289 { 4290 struct ixgbe_hw *hw = &adapter->hw; 4291 int num_tc = netdev_get_num_tc(adapter->netdev); 4292 int i; 4293 4294 if (!num_tc) 4295 num_tc = 1; 4296 4297 for (i = 0; i < num_tc; i++) { 4298 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 4299 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 4300 4301 /* Low water marks must not be larger than high water marks */ 4302 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 4303 hw->fc.low_water[i] = 0; 4304 } 4305 4306 for (; i < MAX_TRAFFIC_CLASS; i++) 4307 hw->fc.high_water[i] = 0; 4308 } 4309 4310 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 4311 { 4312 struct ixgbe_hw *hw = &adapter->hw; 4313 int hdrm; 4314 u8 tc = netdev_get_num_tc(adapter->netdev); 4315 4316 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 4317 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 4318 hdrm = 32 << adapter->fdir_pballoc; 4319 else 4320 hdrm = 0; 4321 4322 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 4323 ixgbe_pbthresh_setup(adapter); 4324 } 4325 4326 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 4327 { 4328 struct ixgbe_hw *hw = &adapter->hw; 4329 struct hlist_node *node2; 4330 struct ixgbe_fdir_filter *filter; 4331 4332 spin_lock(&adapter->fdir_perfect_lock); 4333 4334 if (!hlist_empty(&adapter->fdir_filter_list)) 4335 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 4336 4337 hlist_for_each_entry_safe(filter, node2, 4338 &adapter->fdir_filter_list, fdir_node) { 4339 ixgbe_fdir_write_perfect_filter_82599(hw, 4340 &filter->filter, 4341 filter->sw_idx, 4342 (filter->action == IXGBE_FDIR_DROP_QUEUE) ? 4343 IXGBE_FDIR_DROP_QUEUE : 4344 adapter->rx_ring[filter->action]->reg_idx); 4345 } 4346 4347 spin_unlock(&adapter->fdir_perfect_lock); 4348 } 4349 4350 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool, 4351 struct ixgbe_adapter *adapter) 4352 { 4353 struct ixgbe_hw *hw = &adapter->hw; 4354 u32 vmolr; 4355 4356 /* No unicast promiscuous support for VMDQ devices. */ 4357 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool)); 4358 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE); 4359 4360 /* clear the affected bit */ 4361 vmolr &= ~IXGBE_VMOLR_MPE; 4362 4363 if (dev->flags & IFF_ALLMULTI) { 4364 vmolr |= IXGBE_VMOLR_MPE; 4365 } else { 4366 vmolr |= IXGBE_VMOLR_ROMPE; 4367 hw->mac.ops.update_mc_addr_list(hw, dev); 4368 } 4369 ixgbe_write_uc_addr_list(adapter->netdev, pool); 4370 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr); 4371 } 4372 4373 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter) 4374 { 4375 struct ixgbe_adapter *adapter = vadapter->real_adapter; 4376 int rss_i = adapter->num_rx_queues_per_pool; 4377 struct ixgbe_hw *hw = &adapter->hw; 4378 u16 pool = vadapter->pool; 4379 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4380 IXGBE_PSRTYPE_UDPHDR | 4381 IXGBE_PSRTYPE_IPV4HDR | 4382 IXGBE_PSRTYPE_L2HDR | 4383 IXGBE_PSRTYPE_IPV6HDR; 4384 4385 if (hw->mac.type == ixgbe_mac_82598EB) 4386 return; 4387 4388 if (rss_i > 3) 4389 psrtype |= 2 << 29; 4390 else if (rss_i > 1) 4391 psrtype |= 1 << 29; 4392 4393 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4394 } 4395 4396 /** 4397 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 4398 * @rx_ring: ring to free buffers from 4399 **/ 4400 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 4401 { 4402 struct device *dev = rx_ring->dev; 4403 unsigned long size; 4404 u16 i; 4405 4406 /* ring already cleared, nothing to do */ 4407 if (!rx_ring->rx_buffer_info) 4408 return; 4409 4410 /* Free all the Rx ring sk_buffs */ 4411 for (i = 0; i < rx_ring->count; i++) { 4412 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 4413 4414 if (rx_buffer->skb) { 4415 struct sk_buff *skb = rx_buffer->skb; 4416 if (IXGBE_CB(skb)->page_released) 4417 dma_unmap_page(dev, 4418 IXGBE_CB(skb)->dma, 4419 ixgbe_rx_bufsz(rx_ring), 4420 DMA_FROM_DEVICE); 4421 dev_kfree_skb(skb); 4422 rx_buffer->skb = NULL; 4423 } 4424 4425 if (!rx_buffer->page) 4426 continue; 4427 4428 dma_unmap_page(dev, rx_buffer->dma, 4429 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 4430 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring)); 4431 4432 rx_buffer->page = NULL; 4433 } 4434 4435 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 4436 memset(rx_ring->rx_buffer_info, 0, size); 4437 4438 /* Zero out the descriptor ring */ 4439 memset(rx_ring->desc, 0, rx_ring->size); 4440 4441 rx_ring->next_to_alloc = 0; 4442 rx_ring->next_to_clean = 0; 4443 rx_ring->next_to_use = 0; 4444 } 4445 4446 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter, 4447 struct ixgbe_ring *rx_ring) 4448 { 4449 struct ixgbe_adapter *adapter = vadapter->real_adapter; 4450 int index = rx_ring->queue_index + vadapter->rx_base_queue; 4451 4452 /* shutdown specific queue receive and wait for dma to settle */ 4453 ixgbe_disable_rx_queue(adapter, rx_ring); 4454 usleep_range(10000, 20000); 4455 ixgbe_irq_disable_queues(adapter, ((u64)1 << index)); 4456 ixgbe_clean_rx_ring(rx_ring); 4457 rx_ring->l2_accel_priv = NULL; 4458 } 4459 4460 static int ixgbe_fwd_ring_down(struct net_device *vdev, 4461 struct ixgbe_fwd_adapter *accel) 4462 { 4463 struct ixgbe_adapter *adapter = accel->real_adapter; 4464 unsigned int rxbase = accel->rx_base_queue; 4465 unsigned int txbase = accel->tx_base_queue; 4466 int i; 4467 4468 netif_tx_stop_all_queues(vdev); 4469 4470 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4471 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 4472 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev; 4473 } 4474 4475 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4476 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL; 4477 adapter->tx_ring[txbase + i]->netdev = adapter->netdev; 4478 } 4479 4480 4481 return 0; 4482 } 4483 4484 static int ixgbe_fwd_ring_up(struct net_device *vdev, 4485 struct ixgbe_fwd_adapter *accel) 4486 { 4487 struct ixgbe_adapter *adapter = accel->real_adapter; 4488 unsigned int rxbase, txbase, queues; 4489 int i, baseq, err = 0; 4490 4491 if (!test_bit(accel->pool, &adapter->fwd_bitmask)) 4492 return 0; 4493 4494 baseq = accel->pool * adapter->num_rx_queues_per_pool; 4495 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 4496 accel->pool, adapter->num_rx_pools, 4497 baseq, baseq + adapter->num_rx_queues_per_pool, 4498 adapter->fwd_bitmask); 4499 4500 accel->netdev = vdev; 4501 accel->rx_base_queue = rxbase = baseq; 4502 accel->tx_base_queue = txbase = baseq; 4503 4504 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 4505 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 4506 4507 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4508 adapter->rx_ring[rxbase + i]->netdev = vdev; 4509 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel; 4510 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]); 4511 } 4512 4513 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4514 adapter->tx_ring[txbase + i]->netdev = vdev; 4515 adapter->tx_ring[txbase + i]->l2_accel_priv = accel; 4516 } 4517 4518 queues = min_t(unsigned int, 4519 adapter->num_rx_queues_per_pool, vdev->num_tx_queues); 4520 err = netif_set_real_num_tx_queues(vdev, queues); 4521 if (err) 4522 goto fwd_queue_err; 4523 4524 err = netif_set_real_num_rx_queues(vdev, queues); 4525 if (err) 4526 goto fwd_queue_err; 4527 4528 if (is_valid_ether_addr(vdev->dev_addr)) 4529 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool); 4530 4531 ixgbe_fwd_psrtype(accel); 4532 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter); 4533 return err; 4534 fwd_queue_err: 4535 ixgbe_fwd_ring_down(vdev, accel); 4536 return err; 4537 } 4538 4539 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 4540 { 4541 struct net_device *upper; 4542 struct list_head *iter; 4543 int err; 4544 4545 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 4546 if (netif_is_macvlan(upper)) { 4547 struct macvlan_dev *dfwd = netdev_priv(upper); 4548 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 4549 4550 if (dfwd->fwd_priv) { 4551 err = ixgbe_fwd_ring_up(upper, vadapter); 4552 if (err) 4553 continue; 4554 } 4555 } 4556 } 4557 } 4558 4559 static void ixgbe_configure(struct ixgbe_adapter *adapter) 4560 { 4561 struct ixgbe_hw *hw = &adapter->hw; 4562 4563 ixgbe_configure_pb(adapter); 4564 #ifdef CONFIG_IXGBE_DCB 4565 ixgbe_configure_dcb(adapter); 4566 #endif 4567 /* 4568 * We must restore virtualization before VLANs or else 4569 * the VLVF registers will not be populated 4570 */ 4571 ixgbe_configure_virtualization(adapter); 4572 4573 ixgbe_set_rx_mode(adapter->netdev); 4574 ixgbe_restore_vlan(adapter); 4575 4576 switch (hw->mac.type) { 4577 case ixgbe_mac_82599EB: 4578 case ixgbe_mac_X540: 4579 hw->mac.ops.disable_rx_buff(hw); 4580 break; 4581 default: 4582 break; 4583 } 4584 4585 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 4586 ixgbe_init_fdir_signature_82599(&adapter->hw, 4587 adapter->fdir_pballoc); 4588 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 4589 ixgbe_init_fdir_perfect_82599(&adapter->hw, 4590 adapter->fdir_pballoc); 4591 ixgbe_fdir_filter_restore(adapter); 4592 } 4593 4594 switch (hw->mac.type) { 4595 case ixgbe_mac_82599EB: 4596 case ixgbe_mac_X540: 4597 hw->mac.ops.enable_rx_buff(hw); 4598 break; 4599 default: 4600 break; 4601 } 4602 4603 #ifdef IXGBE_FCOE 4604 /* configure FCoE L2 filters, redirection table, and Rx control */ 4605 ixgbe_configure_fcoe(adapter); 4606 4607 #endif /* IXGBE_FCOE */ 4608 ixgbe_configure_tx(adapter); 4609 ixgbe_configure_rx(adapter); 4610 ixgbe_configure_dfwd(adapter); 4611 } 4612 4613 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 4614 { 4615 switch (hw->phy.type) { 4616 case ixgbe_phy_sfp_avago: 4617 case ixgbe_phy_sfp_ftl: 4618 case ixgbe_phy_sfp_intel: 4619 case ixgbe_phy_sfp_unknown: 4620 case ixgbe_phy_sfp_passive_tyco: 4621 case ixgbe_phy_sfp_passive_unknown: 4622 case ixgbe_phy_sfp_active_unknown: 4623 case ixgbe_phy_sfp_ftl_active: 4624 case ixgbe_phy_qsfp_passive_unknown: 4625 case ixgbe_phy_qsfp_active_unknown: 4626 case ixgbe_phy_qsfp_intel: 4627 case ixgbe_phy_qsfp_unknown: 4628 /* ixgbe_phy_none is set when no SFP module is present */ 4629 case ixgbe_phy_none: 4630 return true; 4631 case ixgbe_phy_nl: 4632 if (hw->mac.type == ixgbe_mac_82598EB) 4633 return true; 4634 default: 4635 return false; 4636 } 4637 } 4638 4639 /** 4640 * ixgbe_sfp_link_config - set up SFP+ link 4641 * @adapter: pointer to private adapter struct 4642 **/ 4643 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 4644 { 4645 /* 4646 * We are assuming the worst case scenario here, and that 4647 * is that an SFP was inserted/removed after the reset 4648 * but before SFP detection was enabled. As such the best 4649 * solution is to just start searching as soon as we start 4650 */ 4651 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 4652 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 4653 4654 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 4655 } 4656 4657 /** 4658 * ixgbe_non_sfp_link_config - set up non-SFP+ link 4659 * @hw: pointer to private hardware struct 4660 * 4661 * Returns 0 on success, negative on failure 4662 **/ 4663 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 4664 { 4665 u32 speed; 4666 bool autoneg, link_up = false; 4667 u32 ret = IXGBE_ERR_LINK_SETUP; 4668 4669 if (hw->mac.ops.check_link) 4670 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 4671 4672 if (ret) 4673 return ret; 4674 4675 speed = hw->phy.autoneg_advertised; 4676 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 4677 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 4678 &autoneg); 4679 if (ret) 4680 return ret; 4681 4682 if (hw->mac.ops.setup_link) 4683 ret = hw->mac.ops.setup_link(hw, speed, link_up); 4684 4685 return ret; 4686 } 4687 4688 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 4689 { 4690 struct ixgbe_hw *hw = &adapter->hw; 4691 u32 gpie = 0; 4692 4693 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 4694 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 4695 IXGBE_GPIE_OCD; 4696 gpie |= IXGBE_GPIE_EIAME; 4697 /* 4698 * use EIAM to auto-mask when MSI-X interrupt is asserted 4699 * this saves a register write for every interrupt 4700 */ 4701 switch (hw->mac.type) { 4702 case ixgbe_mac_82598EB: 4703 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 4704 break; 4705 case ixgbe_mac_82599EB: 4706 case ixgbe_mac_X540: 4707 case ixgbe_mac_X550: 4708 case ixgbe_mac_X550EM_x: 4709 default: 4710 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 4711 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 4712 break; 4713 } 4714 } else { 4715 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 4716 * specifically only auto mask tx and rx interrupts */ 4717 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 4718 } 4719 4720 /* XXX: to interrupt immediately for EICS writes, enable this */ 4721 /* gpie |= IXGBE_GPIE_EIMEN; */ 4722 4723 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 4724 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 4725 4726 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4727 case IXGBE_82599_VMDQ_8Q_MASK: 4728 gpie |= IXGBE_GPIE_VTMODE_16; 4729 break; 4730 case IXGBE_82599_VMDQ_4Q_MASK: 4731 gpie |= IXGBE_GPIE_VTMODE_32; 4732 break; 4733 default: 4734 gpie |= IXGBE_GPIE_VTMODE_64; 4735 break; 4736 } 4737 } 4738 4739 /* Enable Thermal over heat sensor interrupt */ 4740 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 4741 switch (adapter->hw.mac.type) { 4742 case ixgbe_mac_82599EB: 4743 gpie |= IXGBE_SDP0_GPIEN; 4744 break; 4745 case ixgbe_mac_X540: 4746 gpie |= IXGBE_EIMS_TS; 4747 break; 4748 default: 4749 break; 4750 } 4751 } 4752 4753 /* Enable fan failure interrupt */ 4754 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 4755 gpie |= IXGBE_SDP1_GPIEN; 4756 4757 if (hw->mac.type == ixgbe_mac_82599EB) { 4758 gpie |= IXGBE_SDP1_GPIEN; 4759 gpie |= IXGBE_SDP2_GPIEN; 4760 } 4761 4762 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 4763 } 4764 4765 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 4766 { 4767 struct ixgbe_hw *hw = &adapter->hw; 4768 int err; 4769 u32 ctrl_ext; 4770 4771 ixgbe_get_hw_control(adapter); 4772 ixgbe_setup_gpie(adapter); 4773 4774 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 4775 ixgbe_configure_msix(adapter); 4776 else 4777 ixgbe_configure_msi_and_legacy(adapter); 4778 4779 /* enable the optics for 82599 SFP+ fiber */ 4780 if (hw->mac.ops.enable_tx_laser) 4781 hw->mac.ops.enable_tx_laser(hw); 4782 4783 smp_mb__before_atomic(); 4784 clear_bit(__IXGBE_DOWN, &adapter->state); 4785 ixgbe_napi_enable_all(adapter); 4786 4787 if (ixgbe_is_sfp(hw)) { 4788 ixgbe_sfp_link_config(adapter); 4789 } else { 4790 err = ixgbe_non_sfp_link_config(hw); 4791 if (err) 4792 e_err(probe, "link_config FAILED %d\n", err); 4793 } 4794 4795 /* clear any pending interrupts, may auto mask */ 4796 IXGBE_READ_REG(hw, IXGBE_EICR); 4797 ixgbe_irq_enable(adapter, true, true); 4798 4799 /* 4800 * If this adapter has a fan, check to see if we had a failure 4801 * before we enabled the interrupt. 4802 */ 4803 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 4804 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4805 if (esdp & IXGBE_ESDP_SDP1) 4806 e_crit(drv, "Fan has stopped, replace the adapter\n"); 4807 } 4808 4809 /* bring the link up in the watchdog, this could race with our first 4810 * link up interrupt but shouldn't be a problem */ 4811 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4812 adapter->link_check_timeout = jiffies; 4813 mod_timer(&adapter->service_timer, jiffies); 4814 4815 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 4816 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 4817 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 4818 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 4819 } 4820 4821 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 4822 { 4823 WARN_ON(in_interrupt()); 4824 /* put off any impending NetWatchDogTimeout */ 4825 adapter->netdev->trans_start = jiffies; 4826 4827 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 4828 usleep_range(1000, 2000); 4829 ixgbe_down(adapter); 4830 /* 4831 * If SR-IOV enabled then wait a bit before bringing the adapter 4832 * back up to give the VFs time to respond to the reset. The 4833 * two second wait is based upon the watchdog timer cycle in 4834 * the VF driver. 4835 */ 4836 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4837 msleep(2000); 4838 ixgbe_up(adapter); 4839 clear_bit(__IXGBE_RESETTING, &adapter->state); 4840 } 4841 4842 void ixgbe_up(struct ixgbe_adapter *adapter) 4843 { 4844 /* hardware has been reset, we need to reload some things */ 4845 ixgbe_configure(adapter); 4846 4847 ixgbe_up_complete(adapter); 4848 } 4849 4850 void ixgbe_reset(struct ixgbe_adapter *adapter) 4851 { 4852 struct ixgbe_hw *hw = &adapter->hw; 4853 struct net_device *netdev = adapter->netdev; 4854 int err; 4855 u8 old_addr[ETH_ALEN]; 4856 4857 if (ixgbe_removed(hw->hw_addr)) 4858 return; 4859 /* lock SFP init bit to prevent race conditions with the watchdog */ 4860 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 4861 usleep_range(1000, 2000); 4862 4863 /* clear all SFP and link config related flags while holding SFP_INIT */ 4864 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 4865 IXGBE_FLAG2_SFP_NEEDS_RESET); 4866 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 4867 4868 err = hw->mac.ops.init_hw(hw); 4869 switch (err) { 4870 case 0: 4871 case IXGBE_ERR_SFP_NOT_PRESENT: 4872 case IXGBE_ERR_SFP_NOT_SUPPORTED: 4873 break; 4874 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 4875 e_dev_err("master disable timed out\n"); 4876 break; 4877 case IXGBE_ERR_EEPROM_VERSION: 4878 /* We are running on a pre-production device, log a warning */ 4879 e_dev_warn("This device is a pre-production adapter/LOM. " 4880 "Please be aware there may be issues associated with " 4881 "your hardware. If you are experiencing problems " 4882 "please contact your Intel or hardware " 4883 "representative who provided you with this " 4884 "hardware.\n"); 4885 break; 4886 default: 4887 e_dev_err("Hardware Error: %d\n", err); 4888 } 4889 4890 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 4891 /* do not flush user set addresses */ 4892 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len); 4893 ixgbe_flush_sw_mac_table(adapter); 4894 ixgbe_mac_set_default_filter(adapter, old_addr); 4895 4896 /* update SAN MAC vmdq pool selection */ 4897 if (hw->mac.san_mac_rar_index) 4898 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 4899 4900 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 4901 ixgbe_ptp_reset(adapter); 4902 } 4903 4904 /** 4905 * ixgbe_clean_tx_ring - Free Tx Buffers 4906 * @tx_ring: ring to be cleaned 4907 **/ 4908 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 4909 { 4910 struct ixgbe_tx_buffer *tx_buffer_info; 4911 unsigned long size; 4912 u16 i; 4913 4914 /* ring already cleared, nothing to do */ 4915 if (!tx_ring->tx_buffer_info) 4916 return; 4917 4918 /* Free all the Tx ring sk_buffs */ 4919 for (i = 0; i < tx_ring->count; i++) { 4920 tx_buffer_info = &tx_ring->tx_buffer_info[i]; 4921 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); 4922 } 4923 4924 netdev_tx_reset_queue(txring_txq(tx_ring)); 4925 4926 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 4927 memset(tx_ring->tx_buffer_info, 0, size); 4928 4929 /* Zero out the descriptor ring */ 4930 memset(tx_ring->desc, 0, tx_ring->size); 4931 4932 tx_ring->next_to_use = 0; 4933 tx_ring->next_to_clean = 0; 4934 } 4935 4936 /** 4937 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 4938 * @adapter: board private structure 4939 **/ 4940 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 4941 { 4942 int i; 4943 4944 for (i = 0; i < adapter->num_rx_queues; i++) 4945 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 4946 } 4947 4948 /** 4949 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 4950 * @adapter: board private structure 4951 **/ 4952 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 4953 { 4954 int i; 4955 4956 for (i = 0; i < adapter->num_tx_queues; i++) 4957 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 4958 } 4959 4960 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 4961 { 4962 struct hlist_node *node2; 4963 struct ixgbe_fdir_filter *filter; 4964 4965 spin_lock(&adapter->fdir_perfect_lock); 4966 4967 hlist_for_each_entry_safe(filter, node2, 4968 &adapter->fdir_filter_list, fdir_node) { 4969 hlist_del(&filter->fdir_node); 4970 kfree(filter); 4971 } 4972 adapter->fdir_filter_count = 0; 4973 4974 spin_unlock(&adapter->fdir_perfect_lock); 4975 } 4976 4977 void ixgbe_down(struct ixgbe_adapter *adapter) 4978 { 4979 struct net_device *netdev = adapter->netdev; 4980 struct ixgbe_hw *hw = &adapter->hw; 4981 struct net_device *upper; 4982 struct list_head *iter; 4983 u32 rxctrl; 4984 int i; 4985 4986 /* signal that we are down to the interrupt handler */ 4987 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 4988 return; /* do nothing if already down */ 4989 4990 /* disable receives */ 4991 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4992 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); 4993 4994 /* disable all enabled rx queues */ 4995 for (i = 0; i < adapter->num_rx_queues; i++) 4996 /* this call also flushes the previous write */ 4997 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); 4998 4999 usleep_range(10000, 20000); 5000 5001 netif_tx_stop_all_queues(netdev); 5002 5003 /* call carrier off first to avoid false dev_watchdog timeouts */ 5004 netif_carrier_off(netdev); 5005 netif_tx_disable(netdev); 5006 5007 /* disable any upper devices */ 5008 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 5009 if (netif_is_macvlan(upper)) { 5010 struct macvlan_dev *vlan = netdev_priv(upper); 5011 5012 if (vlan->fwd_priv) { 5013 netif_tx_stop_all_queues(upper); 5014 netif_carrier_off(upper); 5015 netif_tx_disable(upper); 5016 } 5017 } 5018 } 5019 5020 ixgbe_irq_disable(adapter); 5021 5022 ixgbe_napi_disable_all(adapter); 5023 5024 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT | 5025 IXGBE_FLAG2_RESET_REQUESTED); 5026 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 5027 5028 del_timer_sync(&adapter->service_timer); 5029 5030 if (adapter->num_vfs) { 5031 /* Clear EITR Select mapping */ 5032 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 5033 5034 /* Mark all the VFs as inactive */ 5035 for (i = 0 ; i < adapter->num_vfs; i++) 5036 adapter->vfinfo[i].clear_to_send = false; 5037 5038 /* ping all the active vfs to let them know we are going down */ 5039 ixgbe_ping_all_vfs(adapter); 5040 5041 /* Disable all VFTE/VFRE TX/RX */ 5042 ixgbe_disable_tx_rx(adapter); 5043 } 5044 5045 /* disable transmits in the hardware now that interrupts are off */ 5046 for (i = 0; i < adapter->num_tx_queues; i++) { 5047 u8 reg_idx = adapter->tx_ring[i]->reg_idx; 5048 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5049 } 5050 5051 /* Disable the Tx DMA engine on 82599 and later MAC */ 5052 switch (hw->mac.type) { 5053 case ixgbe_mac_82599EB: 5054 case ixgbe_mac_X540: 5055 case ixgbe_mac_X550: 5056 case ixgbe_mac_X550EM_x: 5057 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5058 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5059 ~IXGBE_DMATXCTL_TE)); 5060 break; 5061 default: 5062 break; 5063 } 5064 5065 if (!pci_channel_offline(adapter->pdev)) 5066 ixgbe_reset(adapter); 5067 5068 /* power down the optics for 82599 SFP+ fiber */ 5069 if (hw->mac.ops.disable_tx_laser) 5070 hw->mac.ops.disable_tx_laser(hw); 5071 5072 ixgbe_clean_all_tx_rings(adapter); 5073 ixgbe_clean_all_rx_rings(adapter); 5074 5075 #ifdef CONFIG_IXGBE_DCA 5076 /* since we reset the hardware DCA settings were cleared */ 5077 ixgbe_setup_dca(adapter); 5078 #endif 5079 } 5080 5081 /** 5082 * ixgbe_tx_timeout - Respond to a Tx Hang 5083 * @netdev: network interface device structure 5084 **/ 5085 static void ixgbe_tx_timeout(struct net_device *netdev) 5086 { 5087 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5088 5089 /* Do the reset outside of interrupt context */ 5090 ixgbe_tx_timeout_reset(adapter); 5091 } 5092 5093 /** 5094 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 5095 * @adapter: board private structure to initialize 5096 * 5097 * ixgbe_sw_init initializes the Adapter private data structure. 5098 * Fields are initialized based on PCI device information and 5099 * OS network device settings (MTU size). 5100 **/ 5101 static int ixgbe_sw_init(struct ixgbe_adapter *adapter) 5102 { 5103 struct ixgbe_hw *hw = &adapter->hw; 5104 struct pci_dev *pdev = adapter->pdev; 5105 unsigned int rss, fdir; 5106 u32 fwsm; 5107 #ifdef CONFIG_IXGBE_DCB 5108 int j; 5109 struct tc_configuration *tc; 5110 #endif 5111 5112 /* PCI config space info */ 5113 5114 hw->vendor_id = pdev->vendor; 5115 hw->device_id = pdev->device; 5116 hw->revision_id = pdev->revision; 5117 hw->subsystem_vendor_id = pdev->subsystem_vendor; 5118 hw->subsystem_device_id = pdev->subsystem_device; 5119 5120 /* Set common capability flags and settings */ 5121 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 5122 adapter->ring_feature[RING_F_RSS].limit = rss; 5123 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 5124 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 5125 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 5126 adapter->atr_sample_rate = 20; 5127 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 5128 adapter->ring_feature[RING_F_FDIR].limit = fdir; 5129 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 5130 #ifdef CONFIG_IXGBE_DCA 5131 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 5132 #endif 5133 #ifdef IXGBE_FCOE 5134 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 5135 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 5136 #ifdef CONFIG_IXGBE_DCB 5137 /* Default traffic class to use for FCoE */ 5138 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 5139 #endif /* CONFIG_IXGBE_DCB */ 5140 #endif /* IXGBE_FCOE */ 5141 5142 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) * 5143 hw->mac.num_rar_entries, 5144 GFP_ATOMIC); 5145 5146 /* Set MAC specific capability flags and exceptions */ 5147 switch (hw->mac.type) { 5148 case ixgbe_mac_82598EB: 5149 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 5150 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 5151 5152 if (hw->device_id == IXGBE_DEV_ID_82598AT) 5153 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 5154 5155 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 5156 adapter->ring_feature[RING_F_FDIR].limit = 0; 5157 adapter->atr_sample_rate = 0; 5158 adapter->fdir_pballoc = 0; 5159 #ifdef IXGBE_FCOE 5160 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 5161 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 5162 #ifdef CONFIG_IXGBE_DCB 5163 adapter->fcoe.up = 0; 5164 #endif /* IXGBE_DCB */ 5165 #endif /* IXGBE_FCOE */ 5166 break; 5167 case ixgbe_mac_82599EB: 5168 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 5169 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 5170 break; 5171 case ixgbe_mac_X540: 5172 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM); 5173 if (fwsm & IXGBE_FWSM_TS_ENABLED) 5174 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 5175 break; 5176 case ixgbe_mac_X550EM_x: 5177 case ixgbe_mac_X550: 5178 #ifdef CONFIG_IXGBE_DCA 5179 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 5180 #endif 5181 break; 5182 default: 5183 break; 5184 } 5185 5186 #ifdef IXGBE_FCOE 5187 /* FCoE support exists, always init the FCoE lock */ 5188 spin_lock_init(&adapter->fcoe.lock); 5189 5190 #endif 5191 /* n-tuple support exists, always init our spinlock */ 5192 spin_lock_init(&adapter->fdir_perfect_lock); 5193 5194 #ifdef CONFIG_IXGBE_DCB 5195 switch (hw->mac.type) { 5196 case ixgbe_mac_X540: 5197 case ixgbe_mac_X550: 5198 case ixgbe_mac_X550EM_x: 5199 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 5200 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 5201 break; 5202 default: 5203 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 5204 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 5205 break; 5206 } 5207 5208 /* Configure DCB traffic classes */ 5209 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 5210 tc = &adapter->dcb_cfg.tc_config[j]; 5211 tc->path[DCB_TX_CONFIG].bwg_id = 0; 5212 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 5213 tc->path[DCB_RX_CONFIG].bwg_id = 0; 5214 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 5215 tc->dcb_pfc = pfc_disabled; 5216 } 5217 5218 /* Initialize default user to priority mapping, UPx->TC0 */ 5219 tc = &adapter->dcb_cfg.tc_config[0]; 5220 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 5221 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 5222 5223 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 5224 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 5225 adapter->dcb_cfg.pfc_mode_enable = false; 5226 adapter->dcb_set_bitmap = 0x00; 5227 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 5228 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 5229 sizeof(adapter->temp_dcb_cfg)); 5230 5231 #endif 5232 5233 /* default flow control settings */ 5234 hw->fc.requested_mode = ixgbe_fc_full; 5235 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 5236 ixgbe_pbthresh_setup(adapter); 5237 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 5238 hw->fc.send_xon = true; 5239 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 5240 5241 #ifdef CONFIG_PCI_IOV 5242 if (max_vfs > 0) 5243 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 5244 5245 /* assign number of SR-IOV VFs */ 5246 if (hw->mac.type != ixgbe_mac_82598EB) { 5247 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 5248 adapter->num_vfs = 0; 5249 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 5250 } else { 5251 adapter->num_vfs = max_vfs; 5252 } 5253 } 5254 #endif /* CONFIG_PCI_IOV */ 5255 5256 /* enable itr by default in dynamic mode */ 5257 adapter->rx_itr_setting = 1; 5258 adapter->tx_itr_setting = 1; 5259 5260 /* set default ring sizes */ 5261 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 5262 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 5263 5264 /* set default work limits */ 5265 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 5266 5267 /* initialize eeprom parameters */ 5268 if (ixgbe_init_eeprom_params_generic(hw)) { 5269 e_dev_err("EEPROM initialization failed\n"); 5270 return -EIO; 5271 } 5272 5273 /* PF holds first pool slot */ 5274 set_bit(0, &adapter->fwd_bitmask); 5275 set_bit(__IXGBE_DOWN, &adapter->state); 5276 5277 return 0; 5278 } 5279 5280 /** 5281 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 5282 * @tx_ring: tx descriptor ring (for a specific queue) to setup 5283 * 5284 * Return 0 on success, negative on failure 5285 **/ 5286 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 5287 { 5288 struct device *dev = tx_ring->dev; 5289 int orig_node = dev_to_node(dev); 5290 int ring_node = -1; 5291 int size; 5292 5293 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 5294 5295 if (tx_ring->q_vector) 5296 ring_node = tx_ring->q_vector->numa_node; 5297 5298 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node); 5299 if (!tx_ring->tx_buffer_info) 5300 tx_ring->tx_buffer_info = vzalloc(size); 5301 if (!tx_ring->tx_buffer_info) 5302 goto err; 5303 5304 u64_stats_init(&tx_ring->syncp); 5305 5306 /* round up to nearest 4K */ 5307 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 5308 tx_ring->size = ALIGN(tx_ring->size, 4096); 5309 5310 set_dev_node(dev, ring_node); 5311 tx_ring->desc = dma_alloc_coherent(dev, 5312 tx_ring->size, 5313 &tx_ring->dma, 5314 GFP_KERNEL); 5315 set_dev_node(dev, orig_node); 5316 if (!tx_ring->desc) 5317 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 5318 &tx_ring->dma, GFP_KERNEL); 5319 if (!tx_ring->desc) 5320 goto err; 5321 5322 tx_ring->next_to_use = 0; 5323 tx_ring->next_to_clean = 0; 5324 return 0; 5325 5326 err: 5327 vfree(tx_ring->tx_buffer_info); 5328 tx_ring->tx_buffer_info = NULL; 5329 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 5330 return -ENOMEM; 5331 } 5332 5333 /** 5334 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 5335 * @adapter: board private structure 5336 * 5337 * If this function returns with an error, then it's possible one or 5338 * more of the rings is populated (while the rest are not). It is the 5339 * callers duty to clean those orphaned rings. 5340 * 5341 * Return 0 on success, negative on failure 5342 **/ 5343 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 5344 { 5345 int i, err = 0; 5346 5347 for (i = 0; i < adapter->num_tx_queues; i++) { 5348 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 5349 if (!err) 5350 continue; 5351 5352 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 5353 goto err_setup_tx; 5354 } 5355 5356 return 0; 5357 err_setup_tx: 5358 /* rewind the index freeing the rings as we go */ 5359 while (i--) 5360 ixgbe_free_tx_resources(adapter->tx_ring[i]); 5361 return err; 5362 } 5363 5364 /** 5365 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 5366 * @rx_ring: rx descriptor ring (for a specific queue) to setup 5367 * 5368 * Returns 0 on success, negative on failure 5369 **/ 5370 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) 5371 { 5372 struct device *dev = rx_ring->dev; 5373 int orig_node = dev_to_node(dev); 5374 int ring_node = -1; 5375 int size; 5376 5377 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 5378 5379 if (rx_ring->q_vector) 5380 ring_node = rx_ring->q_vector->numa_node; 5381 5382 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node); 5383 if (!rx_ring->rx_buffer_info) 5384 rx_ring->rx_buffer_info = vzalloc(size); 5385 if (!rx_ring->rx_buffer_info) 5386 goto err; 5387 5388 u64_stats_init(&rx_ring->syncp); 5389 5390 /* Round up to nearest 4K */ 5391 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 5392 rx_ring->size = ALIGN(rx_ring->size, 4096); 5393 5394 set_dev_node(dev, ring_node); 5395 rx_ring->desc = dma_alloc_coherent(dev, 5396 rx_ring->size, 5397 &rx_ring->dma, 5398 GFP_KERNEL); 5399 set_dev_node(dev, orig_node); 5400 if (!rx_ring->desc) 5401 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 5402 &rx_ring->dma, GFP_KERNEL); 5403 if (!rx_ring->desc) 5404 goto err; 5405 5406 rx_ring->next_to_clean = 0; 5407 rx_ring->next_to_use = 0; 5408 5409 return 0; 5410 err: 5411 vfree(rx_ring->rx_buffer_info); 5412 rx_ring->rx_buffer_info = NULL; 5413 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 5414 return -ENOMEM; 5415 } 5416 5417 /** 5418 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 5419 * @adapter: board private structure 5420 * 5421 * If this function returns with an error, then it's possible one or 5422 * more of the rings is populated (while the rest are not). It is the 5423 * callers duty to clean those orphaned rings. 5424 * 5425 * Return 0 on success, negative on failure 5426 **/ 5427 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 5428 { 5429 int i, err = 0; 5430 5431 for (i = 0; i < adapter->num_rx_queues; i++) { 5432 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); 5433 if (!err) 5434 continue; 5435 5436 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 5437 goto err_setup_rx; 5438 } 5439 5440 #ifdef IXGBE_FCOE 5441 err = ixgbe_setup_fcoe_ddp_resources(adapter); 5442 if (!err) 5443 #endif 5444 return 0; 5445 err_setup_rx: 5446 /* rewind the index freeing the rings as we go */ 5447 while (i--) 5448 ixgbe_free_rx_resources(adapter->rx_ring[i]); 5449 return err; 5450 } 5451 5452 /** 5453 * ixgbe_free_tx_resources - Free Tx Resources per Queue 5454 * @tx_ring: Tx descriptor ring for a specific queue 5455 * 5456 * Free all transmit software resources 5457 **/ 5458 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 5459 { 5460 ixgbe_clean_tx_ring(tx_ring); 5461 5462 vfree(tx_ring->tx_buffer_info); 5463 tx_ring->tx_buffer_info = NULL; 5464 5465 /* if not set, then don't free */ 5466 if (!tx_ring->desc) 5467 return; 5468 5469 dma_free_coherent(tx_ring->dev, tx_ring->size, 5470 tx_ring->desc, tx_ring->dma); 5471 5472 tx_ring->desc = NULL; 5473 } 5474 5475 /** 5476 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 5477 * @adapter: board private structure 5478 * 5479 * Free all transmit software resources 5480 **/ 5481 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 5482 { 5483 int i; 5484 5485 for (i = 0; i < adapter->num_tx_queues; i++) 5486 if (adapter->tx_ring[i]->desc) 5487 ixgbe_free_tx_resources(adapter->tx_ring[i]); 5488 } 5489 5490 /** 5491 * ixgbe_free_rx_resources - Free Rx Resources 5492 * @rx_ring: ring to clean the resources from 5493 * 5494 * Free all receive software resources 5495 **/ 5496 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 5497 { 5498 ixgbe_clean_rx_ring(rx_ring); 5499 5500 vfree(rx_ring->rx_buffer_info); 5501 rx_ring->rx_buffer_info = NULL; 5502 5503 /* if not set, then don't free */ 5504 if (!rx_ring->desc) 5505 return; 5506 5507 dma_free_coherent(rx_ring->dev, rx_ring->size, 5508 rx_ring->desc, rx_ring->dma); 5509 5510 rx_ring->desc = NULL; 5511 } 5512 5513 /** 5514 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 5515 * @adapter: board private structure 5516 * 5517 * Free all receive software resources 5518 **/ 5519 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 5520 { 5521 int i; 5522 5523 #ifdef IXGBE_FCOE 5524 ixgbe_free_fcoe_ddp_resources(adapter); 5525 5526 #endif 5527 for (i = 0; i < adapter->num_rx_queues; i++) 5528 if (adapter->rx_ring[i]->desc) 5529 ixgbe_free_rx_resources(adapter->rx_ring[i]); 5530 } 5531 5532 /** 5533 * ixgbe_change_mtu - Change the Maximum Transfer Unit 5534 * @netdev: network interface device structure 5535 * @new_mtu: new value for maximum frame size 5536 * 5537 * Returns 0 on success, negative on failure 5538 **/ 5539 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 5540 { 5541 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5542 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; 5543 5544 /* MTU < 68 is an error and causes problems on some kernels */ 5545 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) 5546 return -EINVAL; 5547 5548 /* 5549 * For 82599EB we cannot allow legacy VFs to enable their receive 5550 * paths when MTU greater than 1500 is configured. So display a 5551 * warning that legacy VFs will be disabled. 5552 */ 5553 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 5554 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 5555 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 5556 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 5557 5558 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 5559 5560 /* must set new MTU before calling down or up */ 5561 netdev->mtu = new_mtu; 5562 5563 if (netif_running(netdev)) 5564 ixgbe_reinit_locked(adapter); 5565 5566 return 0; 5567 } 5568 5569 /** 5570 * ixgbe_open - Called when a network interface is made active 5571 * @netdev: network interface device structure 5572 * 5573 * Returns 0 on success, negative value on failure 5574 * 5575 * The open entry point is called when a network interface is made 5576 * active by the system (IFF_UP). At this point all resources needed 5577 * for transmit and receive operations are allocated, the interrupt 5578 * handler is registered with the OS, the watchdog timer is started, 5579 * and the stack is notified that the interface is ready. 5580 **/ 5581 static int ixgbe_open(struct net_device *netdev) 5582 { 5583 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5584 int err, queues; 5585 5586 /* disallow open during test */ 5587 if (test_bit(__IXGBE_TESTING, &adapter->state)) 5588 return -EBUSY; 5589 5590 netif_carrier_off(netdev); 5591 5592 /* allocate transmit descriptors */ 5593 err = ixgbe_setup_all_tx_resources(adapter); 5594 if (err) 5595 goto err_setup_tx; 5596 5597 /* allocate receive descriptors */ 5598 err = ixgbe_setup_all_rx_resources(adapter); 5599 if (err) 5600 goto err_setup_rx; 5601 5602 ixgbe_configure(adapter); 5603 5604 err = ixgbe_request_irq(adapter); 5605 if (err) 5606 goto err_req_irq; 5607 5608 /* Notify the stack of the actual queue counts. */ 5609 if (adapter->num_rx_pools > 1) 5610 queues = adapter->num_rx_queues_per_pool; 5611 else 5612 queues = adapter->num_tx_queues; 5613 5614 err = netif_set_real_num_tx_queues(netdev, queues); 5615 if (err) 5616 goto err_set_queues; 5617 5618 if (adapter->num_rx_pools > 1 && 5619 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES) 5620 queues = IXGBE_MAX_L2A_QUEUES; 5621 else 5622 queues = adapter->num_rx_queues; 5623 err = netif_set_real_num_rx_queues(netdev, queues); 5624 if (err) 5625 goto err_set_queues; 5626 5627 ixgbe_ptp_init(adapter); 5628 5629 ixgbe_up_complete(adapter); 5630 5631 return 0; 5632 5633 err_set_queues: 5634 ixgbe_free_irq(adapter); 5635 err_req_irq: 5636 ixgbe_free_all_rx_resources(adapter); 5637 err_setup_rx: 5638 ixgbe_free_all_tx_resources(adapter); 5639 err_setup_tx: 5640 ixgbe_reset(adapter); 5641 5642 return err; 5643 } 5644 5645 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 5646 { 5647 ixgbe_ptp_suspend(adapter); 5648 5649 ixgbe_down(adapter); 5650 ixgbe_free_irq(adapter); 5651 5652 ixgbe_free_all_tx_resources(adapter); 5653 ixgbe_free_all_rx_resources(adapter); 5654 } 5655 5656 /** 5657 * ixgbe_close - Disables a network interface 5658 * @netdev: network interface device structure 5659 * 5660 * Returns 0, this is not allowed to fail 5661 * 5662 * The close entry point is called when an interface is de-activated 5663 * by the OS. The hardware is still under the drivers control, but 5664 * needs to be disabled. A global MAC reset is issued to stop the 5665 * hardware, and all transmit and receive resources are freed. 5666 **/ 5667 static int ixgbe_close(struct net_device *netdev) 5668 { 5669 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5670 5671 ixgbe_ptp_stop(adapter); 5672 5673 ixgbe_close_suspend(adapter); 5674 5675 ixgbe_fdir_filter_exit(adapter); 5676 5677 ixgbe_release_hw_control(adapter); 5678 5679 return 0; 5680 } 5681 5682 #ifdef CONFIG_PM 5683 static int ixgbe_resume(struct pci_dev *pdev) 5684 { 5685 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 5686 struct net_device *netdev = adapter->netdev; 5687 u32 err; 5688 5689 adapter->hw.hw_addr = adapter->io_addr; 5690 pci_set_power_state(pdev, PCI_D0); 5691 pci_restore_state(pdev); 5692 /* 5693 * pci_restore_state clears dev->state_saved so call 5694 * pci_save_state to restore it. 5695 */ 5696 pci_save_state(pdev); 5697 5698 err = pci_enable_device_mem(pdev); 5699 if (err) { 5700 e_dev_err("Cannot enable PCI device from suspend\n"); 5701 return err; 5702 } 5703 smp_mb__before_atomic(); 5704 clear_bit(__IXGBE_DISABLED, &adapter->state); 5705 pci_set_master(pdev); 5706 5707 pci_wake_from_d3(pdev, false); 5708 5709 ixgbe_reset(adapter); 5710 5711 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 5712 5713 rtnl_lock(); 5714 err = ixgbe_init_interrupt_scheme(adapter); 5715 if (!err && netif_running(netdev)) 5716 err = ixgbe_open(netdev); 5717 5718 rtnl_unlock(); 5719 5720 if (err) 5721 return err; 5722 5723 netif_device_attach(netdev); 5724 5725 return 0; 5726 } 5727 #endif /* CONFIG_PM */ 5728 5729 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 5730 { 5731 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 5732 struct net_device *netdev = adapter->netdev; 5733 struct ixgbe_hw *hw = &adapter->hw; 5734 u32 ctrl, fctrl; 5735 u32 wufc = adapter->wol; 5736 #ifdef CONFIG_PM 5737 int retval = 0; 5738 #endif 5739 5740 netif_device_detach(netdev); 5741 5742 rtnl_lock(); 5743 if (netif_running(netdev)) 5744 ixgbe_close_suspend(adapter); 5745 rtnl_unlock(); 5746 5747 ixgbe_clear_interrupt_scheme(adapter); 5748 5749 #ifdef CONFIG_PM 5750 retval = pci_save_state(pdev); 5751 if (retval) 5752 return retval; 5753 5754 #endif 5755 if (hw->mac.ops.stop_link_on_d3) 5756 hw->mac.ops.stop_link_on_d3(hw); 5757 5758 if (wufc) { 5759 ixgbe_set_rx_mode(netdev); 5760 5761 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 5762 if (hw->mac.ops.enable_tx_laser) 5763 hw->mac.ops.enable_tx_laser(hw); 5764 5765 /* turn on all-multi mode if wake on multicast is enabled */ 5766 if (wufc & IXGBE_WUFC_MC) { 5767 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 5768 fctrl |= IXGBE_FCTRL_MPE; 5769 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 5770 } 5771 5772 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 5773 ctrl |= IXGBE_CTRL_GIO_DIS; 5774 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 5775 5776 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 5777 } else { 5778 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 5779 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 5780 } 5781 5782 switch (hw->mac.type) { 5783 case ixgbe_mac_82598EB: 5784 pci_wake_from_d3(pdev, false); 5785 break; 5786 case ixgbe_mac_82599EB: 5787 case ixgbe_mac_X540: 5788 case ixgbe_mac_X550: 5789 case ixgbe_mac_X550EM_x: 5790 pci_wake_from_d3(pdev, !!wufc); 5791 break; 5792 default: 5793 break; 5794 } 5795 5796 *enable_wake = !!wufc; 5797 5798 ixgbe_release_hw_control(adapter); 5799 5800 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 5801 pci_disable_device(pdev); 5802 5803 return 0; 5804 } 5805 5806 #ifdef CONFIG_PM 5807 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 5808 { 5809 int retval; 5810 bool wake; 5811 5812 retval = __ixgbe_shutdown(pdev, &wake); 5813 if (retval) 5814 return retval; 5815 5816 if (wake) { 5817 pci_prepare_to_sleep(pdev); 5818 } else { 5819 pci_wake_from_d3(pdev, false); 5820 pci_set_power_state(pdev, PCI_D3hot); 5821 } 5822 5823 return 0; 5824 } 5825 #endif /* CONFIG_PM */ 5826 5827 static void ixgbe_shutdown(struct pci_dev *pdev) 5828 { 5829 bool wake; 5830 5831 __ixgbe_shutdown(pdev, &wake); 5832 5833 if (system_state == SYSTEM_POWER_OFF) { 5834 pci_wake_from_d3(pdev, wake); 5835 pci_set_power_state(pdev, PCI_D3hot); 5836 } 5837 } 5838 5839 /** 5840 * ixgbe_update_stats - Update the board statistics counters. 5841 * @adapter: board private structure 5842 **/ 5843 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 5844 { 5845 struct net_device *netdev = adapter->netdev; 5846 struct ixgbe_hw *hw = &adapter->hw; 5847 struct ixgbe_hw_stats *hwstats = &adapter->stats; 5848 u64 total_mpc = 0; 5849 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 5850 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 5851 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 5852 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 5853 5854 if (test_bit(__IXGBE_DOWN, &adapter->state) || 5855 test_bit(__IXGBE_RESETTING, &adapter->state)) 5856 return; 5857 5858 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 5859 u64 rsc_count = 0; 5860 u64 rsc_flush = 0; 5861 for (i = 0; i < adapter->num_rx_queues; i++) { 5862 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 5863 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 5864 } 5865 adapter->rsc_total_count = rsc_count; 5866 adapter->rsc_total_flush = rsc_flush; 5867 } 5868 5869 for (i = 0; i < adapter->num_rx_queues; i++) { 5870 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 5871 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 5872 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 5873 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 5874 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 5875 bytes += rx_ring->stats.bytes; 5876 packets += rx_ring->stats.packets; 5877 } 5878 adapter->non_eop_descs = non_eop_descs; 5879 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 5880 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 5881 adapter->hw_csum_rx_error = hw_csum_rx_error; 5882 netdev->stats.rx_bytes = bytes; 5883 netdev->stats.rx_packets = packets; 5884 5885 bytes = 0; 5886 packets = 0; 5887 /* gather some stats to the adapter struct that are per queue */ 5888 for (i = 0; i < adapter->num_tx_queues; i++) { 5889 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 5890 restart_queue += tx_ring->tx_stats.restart_queue; 5891 tx_busy += tx_ring->tx_stats.tx_busy; 5892 bytes += tx_ring->stats.bytes; 5893 packets += tx_ring->stats.packets; 5894 } 5895 adapter->restart_queue = restart_queue; 5896 adapter->tx_busy = tx_busy; 5897 netdev->stats.tx_bytes = bytes; 5898 netdev->stats.tx_packets = packets; 5899 5900 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 5901 5902 /* 8 register reads */ 5903 for (i = 0; i < 8; i++) { 5904 /* for packet buffers not used, the register should read 0 */ 5905 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 5906 missed_rx += mpc; 5907 hwstats->mpc[i] += mpc; 5908 total_mpc += hwstats->mpc[i]; 5909 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 5910 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 5911 switch (hw->mac.type) { 5912 case ixgbe_mac_82598EB: 5913 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 5914 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 5915 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 5916 hwstats->pxonrxc[i] += 5917 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 5918 break; 5919 case ixgbe_mac_82599EB: 5920 case ixgbe_mac_X540: 5921 case ixgbe_mac_X550: 5922 case ixgbe_mac_X550EM_x: 5923 hwstats->pxonrxc[i] += 5924 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 5925 break; 5926 default: 5927 break; 5928 } 5929 } 5930 5931 /*16 register reads */ 5932 for (i = 0; i < 16; i++) { 5933 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 5934 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 5935 if ((hw->mac.type == ixgbe_mac_82599EB) || 5936 (hw->mac.type == ixgbe_mac_X540) || 5937 (hw->mac.type == ixgbe_mac_X550) || 5938 (hw->mac.type == ixgbe_mac_X550EM_x)) { 5939 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 5940 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 5941 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 5942 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 5943 } 5944 } 5945 5946 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 5947 /* work around hardware counting issue */ 5948 hwstats->gprc -= missed_rx; 5949 5950 ixgbe_update_xoff_received(adapter); 5951 5952 /* 82598 hardware only has a 32 bit counter in the high register */ 5953 switch (hw->mac.type) { 5954 case ixgbe_mac_82598EB: 5955 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 5956 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 5957 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 5958 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 5959 break; 5960 case ixgbe_mac_X540: 5961 case ixgbe_mac_X550: 5962 case ixgbe_mac_X550EM_x: 5963 /* OS2BMC stats are X540 and later */ 5964 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 5965 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 5966 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 5967 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 5968 case ixgbe_mac_82599EB: 5969 for (i = 0; i < 16; i++) 5970 adapter->hw_rx_no_dma_resources += 5971 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 5972 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 5973 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 5974 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 5975 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 5976 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 5977 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 5978 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 5979 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 5980 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 5981 #ifdef IXGBE_FCOE 5982 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 5983 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 5984 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 5985 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 5986 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 5987 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 5988 /* Add up per cpu counters for total ddp aloc fail */ 5989 if (adapter->fcoe.ddp_pool) { 5990 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 5991 struct ixgbe_fcoe_ddp_pool *ddp_pool; 5992 unsigned int cpu; 5993 u64 noddp = 0, noddp_ext_buff = 0; 5994 for_each_possible_cpu(cpu) { 5995 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 5996 noddp += ddp_pool->noddp; 5997 noddp_ext_buff += ddp_pool->noddp_ext_buff; 5998 } 5999 hwstats->fcoe_noddp = noddp; 6000 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 6001 } 6002 #endif /* IXGBE_FCOE */ 6003 break; 6004 default: 6005 break; 6006 } 6007 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 6008 hwstats->bprc += bprc; 6009 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 6010 if (hw->mac.type == ixgbe_mac_82598EB) 6011 hwstats->mprc -= bprc; 6012 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 6013 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 6014 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 6015 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 6016 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 6017 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 6018 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 6019 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 6020 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 6021 hwstats->lxontxc += lxon; 6022 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 6023 hwstats->lxofftxc += lxoff; 6024 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 6025 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 6026 /* 6027 * 82598 errata - tx of flow control packets is included in tx counters 6028 */ 6029 xon_off_tot = lxon + lxoff; 6030 hwstats->gptc -= xon_off_tot; 6031 hwstats->mptc -= xon_off_tot; 6032 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 6033 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 6034 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 6035 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 6036 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 6037 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 6038 hwstats->ptc64 -= xon_off_tot; 6039 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 6040 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 6041 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 6042 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 6043 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 6044 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 6045 6046 /* Fill out the OS statistics structure */ 6047 netdev->stats.multicast = hwstats->mprc; 6048 6049 /* Rx Errors */ 6050 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 6051 netdev->stats.rx_dropped = 0; 6052 netdev->stats.rx_length_errors = hwstats->rlec; 6053 netdev->stats.rx_crc_errors = hwstats->crcerrs; 6054 netdev->stats.rx_missed_errors = total_mpc; 6055 } 6056 6057 /** 6058 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 6059 * @adapter: pointer to the device adapter structure 6060 **/ 6061 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 6062 { 6063 struct ixgbe_hw *hw = &adapter->hw; 6064 int i; 6065 6066 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 6067 return; 6068 6069 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6070 6071 /* if interface is down do nothing */ 6072 if (test_bit(__IXGBE_DOWN, &adapter->state)) 6073 return; 6074 6075 /* do nothing if we are not using signature filters */ 6076 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 6077 return; 6078 6079 adapter->fdir_overflow++; 6080 6081 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 6082 for (i = 0; i < adapter->num_tx_queues; i++) 6083 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 6084 &(adapter->tx_ring[i]->state)); 6085 /* re-enable flow director interrupts */ 6086 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 6087 } else { 6088 e_err(probe, "failed to finish FDIR re-initialization, " 6089 "ignored adding FDIR ATR filters\n"); 6090 } 6091 } 6092 6093 /** 6094 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 6095 * @adapter: pointer to the device adapter structure 6096 * 6097 * This function serves two purposes. First it strobes the interrupt lines 6098 * in order to make certain interrupts are occurring. Secondly it sets the 6099 * bits needed to check for TX hangs. As a result we should immediately 6100 * determine if a hang has occurred. 6101 */ 6102 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 6103 { 6104 struct ixgbe_hw *hw = &adapter->hw; 6105 u64 eics = 0; 6106 int i; 6107 6108 /* If we're down, removing or resetting, just bail */ 6109 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6110 test_bit(__IXGBE_REMOVING, &adapter->state) || 6111 test_bit(__IXGBE_RESETTING, &adapter->state)) 6112 return; 6113 6114 /* Force detection of hung controller */ 6115 if (netif_carrier_ok(adapter->netdev)) { 6116 for (i = 0; i < adapter->num_tx_queues; i++) 6117 set_check_for_tx_hang(adapter->tx_ring[i]); 6118 } 6119 6120 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 6121 /* 6122 * for legacy and MSI interrupts don't set any bits 6123 * that are enabled for EIAM, because this operation 6124 * would set *both* EIMS and EICS for any bit in EIAM 6125 */ 6126 IXGBE_WRITE_REG(hw, IXGBE_EICS, 6127 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 6128 } else { 6129 /* get one bit for every active tx/rx interrupt vector */ 6130 for (i = 0; i < adapter->num_q_vectors; i++) { 6131 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 6132 if (qv->rx.ring || qv->tx.ring) 6133 eics |= ((u64)1 << i); 6134 } 6135 } 6136 6137 /* Cause software interrupt to ensure rings are cleaned */ 6138 ixgbe_irq_rearm_queues(adapter, eics); 6139 6140 } 6141 6142 /** 6143 * ixgbe_watchdog_update_link - update the link status 6144 * @adapter: pointer to the device adapter structure 6145 * @link_speed: pointer to a u32 to store the link_speed 6146 **/ 6147 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 6148 { 6149 struct ixgbe_hw *hw = &adapter->hw; 6150 u32 link_speed = adapter->link_speed; 6151 bool link_up = adapter->link_up; 6152 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 6153 6154 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 6155 return; 6156 6157 if (hw->mac.ops.check_link) { 6158 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 6159 } else { 6160 /* always assume link is up, if no check link function */ 6161 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 6162 link_up = true; 6163 } 6164 6165 if (adapter->ixgbe_ieee_pfc) 6166 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 6167 6168 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 6169 hw->mac.ops.fc_enable(hw); 6170 ixgbe_set_rx_drop_en(adapter); 6171 } 6172 6173 if (link_up || 6174 time_after(jiffies, (adapter->link_check_timeout + 6175 IXGBE_TRY_LINK_TIMEOUT))) { 6176 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 6177 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 6178 IXGBE_WRITE_FLUSH(hw); 6179 } 6180 6181 adapter->link_up = link_up; 6182 adapter->link_speed = link_speed; 6183 } 6184 6185 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 6186 { 6187 #ifdef CONFIG_IXGBE_DCB 6188 struct net_device *netdev = adapter->netdev; 6189 struct dcb_app app = { 6190 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 6191 .protocol = 0, 6192 }; 6193 u8 up = 0; 6194 6195 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 6196 up = dcb_ieee_getapp_mask(netdev, &app); 6197 6198 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 6199 #endif 6200 } 6201 6202 /** 6203 * ixgbe_watchdog_link_is_up - update netif_carrier status and 6204 * print link up message 6205 * @adapter: pointer to the device adapter structure 6206 **/ 6207 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 6208 { 6209 struct net_device *netdev = adapter->netdev; 6210 struct ixgbe_hw *hw = &adapter->hw; 6211 struct net_device *upper; 6212 struct list_head *iter; 6213 u32 link_speed = adapter->link_speed; 6214 bool flow_rx, flow_tx; 6215 6216 /* only continue if link was previously down */ 6217 if (netif_carrier_ok(netdev)) 6218 return; 6219 6220 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 6221 6222 switch (hw->mac.type) { 6223 case ixgbe_mac_82598EB: { 6224 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6225 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 6226 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 6227 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 6228 } 6229 break; 6230 case ixgbe_mac_X540: 6231 case ixgbe_mac_X550: 6232 case ixgbe_mac_X550EM_x: 6233 case ixgbe_mac_82599EB: { 6234 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 6235 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 6236 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 6237 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 6238 } 6239 break; 6240 default: 6241 flow_tx = false; 6242 flow_rx = false; 6243 break; 6244 } 6245 6246 adapter->last_rx_ptp_check = jiffies; 6247 6248 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 6249 ixgbe_ptp_start_cyclecounter(adapter); 6250 6251 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", 6252 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? 6253 "10 Gbps" : 6254 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? 6255 "1 Gbps" : 6256 (link_speed == IXGBE_LINK_SPEED_100_FULL ? 6257 "100 Mbps" : 6258 "unknown speed"))), 6259 ((flow_rx && flow_tx) ? "RX/TX" : 6260 (flow_rx ? "RX" : 6261 (flow_tx ? "TX" : "None")))); 6262 6263 netif_carrier_on(netdev); 6264 ixgbe_check_vf_rate_limit(adapter); 6265 6266 /* enable transmits */ 6267 netif_tx_wake_all_queues(adapter->netdev); 6268 6269 /* enable any upper devices */ 6270 rtnl_lock(); 6271 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 6272 if (netif_is_macvlan(upper)) { 6273 struct macvlan_dev *vlan = netdev_priv(upper); 6274 6275 if (vlan->fwd_priv) 6276 netif_tx_wake_all_queues(upper); 6277 } 6278 } 6279 rtnl_unlock(); 6280 6281 /* update the default user priority for VFs */ 6282 ixgbe_update_default_up(adapter); 6283 6284 /* ping all the active vfs to let them know link has changed */ 6285 ixgbe_ping_all_vfs(adapter); 6286 } 6287 6288 /** 6289 * ixgbe_watchdog_link_is_down - update netif_carrier status and 6290 * print link down message 6291 * @adapter: pointer to the adapter structure 6292 **/ 6293 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 6294 { 6295 struct net_device *netdev = adapter->netdev; 6296 struct ixgbe_hw *hw = &adapter->hw; 6297 6298 adapter->link_up = false; 6299 adapter->link_speed = 0; 6300 6301 /* only continue if link was up previously */ 6302 if (!netif_carrier_ok(netdev)) 6303 return; 6304 6305 /* poll for SFP+ cable when link is down */ 6306 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 6307 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 6308 6309 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 6310 ixgbe_ptp_start_cyclecounter(adapter); 6311 6312 e_info(drv, "NIC Link is Down\n"); 6313 netif_carrier_off(netdev); 6314 6315 /* ping all the active vfs to let them know link has changed */ 6316 ixgbe_ping_all_vfs(adapter); 6317 } 6318 6319 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 6320 { 6321 int i; 6322 6323 for (i = 0; i < adapter->num_tx_queues; i++) { 6324 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 6325 6326 if (tx_ring->next_to_use != tx_ring->next_to_clean) 6327 return true; 6328 } 6329 6330 return false; 6331 } 6332 6333 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 6334 { 6335 struct ixgbe_hw *hw = &adapter->hw; 6336 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 6337 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 6338 6339 int i, j; 6340 6341 if (!adapter->num_vfs) 6342 return false; 6343 6344 /* resetting the PF is only needed for MAC before X550 */ 6345 if (hw->mac.type >= ixgbe_mac_X550) 6346 return false; 6347 6348 for (i = 0; i < adapter->num_vfs; i++) { 6349 for (j = 0; j < q_per_pool; j++) { 6350 u32 h, t; 6351 6352 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 6353 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 6354 6355 if (h != t) 6356 return true; 6357 } 6358 } 6359 6360 return false; 6361 } 6362 6363 /** 6364 * ixgbe_watchdog_flush_tx - flush queues on link down 6365 * @adapter: pointer to the device adapter structure 6366 **/ 6367 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 6368 { 6369 if (!netif_carrier_ok(adapter->netdev)) { 6370 if (ixgbe_ring_tx_pending(adapter) || 6371 ixgbe_vf_tx_pending(adapter)) { 6372 /* We've lost link, so the controller stops DMA, 6373 * but we've got queued Tx work that's never going 6374 * to get done, so reset controller to flush Tx. 6375 * (Do the reset outside of interrupt context). 6376 */ 6377 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 6378 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 6379 } 6380 } 6381 } 6382 6383 #ifdef CONFIG_PCI_IOV 6384 static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter, 6385 struct pci_dev *vfdev) 6386 { 6387 if (!pci_wait_for_pending_transaction(vfdev)) 6388 e_dev_warn("Issuing VFLR with pending transactions\n"); 6389 6390 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev)); 6391 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 6392 6393 msleep(100); 6394 } 6395 6396 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 6397 { 6398 struct ixgbe_hw *hw = &adapter->hw; 6399 struct pci_dev *pdev = adapter->pdev; 6400 struct pci_dev *vfdev; 6401 u32 gpc; 6402 int pos; 6403 unsigned short vf_id; 6404 6405 if (!(netif_carrier_ok(adapter->netdev))) 6406 return; 6407 6408 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 6409 if (gpc) /* If incrementing then no need for the check below */ 6410 return; 6411 /* Check to see if a bad DMA write target from an errant or 6412 * malicious VF has caused a PCIe error. If so then we can 6413 * issue a VFLR to the offending VF(s) and then resume without 6414 * requesting a full slot reset. 6415 */ 6416 6417 if (!pdev) 6418 return; 6419 6420 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); 6421 if (!pos) 6422 return; 6423 6424 /* get the device ID for the VF */ 6425 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &vf_id); 6426 6427 /* check status reg for all VFs owned by this PF */ 6428 vfdev = pci_get_device(pdev->vendor, vf_id, NULL); 6429 while (vfdev) { 6430 if (vfdev->is_virtfn && (vfdev->physfn == pdev)) { 6431 u16 status_reg; 6432 6433 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 6434 if (status_reg & PCI_STATUS_REC_MASTER_ABORT) 6435 /* issue VFLR */ 6436 ixgbe_issue_vf_flr(adapter, vfdev); 6437 } 6438 6439 vfdev = pci_get_device(pdev->vendor, vf_id, vfdev); 6440 } 6441 } 6442 6443 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 6444 { 6445 u32 ssvpc; 6446 6447 /* Do not perform spoof check for 82598 or if not in IOV mode */ 6448 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 6449 adapter->num_vfs == 0) 6450 return; 6451 6452 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 6453 6454 /* 6455 * ssvpc register is cleared on read, if zero then no 6456 * spoofed packets in the last interval. 6457 */ 6458 if (!ssvpc) 6459 return; 6460 6461 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 6462 } 6463 #else 6464 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 6465 { 6466 } 6467 6468 static void 6469 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 6470 { 6471 } 6472 #endif /* CONFIG_PCI_IOV */ 6473 6474 6475 /** 6476 * ixgbe_watchdog_subtask - check and bring link up 6477 * @adapter: pointer to the device adapter structure 6478 **/ 6479 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 6480 { 6481 /* if interface is down, removing or resetting, do nothing */ 6482 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6483 test_bit(__IXGBE_REMOVING, &adapter->state) || 6484 test_bit(__IXGBE_RESETTING, &adapter->state)) 6485 return; 6486 6487 ixgbe_watchdog_update_link(adapter); 6488 6489 if (adapter->link_up) 6490 ixgbe_watchdog_link_is_up(adapter); 6491 else 6492 ixgbe_watchdog_link_is_down(adapter); 6493 6494 ixgbe_check_for_bad_vf(adapter); 6495 ixgbe_spoof_check(adapter); 6496 ixgbe_update_stats(adapter); 6497 6498 ixgbe_watchdog_flush_tx(adapter); 6499 } 6500 6501 /** 6502 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 6503 * @adapter: the ixgbe adapter structure 6504 **/ 6505 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 6506 { 6507 struct ixgbe_hw *hw = &adapter->hw; 6508 s32 err; 6509 6510 /* not searching for SFP so there is nothing to do here */ 6511 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 6512 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 6513 return; 6514 6515 /* someone else is in init, wait until next service event */ 6516 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 6517 return; 6518 6519 err = hw->phy.ops.identify_sfp(hw); 6520 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 6521 goto sfp_out; 6522 6523 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 6524 /* If no cable is present, then we need to reset 6525 * the next time we find a good cable. */ 6526 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 6527 } 6528 6529 /* exit on error */ 6530 if (err) 6531 goto sfp_out; 6532 6533 /* exit if reset not needed */ 6534 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 6535 goto sfp_out; 6536 6537 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 6538 6539 /* 6540 * A module may be identified correctly, but the EEPROM may not have 6541 * support for that module. setup_sfp() will fail in that case, so 6542 * we should not allow that module to load. 6543 */ 6544 if (hw->mac.type == ixgbe_mac_82598EB) 6545 err = hw->phy.ops.reset(hw); 6546 else 6547 err = hw->mac.ops.setup_sfp(hw); 6548 6549 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 6550 goto sfp_out; 6551 6552 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 6553 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 6554 6555 sfp_out: 6556 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 6557 6558 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 6559 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 6560 e_dev_err("failed to initialize because an unsupported " 6561 "SFP+ module type was detected.\n"); 6562 e_dev_err("Reload the driver after installing a " 6563 "supported module.\n"); 6564 unregister_netdev(adapter->netdev); 6565 } 6566 } 6567 6568 /** 6569 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 6570 * @adapter: the ixgbe adapter structure 6571 **/ 6572 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 6573 { 6574 struct ixgbe_hw *hw = &adapter->hw; 6575 u32 speed; 6576 bool autoneg = false; 6577 6578 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 6579 return; 6580 6581 /* someone else is in init, wait until next service event */ 6582 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 6583 return; 6584 6585 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 6586 6587 speed = hw->phy.autoneg_advertised; 6588 if ((!speed) && (hw->mac.ops.get_link_capabilities)) { 6589 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg); 6590 6591 /* setup the highest link when no autoneg */ 6592 if (!autoneg) { 6593 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 6594 speed = IXGBE_LINK_SPEED_10GB_FULL; 6595 } 6596 } 6597 6598 if (hw->mac.ops.setup_link) 6599 hw->mac.ops.setup_link(hw, speed, true); 6600 6601 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 6602 adapter->link_check_timeout = jiffies; 6603 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 6604 } 6605 6606 /** 6607 * ixgbe_service_timer - Timer Call-back 6608 * @data: pointer to adapter cast into an unsigned long 6609 **/ 6610 static void ixgbe_service_timer(unsigned long data) 6611 { 6612 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; 6613 unsigned long next_event_offset; 6614 6615 /* poll faster when waiting for link */ 6616 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 6617 next_event_offset = HZ / 10; 6618 else 6619 next_event_offset = HZ * 2; 6620 6621 /* Reset the timer */ 6622 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 6623 6624 ixgbe_service_event_schedule(adapter); 6625 } 6626 6627 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 6628 { 6629 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED)) 6630 return; 6631 6632 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED; 6633 6634 /* If we're already down, removing or resetting, just bail */ 6635 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6636 test_bit(__IXGBE_REMOVING, &adapter->state) || 6637 test_bit(__IXGBE_RESETTING, &adapter->state)) 6638 return; 6639 6640 ixgbe_dump(adapter); 6641 netdev_err(adapter->netdev, "Reset adapter\n"); 6642 adapter->tx_timeout_count++; 6643 6644 rtnl_lock(); 6645 ixgbe_reinit_locked(adapter); 6646 rtnl_unlock(); 6647 } 6648 6649 /** 6650 * ixgbe_service_task - manages and runs subtasks 6651 * @work: pointer to work_struct containing our data 6652 **/ 6653 static void ixgbe_service_task(struct work_struct *work) 6654 { 6655 struct ixgbe_adapter *adapter = container_of(work, 6656 struct ixgbe_adapter, 6657 service_task); 6658 if (ixgbe_removed(adapter->hw.hw_addr)) { 6659 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 6660 rtnl_lock(); 6661 ixgbe_down(adapter); 6662 rtnl_unlock(); 6663 } 6664 ixgbe_service_event_complete(adapter); 6665 return; 6666 } 6667 ixgbe_reset_subtask(adapter); 6668 ixgbe_sfp_detection_subtask(adapter); 6669 ixgbe_sfp_link_config_subtask(adapter); 6670 ixgbe_check_overtemp_subtask(adapter); 6671 ixgbe_watchdog_subtask(adapter); 6672 ixgbe_fdir_reinit_subtask(adapter); 6673 ixgbe_check_hang_subtask(adapter); 6674 6675 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 6676 ixgbe_ptp_overflow_check(adapter); 6677 ixgbe_ptp_rx_hang(adapter); 6678 } 6679 6680 ixgbe_service_event_complete(adapter); 6681 } 6682 6683 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 6684 struct ixgbe_tx_buffer *first, 6685 u8 *hdr_len) 6686 { 6687 struct sk_buff *skb = first->skb; 6688 u32 vlan_macip_lens, type_tucmd; 6689 u32 mss_l4len_idx, l4len; 6690 int err; 6691 6692 if (skb->ip_summed != CHECKSUM_PARTIAL) 6693 return 0; 6694 6695 if (!skb_is_gso(skb)) 6696 return 0; 6697 6698 err = skb_cow_head(skb, 0); 6699 if (err < 0) 6700 return err; 6701 6702 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 6703 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 6704 6705 if (first->protocol == htons(ETH_P_IP)) { 6706 struct iphdr *iph = ip_hdr(skb); 6707 iph->tot_len = 0; 6708 iph->check = 0; 6709 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 6710 iph->daddr, 0, 6711 IPPROTO_TCP, 6712 0); 6713 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 6714 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 6715 IXGBE_TX_FLAGS_CSUM | 6716 IXGBE_TX_FLAGS_IPV4; 6717 } else if (skb_is_gso_v6(skb)) { 6718 ipv6_hdr(skb)->payload_len = 0; 6719 tcp_hdr(skb)->check = 6720 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 6721 &ipv6_hdr(skb)->daddr, 6722 0, IPPROTO_TCP, 0); 6723 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 6724 IXGBE_TX_FLAGS_CSUM; 6725 } 6726 6727 /* compute header lengths */ 6728 l4len = tcp_hdrlen(skb); 6729 *hdr_len = skb_transport_offset(skb) + l4len; 6730 6731 /* update gso size and bytecount with header size */ 6732 first->gso_segs = skb_shinfo(skb)->gso_segs; 6733 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6734 6735 /* mss_l4len_id: use 0 as index for TSO */ 6736 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; 6737 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 6738 6739 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 6740 vlan_macip_lens = skb_network_header_len(skb); 6741 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 6742 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 6743 6744 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 6745 mss_l4len_idx); 6746 6747 return 1; 6748 } 6749 6750 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 6751 struct ixgbe_tx_buffer *first) 6752 { 6753 struct sk_buff *skb = first->skb; 6754 u32 vlan_macip_lens = 0; 6755 u32 mss_l4len_idx = 0; 6756 u32 type_tucmd = 0; 6757 6758 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6759 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) && 6760 !(first->tx_flags & IXGBE_TX_FLAGS_CC)) 6761 return; 6762 } else { 6763 u8 l4_hdr = 0; 6764 switch (first->protocol) { 6765 case htons(ETH_P_IP): 6766 vlan_macip_lens |= skb_network_header_len(skb); 6767 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 6768 l4_hdr = ip_hdr(skb)->protocol; 6769 break; 6770 case htons(ETH_P_IPV6): 6771 vlan_macip_lens |= skb_network_header_len(skb); 6772 l4_hdr = ipv6_hdr(skb)->nexthdr; 6773 break; 6774 default: 6775 if (unlikely(net_ratelimit())) { 6776 dev_warn(tx_ring->dev, 6777 "partial checksum but proto=%x!\n", 6778 first->protocol); 6779 } 6780 break; 6781 } 6782 6783 switch (l4_hdr) { 6784 case IPPROTO_TCP: 6785 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP; 6786 mss_l4len_idx = tcp_hdrlen(skb) << 6787 IXGBE_ADVTXD_L4LEN_SHIFT; 6788 break; 6789 case IPPROTO_SCTP: 6790 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; 6791 mss_l4len_idx = sizeof(struct sctphdr) << 6792 IXGBE_ADVTXD_L4LEN_SHIFT; 6793 break; 6794 case IPPROTO_UDP: 6795 mss_l4len_idx = sizeof(struct udphdr) << 6796 IXGBE_ADVTXD_L4LEN_SHIFT; 6797 break; 6798 default: 6799 if (unlikely(net_ratelimit())) { 6800 dev_warn(tx_ring->dev, 6801 "partial checksum but l4 proto=%x!\n", 6802 l4_hdr); 6803 } 6804 break; 6805 } 6806 6807 /* update TX checksum flag */ 6808 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 6809 } 6810 6811 /* vlan_macip_lens: MACLEN, VLAN tag */ 6812 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 6813 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 6814 6815 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, 6816 type_tucmd, mss_l4len_idx); 6817 } 6818 6819 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 6820 ((_flag <= _result) ? \ 6821 ((u32)(_input & _flag) * (_result / _flag)) : \ 6822 ((u32)(_input & _flag) / (_flag / _result))) 6823 6824 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6825 { 6826 /* set type for advanced descriptor with frame checksum insertion */ 6827 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 6828 IXGBE_ADVTXD_DCMD_DEXT | 6829 IXGBE_ADVTXD_DCMD_IFCS; 6830 6831 /* set HW vlan bit if vlan is present */ 6832 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 6833 IXGBE_ADVTXD_DCMD_VLE); 6834 6835 /* set segmentation enable bits for TSO/FSO */ 6836 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 6837 IXGBE_ADVTXD_DCMD_TSE); 6838 6839 /* set timestamp bit if present */ 6840 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 6841 IXGBE_ADVTXD_MAC_TSTAMP); 6842 6843 /* insert frame checksum */ 6844 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 6845 6846 return cmd_type; 6847 } 6848 6849 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 6850 u32 tx_flags, unsigned int paylen) 6851 { 6852 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 6853 6854 /* enable L4 checksum for TSO and TX checksum offload */ 6855 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 6856 IXGBE_TX_FLAGS_CSUM, 6857 IXGBE_ADVTXD_POPTS_TXSM); 6858 6859 /* enble IPv4 checksum for TSO */ 6860 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 6861 IXGBE_TX_FLAGS_IPV4, 6862 IXGBE_ADVTXD_POPTS_IXSM); 6863 6864 /* 6865 * Check Context must be set if Tx switch is enabled, which it 6866 * always is for case where virtual functions are running 6867 */ 6868 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 6869 IXGBE_TX_FLAGS_CC, 6870 IXGBE_ADVTXD_CC); 6871 6872 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6873 } 6874 6875 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 6876 { 6877 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 6878 6879 /* Herbert's original patch had: 6880 * smp_mb__after_netif_stop_queue(); 6881 * but since that doesn't exist yet, just open code it. 6882 */ 6883 smp_mb(); 6884 6885 /* We need to check again in a case another CPU has just 6886 * made room available. 6887 */ 6888 if (likely(ixgbe_desc_unused(tx_ring) < size)) 6889 return -EBUSY; 6890 6891 /* A reprieve! - use start_queue because it doesn't call schedule */ 6892 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 6893 ++tx_ring->tx_stats.restart_queue; 6894 return 0; 6895 } 6896 6897 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 6898 { 6899 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 6900 return 0; 6901 6902 return __ixgbe_maybe_stop_tx(tx_ring, size); 6903 } 6904 6905 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ 6906 IXGBE_TXD_CMD_RS) 6907 6908 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, 6909 struct ixgbe_tx_buffer *first, 6910 const u8 hdr_len) 6911 { 6912 struct sk_buff *skb = first->skb; 6913 struct ixgbe_tx_buffer *tx_buffer; 6914 union ixgbe_adv_tx_desc *tx_desc; 6915 struct skb_frag_struct *frag; 6916 dma_addr_t dma; 6917 unsigned int data_len, size; 6918 u32 tx_flags = first->tx_flags; 6919 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 6920 u16 i = tx_ring->next_to_use; 6921 6922 tx_desc = IXGBE_TX_DESC(tx_ring, i); 6923 6924 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 6925 6926 size = skb_headlen(skb); 6927 data_len = skb->data_len; 6928 6929 #ifdef IXGBE_FCOE 6930 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 6931 if (data_len < sizeof(struct fcoe_crc_eof)) { 6932 size -= sizeof(struct fcoe_crc_eof) - data_len; 6933 data_len = 0; 6934 } else { 6935 data_len -= sizeof(struct fcoe_crc_eof); 6936 } 6937 } 6938 6939 #endif 6940 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6941 6942 tx_buffer = first; 6943 6944 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6945 if (dma_mapping_error(tx_ring->dev, dma)) 6946 goto dma_error; 6947 6948 /* record length, and DMA address */ 6949 dma_unmap_len_set(tx_buffer, len, size); 6950 dma_unmap_addr_set(tx_buffer, dma, dma); 6951 6952 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6953 6954 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 6955 tx_desc->read.cmd_type_len = 6956 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 6957 6958 i++; 6959 tx_desc++; 6960 if (i == tx_ring->count) { 6961 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 6962 i = 0; 6963 } 6964 tx_desc->read.olinfo_status = 0; 6965 6966 dma += IXGBE_MAX_DATA_PER_TXD; 6967 size -= IXGBE_MAX_DATA_PER_TXD; 6968 6969 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6970 } 6971 6972 if (likely(!data_len)) 6973 break; 6974 6975 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6976 6977 i++; 6978 tx_desc++; 6979 if (i == tx_ring->count) { 6980 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 6981 i = 0; 6982 } 6983 tx_desc->read.olinfo_status = 0; 6984 6985 #ifdef IXGBE_FCOE 6986 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 6987 #else 6988 size = skb_frag_size(frag); 6989 #endif 6990 data_len -= size; 6991 6992 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 6993 DMA_TO_DEVICE); 6994 6995 tx_buffer = &tx_ring->tx_buffer_info[i]; 6996 } 6997 6998 /* write last descriptor with RS and EOP bits */ 6999 cmd_type |= size | IXGBE_TXD_CMD; 7000 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 7001 7002 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 7003 7004 /* set the timestamp */ 7005 first->time_stamp = jiffies; 7006 7007 /* 7008 * Force memory writes to complete before letting h/w know there 7009 * are new descriptors to fetch. (Only applicable for weak-ordered 7010 * memory model archs, such as IA-64). 7011 * 7012 * We also need this memory barrier to make certain all of the 7013 * status bits have been updated before next_to_watch is written. 7014 */ 7015 wmb(); 7016 7017 /* set next_to_watch value indicating a packet is present */ 7018 first->next_to_watch = tx_desc; 7019 7020 i++; 7021 if (i == tx_ring->count) 7022 i = 0; 7023 7024 tx_ring->next_to_use = i; 7025 7026 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 7027 7028 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 7029 writel(i, tx_ring->tail); 7030 7031 /* we need this if more than one processor can write to our tail 7032 * at a time, it synchronizes IO on IA64/Altix systems 7033 */ 7034 mmiowb(); 7035 } 7036 7037 return; 7038 dma_error: 7039 dev_err(tx_ring->dev, "TX DMA map failed\n"); 7040 7041 /* clear dma mappings for failed tx_buffer_info map */ 7042 for (;;) { 7043 tx_buffer = &tx_ring->tx_buffer_info[i]; 7044 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); 7045 if (tx_buffer == first) 7046 break; 7047 if (i == 0) 7048 i = tx_ring->count; 7049 i--; 7050 } 7051 7052 tx_ring->next_to_use = i; 7053 } 7054 7055 static void ixgbe_atr(struct ixgbe_ring *ring, 7056 struct ixgbe_tx_buffer *first) 7057 { 7058 struct ixgbe_q_vector *q_vector = ring->q_vector; 7059 union ixgbe_atr_hash_dword input = { .dword = 0 }; 7060 union ixgbe_atr_hash_dword common = { .dword = 0 }; 7061 union { 7062 unsigned char *network; 7063 struct iphdr *ipv4; 7064 struct ipv6hdr *ipv6; 7065 } hdr; 7066 struct tcphdr *th; 7067 __be16 vlan_id; 7068 7069 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 7070 if (!q_vector) 7071 return; 7072 7073 /* do nothing if sampling is disabled */ 7074 if (!ring->atr_sample_rate) 7075 return; 7076 7077 ring->atr_count++; 7078 7079 /* snag network header to get L4 type and address */ 7080 hdr.network = skb_network_header(first->skb); 7081 7082 /* Currently only IPv4/IPv6 with TCP is supported */ 7083 if ((first->protocol != htons(ETH_P_IPV6) || 7084 hdr.ipv6->nexthdr != IPPROTO_TCP) && 7085 (first->protocol != htons(ETH_P_IP) || 7086 hdr.ipv4->protocol != IPPROTO_TCP)) 7087 return; 7088 7089 th = tcp_hdr(first->skb); 7090 7091 /* skip this packet since it is invalid or the socket is closing */ 7092 if (!th || th->fin) 7093 return; 7094 7095 /* sample on all syn packets or once every atr sample count */ 7096 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 7097 return; 7098 7099 /* reset sample count */ 7100 ring->atr_count = 0; 7101 7102 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 7103 7104 /* 7105 * src and dst are inverted, think how the receiver sees them 7106 * 7107 * The input is broken into two sections, a non-compressed section 7108 * containing vm_pool, vlan_id, and flow_type. The rest of the data 7109 * is XORed together and stored in the compressed dword. 7110 */ 7111 input.formatted.vlan_id = vlan_id; 7112 7113 /* 7114 * since src port and flex bytes occupy the same word XOR them together 7115 * and write the value to source port portion of compressed dword 7116 */ 7117 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 7118 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 7119 else 7120 common.port.src ^= th->dest ^ first->protocol; 7121 common.port.dst ^= th->source; 7122 7123 if (first->protocol == htons(ETH_P_IP)) { 7124 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 7125 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 7126 } else { 7127 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 7128 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 7129 hdr.ipv6->saddr.s6_addr32[1] ^ 7130 hdr.ipv6->saddr.s6_addr32[2] ^ 7131 hdr.ipv6->saddr.s6_addr32[3] ^ 7132 hdr.ipv6->daddr.s6_addr32[0] ^ 7133 hdr.ipv6->daddr.s6_addr32[1] ^ 7134 hdr.ipv6->daddr.s6_addr32[2] ^ 7135 hdr.ipv6->daddr.s6_addr32[3]; 7136 } 7137 7138 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 7139 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 7140 input, common, ring->queue_index); 7141 } 7142 7143 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 7144 void *accel_priv, select_queue_fallback_t fallback) 7145 { 7146 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv; 7147 #ifdef IXGBE_FCOE 7148 struct ixgbe_adapter *adapter; 7149 struct ixgbe_ring_feature *f; 7150 int txq; 7151 #endif 7152 7153 if (fwd_adapter) 7154 return skb->queue_mapping + fwd_adapter->tx_base_queue; 7155 7156 #ifdef IXGBE_FCOE 7157 7158 /* 7159 * only execute the code below if protocol is FCoE 7160 * or FIP and we have FCoE enabled on the adapter 7161 */ 7162 switch (vlan_get_protocol(skb)) { 7163 case htons(ETH_P_FCOE): 7164 case htons(ETH_P_FIP): 7165 adapter = netdev_priv(dev); 7166 7167 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) 7168 break; 7169 default: 7170 return fallback(dev, skb); 7171 } 7172 7173 f = &adapter->ring_feature[RING_F_FCOE]; 7174 7175 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 7176 smp_processor_id(); 7177 7178 while (txq >= f->indices) 7179 txq -= f->indices; 7180 7181 return txq + f->offset; 7182 #else 7183 return fallback(dev, skb); 7184 #endif 7185 } 7186 7187 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 7188 struct ixgbe_adapter *adapter, 7189 struct ixgbe_ring *tx_ring) 7190 { 7191 struct ixgbe_tx_buffer *first; 7192 int tso; 7193 u32 tx_flags = 0; 7194 unsigned short f; 7195 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 7196 __be16 protocol = skb->protocol; 7197 u8 hdr_len = 0; 7198 7199 /* 7200 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 7201 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 7202 * + 2 desc gap to keep tail from touching head, 7203 * + 1 desc for context descriptor, 7204 * otherwise try next time 7205 */ 7206 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 7207 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 7208 7209 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 7210 tx_ring->tx_stats.tx_busy++; 7211 return NETDEV_TX_BUSY; 7212 } 7213 7214 /* record the location of the first descriptor for this packet */ 7215 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 7216 first->skb = skb; 7217 first->bytecount = skb->len; 7218 first->gso_segs = 1; 7219 7220 /* if we have a HW VLAN tag being added default to the HW one */ 7221 if (vlan_tx_tag_present(skb)) { 7222 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 7223 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 7224 /* else if it is a SW VLAN check the next protocol and store the tag */ 7225 } else if (protocol == htons(ETH_P_8021Q)) { 7226 struct vlan_hdr *vhdr, _vhdr; 7227 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 7228 if (!vhdr) 7229 goto out_drop; 7230 7231 protocol = vhdr->h_vlan_encapsulated_proto; 7232 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 7233 IXGBE_TX_FLAGS_VLAN_SHIFT; 7234 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 7235 } 7236 7237 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 7238 adapter->ptp_clock && 7239 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 7240 &adapter->state)) { 7241 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 7242 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 7243 7244 /* schedule check for Tx timestamp */ 7245 adapter->ptp_tx_skb = skb_get(skb); 7246 adapter->ptp_tx_start = jiffies; 7247 schedule_work(&adapter->ptp_tx_work); 7248 } 7249 7250 skb_tx_timestamp(skb); 7251 7252 #ifdef CONFIG_PCI_IOV 7253 /* 7254 * Use the l2switch_enable flag - would be false if the DMA 7255 * Tx switch had been disabled. 7256 */ 7257 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 7258 tx_flags |= IXGBE_TX_FLAGS_CC; 7259 7260 #endif 7261 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 7262 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 7263 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 7264 (skb->priority != TC_PRIO_CONTROL))) { 7265 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 7266 tx_flags |= (skb->priority & 0x7) << 7267 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 7268 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 7269 struct vlan_ethhdr *vhdr; 7270 7271 if (skb_cow_head(skb, 0)) 7272 goto out_drop; 7273 vhdr = (struct vlan_ethhdr *)skb->data; 7274 vhdr->h_vlan_TCI = htons(tx_flags >> 7275 IXGBE_TX_FLAGS_VLAN_SHIFT); 7276 } else { 7277 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 7278 } 7279 } 7280 7281 /* record initial flags and protocol */ 7282 first->tx_flags = tx_flags; 7283 first->protocol = protocol; 7284 7285 #ifdef IXGBE_FCOE 7286 /* setup tx offload for FCoE */ 7287 if ((protocol == htons(ETH_P_FCOE)) && 7288 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 7289 tso = ixgbe_fso(tx_ring, first, &hdr_len); 7290 if (tso < 0) 7291 goto out_drop; 7292 7293 goto xmit_fcoe; 7294 } 7295 7296 #endif /* IXGBE_FCOE */ 7297 tso = ixgbe_tso(tx_ring, first, &hdr_len); 7298 if (tso < 0) 7299 goto out_drop; 7300 else if (!tso) 7301 ixgbe_tx_csum(tx_ring, first); 7302 7303 /* add the ATR filter if ATR is on */ 7304 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 7305 ixgbe_atr(tx_ring, first); 7306 7307 #ifdef IXGBE_FCOE 7308 xmit_fcoe: 7309 #endif /* IXGBE_FCOE */ 7310 ixgbe_tx_map(tx_ring, first, hdr_len); 7311 7312 return NETDEV_TX_OK; 7313 7314 out_drop: 7315 dev_kfree_skb_any(first->skb); 7316 first->skb = NULL; 7317 7318 return NETDEV_TX_OK; 7319 } 7320 7321 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 7322 struct net_device *netdev, 7323 struct ixgbe_ring *ring) 7324 { 7325 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7326 struct ixgbe_ring *tx_ring; 7327 7328 /* 7329 * The minimum packet size for olinfo paylen is 17 so pad the skb 7330 * in order to meet this minimum size requirement. 7331 */ 7332 if (skb_put_padto(skb, 17)) 7333 return NETDEV_TX_OK; 7334 7335 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; 7336 7337 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 7338 } 7339 7340 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 7341 struct net_device *netdev) 7342 { 7343 return __ixgbe_xmit_frame(skb, netdev, NULL); 7344 } 7345 7346 /** 7347 * ixgbe_set_mac - Change the Ethernet Address of the NIC 7348 * @netdev: network interface device structure 7349 * @p: pointer to an address structure 7350 * 7351 * Returns 0 on success, negative on failure 7352 **/ 7353 static int ixgbe_set_mac(struct net_device *netdev, void *p) 7354 { 7355 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7356 struct ixgbe_hw *hw = &adapter->hw; 7357 struct sockaddr *addr = p; 7358 int ret; 7359 7360 if (!is_valid_ether_addr(addr->sa_data)) 7361 return -EADDRNOTAVAIL; 7362 7363 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0)); 7364 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 7365 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 7366 7367 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0)); 7368 return ret > 0 ? 0 : ret; 7369 } 7370 7371 static int 7372 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 7373 { 7374 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7375 struct ixgbe_hw *hw = &adapter->hw; 7376 u16 value; 7377 int rc; 7378 7379 if (prtad != hw->phy.mdio.prtad) 7380 return -EINVAL; 7381 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 7382 if (!rc) 7383 rc = value; 7384 return rc; 7385 } 7386 7387 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 7388 u16 addr, u16 value) 7389 { 7390 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7391 struct ixgbe_hw *hw = &adapter->hw; 7392 7393 if (prtad != hw->phy.mdio.prtad) 7394 return -EINVAL; 7395 return hw->phy.ops.write_reg(hw, addr, devad, value); 7396 } 7397 7398 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 7399 { 7400 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7401 7402 switch (cmd) { 7403 case SIOCSHWTSTAMP: 7404 return ixgbe_ptp_set_ts_config(adapter, req); 7405 case SIOCGHWTSTAMP: 7406 return ixgbe_ptp_get_ts_config(adapter, req); 7407 default: 7408 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 7409 } 7410 } 7411 7412 /** 7413 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 7414 * netdev->dev_addrs 7415 * @netdev: network interface device structure 7416 * 7417 * Returns non-zero on failure 7418 **/ 7419 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 7420 { 7421 int err = 0; 7422 struct ixgbe_adapter *adapter = netdev_priv(dev); 7423 struct ixgbe_hw *hw = &adapter->hw; 7424 7425 if (is_valid_ether_addr(hw->mac.san_addr)) { 7426 rtnl_lock(); 7427 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 7428 rtnl_unlock(); 7429 7430 /* update SAN MAC vmdq pool selection */ 7431 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 7432 } 7433 return err; 7434 } 7435 7436 /** 7437 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 7438 * netdev->dev_addrs 7439 * @netdev: network interface device structure 7440 * 7441 * Returns non-zero on failure 7442 **/ 7443 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 7444 { 7445 int err = 0; 7446 struct ixgbe_adapter *adapter = netdev_priv(dev); 7447 struct ixgbe_mac_info *mac = &adapter->hw.mac; 7448 7449 if (is_valid_ether_addr(mac->san_addr)) { 7450 rtnl_lock(); 7451 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 7452 rtnl_unlock(); 7453 } 7454 return err; 7455 } 7456 7457 #ifdef CONFIG_NET_POLL_CONTROLLER 7458 /* 7459 * Polling 'interrupt' - used by things like netconsole to send skbs 7460 * without having to re-enable interrupts. It's not called while 7461 * the interrupt routine is executing. 7462 */ 7463 static void ixgbe_netpoll(struct net_device *netdev) 7464 { 7465 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7466 int i; 7467 7468 /* if interface is down do nothing */ 7469 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7470 return; 7471 7472 adapter->flags |= IXGBE_FLAG_IN_NETPOLL; 7473 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 7474 for (i = 0; i < adapter->num_q_vectors; i++) 7475 ixgbe_msix_clean_rings(0, adapter->q_vector[i]); 7476 } else { 7477 ixgbe_intr(adapter->pdev->irq, netdev); 7478 } 7479 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; 7480 } 7481 7482 #endif 7483 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, 7484 struct rtnl_link_stats64 *stats) 7485 { 7486 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7487 int i; 7488 7489 rcu_read_lock(); 7490 for (i = 0; i < adapter->num_rx_queues; i++) { 7491 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); 7492 u64 bytes, packets; 7493 unsigned int start; 7494 7495 if (ring) { 7496 do { 7497 start = u64_stats_fetch_begin_irq(&ring->syncp); 7498 packets = ring->stats.packets; 7499 bytes = ring->stats.bytes; 7500 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 7501 stats->rx_packets += packets; 7502 stats->rx_bytes += bytes; 7503 } 7504 } 7505 7506 for (i = 0; i < adapter->num_tx_queues; i++) { 7507 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); 7508 u64 bytes, packets; 7509 unsigned int start; 7510 7511 if (ring) { 7512 do { 7513 start = u64_stats_fetch_begin_irq(&ring->syncp); 7514 packets = ring->stats.packets; 7515 bytes = ring->stats.bytes; 7516 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 7517 stats->tx_packets += packets; 7518 stats->tx_bytes += bytes; 7519 } 7520 } 7521 rcu_read_unlock(); 7522 /* following stats updated by ixgbe_watchdog_task() */ 7523 stats->multicast = netdev->stats.multicast; 7524 stats->rx_errors = netdev->stats.rx_errors; 7525 stats->rx_length_errors = netdev->stats.rx_length_errors; 7526 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 7527 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 7528 return stats; 7529 } 7530 7531 #ifdef CONFIG_IXGBE_DCB 7532 /** 7533 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 7534 * @adapter: pointer to ixgbe_adapter 7535 * @tc: number of traffic classes currently enabled 7536 * 7537 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 7538 * 802.1Q priority maps to a packet buffer that exists. 7539 */ 7540 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 7541 { 7542 struct ixgbe_hw *hw = &adapter->hw; 7543 u32 reg, rsave; 7544 int i; 7545 7546 /* 82598 have a static priority to TC mapping that can not 7547 * be changed so no validation is needed. 7548 */ 7549 if (hw->mac.type == ixgbe_mac_82598EB) 7550 return; 7551 7552 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 7553 rsave = reg; 7554 7555 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 7556 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 7557 7558 /* If up2tc is out of bounds default to zero */ 7559 if (up2tc > tc) 7560 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 7561 } 7562 7563 if (reg != rsave) 7564 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 7565 7566 return; 7567 } 7568 7569 /** 7570 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 7571 * @adapter: Pointer to adapter struct 7572 * 7573 * Populate the netdev user priority to tc map 7574 */ 7575 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 7576 { 7577 struct net_device *dev = adapter->netdev; 7578 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 7579 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 7580 u8 prio; 7581 7582 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 7583 u8 tc = 0; 7584 7585 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 7586 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 7587 else if (ets) 7588 tc = ets->prio_tc[prio]; 7589 7590 netdev_set_prio_tc_map(dev, prio, tc); 7591 } 7592 } 7593 7594 #endif /* CONFIG_IXGBE_DCB */ 7595 /** 7596 * ixgbe_setup_tc - configure net_device for multiple traffic classes 7597 * 7598 * @netdev: net device to configure 7599 * @tc: number of traffic classes to enable 7600 */ 7601 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 7602 { 7603 struct ixgbe_adapter *adapter = netdev_priv(dev); 7604 struct ixgbe_hw *hw = &adapter->hw; 7605 bool pools; 7606 7607 /* Hardware supports up to 8 traffic classes */ 7608 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs || 7609 (hw->mac.type == ixgbe_mac_82598EB && 7610 tc < MAX_TRAFFIC_CLASS)) 7611 return -EINVAL; 7612 7613 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1); 7614 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS) 7615 return -EBUSY; 7616 7617 /* Hardware has to reinitialize queues and interrupts to 7618 * match packet buffer alignment. Unfortunately, the 7619 * hardware is not flexible enough to do this dynamically. 7620 */ 7621 if (netif_running(dev)) 7622 ixgbe_close(dev); 7623 ixgbe_clear_interrupt_scheme(adapter); 7624 7625 #ifdef CONFIG_IXGBE_DCB 7626 if (tc) { 7627 netdev_set_num_tc(dev, tc); 7628 ixgbe_set_prio_tc_map(adapter); 7629 7630 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 7631 7632 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 7633 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 7634 adapter->hw.fc.requested_mode = ixgbe_fc_none; 7635 } 7636 } else { 7637 netdev_reset_tc(dev); 7638 7639 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 7640 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 7641 7642 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 7643 7644 adapter->temp_dcb_cfg.pfc_mode_enable = false; 7645 adapter->dcb_cfg.pfc_mode_enable = false; 7646 } 7647 7648 ixgbe_validate_rtr(adapter, tc); 7649 7650 #endif /* CONFIG_IXGBE_DCB */ 7651 ixgbe_init_interrupt_scheme(adapter); 7652 7653 if (netif_running(dev)) 7654 return ixgbe_open(dev); 7655 7656 return 0; 7657 } 7658 7659 #ifdef CONFIG_PCI_IOV 7660 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 7661 { 7662 struct net_device *netdev = adapter->netdev; 7663 7664 rtnl_lock(); 7665 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev)); 7666 rtnl_unlock(); 7667 } 7668 7669 #endif 7670 void ixgbe_do_reset(struct net_device *netdev) 7671 { 7672 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7673 7674 if (netif_running(netdev)) 7675 ixgbe_reinit_locked(adapter); 7676 else 7677 ixgbe_reset(adapter); 7678 } 7679 7680 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 7681 netdev_features_t features) 7682 { 7683 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7684 7685 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 7686 if (!(features & NETIF_F_RXCSUM)) 7687 features &= ~NETIF_F_LRO; 7688 7689 /* Turn off LRO if not RSC capable */ 7690 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 7691 features &= ~NETIF_F_LRO; 7692 7693 return features; 7694 } 7695 7696 static int ixgbe_set_features(struct net_device *netdev, 7697 netdev_features_t features) 7698 { 7699 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7700 netdev_features_t changed = netdev->features ^ features; 7701 bool need_reset = false; 7702 7703 /* Make sure RSC matches LRO, reset if change */ 7704 if (!(features & NETIF_F_LRO)) { 7705 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 7706 need_reset = true; 7707 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 7708 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 7709 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 7710 if (adapter->rx_itr_setting == 1 || 7711 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 7712 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 7713 need_reset = true; 7714 } else if ((changed ^ features) & NETIF_F_LRO) { 7715 e_info(probe, "rx-usecs set too low, " 7716 "disabling RSC\n"); 7717 } 7718 } 7719 7720 /* 7721 * Check if Flow Director n-tuple support was enabled or disabled. If 7722 * the state changed, we need to reset. 7723 */ 7724 switch (features & NETIF_F_NTUPLE) { 7725 case NETIF_F_NTUPLE: 7726 /* turn off ATR, enable perfect filters and reset */ 7727 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 7728 need_reset = true; 7729 7730 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 7731 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 7732 break; 7733 default: 7734 /* turn off perfect filters, enable ATR and reset */ 7735 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 7736 need_reset = true; 7737 7738 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 7739 7740 /* We cannot enable ATR if SR-IOV is enabled */ 7741 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 7742 break; 7743 7744 /* We cannot enable ATR if we have 2 or more traffic classes */ 7745 if (netdev_get_num_tc(netdev) > 1) 7746 break; 7747 7748 /* We cannot enable ATR if RSS is disabled */ 7749 if (adapter->ring_feature[RING_F_RSS].limit <= 1) 7750 break; 7751 7752 /* A sample rate of 0 indicates ATR disabled */ 7753 if (!adapter->atr_sample_rate) 7754 break; 7755 7756 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 7757 break; 7758 } 7759 7760 if (features & NETIF_F_HW_VLAN_CTAG_RX) 7761 ixgbe_vlan_strip_enable(adapter); 7762 else 7763 ixgbe_vlan_strip_disable(adapter); 7764 7765 if (changed & NETIF_F_RXALL) 7766 need_reset = true; 7767 7768 netdev->features = features; 7769 if (need_reset) 7770 ixgbe_do_reset(netdev); 7771 7772 return 0; 7773 } 7774 7775 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 7776 struct net_device *dev, 7777 const unsigned char *addr, u16 vid, 7778 u16 flags) 7779 { 7780 /* guarantee we can provide a unique filter for the unicast address */ 7781 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 7782 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev)) 7783 return -ENOMEM; 7784 } 7785 7786 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 7787 } 7788 7789 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 7790 struct nlmsghdr *nlh) 7791 { 7792 struct ixgbe_adapter *adapter = netdev_priv(dev); 7793 struct nlattr *attr, *br_spec; 7794 int rem; 7795 7796 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 7797 return -EOPNOTSUPP; 7798 7799 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 7800 if (!br_spec) 7801 return -EINVAL; 7802 7803 nla_for_each_nested(attr, br_spec, rem) { 7804 __u16 mode; 7805 u32 reg = 0; 7806 7807 if (nla_type(attr) != IFLA_BRIDGE_MODE) 7808 continue; 7809 7810 if (nla_len(attr) < sizeof(mode)) 7811 return -EINVAL; 7812 7813 mode = nla_get_u16(attr); 7814 if (mode == BRIDGE_MODE_VEPA) { 7815 reg = 0; 7816 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB; 7817 } else if (mode == BRIDGE_MODE_VEB) { 7818 reg = IXGBE_PFDTXGSWC_VT_LBEN; 7819 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB; 7820 } else 7821 return -EINVAL; 7822 7823 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg); 7824 7825 e_info(drv, "enabling bridge mode: %s\n", 7826 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 7827 } 7828 7829 return 0; 7830 } 7831 7832 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 7833 struct net_device *dev, 7834 u32 filter_mask) 7835 { 7836 struct ixgbe_adapter *adapter = netdev_priv(dev); 7837 u16 mode; 7838 7839 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 7840 return 0; 7841 7842 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB) 7843 mode = BRIDGE_MODE_VEB; 7844 else 7845 mode = BRIDGE_MODE_VEPA; 7846 7847 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode, 0, 0); 7848 } 7849 7850 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 7851 { 7852 struct ixgbe_fwd_adapter *fwd_adapter = NULL; 7853 struct ixgbe_adapter *adapter = netdev_priv(pdev); 7854 int used_pools = adapter->num_vfs + adapter->num_rx_pools; 7855 unsigned int limit; 7856 int pool, err; 7857 7858 /* Hardware has a limited number of available pools. Each VF, and the 7859 * PF require a pool. Check to ensure we don't attempt to use more 7860 * then the available number of pools. 7861 */ 7862 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 7863 return ERR_PTR(-EINVAL); 7864 7865 #ifdef CONFIG_RPS 7866 if (vdev->num_rx_queues != vdev->num_tx_queues) { 7867 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n", 7868 vdev->name); 7869 return ERR_PTR(-EINVAL); 7870 } 7871 #endif 7872 /* Check for hardware restriction on number of rx/tx queues */ 7873 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES || 7874 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) { 7875 netdev_info(pdev, 7876 "%s: Supports RX/TX Queue counts 1,2, and 4\n", 7877 pdev->name); 7878 return ERR_PTR(-EINVAL); 7879 } 7880 7881 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 7882 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) || 7883 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS)) 7884 return ERR_PTR(-EBUSY); 7885 7886 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL); 7887 if (!fwd_adapter) 7888 return ERR_PTR(-ENOMEM); 7889 7890 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32); 7891 adapter->num_rx_pools++; 7892 set_bit(pool, &adapter->fwd_bitmask); 7893 limit = find_last_bit(&adapter->fwd_bitmask, 32); 7894 7895 /* Enable VMDq flag so device will be set in VM mode */ 7896 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED; 7897 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 7898 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues; 7899 7900 /* Force reinit of ring allocation with VMDQ enabled */ 7901 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 7902 if (err) 7903 goto fwd_add_err; 7904 fwd_adapter->pool = pool; 7905 fwd_adapter->real_adapter = adapter; 7906 err = ixgbe_fwd_ring_up(vdev, fwd_adapter); 7907 if (err) 7908 goto fwd_add_err; 7909 netif_tx_start_all_queues(vdev); 7910 return fwd_adapter; 7911 fwd_add_err: 7912 /* unwind counter and free adapter struct */ 7913 netdev_info(pdev, 7914 "%s: dfwd hardware acceleration failed\n", vdev->name); 7915 clear_bit(pool, &adapter->fwd_bitmask); 7916 adapter->num_rx_pools--; 7917 kfree(fwd_adapter); 7918 return ERR_PTR(err); 7919 } 7920 7921 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 7922 { 7923 struct ixgbe_fwd_adapter *fwd_adapter = priv; 7924 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter; 7925 unsigned int limit; 7926 7927 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask); 7928 adapter->num_rx_pools--; 7929 7930 limit = find_last_bit(&adapter->fwd_bitmask, 32); 7931 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 7932 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter); 7933 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 7934 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 7935 fwd_adapter->pool, adapter->num_rx_pools, 7936 fwd_adapter->rx_base_queue, 7937 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool, 7938 adapter->fwd_bitmask); 7939 kfree(fwd_adapter); 7940 } 7941 7942 static const struct net_device_ops ixgbe_netdev_ops = { 7943 .ndo_open = ixgbe_open, 7944 .ndo_stop = ixgbe_close, 7945 .ndo_start_xmit = ixgbe_xmit_frame, 7946 .ndo_select_queue = ixgbe_select_queue, 7947 .ndo_set_rx_mode = ixgbe_set_rx_mode, 7948 .ndo_validate_addr = eth_validate_addr, 7949 .ndo_set_mac_address = ixgbe_set_mac, 7950 .ndo_change_mtu = ixgbe_change_mtu, 7951 .ndo_tx_timeout = ixgbe_tx_timeout, 7952 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 7953 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 7954 .ndo_do_ioctl = ixgbe_ioctl, 7955 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 7956 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 7957 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 7958 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 7959 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 7960 .ndo_get_stats64 = ixgbe_get_stats64, 7961 #ifdef CONFIG_IXGBE_DCB 7962 .ndo_setup_tc = ixgbe_setup_tc, 7963 #endif 7964 #ifdef CONFIG_NET_POLL_CONTROLLER 7965 .ndo_poll_controller = ixgbe_netpoll, 7966 #endif 7967 #ifdef CONFIG_NET_RX_BUSY_POLL 7968 .ndo_busy_poll = ixgbe_low_latency_recv, 7969 #endif 7970 #ifdef IXGBE_FCOE 7971 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 7972 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 7973 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 7974 .ndo_fcoe_enable = ixgbe_fcoe_enable, 7975 .ndo_fcoe_disable = ixgbe_fcoe_disable, 7976 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 7977 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 7978 #endif /* IXGBE_FCOE */ 7979 .ndo_set_features = ixgbe_set_features, 7980 .ndo_fix_features = ixgbe_fix_features, 7981 .ndo_fdb_add = ixgbe_ndo_fdb_add, 7982 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 7983 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 7984 .ndo_dfwd_add_station = ixgbe_fwd_add, 7985 .ndo_dfwd_del_station = ixgbe_fwd_del, 7986 }; 7987 7988 /** 7989 * ixgbe_enumerate_functions - Get the number of ports this device has 7990 * @adapter: adapter structure 7991 * 7992 * This function enumerates the phsyical functions co-located on a single slot, 7993 * in order to determine how many ports a device has. This is most useful in 7994 * determining the required GT/s of PCIe bandwidth necessary for optimal 7995 * performance. 7996 **/ 7997 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 7998 { 7999 struct pci_dev *entry, *pdev = adapter->pdev; 8000 int physfns = 0; 8001 8002 /* Some cards can not use the generic count PCIe functions method, 8003 * because they are behind a parent switch, so we hardcode these with 8004 * the correct number of functions. 8005 */ 8006 if (ixgbe_pcie_from_parent(&adapter->hw)) 8007 physfns = 4; 8008 8009 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 8010 /* don't count virtual functions */ 8011 if (entry->is_virtfn) 8012 continue; 8013 8014 /* When the devices on the bus don't all match our device ID, 8015 * we can't reliably determine the correct number of 8016 * functions. This can occur if a function has been direct 8017 * attached to a virtual machine using VT-d, for example. In 8018 * this case, simply return -1 to indicate this. 8019 */ 8020 if ((entry->vendor != pdev->vendor) || 8021 (entry->device != pdev->device)) 8022 return -1; 8023 8024 physfns++; 8025 } 8026 8027 return physfns; 8028 } 8029 8030 /** 8031 * ixgbe_wol_supported - Check whether device supports WoL 8032 * @hw: hw specific details 8033 * @device_id: the device ID 8034 * @subdev_id: the subsystem device ID 8035 * 8036 * This function is used by probe and ethtool to determine 8037 * which devices have WoL support 8038 * 8039 **/ 8040 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 8041 u16 subdevice_id) 8042 { 8043 struct ixgbe_hw *hw = &adapter->hw; 8044 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 8045 int is_wol_supported = 0; 8046 8047 switch (device_id) { 8048 case IXGBE_DEV_ID_82599_SFP: 8049 /* Only these subdevices could supports WOL */ 8050 switch (subdevice_id) { 8051 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 8052 case IXGBE_SUBDEV_ID_82599_560FLR: 8053 /* only support first port */ 8054 if (hw->bus.func != 0) 8055 break; 8056 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 8057 case IXGBE_SUBDEV_ID_82599_SFP: 8058 case IXGBE_SUBDEV_ID_82599_RNDC: 8059 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 8060 case IXGBE_SUBDEV_ID_82599_LOM_SFP: 8061 is_wol_supported = 1; 8062 break; 8063 } 8064 break; 8065 case IXGBE_DEV_ID_82599EN_SFP: 8066 /* Only this subdevice supports WOL */ 8067 switch (subdevice_id) { 8068 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 8069 is_wol_supported = 1; 8070 break; 8071 } 8072 break; 8073 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 8074 /* All except this subdevice support WOL */ 8075 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 8076 is_wol_supported = 1; 8077 break; 8078 case IXGBE_DEV_ID_82599_KX4: 8079 is_wol_supported = 1; 8080 break; 8081 case IXGBE_DEV_ID_X540T: 8082 case IXGBE_DEV_ID_X540T1: 8083 /* check eeprom to see if enabled wol */ 8084 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 8085 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 8086 (hw->bus.func == 0))) { 8087 is_wol_supported = 1; 8088 } 8089 break; 8090 } 8091 8092 return is_wol_supported; 8093 } 8094 8095 /** 8096 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM 8097 * @adapter: Pointer to adapter struct 8098 */ 8099 static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter) 8100 { 8101 #ifdef CONFIG_OF 8102 struct device_node *dp = pci_device_to_OF_node(adapter->pdev); 8103 struct ixgbe_hw *hw = &adapter->hw; 8104 const unsigned char *addr; 8105 8106 addr = of_get_mac_address(dp); 8107 if (addr) { 8108 ether_addr_copy(hw->mac.perm_addr, addr); 8109 return; 8110 } 8111 #endif /* CONFIG_OF */ 8112 8113 #ifdef CONFIG_SPARC 8114 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr); 8115 #endif /* CONFIG_SPARC */ 8116 } 8117 8118 /** 8119 * ixgbe_probe - Device Initialization Routine 8120 * @pdev: PCI device information struct 8121 * @ent: entry in ixgbe_pci_tbl 8122 * 8123 * Returns 0 on success, negative on failure 8124 * 8125 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 8126 * The OS initialization, configuring of the adapter private structure, 8127 * and a hardware reset occur. 8128 **/ 8129 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 8130 { 8131 struct net_device *netdev; 8132 struct ixgbe_adapter *adapter = NULL; 8133 struct ixgbe_hw *hw; 8134 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 8135 int i, err, pci_using_dac, expected_gts; 8136 unsigned int indices = MAX_TX_QUEUES; 8137 u8 part_str[IXGBE_PBANUM_LENGTH]; 8138 bool disable_dev = false; 8139 #ifdef IXGBE_FCOE 8140 u16 device_caps; 8141 #endif 8142 u32 eec; 8143 8144 /* Catch broken hardware that put the wrong VF device ID in 8145 * the PCIe SR-IOV capability. 8146 */ 8147 if (pdev->is_virtfn) { 8148 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 8149 pci_name(pdev), pdev->vendor, pdev->device); 8150 return -EINVAL; 8151 } 8152 8153 err = pci_enable_device_mem(pdev); 8154 if (err) 8155 return err; 8156 8157 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 8158 pci_using_dac = 1; 8159 } else { 8160 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 8161 if (err) { 8162 dev_err(&pdev->dev, 8163 "No usable DMA configuration, aborting\n"); 8164 goto err_dma; 8165 } 8166 pci_using_dac = 0; 8167 } 8168 8169 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 8170 IORESOURCE_MEM), ixgbe_driver_name); 8171 if (err) { 8172 dev_err(&pdev->dev, 8173 "pci_request_selected_regions failed 0x%x\n", err); 8174 goto err_pci_reg; 8175 } 8176 8177 pci_enable_pcie_error_reporting(pdev); 8178 8179 pci_set_master(pdev); 8180 pci_save_state(pdev); 8181 8182 if (ii->mac == ixgbe_mac_82598EB) { 8183 #ifdef CONFIG_IXGBE_DCB 8184 /* 8 TC w/ 4 queues per TC */ 8185 indices = 4 * MAX_TRAFFIC_CLASS; 8186 #else 8187 indices = IXGBE_MAX_RSS_INDICES; 8188 #endif 8189 } 8190 8191 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 8192 if (!netdev) { 8193 err = -ENOMEM; 8194 goto err_alloc_etherdev; 8195 } 8196 8197 SET_NETDEV_DEV(netdev, &pdev->dev); 8198 8199 adapter = netdev_priv(netdev); 8200 8201 adapter->netdev = netdev; 8202 adapter->pdev = pdev; 8203 hw = &adapter->hw; 8204 hw->back = adapter; 8205 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 8206 8207 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 8208 pci_resource_len(pdev, 0)); 8209 adapter->io_addr = hw->hw_addr; 8210 if (!hw->hw_addr) { 8211 err = -EIO; 8212 goto err_ioremap; 8213 } 8214 8215 netdev->netdev_ops = &ixgbe_netdev_ops; 8216 ixgbe_set_ethtool_ops(netdev); 8217 netdev->watchdog_timeo = 5 * HZ; 8218 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 8219 8220 /* Setup hw api */ 8221 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); 8222 hw->mac.type = ii->mac; 8223 8224 /* EEPROM */ 8225 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); 8226 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 8227 if (ixgbe_removed(hw->hw_addr)) { 8228 err = -EIO; 8229 goto err_ioremap; 8230 } 8231 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 8232 if (!(eec & (1 << 8))) 8233 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 8234 8235 /* PHY */ 8236 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); 8237 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 8238 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 8239 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 8240 hw->phy.mdio.mmds = 0; 8241 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 8242 hw->phy.mdio.dev = netdev; 8243 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 8244 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 8245 8246 ii->get_invariants(hw); 8247 8248 /* setup the private structure */ 8249 err = ixgbe_sw_init(adapter); 8250 if (err) 8251 goto err_sw_init; 8252 8253 /* Make it possible the adapter to be woken up via WOL */ 8254 switch (adapter->hw.mac.type) { 8255 case ixgbe_mac_82599EB: 8256 case ixgbe_mac_X540: 8257 case ixgbe_mac_X550: 8258 case ixgbe_mac_X550EM_x: 8259 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 8260 break; 8261 default: 8262 break; 8263 } 8264 8265 /* 8266 * If there is a fan on this device and it has failed log the 8267 * failure. 8268 */ 8269 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 8270 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 8271 if (esdp & IXGBE_ESDP_SDP1) 8272 e_crit(probe, "Fan has stopped, replace the adapter\n"); 8273 } 8274 8275 if (allow_unsupported_sfp) 8276 hw->allow_unsupported_sfp = allow_unsupported_sfp; 8277 8278 /* reset_hw fills in the perm_addr as well */ 8279 hw->phy.reset_if_overtemp = true; 8280 err = hw->mac.ops.reset_hw(hw); 8281 hw->phy.reset_if_overtemp = false; 8282 if (err == IXGBE_ERR_SFP_NOT_PRESENT && 8283 hw->mac.type == ixgbe_mac_82598EB) { 8284 err = 0; 8285 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 8286 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 8287 e_dev_err("Reload the driver after installing a supported module.\n"); 8288 goto err_sw_init; 8289 } else if (err) { 8290 e_dev_err("HW Init failed: %d\n", err); 8291 goto err_sw_init; 8292 } 8293 8294 #ifdef CONFIG_PCI_IOV 8295 /* SR-IOV not supported on the 82598 */ 8296 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 8297 goto skip_sriov; 8298 /* Mailbox */ 8299 ixgbe_init_mbx_params_pf(hw); 8300 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops)); 8301 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 8302 ixgbe_enable_sriov(adapter); 8303 skip_sriov: 8304 8305 #endif 8306 netdev->features = NETIF_F_SG | 8307 NETIF_F_IP_CSUM | 8308 NETIF_F_IPV6_CSUM | 8309 NETIF_F_HW_VLAN_CTAG_TX | 8310 NETIF_F_HW_VLAN_CTAG_RX | 8311 NETIF_F_HW_VLAN_CTAG_FILTER | 8312 NETIF_F_TSO | 8313 NETIF_F_TSO6 | 8314 NETIF_F_RXHASH | 8315 NETIF_F_RXCSUM; 8316 8317 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD; 8318 8319 switch (adapter->hw.mac.type) { 8320 case ixgbe_mac_82599EB: 8321 case ixgbe_mac_X540: 8322 case ixgbe_mac_X550: 8323 case ixgbe_mac_X550EM_x: 8324 netdev->features |= NETIF_F_SCTP_CSUM; 8325 netdev->hw_features |= NETIF_F_SCTP_CSUM | 8326 NETIF_F_NTUPLE; 8327 break; 8328 default: 8329 break; 8330 } 8331 8332 netdev->hw_features |= NETIF_F_RXALL; 8333 8334 netdev->vlan_features |= NETIF_F_TSO; 8335 netdev->vlan_features |= NETIF_F_TSO6; 8336 netdev->vlan_features |= NETIF_F_IP_CSUM; 8337 netdev->vlan_features |= NETIF_F_IPV6_CSUM; 8338 netdev->vlan_features |= NETIF_F_SG; 8339 8340 netdev->priv_flags |= IFF_UNICAST_FLT; 8341 netdev->priv_flags |= IFF_SUPP_NOFCS; 8342 8343 #ifdef CONFIG_IXGBE_DCB 8344 netdev->dcbnl_ops = &dcbnl_ops; 8345 #endif 8346 8347 #ifdef IXGBE_FCOE 8348 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 8349 unsigned int fcoe_l; 8350 8351 if (hw->mac.ops.get_device_caps) { 8352 hw->mac.ops.get_device_caps(hw, &device_caps); 8353 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 8354 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 8355 } 8356 8357 8358 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 8359 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 8360 8361 netdev->features |= NETIF_F_FSO | 8362 NETIF_F_FCOE_CRC; 8363 8364 netdev->vlan_features |= NETIF_F_FSO | 8365 NETIF_F_FCOE_CRC | 8366 NETIF_F_FCOE_MTU; 8367 } 8368 #endif /* IXGBE_FCOE */ 8369 if (pci_using_dac) { 8370 netdev->features |= NETIF_F_HIGHDMA; 8371 netdev->vlan_features |= NETIF_F_HIGHDMA; 8372 } 8373 8374 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 8375 netdev->hw_features |= NETIF_F_LRO; 8376 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 8377 netdev->features |= NETIF_F_LRO; 8378 8379 /* make sure the EEPROM is good */ 8380 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 8381 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 8382 err = -EIO; 8383 goto err_sw_init; 8384 } 8385 8386 ixgbe_get_platform_mac_addr(adapter); 8387 8388 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 8389 8390 if (!is_valid_ether_addr(netdev->dev_addr)) { 8391 e_dev_err("invalid MAC address\n"); 8392 err = -EIO; 8393 goto err_sw_init; 8394 } 8395 8396 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr); 8397 8398 setup_timer(&adapter->service_timer, &ixgbe_service_timer, 8399 (unsigned long) adapter); 8400 8401 if (ixgbe_removed(hw->hw_addr)) { 8402 err = -EIO; 8403 goto err_sw_init; 8404 } 8405 INIT_WORK(&adapter->service_task, ixgbe_service_task); 8406 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 8407 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 8408 8409 err = ixgbe_init_interrupt_scheme(adapter); 8410 if (err) 8411 goto err_sw_init; 8412 8413 /* WOL not supported for all devices */ 8414 adapter->wol = 0; 8415 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 8416 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 8417 pdev->subsystem_device); 8418 if (hw->wol_enabled) 8419 adapter->wol = IXGBE_WUFC_MAG; 8420 8421 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 8422 8423 /* save off EEPROM version number */ 8424 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); 8425 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); 8426 8427 /* pick up the PCI bus settings for reporting later */ 8428 hw->mac.ops.get_bus_info(hw); 8429 if (ixgbe_pcie_from_parent(hw)) 8430 ixgbe_get_parent_bus_info(adapter); 8431 8432 /* calculate the expected PCIe bandwidth required for optimal 8433 * performance. Note that some older parts will never have enough 8434 * bandwidth due to being older generation PCIe parts. We clamp these 8435 * parts to ensure no warning is displayed if it can't be fixed. 8436 */ 8437 switch (hw->mac.type) { 8438 case ixgbe_mac_82598EB: 8439 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 8440 break; 8441 default: 8442 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 8443 break; 8444 } 8445 8446 /* don't check link if we failed to enumerate functions */ 8447 if (expected_gts > 0) 8448 ixgbe_check_minimum_link(adapter, expected_gts); 8449 8450 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 8451 if (err) 8452 strlcpy(part_str, "Unknown", sizeof(part_str)); 8453 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 8454 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 8455 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 8456 part_str); 8457 else 8458 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 8459 hw->mac.type, hw->phy.type, part_str); 8460 8461 e_dev_info("%pM\n", netdev->dev_addr); 8462 8463 /* reset the hardware with the new settings */ 8464 err = hw->mac.ops.start_hw(hw); 8465 if (err == IXGBE_ERR_EEPROM_VERSION) { 8466 /* We are running on a pre-production device, log a warning */ 8467 e_dev_warn("This device is a pre-production adapter/LOM. " 8468 "Please be aware there may be issues associated " 8469 "with your hardware. If you are experiencing " 8470 "problems please contact your Intel or hardware " 8471 "representative who provided you with this " 8472 "hardware.\n"); 8473 } 8474 strcpy(netdev->name, "eth%d"); 8475 err = register_netdev(netdev); 8476 if (err) 8477 goto err_register; 8478 8479 pci_set_drvdata(pdev, adapter); 8480 8481 /* power down the optics for 82599 SFP+ fiber */ 8482 if (hw->mac.ops.disable_tx_laser) 8483 hw->mac.ops.disable_tx_laser(hw); 8484 8485 /* carrier off reporting is important to ethtool even BEFORE open */ 8486 netif_carrier_off(netdev); 8487 8488 #ifdef CONFIG_IXGBE_DCA 8489 if (dca_add_requester(&pdev->dev) == 0) { 8490 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 8491 ixgbe_setup_dca(adapter); 8492 } 8493 #endif 8494 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 8495 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 8496 for (i = 0; i < adapter->num_vfs; i++) 8497 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 8498 } 8499 8500 /* firmware requires driver version to be 0xFFFFFFFF 8501 * since os does not support feature 8502 */ 8503 if (hw->mac.ops.set_fw_drv_ver) 8504 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 8505 0xFF); 8506 8507 /* add san mac addr to netdev */ 8508 ixgbe_add_sanmac_netdev(netdev); 8509 8510 e_dev_info("%s\n", ixgbe_default_device_descr); 8511 8512 #ifdef CONFIG_IXGBE_HWMON 8513 if (ixgbe_sysfs_init(adapter)) 8514 e_err(probe, "failed to allocate sysfs resources\n"); 8515 #endif /* CONFIG_IXGBE_HWMON */ 8516 8517 ixgbe_dbg_adapter_init(adapter); 8518 8519 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 8520 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 8521 hw->mac.ops.setup_link(hw, 8522 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 8523 true); 8524 8525 return 0; 8526 8527 err_register: 8528 ixgbe_release_hw_control(adapter); 8529 ixgbe_clear_interrupt_scheme(adapter); 8530 err_sw_init: 8531 ixgbe_disable_sriov(adapter); 8532 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 8533 iounmap(adapter->io_addr); 8534 kfree(adapter->mac_table); 8535 err_ioremap: 8536 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 8537 free_netdev(netdev); 8538 err_alloc_etherdev: 8539 pci_release_selected_regions(pdev, 8540 pci_select_bars(pdev, IORESOURCE_MEM)); 8541 err_pci_reg: 8542 err_dma: 8543 if (!adapter || disable_dev) 8544 pci_disable_device(pdev); 8545 return err; 8546 } 8547 8548 /** 8549 * ixgbe_remove - Device Removal Routine 8550 * @pdev: PCI device information struct 8551 * 8552 * ixgbe_remove is called by the PCI subsystem to alert the driver 8553 * that it should release a PCI device. The could be caused by a 8554 * Hot-Plug event, or because the driver is going to be removed from 8555 * memory. 8556 **/ 8557 static void ixgbe_remove(struct pci_dev *pdev) 8558 { 8559 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 8560 struct net_device *netdev; 8561 bool disable_dev; 8562 8563 /* if !adapter then we already cleaned up in probe */ 8564 if (!adapter) 8565 return; 8566 8567 netdev = adapter->netdev; 8568 ixgbe_dbg_adapter_exit(adapter); 8569 8570 set_bit(__IXGBE_REMOVING, &adapter->state); 8571 cancel_work_sync(&adapter->service_task); 8572 8573 8574 #ifdef CONFIG_IXGBE_DCA 8575 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 8576 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 8577 dca_remove_requester(&pdev->dev); 8578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); 8579 } 8580 8581 #endif 8582 #ifdef CONFIG_IXGBE_HWMON 8583 ixgbe_sysfs_exit(adapter); 8584 #endif /* CONFIG_IXGBE_HWMON */ 8585 8586 /* remove the added san mac */ 8587 ixgbe_del_sanmac_netdev(netdev); 8588 8589 if (netdev->reg_state == NETREG_REGISTERED) 8590 unregister_netdev(netdev); 8591 8592 #ifdef CONFIG_PCI_IOV 8593 /* 8594 * Only disable SR-IOV on unload if the user specified the now 8595 * deprecated max_vfs module parameter. 8596 */ 8597 if (max_vfs) 8598 ixgbe_disable_sriov(adapter); 8599 #endif 8600 ixgbe_clear_interrupt_scheme(adapter); 8601 8602 ixgbe_release_hw_control(adapter); 8603 8604 #ifdef CONFIG_DCB 8605 kfree(adapter->ixgbe_ieee_pfc); 8606 kfree(adapter->ixgbe_ieee_ets); 8607 8608 #endif 8609 iounmap(adapter->io_addr); 8610 pci_release_selected_regions(pdev, pci_select_bars(pdev, 8611 IORESOURCE_MEM)); 8612 8613 e_dev_info("complete\n"); 8614 8615 kfree(adapter->mac_table); 8616 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 8617 free_netdev(netdev); 8618 8619 pci_disable_pcie_error_reporting(pdev); 8620 8621 if (disable_dev) 8622 pci_disable_device(pdev); 8623 } 8624 8625 /** 8626 * ixgbe_io_error_detected - called when PCI error is detected 8627 * @pdev: Pointer to PCI device 8628 * @state: The current pci connection state 8629 * 8630 * This function is called after a PCI bus error affecting 8631 * this device has been detected. 8632 */ 8633 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 8634 pci_channel_state_t state) 8635 { 8636 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 8637 struct net_device *netdev = adapter->netdev; 8638 8639 #ifdef CONFIG_PCI_IOV 8640 struct ixgbe_hw *hw = &adapter->hw; 8641 struct pci_dev *bdev, *vfdev; 8642 u32 dw0, dw1, dw2, dw3; 8643 int vf, pos; 8644 u16 req_id, pf_func; 8645 8646 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 8647 adapter->num_vfs == 0) 8648 goto skip_bad_vf_detection; 8649 8650 bdev = pdev->bus->self; 8651 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 8652 bdev = bdev->bus->self; 8653 8654 if (!bdev) 8655 goto skip_bad_vf_detection; 8656 8657 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 8658 if (!pos) 8659 goto skip_bad_vf_detection; 8660 8661 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 8662 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 8663 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 8664 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 8665 if (ixgbe_removed(hw->hw_addr)) 8666 goto skip_bad_vf_detection; 8667 8668 req_id = dw1 >> 16; 8669 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 8670 if (!(req_id & 0x0080)) 8671 goto skip_bad_vf_detection; 8672 8673 pf_func = req_id & 0x01; 8674 if ((pf_func & 1) == (pdev->devfn & 1)) { 8675 unsigned int device_id; 8676 8677 vf = (req_id & 0x7F) >> 1; 8678 e_dev_err("VF %d has caused a PCIe error\n", vf); 8679 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 8680 "%8.8x\tdw3: %8.8x\n", 8681 dw0, dw1, dw2, dw3); 8682 switch (adapter->hw.mac.type) { 8683 case ixgbe_mac_82599EB: 8684 device_id = IXGBE_82599_VF_DEVICE_ID; 8685 break; 8686 case ixgbe_mac_X540: 8687 device_id = IXGBE_X540_VF_DEVICE_ID; 8688 break; 8689 case ixgbe_mac_X550: 8690 device_id = IXGBE_DEV_ID_X550_VF; 8691 break; 8692 case ixgbe_mac_X550EM_x: 8693 device_id = IXGBE_DEV_ID_X550EM_X_VF; 8694 break; 8695 default: 8696 device_id = 0; 8697 break; 8698 } 8699 8700 /* Find the pci device of the offending VF */ 8701 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 8702 while (vfdev) { 8703 if (vfdev->devfn == (req_id & 0xFF)) 8704 break; 8705 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 8706 device_id, vfdev); 8707 } 8708 /* 8709 * There's a slim chance the VF could have been hot plugged, 8710 * so if it is no longer present we don't need to issue the 8711 * VFLR. Just clean up the AER in that case. 8712 */ 8713 if (vfdev) { 8714 ixgbe_issue_vf_flr(adapter, vfdev); 8715 /* Free device reference count */ 8716 pci_dev_put(vfdev); 8717 } 8718 8719 pci_cleanup_aer_uncorrect_error_status(pdev); 8720 } 8721 8722 /* 8723 * Even though the error may have occurred on the other port 8724 * we still need to increment the vf error reference count for 8725 * both ports because the I/O resume function will be called 8726 * for both of them. 8727 */ 8728 adapter->vferr_refcount++; 8729 8730 return PCI_ERS_RESULT_RECOVERED; 8731 8732 skip_bad_vf_detection: 8733 #endif /* CONFIG_PCI_IOV */ 8734 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 8735 return PCI_ERS_RESULT_DISCONNECT; 8736 8737 rtnl_lock(); 8738 netif_device_detach(netdev); 8739 8740 if (state == pci_channel_io_perm_failure) { 8741 rtnl_unlock(); 8742 return PCI_ERS_RESULT_DISCONNECT; 8743 } 8744 8745 if (netif_running(netdev)) 8746 ixgbe_down(adapter); 8747 8748 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 8749 pci_disable_device(pdev); 8750 rtnl_unlock(); 8751 8752 /* Request a slot reset. */ 8753 return PCI_ERS_RESULT_NEED_RESET; 8754 } 8755 8756 /** 8757 * ixgbe_io_slot_reset - called after the pci bus has been reset. 8758 * @pdev: Pointer to PCI device 8759 * 8760 * Restart the card from scratch, as if from a cold-boot. 8761 */ 8762 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 8763 { 8764 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 8765 pci_ers_result_t result; 8766 int err; 8767 8768 if (pci_enable_device_mem(pdev)) { 8769 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 8770 result = PCI_ERS_RESULT_DISCONNECT; 8771 } else { 8772 smp_mb__before_atomic(); 8773 clear_bit(__IXGBE_DISABLED, &adapter->state); 8774 adapter->hw.hw_addr = adapter->io_addr; 8775 pci_set_master(pdev); 8776 pci_restore_state(pdev); 8777 pci_save_state(pdev); 8778 8779 pci_wake_from_d3(pdev, false); 8780 8781 ixgbe_reset(adapter); 8782 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 8783 result = PCI_ERS_RESULT_RECOVERED; 8784 } 8785 8786 err = pci_cleanup_aer_uncorrect_error_status(pdev); 8787 if (err) { 8788 e_dev_err("pci_cleanup_aer_uncorrect_error_status " 8789 "failed 0x%0x\n", err); 8790 /* non-fatal, continue */ 8791 } 8792 8793 return result; 8794 } 8795 8796 /** 8797 * ixgbe_io_resume - called when traffic can start flowing again. 8798 * @pdev: Pointer to PCI device 8799 * 8800 * This callback is called when the error recovery driver tells us that 8801 * its OK to resume normal operation. 8802 */ 8803 static void ixgbe_io_resume(struct pci_dev *pdev) 8804 { 8805 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 8806 struct net_device *netdev = adapter->netdev; 8807 8808 #ifdef CONFIG_PCI_IOV 8809 if (adapter->vferr_refcount) { 8810 e_info(drv, "Resuming after VF err\n"); 8811 adapter->vferr_refcount--; 8812 return; 8813 } 8814 8815 #endif 8816 if (netif_running(netdev)) 8817 ixgbe_up(adapter); 8818 8819 netif_device_attach(netdev); 8820 } 8821 8822 static const struct pci_error_handlers ixgbe_err_handler = { 8823 .error_detected = ixgbe_io_error_detected, 8824 .slot_reset = ixgbe_io_slot_reset, 8825 .resume = ixgbe_io_resume, 8826 }; 8827 8828 static struct pci_driver ixgbe_driver = { 8829 .name = ixgbe_driver_name, 8830 .id_table = ixgbe_pci_tbl, 8831 .probe = ixgbe_probe, 8832 .remove = ixgbe_remove, 8833 #ifdef CONFIG_PM 8834 .suspend = ixgbe_suspend, 8835 .resume = ixgbe_resume, 8836 #endif 8837 .shutdown = ixgbe_shutdown, 8838 .sriov_configure = ixgbe_pci_sriov_configure, 8839 .err_handler = &ixgbe_err_handler 8840 }; 8841 8842 /** 8843 * ixgbe_init_module - Driver Registration Routine 8844 * 8845 * ixgbe_init_module is the first routine called when the driver is 8846 * loaded. All it does is register with the PCI subsystem. 8847 **/ 8848 static int __init ixgbe_init_module(void) 8849 { 8850 int ret; 8851 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 8852 pr_info("%s\n", ixgbe_copyright); 8853 8854 ixgbe_dbg_init(); 8855 8856 ret = pci_register_driver(&ixgbe_driver); 8857 if (ret) { 8858 ixgbe_dbg_exit(); 8859 return ret; 8860 } 8861 8862 #ifdef CONFIG_IXGBE_DCA 8863 dca_register_notify(&dca_notifier); 8864 #endif 8865 8866 return 0; 8867 } 8868 8869 module_init(ixgbe_init_module); 8870 8871 /** 8872 * ixgbe_exit_module - Driver Exit Cleanup Routine 8873 * 8874 * ixgbe_exit_module is called just before the driver is removed 8875 * from memory. 8876 **/ 8877 static void __exit ixgbe_exit_module(void) 8878 { 8879 #ifdef CONFIG_IXGBE_DCA 8880 dca_unregister_notify(&dca_notifier); 8881 #endif 8882 pci_unregister_driver(&ixgbe_driver); 8883 8884 ixgbe_dbg_exit(); 8885 8886 rcu_barrier(); /* Wait for completion of call_rcu()'s */ 8887 } 8888 8889 #ifdef CONFIG_IXGBE_DCA 8890 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 8891 void *p) 8892 { 8893 int ret_val; 8894 8895 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 8896 __ixgbe_notify_dca); 8897 8898 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 8899 } 8900 8901 #endif /* CONFIG_IXGBE_DCA */ 8902 8903 module_exit(ixgbe_exit_module); 8904 8905 /* ixgbe_main.c */ 8906