1ae06c70bSJeff Kirsher /* SPDX-License-Identifier: GPL-2.0 */ 2*51dce24bSJeff Kirsher /* Copyright(c) 2013 - 2018 Intel Corporation. */ 304a5aefbSAlexander Duyck 404a5aefbSAlexander Duyck #ifndef _FM10K_COMMON_H_ 504a5aefbSAlexander Duyck #define _FM10K_COMMON_H_ 604a5aefbSAlexander Duyck 704a5aefbSAlexander Duyck #include "fm10k_type.h" 804a5aefbSAlexander Duyck 904a5aefbSAlexander Duyck #define FM10K_REMOVED(hw_addr) unlikely(!(hw_addr)) 1004a5aefbSAlexander Duyck 1104a5aefbSAlexander Duyck /* PCI configuration read */ 1204a5aefbSAlexander Duyck u16 fm10k_read_pci_cfg_word(struct fm10k_hw *hw, u32 reg); 1304a5aefbSAlexander Duyck 1404a5aefbSAlexander Duyck /* read operations, indexed using DWORDS */ 1504a5aefbSAlexander Duyck u32 fm10k_read_reg(struct fm10k_hw *hw, int reg); 1604a5aefbSAlexander Duyck 1704a5aefbSAlexander Duyck /* write operations, indexed using DWORDS */ 1804a5aefbSAlexander Duyck #define fm10k_write_reg(hw, reg, val) \ 1904a5aefbSAlexander Duyck do { \ 20ce4dad2cSJacob Keller u32 __iomem *hw_addr = READ_ONCE((hw)->hw_addr); \ 2104a5aefbSAlexander Duyck if (!FM10K_REMOVED(hw_addr)) \ 2204a5aefbSAlexander Duyck writel((val), &hw_addr[(reg)]); \ 2304a5aefbSAlexander Duyck } while (0) 2404a5aefbSAlexander Duyck 255f226ddbSAlexander Duyck /* Switch register write operations, index using DWORDS */ 265f226ddbSAlexander Duyck #define fm10k_write_sw_reg(hw, reg, val) \ 275f226ddbSAlexander Duyck do { \ 28ce4dad2cSJacob Keller u32 __iomem *sw_addr = READ_ONCE((hw)->sw_addr); \ 295f226ddbSAlexander Duyck if (!FM10K_REMOVED(sw_addr)) \ 305f226ddbSAlexander Duyck writel((val), &sw_addr[(reg)]); \ 315f226ddbSAlexander Duyck } while (0) 325f226ddbSAlexander Duyck 3304a5aefbSAlexander Duyck /* read ctrl register which has no clear on read fields as PCIe flush */ 3404a5aefbSAlexander Duyck #define fm10k_write_flush(hw) fm10k_read_reg((hw), FM10K_CTRL) 35b6fec18fSAlexander Duyck s32 fm10k_get_bus_info_generic(struct fm10k_hw *hw); 36b6fec18fSAlexander Duyck s32 fm10k_get_invariants_generic(struct fm10k_hw *hw); 37b6fec18fSAlexander Duyck s32 fm10k_disable_queues_generic(struct fm10k_hw *hw, u16 q_cnt); 38b6fec18fSAlexander Duyck s32 fm10k_start_hw_generic(struct fm10k_hw *hw); 39b6fec18fSAlexander Duyck s32 fm10k_stop_hw_generic(struct fm10k_hw *hw); 40b6fec18fSAlexander Duyck u32 fm10k_read_hw_stats_32b(struct fm10k_hw *hw, u32 addr, 41b6fec18fSAlexander Duyck struct fm10k_hw_stat *stat); 42b6fec18fSAlexander Duyck #define fm10k_update_hw_base_32b(stat, delta) ((stat)->base_l += (delta)) 43b6fec18fSAlexander Duyck void fm10k_update_hw_stats_q(struct fm10k_hw *hw, struct fm10k_hw_stats_q *q, 44b6fec18fSAlexander Duyck u32 idx, u32 count); 45b6fec18fSAlexander Duyck #define fm10k_unbind_hw_stats_32b(s) ((s)->base_h = 0) 46b6fec18fSAlexander Duyck void fm10k_unbind_hw_stats_q(struct fm10k_hw_stats_q *q, u32 idx, u32 count); 47b6fec18fSAlexander Duyck s32 fm10k_get_host_state_generic(struct fm10k_hw *hw, bool *host_ready); 4804a5aefbSAlexander Duyck #endif /* _FM10K_COMMON_H_ */ 49