1 /* Intel PRO/1000 Linux driver 2 * Copyright(c) 1999 - 2015 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * Linux NICS <linux.nics@intel.com> 18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 */ 21 22 /* 82562G 10/100 Network Connection 23 * 82562G-2 10/100 Network Connection 24 * 82562GT 10/100 Network Connection 25 * 82562GT-2 10/100 Network Connection 26 * 82562V 10/100 Network Connection 27 * 82562V-2 10/100 Network Connection 28 * 82566DC-2 Gigabit Network Connection 29 * 82566DC Gigabit Network Connection 30 * 82566DM-2 Gigabit Network Connection 31 * 82566DM Gigabit Network Connection 32 * 82566MC Gigabit Network Connection 33 * 82566MM Gigabit Network Connection 34 * 82567LM Gigabit Network Connection 35 * 82567LF Gigabit Network Connection 36 * 82567V Gigabit Network Connection 37 * 82567LM-2 Gigabit Network Connection 38 * 82567LF-2 Gigabit Network Connection 39 * 82567V-2 Gigabit Network Connection 40 * 82567LF-3 Gigabit Network Connection 41 * 82567LM-3 Gigabit Network Connection 42 * 82567LM-4 Gigabit Network Connection 43 * 82577LM Gigabit Network Connection 44 * 82577LC Gigabit Network Connection 45 * 82578DM Gigabit Network Connection 46 * 82578DC Gigabit Network Connection 47 * 82579LM Gigabit Network Connection 48 * 82579V Gigabit Network Connection 49 * Ethernet Connection I217-LM 50 * Ethernet Connection I217-V 51 * Ethernet Connection I218-V 52 * Ethernet Connection I218-LM 53 * Ethernet Connection (2) I218-LM 54 * Ethernet Connection (2) I218-V 55 * Ethernet Connection (3) I218-LM 56 * Ethernet Connection (3) I218-V 57 */ 58 59 #include "e1000.h" 60 61 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 62 /* Offset 04h HSFSTS */ 63 union ich8_hws_flash_status { 64 struct ich8_hsfsts { 65 u16 flcdone:1; /* bit 0 Flash Cycle Done */ 66 u16 flcerr:1; /* bit 1 Flash Cycle Error */ 67 u16 dael:1; /* bit 2 Direct Access error Log */ 68 u16 berasesz:2; /* bit 4:3 Sector Erase Size */ 69 u16 flcinprog:1; /* bit 5 flash cycle in Progress */ 70 u16 reserved1:2; /* bit 13:6 Reserved */ 71 u16 reserved2:6; /* bit 13:6 Reserved */ 72 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ 73 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ 74 } hsf_status; 75 u16 regval; 76 }; 77 78 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 79 /* Offset 06h FLCTL */ 80 union ich8_hws_flash_ctrl { 81 struct ich8_hsflctl { 82 u16 flcgo:1; /* 0 Flash Cycle Go */ 83 u16 flcycle:2; /* 2:1 Flash Cycle */ 84 u16 reserved:5; /* 7:3 Reserved */ 85 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ 86 u16 flockdn:6; /* 15:10 Reserved */ 87 } hsf_ctrl; 88 u16 regval; 89 }; 90 91 /* ICH Flash Region Access Permissions */ 92 union ich8_hws_flash_regacc { 93 struct ich8_flracc { 94 u32 grra:8; /* 0:7 GbE region Read Access */ 95 u32 grwa:8; /* 8:15 GbE region Write Access */ 96 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ 97 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ 98 } hsf_flregacc; 99 u16 regval; 100 }; 101 102 /* ICH Flash Protected Region */ 103 union ich8_flash_protected_range { 104 struct ich8_pr { 105 u32 base:13; /* 0:12 Protected Range Base */ 106 u32 reserved1:2; /* 13:14 Reserved */ 107 u32 rpe:1; /* 15 Read Protection Enable */ 108 u32 limit:13; /* 16:28 Protected Range Limit */ 109 u32 reserved2:2; /* 29:30 Reserved */ 110 u32 wpe:1; /* 31 Write Protection Enable */ 111 } range; 112 u32 regval; 113 }; 114 115 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 116 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 117 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 118 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 119 u32 offset, u8 byte); 120 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 121 u8 *data); 122 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 123 u16 *data); 124 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 125 u8 size, u16 *data); 126 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 127 u32 *data); 128 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, 129 u32 offset, u32 *data); 130 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, 131 u32 offset, u32 data); 132 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 133 u32 offset, u32 dword); 134 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 135 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 136 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 137 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 138 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 139 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 140 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 141 static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 142 static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 143 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 144 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 145 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); 146 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 147 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 148 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 149 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 150 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 151 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 152 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw); 153 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 154 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 155 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); 156 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); 157 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state); 158 159 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) 160 { 161 return readw(hw->flash_address + reg); 162 } 163 164 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) 165 { 166 return readl(hw->flash_address + reg); 167 } 168 169 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) 170 { 171 writew(val, hw->flash_address + reg); 172 } 173 174 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) 175 { 176 writel(val, hw->flash_address + reg); 177 } 178 179 #define er16flash(reg) __er16flash(hw, (reg)) 180 #define er32flash(reg) __er32flash(hw, (reg)) 181 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) 182 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) 183 184 /** 185 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 186 * @hw: pointer to the HW structure 187 * 188 * Test access to the PHY registers by reading the PHY ID registers. If 189 * the PHY ID is already known (e.g. resume path) compare it with known ID, 190 * otherwise assume the read PHY ID is correct if it is valid. 191 * 192 * Assumes the sw/fw/hw semaphore is already acquired. 193 **/ 194 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 195 { 196 u16 phy_reg = 0; 197 u32 phy_id = 0; 198 s32 ret_val = 0; 199 u16 retry_count; 200 u32 mac_reg = 0; 201 202 for (retry_count = 0; retry_count < 2; retry_count++) { 203 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); 204 if (ret_val || (phy_reg == 0xFFFF)) 205 continue; 206 phy_id = (u32)(phy_reg << 16); 207 208 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); 209 if (ret_val || (phy_reg == 0xFFFF)) { 210 phy_id = 0; 211 continue; 212 } 213 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 214 break; 215 } 216 217 if (hw->phy.id) { 218 if (hw->phy.id == phy_id) 219 goto out; 220 } else if (phy_id) { 221 hw->phy.id = phy_id; 222 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 223 goto out; 224 } 225 226 /* In case the PHY needs to be in mdio slow mode, 227 * set slow mode and try to get the PHY id again. 228 */ 229 if (hw->mac.type < e1000_pch_lpt) { 230 hw->phy.ops.release(hw); 231 ret_val = e1000_set_mdio_slow_mode_hv(hw); 232 if (!ret_val) 233 ret_val = e1000e_get_phy_id(hw); 234 hw->phy.ops.acquire(hw); 235 } 236 237 if (ret_val) 238 return false; 239 out: 240 if ((hw->mac.type == e1000_pch_lpt) || 241 (hw->mac.type == e1000_pch_spt)) { 242 /* Unforce SMBus mode in PHY */ 243 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); 244 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 245 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); 246 247 /* Unforce SMBus mode in MAC */ 248 mac_reg = er32(CTRL_EXT); 249 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 250 ew32(CTRL_EXT, mac_reg); 251 } 252 253 return true; 254 } 255 256 /** 257 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 258 * @hw: pointer to the HW structure 259 * 260 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 261 * used to reset the PHY to a quiescent state when necessary. 262 **/ 263 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) 264 { 265 u32 mac_reg; 266 267 /* Set Phy Config Counter to 50msec */ 268 mac_reg = er32(FEXTNVM3); 269 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 270 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 271 ew32(FEXTNVM3, mac_reg); 272 273 /* Toggle LANPHYPC Value bit */ 274 mac_reg = er32(CTRL); 275 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 276 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 277 ew32(CTRL, mac_reg); 278 e1e_flush(); 279 usleep_range(10, 20); 280 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 281 ew32(CTRL, mac_reg); 282 e1e_flush(); 283 284 if (hw->mac.type < e1000_pch_lpt) { 285 msleep(50); 286 } else { 287 u16 count = 20; 288 289 do { 290 usleep_range(5000, 10000); 291 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--); 292 293 msleep(30); 294 } 295 } 296 297 /** 298 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 299 * @hw: pointer to the HW structure 300 * 301 * Workarounds/flow necessary for PHY initialization during driver load 302 * and resume paths. 303 **/ 304 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 305 { 306 struct e1000_adapter *adapter = hw->adapter; 307 u32 mac_reg, fwsm = er32(FWSM); 308 s32 ret_val; 309 310 /* Gate automatic PHY configuration by hardware on managed and 311 * non-managed 82579 and newer adapters. 312 */ 313 e1000_gate_hw_phy_config_ich8lan(hw, true); 314 315 /* It is not possible to be certain of the current state of ULP 316 * so forcibly disable it. 317 */ 318 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; 319 e1000_disable_ulp_lpt_lp(hw, true); 320 321 ret_val = hw->phy.ops.acquire(hw); 322 if (ret_val) { 323 e_dbg("Failed to initialize PHY flow\n"); 324 goto out; 325 } 326 327 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 328 * inaccessible and resetting the PHY is not blocked, toggle the 329 * LANPHYPC Value bit to force the interconnect to PCIe mode. 330 */ 331 switch (hw->mac.type) { 332 case e1000_pch_lpt: 333 case e1000_pch_spt: 334 if (e1000_phy_is_accessible_pchlan(hw)) 335 break; 336 337 /* Before toggling LANPHYPC, see if PHY is accessible by 338 * forcing MAC to SMBus mode first. 339 */ 340 mac_reg = er32(CTRL_EXT); 341 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 342 ew32(CTRL_EXT, mac_reg); 343 344 /* Wait 50 milliseconds for MAC to finish any retries 345 * that it might be trying to perform from previous 346 * attempts to acknowledge any phy read requests. 347 */ 348 msleep(50); 349 350 /* fall-through */ 351 case e1000_pch2lan: 352 if (e1000_phy_is_accessible_pchlan(hw)) 353 break; 354 355 /* fall-through */ 356 case e1000_pchlan: 357 if ((hw->mac.type == e1000_pchlan) && 358 (fwsm & E1000_ICH_FWSM_FW_VALID)) 359 break; 360 361 if (hw->phy.ops.check_reset_block(hw)) { 362 e_dbg("Required LANPHYPC toggle blocked by ME\n"); 363 ret_val = -E1000_ERR_PHY; 364 break; 365 } 366 367 /* Toggle LANPHYPC Value bit */ 368 e1000_toggle_lanphypc_pch_lpt(hw); 369 if (hw->mac.type >= e1000_pch_lpt) { 370 if (e1000_phy_is_accessible_pchlan(hw)) 371 break; 372 373 /* Toggling LANPHYPC brings the PHY out of SMBus mode 374 * so ensure that the MAC is also out of SMBus mode 375 */ 376 mac_reg = er32(CTRL_EXT); 377 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 378 ew32(CTRL_EXT, mac_reg); 379 380 if (e1000_phy_is_accessible_pchlan(hw)) 381 break; 382 383 ret_val = -E1000_ERR_PHY; 384 } 385 break; 386 default: 387 break; 388 } 389 390 hw->phy.ops.release(hw); 391 if (!ret_val) { 392 393 /* Check to see if able to reset PHY. Print error if not */ 394 if (hw->phy.ops.check_reset_block(hw)) { 395 e_err("Reset blocked by ME\n"); 396 goto out; 397 } 398 399 /* Reset the PHY before any access to it. Doing so, ensures 400 * that the PHY is in a known good state before we read/write 401 * PHY registers. The generic reset is sufficient here, 402 * because we haven't determined the PHY type yet. 403 */ 404 ret_val = e1000e_phy_hw_reset_generic(hw); 405 if (ret_val) 406 goto out; 407 408 /* On a successful reset, possibly need to wait for the PHY 409 * to quiesce to an accessible state before returning control 410 * to the calling function. If the PHY does not quiesce, then 411 * return E1000E_BLK_PHY_RESET, as this is the condition that 412 * the PHY is in. 413 */ 414 ret_val = hw->phy.ops.check_reset_block(hw); 415 if (ret_val) 416 e_err("ME blocked access to PHY after reset\n"); 417 } 418 419 out: 420 /* Ungate automatic PHY configuration on non-managed 82579 */ 421 if ((hw->mac.type == e1000_pch2lan) && 422 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 423 usleep_range(10000, 20000); 424 e1000_gate_hw_phy_config_ich8lan(hw, false); 425 } 426 427 return ret_val; 428 } 429 430 /** 431 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 432 * @hw: pointer to the HW structure 433 * 434 * Initialize family-specific PHY parameters and function pointers. 435 **/ 436 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 437 { 438 struct e1000_phy_info *phy = &hw->phy; 439 s32 ret_val; 440 441 phy->addr = 1; 442 phy->reset_delay_us = 100; 443 444 phy->ops.set_page = e1000_set_page_igp; 445 phy->ops.read_reg = e1000_read_phy_reg_hv; 446 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 447 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 448 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 449 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 450 phy->ops.write_reg = e1000_write_phy_reg_hv; 451 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 452 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 453 phy->ops.power_up = e1000_power_up_phy_copper; 454 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 455 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 456 457 phy->id = e1000_phy_unknown; 458 459 ret_val = e1000_init_phy_workarounds_pchlan(hw); 460 if (ret_val) 461 return ret_val; 462 463 if (phy->id == e1000_phy_unknown) 464 switch (hw->mac.type) { 465 default: 466 ret_val = e1000e_get_phy_id(hw); 467 if (ret_val) 468 return ret_val; 469 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 470 break; 471 /* fall-through */ 472 case e1000_pch2lan: 473 case e1000_pch_lpt: 474 case e1000_pch_spt: 475 /* In case the PHY needs to be in mdio slow mode, 476 * set slow mode and try to get the PHY id again. 477 */ 478 ret_val = e1000_set_mdio_slow_mode_hv(hw); 479 if (ret_val) 480 return ret_val; 481 ret_val = e1000e_get_phy_id(hw); 482 if (ret_val) 483 return ret_val; 484 break; 485 } 486 phy->type = e1000e_get_phy_type_from_id(phy->id); 487 488 switch (phy->type) { 489 case e1000_phy_82577: 490 case e1000_phy_82579: 491 case e1000_phy_i217: 492 phy->ops.check_polarity = e1000_check_polarity_82577; 493 phy->ops.force_speed_duplex = 494 e1000_phy_force_speed_duplex_82577; 495 phy->ops.get_cable_length = e1000_get_cable_length_82577; 496 phy->ops.get_info = e1000_get_phy_info_82577; 497 phy->ops.commit = e1000e_phy_sw_reset; 498 break; 499 case e1000_phy_82578: 500 phy->ops.check_polarity = e1000_check_polarity_m88; 501 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 502 phy->ops.get_cable_length = e1000e_get_cable_length_m88; 503 phy->ops.get_info = e1000e_get_phy_info_m88; 504 break; 505 default: 506 ret_val = -E1000_ERR_PHY; 507 break; 508 } 509 510 return ret_val; 511 } 512 513 /** 514 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 515 * @hw: pointer to the HW structure 516 * 517 * Initialize family-specific PHY parameters and function pointers. 518 **/ 519 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 520 { 521 struct e1000_phy_info *phy = &hw->phy; 522 s32 ret_val; 523 u16 i = 0; 524 525 phy->addr = 1; 526 phy->reset_delay_us = 100; 527 528 phy->ops.power_up = e1000_power_up_phy_copper; 529 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 530 531 /* We may need to do this twice - once for IGP and if that fails, 532 * we'll set BM func pointers and try again 533 */ 534 ret_val = e1000e_determine_phy_address(hw); 535 if (ret_val) { 536 phy->ops.write_reg = e1000e_write_phy_reg_bm; 537 phy->ops.read_reg = e1000e_read_phy_reg_bm; 538 ret_val = e1000e_determine_phy_address(hw); 539 if (ret_val) { 540 e_dbg("Cannot determine PHY addr. Erroring out\n"); 541 return ret_val; 542 } 543 } 544 545 phy->id = 0; 546 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && 547 (i++ < 100)) { 548 usleep_range(1000, 2000); 549 ret_val = e1000e_get_phy_id(hw); 550 if (ret_val) 551 return ret_val; 552 } 553 554 /* Verify phy id */ 555 switch (phy->id) { 556 case IGP03E1000_E_PHY_ID: 557 phy->type = e1000_phy_igp_3; 558 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 559 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; 560 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; 561 phy->ops.get_info = e1000e_get_phy_info_igp; 562 phy->ops.check_polarity = e1000_check_polarity_igp; 563 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; 564 break; 565 case IFE_E_PHY_ID: 566 case IFE_PLUS_E_PHY_ID: 567 case IFE_C_E_PHY_ID: 568 phy->type = e1000_phy_ife; 569 phy->autoneg_mask = E1000_ALL_NOT_GIG; 570 phy->ops.get_info = e1000_get_phy_info_ife; 571 phy->ops.check_polarity = e1000_check_polarity_ife; 572 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 573 break; 574 case BME1000_E_PHY_ID: 575 phy->type = e1000_phy_bm; 576 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 577 phy->ops.read_reg = e1000e_read_phy_reg_bm; 578 phy->ops.write_reg = e1000e_write_phy_reg_bm; 579 phy->ops.commit = e1000e_phy_sw_reset; 580 phy->ops.get_info = e1000e_get_phy_info_m88; 581 phy->ops.check_polarity = e1000_check_polarity_m88; 582 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 583 break; 584 default: 585 return -E1000_ERR_PHY; 586 } 587 588 return 0; 589 } 590 591 /** 592 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 593 * @hw: pointer to the HW structure 594 * 595 * Initialize family-specific NVM parameters and function 596 * pointers. 597 **/ 598 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 599 { 600 struct e1000_nvm_info *nvm = &hw->nvm; 601 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 602 u32 gfpreg, sector_base_addr, sector_end_addr; 603 u16 i; 604 u32 nvm_size; 605 606 nvm->type = e1000_nvm_flash_sw; 607 608 if (hw->mac.type == e1000_pch_spt) { 609 /* in SPT, gfpreg doesn't exist. NVM size is taken from the 610 * STRAP register. This is because in SPT the GbE Flash region 611 * is no longer accessed through the flash registers. Instead, 612 * the mechanism has changed, and the Flash region access 613 * registers are now implemented in GbE memory space. 614 */ 615 nvm->flash_base_addr = 0; 616 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1) 617 * NVM_SIZE_MULTIPLIER; 618 nvm->flash_bank_size = nvm_size / 2; 619 /* Adjust to word count */ 620 nvm->flash_bank_size /= sizeof(u16); 621 /* Set the base address for flash register access */ 622 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; 623 } else { 624 /* Can't read flash registers if register set isn't mapped. */ 625 if (!hw->flash_address) { 626 e_dbg("ERROR: Flash registers not mapped\n"); 627 return -E1000_ERR_CONFIG; 628 } 629 630 gfpreg = er32flash(ICH_FLASH_GFPREG); 631 632 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 633 * Add 1 to sector_end_addr since this sector is included in 634 * the overall size. 635 */ 636 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 637 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 638 639 /* flash_base_addr is byte-aligned */ 640 nvm->flash_base_addr = sector_base_addr 641 << FLASH_SECTOR_ADDR_SHIFT; 642 643 /* find total size of the NVM, then cut in half since the total 644 * size represents two separate NVM banks. 645 */ 646 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) 647 << FLASH_SECTOR_ADDR_SHIFT); 648 nvm->flash_bank_size /= 2; 649 /* Adjust to word count */ 650 nvm->flash_bank_size /= sizeof(u16); 651 } 652 653 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; 654 655 /* Clear shadow ram */ 656 for (i = 0; i < nvm->word_size; i++) { 657 dev_spec->shadow_ram[i].modified = false; 658 dev_spec->shadow_ram[i].value = 0xFFFF; 659 } 660 661 return 0; 662 } 663 664 /** 665 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 666 * @hw: pointer to the HW structure 667 * 668 * Initialize family-specific MAC parameters and function 669 * pointers. 670 **/ 671 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 672 { 673 struct e1000_mac_info *mac = &hw->mac; 674 675 /* Set media type function pointer */ 676 hw->phy.media_type = e1000_media_type_copper; 677 678 /* Set mta register count */ 679 mac->mta_reg_count = 32; 680 /* Set rar entry count */ 681 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 682 if (mac->type == e1000_ich8lan) 683 mac->rar_entry_count--; 684 /* FWSM register */ 685 mac->has_fwsm = true; 686 /* ARC subsystem not supported */ 687 mac->arc_subsystem_valid = false; 688 /* Adaptive IFS supported */ 689 mac->adaptive_ifs = true; 690 691 /* LED and other operations */ 692 switch (mac->type) { 693 case e1000_ich8lan: 694 case e1000_ich9lan: 695 case e1000_ich10lan: 696 /* check management mode */ 697 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 698 /* ID LED init */ 699 mac->ops.id_led_init = e1000e_id_led_init_generic; 700 /* blink LED */ 701 mac->ops.blink_led = e1000e_blink_led_generic; 702 /* setup LED */ 703 mac->ops.setup_led = e1000e_setup_led_generic; 704 /* cleanup LED */ 705 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 706 /* turn on/off LED */ 707 mac->ops.led_on = e1000_led_on_ich8lan; 708 mac->ops.led_off = e1000_led_off_ich8lan; 709 break; 710 case e1000_pch2lan: 711 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 712 mac->ops.rar_set = e1000_rar_set_pch2lan; 713 /* fall-through */ 714 case e1000_pch_lpt: 715 case e1000_pch_spt: 716 case e1000_pchlan: 717 /* check management mode */ 718 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 719 /* ID LED init */ 720 mac->ops.id_led_init = e1000_id_led_init_pchlan; 721 /* setup LED */ 722 mac->ops.setup_led = e1000_setup_led_pchlan; 723 /* cleanup LED */ 724 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 725 /* turn on/off LED */ 726 mac->ops.led_on = e1000_led_on_pchlan; 727 mac->ops.led_off = e1000_led_off_pchlan; 728 break; 729 default: 730 break; 731 } 732 733 if ((mac->type == e1000_pch_lpt) || (mac->type == e1000_pch_spt)) { 734 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 735 mac->ops.rar_set = e1000_rar_set_pch_lpt; 736 mac->ops.setup_physical_interface = 737 e1000_setup_copper_link_pch_lpt; 738 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt; 739 } 740 741 /* Enable PCS Lock-loss workaround for ICH8 */ 742 if (mac->type == e1000_ich8lan) 743 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); 744 745 return 0; 746 } 747 748 /** 749 * __e1000_access_emi_reg_locked - Read/write EMI register 750 * @hw: pointer to the HW structure 751 * @addr: EMI address to program 752 * @data: pointer to value to read/write from/to the EMI address 753 * @read: boolean flag to indicate read or write 754 * 755 * This helper function assumes the SW/FW/HW Semaphore is already acquired. 756 **/ 757 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 758 u16 *data, bool read) 759 { 760 s32 ret_val; 761 762 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); 763 if (ret_val) 764 return ret_val; 765 766 if (read) 767 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); 768 else 769 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); 770 771 return ret_val; 772 } 773 774 /** 775 * e1000_read_emi_reg_locked - Read Extended Management Interface register 776 * @hw: pointer to the HW structure 777 * @addr: EMI address to program 778 * @data: value to be read from the EMI address 779 * 780 * Assumes the SW/FW/HW Semaphore is already acquired. 781 **/ 782 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 783 { 784 return __e1000_access_emi_reg_locked(hw, addr, data, true); 785 } 786 787 /** 788 * e1000_write_emi_reg_locked - Write Extended Management Interface register 789 * @hw: pointer to the HW structure 790 * @addr: EMI address to program 791 * @data: value to be written to the EMI address 792 * 793 * Assumes the SW/FW/HW Semaphore is already acquired. 794 **/ 795 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 796 { 797 return __e1000_access_emi_reg_locked(hw, addr, &data, false); 798 } 799 800 /** 801 * e1000_set_eee_pchlan - Enable/disable EEE support 802 * @hw: pointer to the HW structure 803 * 804 * Enable/disable EEE based on setting in dev_spec structure, the duplex of 805 * the link and the EEE capabilities of the link partner. The LPI Control 806 * register bits will remain set only if/when link is up. 807 * 808 * EEE LPI must not be asserted earlier than one second after link is up. 809 * On 82579, EEE LPI should not be enabled until such time otherwise there 810 * can be link issues with some switches. Other devices can have EEE LPI 811 * enabled immediately upon link up since they have a timer in hardware which 812 * prevents LPI from being asserted too early. 813 **/ 814 s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 815 { 816 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 817 s32 ret_val; 818 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; 819 820 switch (hw->phy.type) { 821 case e1000_phy_82579: 822 lpa = I82579_EEE_LP_ABILITY; 823 pcs_status = I82579_EEE_PCS_STATUS; 824 adv_addr = I82579_EEE_ADVERTISEMENT; 825 break; 826 case e1000_phy_i217: 827 lpa = I217_EEE_LP_ABILITY; 828 pcs_status = I217_EEE_PCS_STATUS; 829 adv_addr = I217_EEE_ADVERTISEMENT; 830 break; 831 default: 832 return 0; 833 } 834 835 ret_val = hw->phy.ops.acquire(hw); 836 if (ret_val) 837 return ret_val; 838 839 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 840 if (ret_val) 841 goto release; 842 843 /* Clear bits that enable EEE in various speeds */ 844 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 845 846 /* Enable EEE if not disabled by user */ 847 if (!dev_spec->eee_disable) { 848 /* Save off link partner's EEE ability */ 849 ret_val = e1000_read_emi_reg_locked(hw, lpa, 850 &dev_spec->eee_lp_ability); 851 if (ret_val) 852 goto release; 853 854 /* Read EEE advertisement */ 855 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); 856 if (ret_val) 857 goto release; 858 859 /* Enable EEE only for speeds in which the link partner is 860 * EEE capable and for which we advertise EEE. 861 */ 862 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 863 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 864 865 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 866 e1e_rphy_locked(hw, MII_LPA, &data); 867 if (data & LPA_100FULL) 868 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 869 else 870 /* EEE is not supported in 100Half, so ignore 871 * partner's EEE in 100 ability if full-duplex 872 * is not advertised. 873 */ 874 dev_spec->eee_lp_ability &= 875 ~I82579_EEE_100_SUPPORTED; 876 } 877 } 878 879 if (hw->phy.type == e1000_phy_82579) { 880 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 881 &data); 882 if (ret_val) 883 goto release; 884 885 data &= ~I82579_LPI_100_PLL_SHUT; 886 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 887 data); 888 } 889 890 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 891 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 892 if (ret_val) 893 goto release; 894 895 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 896 release: 897 hw->phy.ops.release(hw); 898 899 return ret_val; 900 } 901 902 /** 903 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 904 * @hw: pointer to the HW structure 905 * @link: link up bool flag 906 * 907 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 908 * preventing further DMA write requests. Workaround the issue by disabling 909 * the de-assertion of the clock request when in 1Gpbs mode. 910 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 911 * speeds in order to avoid Tx hangs. 912 **/ 913 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) 914 { 915 u32 fextnvm6 = er32(FEXTNVM6); 916 u32 status = er32(STATUS); 917 s32 ret_val = 0; 918 u16 reg; 919 920 if (link && (status & E1000_STATUS_SPEED_1000)) { 921 ret_val = hw->phy.ops.acquire(hw); 922 if (ret_val) 923 return ret_val; 924 925 ret_val = 926 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 927 ®); 928 if (ret_val) 929 goto release; 930 931 ret_val = 932 e1000e_write_kmrn_reg_locked(hw, 933 E1000_KMRNCTRLSTA_K1_CONFIG, 934 reg & 935 ~E1000_KMRNCTRLSTA_K1_ENABLE); 936 if (ret_val) 937 goto release; 938 939 usleep_range(10, 20); 940 941 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 942 943 ret_val = 944 e1000e_write_kmrn_reg_locked(hw, 945 E1000_KMRNCTRLSTA_K1_CONFIG, 946 reg); 947 release: 948 hw->phy.ops.release(hw); 949 } else { 950 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 951 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 952 953 if ((hw->phy.revision > 5) || !link || 954 ((status & E1000_STATUS_SPEED_100) && 955 (status & E1000_STATUS_FD))) 956 goto update_fextnvm6; 957 958 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®); 959 if (ret_val) 960 return ret_val; 961 962 /* Clear link status transmit timeout */ 963 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 964 965 if (status & E1000_STATUS_SPEED_100) { 966 /* Set inband Tx timeout to 5x10us for 100Half */ 967 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 968 969 /* Do not extend the K1 entry latency for 100Half */ 970 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 971 } else { 972 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 973 reg |= 50 << 974 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 975 976 /* Extend the K1 entry latency for 10 Mbps */ 977 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 978 } 979 980 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg); 981 if (ret_val) 982 return ret_val; 983 984 update_fextnvm6: 985 ew32(FEXTNVM6, fextnvm6); 986 } 987 988 return ret_val; 989 } 990 991 /** 992 * e1000_platform_pm_pch_lpt - Set platform power management values 993 * @hw: pointer to the HW structure 994 * @link: bool indicating link status 995 * 996 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" 997 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed 998 * when link is up (which must not exceed the maximum latency supported 999 * by the platform), otherwise specify there is no LTR requirement. 1000 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop 1001 * latencies in the LTR Extended Capability Structure in the PCIe Extended 1002 * Capability register set, on this device LTR is set by writing the 1003 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and 1004 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) 1005 * message to the PMC. 1006 **/ 1007 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 1008 { 1009 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | 1010 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; 1011 u16 lat_enc = 0; /* latency encoded */ 1012 1013 if (link) { 1014 u16 speed, duplex, scale = 0; 1015 u16 max_snoop, max_nosnoop; 1016 u16 max_ltr_enc; /* max LTR latency encoded */ 1017 u64 value; 1018 u32 rxa; 1019 1020 if (!hw->adapter->max_frame_size) { 1021 e_dbg("max_frame_size not set.\n"); 1022 return -E1000_ERR_CONFIG; 1023 } 1024 1025 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 1026 if (!speed) { 1027 e_dbg("Speed not set.\n"); 1028 return -E1000_ERR_CONFIG; 1029 } 1030 1031 /* Rx Packet Buffer Allocation size (KB) */ 1032 rxa = er32(PBA) & E1000_PBA_RXA_MASK; 1033 1034 /* Determine the maximum latency tolerated by the device. 1035 * 1036 * Per the PCIe spec, the tolerated latencies are encoded as 1037 * a 3-bit encoded scale (only 0-5 are valid) multiplied by 1038 * a 10-bit value (0-1023) to provide a range from 1 ns to 1039 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, 1040 * 1=2^5ns, 2=2^10ns,...5=2^25ns. 1041 */ 1042 rxa *= 512; 1043 value = (rxa > hw->adapter->max_frame_size) ? 1044 (rxa - hw->adapter->max_frame_size) * (16000 / speed) : 1045 0; 1046 1047 while (value > PCI_LTR_VALUE_MASK) { 1048 scale++; 1049 value = DIV_ROUND_UP(value, (1 << 5)); 1050 } 1051 if (scale > E1000_LTRV_SCALE_MAX) { 1052 e_dbg("Invalid LTR latency scale %d\n", scale); 1053 return -E1000_ERR_CONFIG; 1054 } 1055 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value); 1056 1057 /* Determine the maximum latency tolerated by the platform */ 1058 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, 1059 &max_snoop); 1060 pci_read_config_word(hw->adapter->pdev, 1061 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); 1062 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop); 1063 1064 if (lat_enc > max_ltr_enc) 1065 lat_enc = max_ltr_enc; 1066 } 1067 1068 /* Set Snoop and No-Snoop latencies the same */ 1069 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); 1070 ew32(LTRV, reg); 1071 1072 return 0; 1073 } 1074 1075 /** 1076 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP 1077 * @hw: pointer to the HW structure 1078 * @to_sx: boolean indicating a system power state transition to Sx 1079 * 1080 * When link is down, configure ULP mode to significantly reduce the power 1081 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the 1082 * ME firmware to start the ULP configuration. If not on an ME enabled 1083 * system, configure the ULP mode by software. 1084 */ 1085 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) 1086 { 1087 u32 mac_reg; 1088 s32 ret_val = 0; 1089 u16 phy_reg; 1090 1091 if ((hw->mac.type < e1000_pch_lpt) || 1092 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1093 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1094 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1095 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1096 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) 1097 return 0; 1098 1099 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1100 /* Request ME configure ULP mode in the PHY */ 1101 mac_reg = er32(H2ME); 1102 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS; 1103 ew32(H2ME, mac_reg); 1104 1105 goto out; 1106 } 1107 1108 if (!to_sx) { 1109 int i = 0; 1110 1111 /* Poll up to 5 seconds for Cable Disconnected indication */ 1112 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) { 1113 /* Bail if link is re-acquired */ 1114 if (er32(STATUS) & E1000_STATUS_LU) 1115 return -E1000_ERR_PHY; 1116 1117 if (i++ == 100) 1118 break; 1119 1120 msleep(50); 1121 } 1122 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n", 1123 (er32(FEXT) & 1124 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50); 1125 } 1126 1127 ret_val = hw->phy.ops.acquire(hw); 1128 if (ret_val) 1129 goto out; 1130 1131 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable 1132 * LPLU and disable Gig speed when entering ULP 1133 */ 1134 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { 1135 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, 1136 &phy_reg); 1137 if (ret_val) 1138 goto release; 1139 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS; 1140 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1141 phy_reg); 1142 if (ret_val) 1143 goto release; 1144 } 1145 1146 /* Force SMBus mode in PHY */ 1147 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1148 if (ret_val) 1149 goto release; 1150 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS; 1151 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1152 1153 /* Force SMBus mode in MAC */ 1154 mac_reg = er32(CTRL_EXT); 1155 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1156 ew32(CTRL_EXT, mac_reg); 1157 1158 /* Set Inband ULP Exit, Reset to SMBus mode and 1159 * Disable SMBus Release on PERST# in PHY 1160 */ 1161 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1162 if (ret_val) 1163 goto release; 1164 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS | 1165 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1166 if (to_sx) { 1167 if (er32(WUFC) & E1000_WUFC_LNKC) 1168 phy_reg |= I218_ULP_CONFIG1_WOL_HOST; 1169 1170 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP; 1171 } else { 1172 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT; 1173 } 1174 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1175 1176 /* Set Disable SMBus Release on PERST# in MAC */ 1177 mac_reg = er32(FEXTNVM7); 1178 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST; 1179 ew32(FEXTNVM7, mac_reg); 1180 1181 /* Commit ULP changes in PHY by starting auto ULP configuration */ 1182 phy_reg |= I218_ULP_CONFIG1_START; 1183 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1184 release: 1185 hw->phy.ops.release(hw); 1186 out: 1187 if (ret_val) 1188 e_dbg("Error in ULP enable flow: %d\n", ret_val); 1189 else 1190 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; 1191 1192 return ret_val; 1193 } 1194 1195 /** 1196 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1197 * @hw: pointer to the HW structure 1198 * @force: boolean indicating whether or not to force disabling ULP 1199 * 1200 * Un-configure ULP mode when link is up, the system is transitioned from 1201 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1202 * system, poll for an indication from ME that ULP has been un-configured. 1203 * If not on an ME enabled system, un-configure the ULP mode by software. 1204 * 1205 * During nominal operation, this function is called when link is acquired 1206 * to disable ULP mode (force=false); otherwise, for example when unloading 1207 * the driver or during Sx->S0 transitions, this is called with force=true 1208 * to forcibly disable ULP. 1209 */ 1210 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) 1211 { 1212 s32 ret_val = 0; 1213 u32 mac_reg; 1214 u16 phy_reg; 1215 int i = 0; 1216 1217 if ((hw->mac.type < e1000_pch_lpt) || 1218 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1219 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1220 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1221 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1222 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) 1223 return 0; 1224 1225 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1226 if (force) { 1227 /* Request ME un-configure ULP mode in the PHY */ 1228 mac_reg = er32(H2ME); 1229 mac_reg &= ~E1000_H2ME_ULP; 1230 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1231 ew32(H2ME, mac_reg); 1232 } 1233 1234 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */ 1235 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) { 1236 if (i++ == 10) { 1237 ret_val = -E1000_ERR_PHY; 1238 goto out; 1239 } 1240 1241 usleep_range(10000, 20000); 1242 } 1243 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10); 1244 1245 if (force) { 1246 mac_reg = er32(H2ME); 1247 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1248 ew32(H2ME, mac_reg); 1249 } else { 1250 /* Clear H2ME.ULP after ME ULP configuration */ 1251 mac_reg = er32(H2ME); 1252 mac_reg &= ~E1000_H2ME_ULP; 1253 ew32(H2ME, mac_reg); 1254 } 1255 1256 goto out; 1257 } 1258 1259 ret_val = hw->phy.ops.acquire(hw); 1260 if (ret_val) 1261 goto out; 1262 1263 if (force) 1264 /* Toggle LANPHYPC Value bit */ 1265 e1000_toggle_lanphypc_pch_lpt(hw); 1266 1267 /* Unforce SMBus mode in PHY */ 1268 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1269 if (ret_val) { 1270 /* The MAC might be in PCIe mode, so temporarily force to 1271 * SMBus mode in order to access the PHY. 1272 */ 1273 mac_reg = er32(CTRL_EXT); 1274 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1275 ew32(CTRL_EXT, mac_reg); 1276 1277 msleep(50); 1278 1279 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, 1280 &phy_reg); 1281 if (ret_val) 1282 goto release; 1283 } 1284 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1285 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1286 1287 /* Unforce SMBus mode in MAC */ 1288 mac_reg = er32(CTRL_EXT); 1289 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1290 ew32(CTRL_EXT, mac_reg); 1291 1292 /* When ULP mode was previously entered, K1 was disabled by the 1293 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1294 */ 1295 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); 1296 if (ret_val) 1297 goto release; 1298 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1299 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); 1300 1301 /* Clear ULP enabled configuration */ 1302 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1303 if (ret_val) 1304 goto release; 1305 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1306 I218_ULP_CONFIG1_STICKY_ULP | 1307 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1308 I218_ULP_CONFIG1_WOL_HOST | 1309 I218_ULP_CONFIG1_INBAND_EXIT | 1310 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1311 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1312 1313 /* Commit ULP changes by starting auto ULP configuration */ 1314 phy_reg |= I218_ULP_CONFIG1_START; 1315 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1316 1317 /* Clear Disable SMBus Release on PERST# in MAC */ 1318 mac_reg = er32(FEXTNVM7); 1319 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1320 ew32(FEXTNVM7, mac_reg); 1321 1322 release: 1323 hw->phy.ops.release(hw); 1324 if (force) { 1325 e1000_phy_hw_reset(hw); 1326 msleep(50); 1327 } 1328 out: 1329 if (ret_val) 1330 e_dbg("Error in ULP disable flow: %d\n", ret_val); 1331 else 1332 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; 1333 1334 return ret_val; 1335 } 1336 1337 /** 1338 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 1339 * @hw: pointer to the HW structure 1340 * 1341 * Checks to see of the link status of the hardware has changed. If a 1342 * change in link status has been detected, then we read the PHY registers 1343 * to get the current speed/duplex if link exists. 1344 **/ 1345 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 1346 { 1347 struct e1000_mac_info *mac = &hw->mac; 1348 s32 ret_val, tipg_reg = 0; 1349 u16 emi_addr, emi_val = 0; 1350 bool link; 1351 u16 phy_reg; 1352 1353 /* We only want to go out to the PHY registers to see if Auto-Neg 1354 * has completed and/or if our link status has changed. The 1355 * get_link_status flag is set upon receiving a Link Status 1356 * Change or Rx Sequence Error interrupt. 1357 */ 1358 if (!mac->get_link_status) 1359 return 0; 1360 1361 /* First we want to see if the MII Status Register reports 1362 * link. If so, then we want to get the current speed/duplex 1363 * of the PHY. 1364 */ 1365 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1366 if (ret_val) 1367 return ret_val; 1368 1369 if (hw->mac.type == e1000_pchlan) { 1370 ret_val = e1000_k1_gig_workaround_hv(hw, link); 1371 if (ret_val) 1372 return ret_val; 1373 } 1374 1375 /* When connected at 10Mbps half-duplex, some parts are excessively 1376 * aggressive resulting in many collisions. To avoid this, increase 1377 * the IPG and reduce Rx latency in the PHY. 1378 */ 1379 if (((hw->mac.type == e1000_pch2lan) || 1380 (hw->mac.type == e1000_pch_lpt) || 1381 (hw->mac.type == e1000_pch_spt)) && link) { 1382 u32 reg; 1383 1384 reg = er32(STATUS); 1385 tipg_reg = er32(TIPG); 1386 tipg_reg &= ~E1000_TIPG_IPGT_MASK; 1387 1388 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) { 1389 tipg_reg |= 0xFF; 1390 /* Reduce Rx latency in analog PHY */ 1391 emi_val = 0; 1392 } else { 1393 1394 /* Roll back the default values */ 1395 tipg_reg |= 0x08; 1396 emi_val = 1; 1397 } 1398 1399 ew32(TIPG, tipg_reg); 1400 1401 ret_val = hw->phy.ops.acquire(hw); 1402 if (ret_val) 1403 return ret_val; 1404 1405 if (hw->mac.type == e1000_pch2lan) 1406 emi_addr = I82579_RX_CONFIG; 1407 else 1408 emi_addr = I217_RX_CONFIG; 1409 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); 1410 1411 hw->phy.ops.release(hw); 1412 1413 if (ret_val) 1414 return ret_val; 1415 } 1416 1417 /* Work-around I218 hang issue */ 1418 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 1419 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || 1420 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || 1421 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3) || 1422 (hw->mac.type == e1000_pch_spt)) { 1423 ret_val = e1000_k1_workaround_lpt_lp(hw, link); 1424 if (ret_val) 1425 return ret_val; 1426 } 1427 if ((hw->mac.type == e1000_pch_lpt) || 1428 (hw->mac.type == e1000_pch_spt)) { 1429 /* Set platform power management values for 1430 * Latency Tolerance Reporting (LTR) 1431 */ 1432 ret_val = e1000_platform_pm_pch_lpt(hw, link); 1433 if (ret_val) 1434 return ret_val; 1435 } 1436 1437 /* Clear link partner's EEE ability */ 1438 hw->dev_spec.ich8lan.eee_lp_ability = 0; 1439 1440 /* FEXTNVM6 K1-off workaround */ 1441 if (hw->mac.type == e1000_pch_spt) { 1442 u32 pcieanacfg = er32(PCIEANACFG); 1443 u32 fextnvm6 = er32(FEXTNVM6); 1444 1445 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) 1446 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE; 1447 else 1448 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE; 1449 1450 ew32(FEXTNVM6, fextnvm6); 1451 } 1452 1453 if (!link) 1454 return 0; /* No link detected */ 1455 1456 mac->get_link_status = false; 1457 1458 switch (hw->mac.type) { 1459 case e1000_pch2lan: 1460 ret_val = e1000_k1_workaround_lv(hw); 1461 if (ret_val) 1462 return ret_val; 1463 /* fall-thru */ 1464 case e1000_pchlan: 1465 if (hw->phy.type == e1000_phy_82578) { 1466 ret_val = e1000_link_stall_workaround_hv(hw); 1467 if (ret_val) 1468 return ret_val; 1469 } 1470 1471 /* Workaround for PCHx parts in half-duplex: 1472 * Set the number of preambles removed from the packet 1473 * when it is passed from the PHY to the MAC to prevent 1474 * the MAC from misinterpreting the packet type. 1475 */ 1476 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 1477 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1478 1479 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) 1480 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1481 1482 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1483 break; 1484 default: 1485 break; 1486 } 1487 1488 /* Check if there was DownShift, must be checked 1489 * immediately after link-up 1490 */ 1491 e1000e_check_downshift(hw); 1492 1493 /* Enable/Disable EEE after link up */ 1494 if (hw->phy.type > e1000_phy_82579) { 1495 ret_val = e1000_set_eee_pchlan(hw); 1496 if (ret_val) 1497 return ret_val; 1498 } 1499 1500 /* If we are forcing speed/duplex, then we simply return since 1501 * we have already determined whether we have link or not. 1502 */ 1503 if (!mac->autoneg) 1504 return -E1000_ERR_CONFIG; 1505 1506 /* Auto-Neg is enabled. Auto Speed Detection takes care 1507 * of MAC speed/duplex configuration. So we only need to 1508 * configure Collision Distance in the MAC. 1509 */ 1510 mac->ops.config_collision_dist(hw); 1511 1512 /* Configure Flow Control now that Auto-Neg has completed. 1513 * First, we need to restore the desired flow control 1514 * settings because we may have had to re-autoneg with a 1515 * different link partner. 1516 */ 1517 ret_val = e1000e_config_fc_after_link_up(hw); 1518 if (ret_val) 1519 e_dbg("Error configuring flow control\n"); 1520 1521 return ret_val; 1522 } 1523 1524 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) 1525 { 1526 struct e1000_hw *hw = &adapter->hw; 1527 s32 rc; 1528 1529 rc = e1000_init_mac_params_ich8lan(hw); 1530 if (rc) 1531 return rc; 1532 1533 rc = e1000_init_nvm_params_ich8lan(hw); 1534 if (rc) 1535 return rc; 1536 1537 switch (hw->mac.type) { 1538 case e1000_ich8lan: 1539 case e1000_ich9lan: 1540 case e1000_ich10lan: 1541 rc = e1000_init_phy_params_ich8lan(hw); 1542 break; 1543 case e1000_pchlan: 1544 case e1000_pch2lan: 1545 case e1000_pch_lpt: 1546 case e1000_pch_spt: 1547 rc = e1000_init_phy_params_pchlan(hw); 1548 break; 1549 default: 1550 break; 1551 } 1552 if (rc) 1553 return rc; 1554 1555 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or 1556 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). 1557 */ 1558 if ((adapter->hw.phy.type == e1000_phy_ife) || 1559 ((adapter->hw.mac.type >= e1000_pch2lan) && 1560 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { 1561 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; 1562 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 1563 1564 hw->mac.ops.blink_led = NULL; 1565 } 1566 1567 if ((adapter->hw.mac.type == e1000_ich8lan) && 1568 (adapter->hw.phy.type != e1000_phy_ife)) 1569 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; 1570 1571 /* Enable workaround for 82579 w/ ME enabled */ 1572 if ((adapter->hw.mac.type == e1000_pch2lan) && 1573 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 1574 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; 1575 1576 return 0; 1577 } 1578 1579 static DEFINE_MUTEX(nvm_mutex); 1580 1581 /** 1582 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 1583 * @hw: pointer to the HW structure 1584 * 1585 * Acquires the mutex for performing NVM operations. 1586 **/ 1587 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1588 { 1589 mutex_lock(&nvm_mutex); 1590 1591 return 0; 1592 } 1593 1594 /** 1595 * e1000_release_nvm_ich8lan - Release NVM mutex 1596 * @hw: pointer to the HW structure 1597 * 1598 * Releases the mutex used while performing NVM operations. 1599 **/ 1600 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1601 { 1602 mutex_unlock(&nvm_mutex); 1603 } 1604 1605 /** 1606 * e1000_acquire_swflag_ich8lan - Acquire software control flag 1607 * @hw: pointer to the HW structure 1608 * 1609 * Acquires the software control flag for performing PHY and select 1610 * MAC CSR accesses. 1611 **/ 1612 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 1613 { 1614 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 1615 s32 ret_val = 0; 1616 1617 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, 1618 &hw->adapter->state)) { 1619 e_dbg("contention for Phy access\n"); 1620 return -E1000_ERR_PHY; 1621 } 1622 1623 while (timeout) { 1624 extcnf_ctrl = er32(EXTCNF_CTRL); 1625 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 1626 break; 1627 1628 mdelay(1); 1629 timeout--; 1630 } 1631 1632 if (!timeout) { 1633 e_dbg("SW has already locked the resource.\n"); 1634 ret_val = -E1000_ERR_CONFIG; 1635 goto out; 1636 } 1637 1638 timeout = SW_FLAG_TIMEOUT; 1639 1640 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 1641 ew32(EXTCNF_CTRL, extcnf_ctrl); 1642 1643 while (timeout) { 1644 extcnf_ctrl = er32(EXTCNF_CTRL); 1645 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 1646 break; 1647 1648 mdelay(1); 1649 timeout--; 1650 } 1651 1652 if (!timeout) { 1653 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 1654 er32(FWSM), extcnf_ctrl); 1655 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1656 ew32(EXTCNF_CTRL, extcnf_ctrl); 1657 ret_val = -E1000_ERR_CONFIG; 1658 goto out; 1659 } 1660 1661 out: 1662 if (ret_val) 1663 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1664 1665 return ret_val; 1666 } 1667 1668 /** 1669 * e1000_release_swflag_ich8lan - Release software control flag 1670 * @hw: pointer to the HW structure 1671 * 1672 * Releases the software control flag for performing PHY and select 1673 * MAC CSR accesses. 1674 **/ 1675 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 1676 { 1677 u32 extcnf_ctrl; 1678 1679 extcnf_ctrl = er32(EXTCNF_CTRL); 1680 1681 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 1682 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1683 ew32(EXTCNF_CTRL, extcnf_ctrl); 1684 } else { 1685 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); 1686 } 1687 1688 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1689 } 1690 1691 /** 1692 * e1000_check_mng_mode_ich8lan - Checks management mode 1693 * @hw: pointer to the HW structure 1694 * 1695 * This checks if the adapter has any manageability enabled. 1696 * This is a function pointer entry point only called by read/write 1697 * routines for the PHY and NVM parts. 1698 **/ 1699 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 1700 { 1701 u32 fwsm; 1702 1703 fwsm = er32(FWSM); 1704 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1705 ((fwsm & E1000_FWSM_MODE_MASK) == 1706 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1707 } 1708 1709 /** 1710 * e1000_check_mng_mode_pchlan - Checks management mode 1711 * @hw: pointer to the HW structure 1712 * 1713 * This checks if the adapter has iAMT enabled. 1714 * This is a function pointer entry point only called by read/write 1715 * routines for the PHY and NVM parts. 1716 **/ 1717 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 1718 { 1719 u32 fwsm; 1720 1721 fwsm = er32(FWSM); 1722 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1723 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1724 } 1725 1726 /** 1727 * e1000_rar_set_pch2lan - Set receive address register 1728 * @hw: pointer to the HW structure 1729 * @addr: pointer to the receive address 1730 * @index: receive address array register 1731 * 1732 * Sets the receive address array register at index to the address passed 1733 * in by addr. For 82579, RAR[0] is the base address register that is to 1734 * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 1735 * Use SHRA[0-3] in place of those reserved for ME. 1736 **/ 1737 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 1738 { 1739 u32 rar_low, rar_high; 1740 1741 /* HW expects these in little endian so we reverse the byte order 1742 * from network order (big endian) to little endian 1743 */ 1744 rar_low = ((u32)addr[0] | 1745 ((u32)addr[1] << 8) | 1746 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1747 1748 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1749 1750 /* If MAC address zero, no need to set the AV bit */ 1751 if (rar_low || rar_high) 1752 rar_high |= E1000_RAH_AV; 1753 1754 if (index == 0) { 1755 ew32(RAL(index), rar_low); 1756 e1e_flush(); 1757 ew32(RAH(index), rar_high); 1758 e1e_flush(); 1759 return 0; 1760 } 1761 1762 /* RAR[1-6] are owned by manageability. Skip those and program the 1763 * next address into the SHRA register array. 1764 */ 1765 if (index < (u32)(hw->mac.rar_entry_count)) { 1766 s32 ret_val; 1767 1768 ret_val = e1000_acquire_swflag_ich8lan(hw); 1769 if (ret_val) 1770 goto out; 1771 1772 ew32(SHRAL(index - 1), rar_low); 1773 e1e_flush(); 1774 ew32(SHRAH(index - 1), rar_high); 1775 e1e_flush(); 1776 1777 e1000_release_swflag_ich8lan(hw); 1778 1779 /* verify the register updates */ 1780 if ((er32(SHRAL(index - 1)) == rar_low) && 1781 (er32(SHRAH(index - 1)) == rar_high)) 1782 return 0; 1783 1784 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 1785 (index - 1), er32(FWSM)); 1786 } 1787 1788 out: 1789 e_dbg("Failed to write receive address at index %d\n", index); 1790 return -E1000_ERR_CONFIG; 1791 } 1792 1793 /** 1794 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA 1795 * @hw: pointer to the HW structure 1796 * 1797 * Get the number of available receive registers that the Host can 1798 * program. SHRA[0-10] are the shared receive address registers 1799 * that are shared between the Host and manageability engine (ME). 1800 * ME can reserve any number of addresses and the host needs to be 1801 * able to tell how many available registers it has access to. 1802 **/ 1803 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw) 1804 { 1805 u32 wlock_mac; 1806 u32 num_entries; 1807 1808 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 1809 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 1810 1811 switch (wlock_mac) { 1812 case 0: 1813 /* All SHRA[0..10] and RAR[0] available */ 1814 num_entries = hw->mac.rar_entry_count; 1815 break; 1816 case 1: 1817 /* Only RAR[0] available */ 1818 num_entries = 1; 1819 break; 1820 default: 1821 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */ 1822 num_entries = wlock_mac + 1; 1823 break; 1824 } 1825 1826 return num_entries; 1827 } 1828 1829 /** 1830 * e1000_rar_set_pch_lpt - Set receive address registers 1831 * @hw: pointer to the HW structure 1832 * @addr: pointer to the receive address 1833 * @index: receive address array register 1834 * 1835 * Sets the receive address register array at index to the address passed 1836 * in by addr. For LPT, RAR[0] is the base address register that is to 1837 * contain the MAC address. SHRA[0-10] are the shared receive address 1838 * registers that are shared between the Host and manageability engine (ME). 1839 **/ 1840 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) 1841 { 1842 u32 rar_low, rar_high; 1843 u32 wlock_mac; 1844 1845 /* HW expects these in little endian so we reverse the byte order 1846 * from network order (big endian) to little endian 1847 */ 1848 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 1849 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1850 1851 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1852 1853 /* If MAC address zero, no need to set the AV bit */ 1854 if (rar_low || rar_high) 1855 rar_high |= E1000_RAH_AV; 1856 1857 if (index == 0) { 1858 ew32(RAL(index), rar_low); 1859 e1e_flush(); 1860 ew32(RAH(index), rar_high); 1861 e1e_flush(); 1862 return 0; 1863 } 1864 1865 /* The manageability engine (ME) can lock certain SHRAR registers that 1866 * it is using - those registers are unavailable for use. 1867 */ 1868 if (index < hw->mac.rar_entry_count) { 1869 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 1870 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 1871 1872 /* Check if all SHRAR registers are locked */ 1873 if (wlock_mac == 1) 1874 goto out; 1875 1876 if ((wlock_mac == 0) || (index <= wlock_mac)) { 1877 s32 ret_val; 1878 1879 ret_val = e1000_acquire_swflag_ich8lan(hw); 1880 1881 if (ret_val) 1882 goto out; 1883 1884 ew32(SHRAL_PCH_LPT(index - 1), rar_low); 1885 e1e_flush(); 1886 ew32(SHRAH_PCH_LPT(index - 1), rar_high); 1887 e1e_flush(); 1888 1889 e1000_release_swflag_ich8lan(hw); 1890 1891 /* verify the register updates */ 1892 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && 1893 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) 1894 return 0; 1895 } 1896 } 1897 1898 out: 1899 e_dbg("Failed to write receive address at index %d\n", index); 1900 return -E1000_ERR_CONFIG; 1901 } 1902 1903 /** 1904 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 1905 * @hw: pointer to the HW structure 1906 * 1907 * Checks if firmware is blocking the reset of the PHY. 1908 * This is a function pointer entry point only called by 1909 * reset routines. 1910 **/ 1911 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 1912 { 1913 bool blocked = false; 1914 int i = 0; 1915 1916 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) && 1917 (i++ < 10)) 1918 usleep_range(10000, 20000); 1919 return blocked ? E1000_BLK_PHY_RESET : 0; 1920 } 1921 1922 /** 1923 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 1924 * @hw: pointer to the HW structure 1925 * 1926 * Assumes semaphore already acquired. 1927 * 1928 **/ 1929 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) 1930 { 1931 u16 phy_data; 1932 u32 strap = er32(STRAP); 1933 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> 1934 E1000_STRAP_SMT_FREQ_SHIFT; 1935 s32 ret_val; 1936 1937 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 1938 1939 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 1940 if (ret_val) 1941 return ret_val; 1942 1943 phy_data &= ~HV_SMB_ADDR_MASK; 1944 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 1945 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 1946 1947 if (hw->phy.type == e1000_phy_i217) { 1948 /* Restore SMBus frequency */ 1949 if (freq--) { 1950 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 1951 phy_data |= (freq & (1 << 0)) << 1952 HV_SMB_ADDR_FREQ_LOW_SHIFT; 1953 phy_data |= (freq & (1 << 1)) << 1954 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 1955 } else { 1956 e_dbg("Unsupported SMB frequency in PHY\n"); 1957 } 1958 } 1959 1960 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 1961 } 1962 1963 /** 1964 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 1965 * @hw: pointer to the HW structure 1966 * 1967 * SW should configure the LCD from the NVM extended configuration region 1968 * as a workaround for certain parts. 1969 **/ 1970 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 1971 { 1972 struct e1000_phy_info *phy = &hw->phy; 1973 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 1974 s32 ret_val = 0; 1975 u16 word_addr, reg_data, reg_addr, phy_page = 0; 1976 1977 /* Initialize the PHY from the NVM on ICH platforms. This 1978 * is needed due to an issue where the NVM configuration is 1979 * not properly autoloaded after power transitions. 1980 * Therefore, after each PHY reset, we will load the 1981 * configuration data out of the NVM manually. 1982 */ 1983 switch (hw->mac.type) { 1984 case e1000_ich8lan: 1985 if (phy->type != e1000_phy_igp_3) 1986 return ret_val; 1987 1988 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || 1989 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { 1990 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 1991 break; 1992 } 1993 /* Fall-thru */ 1994 case e1000_pchlan: 1995 case e1000_pch2lan: 1996 case e1000_pch_lpt: 1997 case e1000_pch_spt: 1998 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 1999 break; 2000 default: 2001 return ret_val; 2002 } 2003 2004 ret_val = hw->phy.ops.acquire(hw); 2005 if (ret_val) 2006 return ret_val; 2007 2008 data = er32(FEXTNVM); 2009 if (!(data & sw_cfg_mask)) 2010 goto release; 2011 2012 /* Make sure HW does not configure LCD from PHY 2013 * extended configuration before SW configuration 2014 */ 2015 data = er32(EXTCNF_CTRL); 2016 if ((hw->mac.type < e1000_pch2lan) && 2017 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) 2018 goto release; 2019 2020 cnf_size = er32(EXTCNF_SIZE); 2021 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 2022 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 2023 if (!cnf_size) 2024 goto release; 2025 2026 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 2027 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 2028 2029 if (((hw->mac.type == e1000_pchlan) && 2030 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 2031 (hw->mac.type > e1000_pchlan)) { 2032 /* HW configures the SMBus address and LEDs when the 2033 * OEM and LCD Write Enable bits are set in the NVM. 2034 * When both NVM bits are cleared, SW will configure 2035 * them instead. 2036 */ 2037 ret_val = e1000_write_smbus_addr(hw); 2038 if (ret_val) 2039 goto release; 2040 2041 data = er32(LEDCTL); 2042 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 2043 (u16)data); 2044 if (ret_val) 2045 goto release; 2046 } 2047 2048 /* Configure LCD from extended configuration region. */ 2049 2050 /* cnf_base_addr is in DWORD */ 2051 word_addr = (u16)(cnf_base_addr << 1); 2052 2053 for (i = 0; i < cnf_size; i++) { 2054 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data); 2055 if (ret_val) 2056 goto release; 2057 2058 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), 2059 1, ®_addr); 2060 if (ret_val) 2061 goto release; 2062 2063 /* Save off the PHY page for future writes. */ 2064 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 2065 phy_page = reg_data; 2066 continue; 2067 } 2068 2069 reg_addr &= PHY_REG_MASK; 2070 reg_addr |= phy_page; 2071 2072 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); 2073 if (ret_val) 2074 goto release; 2075 } 2076 2077 release: 2078 hw->phy.ops.release(hw); 2079 return ret_val; 2080 } 2081 2082 /** 2083 * e1000_k1_gig_workaround_hv - K1 Si workaround 2084 * @hw: pointer to the HW structure 2085 * @link: link up bool flag 2086 * 2087 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 2088 * from a lower speed. This workaround disables K1 whenever link is at 1Gig 2089 * If link is down, the function will restore the default K1 setting located 2090 * in the NVM. 2091 **/ 2092 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 2093 { 2094 s32 ret_val = 0; 2095 u16 status_reg = 0; 2096 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 2097 2098 if (hw->mac.type != e1000_pchlan) 2099 return 0; 2100 2101 /* Wrap the whole flow with the sw flag */ 2102 ret_val = hw->phy.ops.acquire(hw); 2103 if (ret_val) 2104 return ret_val; 2105 2106 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 2107 if (link) { 2108 if (hw->phy.type == e1000_phy_82578) { 2109 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, 2110 &status_reg); 2111 if (ret_val) 2112 goto release; 2113 2114 status_reg &= (BM_CS_STATUS_LINK_UP | 2115 BM_CS_STATUS_RESOLVED | 2116 BM_CS_STATUS_SPEED_MASK); 2117 2118 if (status_reg == (BM_CS_STATUS_LINK_UP | 2119 BM_CS_STATUS_RESOLVED | 2120 BM_CS_STATUS_SPEED_1000)) 2121 k1_enable = false; 2122 } 2123 2124 if (hw->phy.type == e1000_phy_82577) { 2125 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); 2126 if (ret_val) 2127 goto release; 2128 2129 status_reg &= (HV_M_STATUS_LINK_UP | 2130 HV_M_STATUS_AUTONEG_COMPLETE | 2131 HV_M_STATUS_SPEED_MASK); 2132 2133 if (status_reg == (HV_M_STATUS_LINK_UP | 2134 HV_M_STATUS_AUTONEG_COMPLETE | 2135 HV_M_STATUS_SPEED_1000)) 2136 k1_enable = false; 2137 } 2138 2139 /* Link stall fix for link up */ 2140 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); 2141 if (ret_val) 2142 goto release; 2143 2144 } else { 2145 /* Link stall fix for link down */ 2146 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); 2147 if (ret_val) 2148 goto release; 2149 } 2150 2151 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 2152 2153 release: 2154 hw->phy.ops.release(hw); 2155 2156 return ret_val; 2157 } 2158 2159 /** 2160 * e1000_configure_k1_ich8lan - Configure K1 power state 2161 * @hw: pointer to the HW structure 2162 * @enable: K1 state to configure 2163 * 2164 * Configure the K1 power state based on the provided parameter. 2165 * Assumes semaphore already acquired. 2166 * 2167 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2168 **/ 2169 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 2170 { 2171 s32 ret_val; 2172 u32 ctrl_reg = 0; 2173 u32 ctrl_ext = 0; 2174 u32 reg = 0; 2175 u16 kmrn_reg = 0; 2176 2177 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2178 &kmrn_reg); 2179 if (ret_val) 2180 return ret_val; 2181 2182 if (k1_enable) 2183 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 2184 else 2185 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 2186 2187 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2188 kmrn_reg); 2189 if (ret_val) 2190 return ret_val; 2191 2192 usleep_range(20, 40); 2193 ctrl_ext = er32(CTRL_EXT); 2194 ctrl_reg = er32(CTRL); 2195 2196 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2197 reg |= E1000_CTRL_FRCSPD; 2198 ew32(CTRL, reg); 2199 2200 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 2201 e1e_flush(); 2202 usleep_range(20, 40); 2203 ew32(CTRL, ctrl_reg); 2204 ew32(CTRL_EXT, ctrl_ext); 2205 e1e_flush(); 2206 usleep_range(20, 40); 2207 2208 return 0; 2209 } 2210 2211 /** 2212 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 2213 * @hw: pointer to the HW structure 2214 * @d0_state: boolean if entering d0 or d3 device state 2215 * 2216 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 2217 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 2218 * in NVM determines whether HW should configure LPLU and Gbe Disable. 2219 **/ 2220 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 2221 { 2222 s32 ret_val = 0; 2223 u32 mac_reg; 2224 u16 oem_reg; 2225 2226 if (hw->mac.type < e1000_pchlan) 2227 return ret_val; 2228 2229 ret_val = hw->phy.ops.acquire(hw); 2230 if (ret_val) 2231 return ret_val; 2232 2233 if (hw->mac.type == e1000_pchlan) { 2234 mac_reg = er32(EXTCNF_CTRL); 2235 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 2236 goto release; 2237 } 2238 2239 mac_reg = er32(FEXTNVM); 2240 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 2241 goto release; 2242 2243 mac_reg = er32(PHY_CTRL); 2244 2245 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); 2246 if (ret_val) 2247 goto release; 2248 2249 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 2250 2251 if (d0_state) { 2252 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 2253 oem_reg |= HV_OEM_BITS_GBE_DIS; 2254 2255 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 2256 oem_reg |= HV_OEM_BITS_LPLU; 2257 } else { 2258 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 2259 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 2260 oem_reg |= HV_OEM_BITS_GBE_DIS; 2261 2262 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 2263 E1000_PHY_CTRL_NOND0A_LPLU)) 2264 oem_reg |= HV_OEM_BITS_LPLU; 2265 } 2266 2267 /* Set Restart auto-neg to activate the bits */ 2268 if ((d0_state || (hw->mac.type != e1000_pchlan)) && 2269 !hw->phy.ops.check_reset_block(hw)) 2270 oem_reg |= HV_OEM_BITS_RESTART_AN; 2271 2272 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); 2273 2274 release: 2275 hw->phy.ops.release(hw); 2276 2277 return ret_val; 2278 } 2279 2280 /** 2281 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 2282 * @hw: pointer to the HW structure 2283 **/ 2284 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 2285 { 2286 s32 ret_val; 2287 u16 data; 2288 2289 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); 2290 if (ret_val) 2291 return ret_val; 2292 2293 data |= HV_KMRN_MDIO_SLOW; 2294 2295 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); 2296 2297 return ret_val; 2298 } 2299 2300 /** 2301 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be 2302 * done after every PHY reset. 2303 **/ 2304 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2305 { 2306 s32 ret_val = 0; 2307 u16 phy_data; 2308 2309 if (hw->mac.type != e1000_pchlan) 2310 return 0; 2311 2312 /* Set MDIO slow mode before any other MDIO access */ 2313 if (hw->phy.type == e1000_phy_82577) { 2314 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2315 if (ret_val) 2316 return ret_val; 2317 } 2318 2319 if (((hw->phy.type == e1000_phy_82577) && 2320 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 2321 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 2322 /* Disable generation of early preamble */ 2323 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); 2324 if (ret_val) 2325 return ret_val; 2326 2327 /* Preamble tuning for SSC */ 2328 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); 2329 if (ret_val) 2330 return ret_val; 2331 } 2332 2333 if (hw->phy.type == e1000_phy_82578) { 2334 /* Return registers to default by doing a soft reset then 2335 * writing 0x3140 to the control register. 2336 */ 2337 if (hw->phy.revision < 2) { 2338 e1000e_phy_sw_reset(hw); 2339 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140); 2340 } 2341 } 2342 2343 /* Select page 0 */ 2344 ret_val = hw->phy.ops.acquire(hw); 2345 if (ret_val) 2346 return ret_val; 2347 2348 hw->phy.addr = 1; 2349 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 2350 hw->phy.ops.release(hw); 2351 if (ret_val) 2352 return ret_val; 2353 2354 /* Configure the K1 Si workaround during phy reset assuming there is 2355 * link so that it disables K1 if link is in 1Gbps. 2356 */ 2357 ret_val = e1000_k1_gig_workaround_hv(hw, true); 2358 if (ret_val) 2359 return ret_val; 2360 2361 /* Workaround for link disconnects on a busy hub in half duplex */ 2362 ret_val = hw->phy.ops.acquire(hw); 2363 if (ret_val) 2364 return ret_val; 2365 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); 2366 if (ret_val) 2367 goto release; 2368 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); 2369 if (ret_val) 2370 goto release; 2371 2372 /* set MSE higher to enable link to stay up when noise is high */ 2373 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); 2374 release: 2375 hw->phy.ops.release(hw); 2376 2377 return ret_val; 2378 } 2379 2380 /** 2381 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 2382 * @hw: pointer to the HW structure 2383 **/ 2384 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 2385 { 2386 u32 mac_reg; 2387 u16 i, phy_reg = 0; 2388 s32 ret_val; 2389 2390 ret_val = hw->phy.ops.acquire(hw); 2391 if (ret_val) 2392 return; 2393 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2394 if (ret_val) 2395 goto release; 2396 2397 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */ 2398 for (i = 0; i < (hw->mac.rar_entry_count); i++) { 2399 mac_reg = er32(RAL(i)); 2400 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), 2401 (u16)(mac_reg & 0xFFFF)); 2402 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), 2403 (u16)((mac_reg >> 16) & 0xFFFF)); 2404 2405 mac_reg = er32(RAH(i)); 2406 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 2407 (u16)(mac_reg & 0xFFFF)); 2408 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 2409 (u16)((mac_reg & E1000_RAH_AV) 2410 >> 16)); 2411 } 2412 2413 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2414 2415 release: 2416 hw->phy.ops.release(hw); 2417 } 2418 2419 /** 2420 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 2421 * with 82579 PHY 2422 * @hw: pointer to the HW structure 2423 * @enable: flag to enable/disable workaround when enabling/disabling jumbos 2424 **/ 2425 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 2426 { 2427 s32 ret_val = 0; 2428 u16 phy_reg, data; 2429 u32 mac_reg; 2430 u16 i; 2431 2432 if (hw->mac.type < e1000_pch2lan) 2433 return 0; 2434 2435 /* disable Rx path while enabling/disabling workaround */ 2436 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); 2437 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14)); 2438 if (ret_val) 2439 return ret_val; 2440 2441 if (enable) { 2442 /* Write Rx addresses (rar_entry_count for RAL/H, and 2443 * SHRAL/H) and initial CRC values to the MAC 2444 */ 2445 for (i = 0; i < hw->mac.rar_entry_count; i++) { 2446 u8 mac_addr[ETH_ALEN] = { 0 }; 2447 u32 addr_high, addr_low; 2448 2449 addr_high = er32(RAH(i)); 2450 if (!(addr_high & E1000_RAH_AV)) 2451 continue; 2452 addr_low = er32(RAL(i)); 2453 mac_addr[0] = (addr_low & 0xFF); 2454 mac_addr[1] = ((addr_low >> 8) & 0xFF); 2455 mac_addr[2] = ((addr_low >> 16) & 0xFF); 2456 mac_addr[3] = ((addr_low >> 24) & 0xFF); 2457 mac_addr[4] = (addr_high & 0xFF); 2458 mac_addr[5] = ((addr_high >> 8) & 0xFF); 2459 2460 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr)); 2461 } 2462 2463 /* Write Rx addresses to the PHY */ 2464 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 2465 2466 /* Enable jumbo frame workaround in the MAC */ 2467 mac_reg = er32(FFLT_DBG); 2468 mac_reg &= ~(1 << 14); 2469 mac_reg |= (7 << 15); 2470 ew32(FFLT_DBG, mac_reg); 2471 2472 mac_reg = er32(RCTL); 2473 mac_reg |= E1000_RCTL_SECRC; 2474 ew32(RCTL, mac_reg); 2475 2476 ret_val = e1000e_read_kmrn_reg(hw, 2477 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2478 &data); 2479 if (ret_val) 2480 return ret_val; 2481 ret_val = e1000e_write_kmrn_reg(hw, 2482 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2483 data | (1 << 0)); 2484 if (ret_val) 2485 return ret_val; 2486 ret_val = e1000e_read_kmrn_reg(hw, 2487 E1000_KMRNCTRLSTA_HD_CTRL, 2488 &data); 2489 if (ret_val) 2490 return ret_val; 2491 data &= ~(0xF << 8); 2492 data |= (0xB << 8); 2493 ret_val = e1000e_write_kmrn_reg(hw, 2494 E1000_KMRNCTRLSTA_HD_CTRL, 2495 data); 2496 if (ret_val) 2497 return ret_val; 2498 2499 /* Enable jumbo frame workaround in the PHY */ 2500 e1e_rphy(hw, PHY_REG(769, 23), &data); 2501 data &= ~(0x7F << 5); 2502 data |= (0x37 << 5); 2503 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2504 if (ret_val) 2505 return ret_val; 2506 e1e_rphy(hw, PHY_REG(769, 16), &data); 2507 data &= ~(1 << 13); 2508 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2509 if (ret_val) 2510 return ret_val; 2511 e1e_rphy(hw, PHY_REG(776, 20), &data); 2512 data &= ~(0x3FF << 2); 2513 data |= (E1000_TX_PTR_GAP << 2); 2514 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2515 if (ret_val) 2516 return ret_val; 2517 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); 2518 if (ret_val) 2519 return ret_val; 2520 e1e_rphy(hw, HV_PM_CTRL, &data); 2521 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10)); 2522 if (ret_val) 2523 return ret_val; 2524 } else { 2525 /* Write MAC register values back to h/w defaults */ 2526 mac_reg = er32(FFLT_DBG); 2527 mac_reg &= ~(0xF << 14); 2528 ew32(FFLT_DBG, mac_reg); 2529 2530 mac_reg = er32(RCTL); 2531 mac_reg &= ~E1000_RCTL_SECRC; 2532 ew32(RCTL, mac_reg); 2533 2534 ret_val = e1000e_read_kmrn_reg(hw, 2535 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2536 &data); 2537 if (ret_val) 2538 return ret_val; 2539 ret_val = e1000e_write_kmrn_reg(hw, 2540 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2541 data & ~(1 << 0)); 2542 if (ret_val) 2543 return ret_val; 2544 ret_val = e1000e_read_kmrn_reg(hw, 2545 E1000_KMRNCTRLSTA_HD_CTRL, 2546 &data); 2547 if (ret_val) 2548 return ret_val; 2549 data &= ~(0xF << 8); 2550 data |= (0xB << 8); 2551 ret_val = e1000e_write_kmrn_reg(hw, 2552 E1000_KMRNCTRLSTA_HD_CTRL, 2553 data); 2554 if (ret_val) 2555 return ret_val; 2556 2557 /* Write PHY register values back to h/w defaults */ 2558 e1e_rphy(hw, PHY_REG(769, 23), &data); 2559 data &= ~(0x7F << 5); 2560 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2561 if (ret_val) 2562 return ret_val; 2563 e1e_rphy(hw, PHY_REG(769, 16), &data); 2564 data |= (1 << 13); 2565 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2566 if (ret_val) 2567 return ret_val; 2568 e1e_rphy(hw, PHY_REG(776, 20), &data); 2569 data &= ~(0x3FF << 2); 2570 data |= (0x8 << 2); 2571 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2572 if (ret_val) 2573 return ret_val; 2574 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); 2575 if (ret_val) 2576 return ret_val; 2577 e1e_rphy(hw, HV_PM_CTRL, &data); 2578 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10)); 2579 if (ret_val) 2580 return ret_val; 2581 } 2582 2583 /* re-enable Rx path after enabling/disabling workaround */ 2584 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14)); 2585 } 2586 2587 /** 2588 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 2589 * done after every PHY reset. 2590 **/ 2591 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2592 { 2593 s32 ret_val = 0; 2594 2595 if (hw->mac.type != e1000_pch2lan) 2596 return 0; 2597 2598 /* Set MDIO slow mode before any other MDIO access */ 2599 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2600 if (ret_val) 2601 return ret_val; 2602 2603 ret_val = hw->phy.ops.acquire(hw); 2604 if (ret_val) 2605 return ret_val; 2606 /* set MSE higher to enable link to stay up when noise is high */ 2607 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); 2608 if (ret_val) 2609 goto release; 2610 /* drop link after 5 times MSE threshold was reached */ 2611 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); 2612 release: 2613 hw->phy.ops.release(hw); 2614 2615 return ret_val; 2616 } 2617 2618 /** 2619 * e1000_k1_gig_workaround_lv - K1 Si workaround 2620 * @hw: pointer to the HW structure 2621 * 2622 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps 2623 * Disable K1 in 1000Mbps and 100Mbps 2624 **/ 2625 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 2626 { 2627 s32 ret_val = 0; 2628 u16 status_reg = 0; 2629 2630 if (hw->mac.type != e1000_pch2lan) 2631 return 0; 2632 2633 /* Set K1 beacon duration based on 10Mbs speed */ 2634 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); 2635 if (ret_val) 2636 return ret_val; 2637 2638 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 2639 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 2640 if (status_reg & 2641 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) { 2642 u16 pm_phy_reg; 2643 2644 /* LV 1G/100 Packet drop issue wa */ 2645 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); 2646 if (ret_val) 2647 return ret_val; 2648 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE; 2649 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); 2650 if (ret_val) 2651 return ret_val; 2652 } else { 2653 u32 mac_reg; 2654 2655 mac_reg = er32(FEXTNVM4); 2656 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 2657 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 2658 ew32(FEXTNVM4, mac_reg); 2659 } 2660 } 2661 2662 return ret_val; 2663 } 2664 2665 /** 2666 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 2667 * @hw: pointer to the HW structure 2668 * @gate: boolean set to true to gate, false to ungate 2669 * 2670 * Gate/ungate the automatic PHY configuration via hardware; perform 2671 * the configuration via software instead. 2672 **/ 2673 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 2674 { 2675 u32 extcnf_ctrl; 2676 2677 if (hw->mac.type < e1000_pch2lan) 2678 return; 2679 2680 extcnf_ctrl = er32(EXTCNF_CTRL); 2681 2682 if (gate) 2683 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2684 else 2685 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2686 2687 ew32(EXTCNF_CTRL, extcnf_ctrl); 2688 } 2689 2690 /** 2691 * e1000_lan_init_done_ich8lan - Check for PHY config completion 2692 * @hw: pointer to the HW structure 2693 * 2694 * Check the appropriate indication the MAC has finished configuring the 2695 * PHY after a software reset. 2696 **/ 2697 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 2698 { 2699 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 2700 2701 /* Wait for basic configuration completes before proceeding */ 2702 do { 2703 data = er32(STATUS); 2704 data &= E1000_STATUS_LAN_INIT_DONE; 2705 usleep_range(100, 200); 2706 } while ((!data) && --loop); 2707 2708 /* If basic configuration is incomplete before the above loop 2709 * count reaches 0, loading the configuration from NVM will 2710 * leave the PHY in a bad state possibly resulting in no link. 2711 */ 2712 if (loop == 0) 2713 e_dbg("LAN_INIT_DONE not set, increase timeout\n"); 2714 2715 /* Clear the Init Done bit for the next init event */ 2716 data = er32(STATUS); 2717 data &= ~E1000_STATUS_LAN_INIT_DONE; 2718 ew32(STATUS, data); 2719 } 2720 2721 /** 2722 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 2723 * @hw: pointer to the HW structure 2724 **/ 2725 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 2726 { 2727 s32 ret_val = 0; 2728 u16 reg; 2729 2730 if (hw->phy.ops.check_reset_block(hw)) 2731 return 0; 2732 2733 /* Allow time for h/w to get to quiescent state after reset */ 2734 usleep_range(10000, 20000); 2735 2736 /* Perform any necessary post-reset workarounds */ 2737 switch (hw->mac.type) { 2738 case e1000_pchlan: 2739 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 2740 if (ret_val) 2741 return ret_val; 2742 break; 2743 case e1000_pch2lan: 2744 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 2745 if (ret_val) 2746 return ret_val; 2747 break; 2748 default: 2749 break; 2750 } 2751 2752 /* Clear the host wakeup bit after lcd reset */ 2753 if (hw->mac.type >= e1000_pchlan) { 2754 e1e_rphy(hw, BM_PORT_GEN_CFG, ®); 2755 reg &= ~BM_WUC_HOST_WU_BIT; 2756 e1e_wphy(hw, BM_PORT_GEN_CFG, reg); 2757 } 2758 2759 /* Configure the LCD with the extended configuration region in NVM */ 2760 ret_val = e1000_sw_lcd_config_ich8lan(hw); 2761 if (ret_val) 2762 return ret_val; 2763 2764 /* Configure the LCD with the OEM bits in NVM */ 2765 ret_val = e1000_oem_bits_config_ich8lan(hw, true); 2766 2767 if (hw->mac.type == e1000_pch2lan) { 2768 /* Ungate automatic PHY configuration on non-managed 82579 */ 2769 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 2770 usleep_range(10000, 20000); 2771 e1000_gate_hw_phy_config_ich8lan(hw, false); 2772 } 2773 2774 /* Set EEE LPI Update Timer to 200usec */ 2775 ret_val = hw->phy.ops.acquire(hw); 2776 if (ret_val) 2777 return ret_val; 2778 ret_val = e1000_write_emi_reg_locked(hw, 2779 I82579_LPI_UPDATE_TIMER, 2780 0x1387); 2781 hw->phy.ops.release(hw); 2782 } 2783 2784 return ret_val; 2785 } 2786 2787 /** 2788 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 2789 * @hw: pointer to the HW structure 2790 * 2791 * Resets the PHY 2792 * This is a function pointer entry point called by drivers 2793 * or other shared routines. 2794 **/ 2795 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 2796 { 2797 s32 ret_val = 0; 2798 2799 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 2800 if ((hw->mac.type == e1000_pch2lan) && 2801 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 2802 e1000_gate_hw_phy_config_ich8lan(hw, true); 2803 2804 ret_val = e1000e_phy_hw_reset_generic(hw); 2805 if (ret_val) 2806 return ret_val; 2807 2808 return e1000_post_phy_reset_ich8lan(hw); 2809 } 2810 2811 /** 2812 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 2813 * @hw: pointer to the HW structure 2814 * @active: true to enable LPLU, false to disable 2815 * 2816 * Sets the LPLU state according to the active flag. For PCH, if OEM write 2817 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 2818 * the phy speed. This function will manually set the LPLU bit and restart 2819 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 2820 * since it configures the same bit. 2821 **/ 2822 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 2823 { 2824 s32 ret_val; 2825 u16 oem_reg; 2826 2827 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); 2828 if (ret_val) 2829 return ret_val; 2830 2831 if (active) 2832 oem_reg |= HV_OEM_BITS_LPLU; 2833 else 2834 oem_reg &= ~HV_OEM_BITS_LPLU; 2835 2836 if (!hw->phy.ops.check_reset_block(hw)) 2837 oem_reg |= HV_OEM_BITS_RESTART_AN; 2838 2839 return e1e_wphy(hw, HV_OEM_BITS, oem_reg); 2840 } 2841 2842 /** 2843 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 2844 * @hw: pointer to the HW structure 2845 * @active: true to enable LPLU, false to disable 2846 * 2847 * Sets the LPLU D0 state according to the active flag. When 2848 * activating LPLU this function also disables smart speed 2849 * and vice versa. LPLU will not be activated unless the 2850 * device autonegotiation advertisement meets standards of 2851 * either 10 or 10/100 or 10/100/1000 at all duplexes. 2852 * This is a function pointer entry point only called by 2853 * PHY setup routines. 2854 **/ 2855 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 2856 { 2857 struct e1000_phy_info *phy = &hw->phy; 2858 u32 phy_ctrl; 2859 s32 ret_val = 0; 2860 u16 data; 2861 2862 if (phy->type == e1000_phy_ife) 2863 return 0; 2864 2865 phy_ctrl = er32(PHY_CTRL); 2866 2867 if (active) { 2868 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2869 ew32(PHY_CTRL, phy_ctrl); 2870 2871 if (phy->type != e1000_phy_igp_3) 2872 return 0; 2873 2874 /* Call gig speed drop workaround on LPLU before accessing 2875 * any PHY registers 2876 */ 2877 if (hw->mac.type == e1000_ich8lan) 2878 e1000e_gig_downshift_workaround_ich8lan(hw); 2879 2880 /* When LPLU is enabled, we should disable SmartSpeed */ 2881 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 2882 if (ret_val) 2883 return ret_val; 2884 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2885 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 2886 if (ret_val) 2887 return ret_val; 2888 } else { 2889 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2890 ew32(PHY_CTRL, phy_ctrl); 2891 2892 if (phy->type != e1000_phy_igp_3) 2893 return 0; 2894 2895 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 2896 * during Dx states where the power conservation is most 2897 * important. During driver activity we should enable 2898 * SmartSpeed, so performance is maintained. 2899 */ 2900 if (phy->smart_speed == e1000_smart_speed_on) { 2901 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2902 &data); 2903 if (ret_val) 2904 return ret_val; 2905 2906 data |= IGP01E1000_PSCFR_SMART_SPEED; 2907 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2908 data); 2909 if (ret_val) 2910 return ret_val; 2911 } else if (phy->smart_speed == e1000_smart_speed_off) { 2912 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2913 &data); 2914 if (ret_val) 2915 return ret_val; 2916 2917 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2918 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2919 data); 2920 if (ret_val) 2921 return ret_val; 2922 } 2923 } 2924 2925 return 0; 2926 } 2927 2928 /** 2929 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 2930 * @hw: pointer to the HW structure 2931 * @active: true to enable LPLU, false to disable 2932 * 2933 * Sets the LPLU D3 state according to the active flag. When 2934 * activating LPLU this function also disables smart speed 2935 * and vice versa. LPLU will not be activated unless the 2936 * device autonegotiation advertisement meets standards of 2937 * either 10 or 10/100 or 10/100/1000 at all duplexes. 2938 * This is a function pointer entry point only called by 2939 * PHY setup routines. 2940 **/ 2941 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 2942 { 2943 struct e1000_phy_info *phy = &hw->phy; 2944 u32 phy_ctrl; 2945 s32 ret_val = 0; 2946 u16 data; 2947 2948 phy_ctrl = er32(PHY_CTRL); 2949 2950 if (!active) { 2951 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 2952 ew32(PHY_CTRL, phy_ctrl); 2953 2954 if (phy->type != e1000_phy_igp_3) 2955 return 0; 2956 2957 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 2958 * during Dx states where the power conservation is most 2959 * important. During driver activity we should enable 2960 * SmartSpeed, so performance is maintained. 2961 */ 2962 if (phy->smart_speed == e1000_smart_speed_on) { 2963 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2964 &data); 2965 if (ret_val) 2966 return ret_val; 2967 2968 data |= IGP01E1000_PSCFR_SMART_SPEED; 2969 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2970 data); 2971 if (ret_val) 2972 return ret_val; 2973 } else if (phy->smart_speed == e1000_smart_speed_off) { 2974 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2975 &data); 2976 if (ret_val) 2977 return ret_val; 2978 2979 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2980 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2981 data); 2982 if (ret_val) 2983 return ret_val; 2984 } 2985 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 2986 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 2987 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 2988 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 2989 ew32(PHY_CTRL, phy_ctrl); 2990 2991 if (phy->type != e1000_phy_igp_3) 2992 return 0; 2993 2994 /* Call gig speed drop workaround on LPLU before accessing 2995 * any PHY registers 2996 */ 2997 if (hw->mac.type == e1000_ich8lan) 2998 e1000e_gig_downshift_workaround_ich8lan(hw); 2999 3000 /* When LPLU is enabled, we should disable SmartSpeed */ 3001 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3002 if (ret_val) 3003 return ret_val; 3004 3005 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3006 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3007 } 3008 3009 return ret_val; 3010 } 3011 3012 /** 3013 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 3014 * @hw: pointer to the HW structure 3015 * @bank: pointer to the variable that returns the active bank 3016 * 3017 * Reads signature byte from the NVM using the flash access registers. 3018 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 3019 **/ 3020 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 3021 { 3022 u32 eecd; 3023 struct e1000_nvm_info *nvm = &hw->nvm; 3024 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 3025 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 3026 u8 sig_byte = 0; 3027 s32 ret_val; 3028 3029 switch (hw->mac.type) { 3030 /* In SPT, read from the CTRL_EXT reg instead of 3031 * accessing the sector valid bits from the nvm 3032 */ 3033 case e1000_pch_spt: 3034 *bank = er32(CTRL_EXT) 3035 & E1000_CTRL_EXT_NVMVS; 3036 if ((*bank == 0) || (*bank == 1)) { 3037 e_dbg("ERROR: No valid NVM bank present\n"); 3038 return -E1000_ERR_NVM; 3039 } else { 3040 *bank = *bank - 2; 3041 return 0; 3042 } 3043 break; 3044 case e1000_ich8lan: 3045 case e1000_ich9lan: 3046 eecd = er32(EECD); 3047 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 3048 E1000_EECD_SEC1VAL_VALID_MASK) { 3049 if (eecd & E1000_EECD_SEC1VAL) 3050 *bank = 1; 3051 else 3052 *bank = 0; 3053 3054 return 0; 3055 } 3056 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 3057 /* fall-thru */ 3058 default: 3059 /* set bank to 0 in case flash read fails */ 3060 *bank = 0; 3061 3062 /* Check bank 0 */ 3063 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 3064 &sig_byte); 3065 if (ret_val) 3066 return ret_val; 3067 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3068 E1000_ICH_NVM_SIG_VALUE) { 3069 *bank = 0; 3070 return 0; 3071 } 3072 3073 /* Check bank 1 */ 3074 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 3075 bank1_offset, 3076 &sig_byte); 3077 if (ret_val) 3078 return ret_val; 3079 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3080 E1000_ICH_NVM_SIG_VALUE) { 3081 *bank = 1; 3082 return 0; 3083 } 3084 3085 e_dbg("ERROR: No valid NVM bank present\n"); 3086 return -E1000_ERR_NVM; 3087 } 3088 } 3089 3090 /** 3091 * e1000_read_nvm_spt - NVM access for SPT 3092 * @hw: pointer to the HW structure 3093 * @offset: The offset (in bytes) of the word(s) to read. 3094 * @words: Size of data to read in words. 3095 * @data: pointer to the word(s) to read at offset. 3096 * 3097 * Reads a word(s) from the NVM 3098 **/ 3099 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 3100 u16 *data) 3101 { 3102 struct e1000_nvm_info *nvm = &hw->nvm; 3103 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3104 u32 act_offset; 3105 s32 ret_val = 0; 3106 u32 bank = 0; 3107 u32 dword = 0; 3108 u16 offset_to_read; 3109 u16 i; 3110 3111 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3112 (words == 0)) { 3113 e_dbg("nvm parameter(s) out of bounds\n"); 3114 ret_val = -E1000_ERR_NVM; 3115 goto out; 3116 } 3117 3118 nvm->ops.acquire(hw); 3119 3120 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3121 if (ret_val) { 3122 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3123 bank = 0; 3124 } 3125 3126 act_offset = (bank) ? nvm->flash_bank_size : 0; 3127 act_offset += offset; 3128 3129 ret_val = 0; 3130 3131 for (i = 0; i < words; i += 2) { 3132 if (words - i == 1) { 3133 if (dev_spec->shadow_ram[offset + i].modified) { 3134 data[i] = 3135 dev_spec->shadow_ram[offset + i].value; 3136 } else { 3137 offset_to_read = act_offset + i - 3138 ((act_offset + i) % 2); 3139 ret_val = 3140 e1000_read_flash_dword_ich8lan(hw, 3141 offset_to_read, 3142 &dword); 3143 if (ret_val) 3144 break; 3145 if ((act_offset + i) % 2 == 0) 3146 data[i] = (u16)(dword & 0xFFFF); 3147 else 3148 data[i] = (u16)((dword >> 16) & 0xFFFF); 3149 } 3150 } else { 3151 offset_to_read = act_offset + i; 3152 if (!(dev_spec->shadow_ram[offset + i].modified) || 3153 !(dev_spec->shadow_ram[offset + i + 1].modified)) { 3154 ret_val = 3155 e1000_read_flash_dword_ich8lan(hw, 3156 offset_to_read, 3157 &dword); 3158 if (ret_val) 3159 break; 3160 } 3161 if (dev_spec->shadow_ram[offset + i].modified) 3162 data[i] = 3163 dev_spec->shadow_ram[offset + i].value; 3164 else 3165 data[i] = (u16)(dword & 0xFFFF); 3166 if (dev_spec->shadow_ram[offset + i].modified) 3167 data[i + 1] = 3168 dev_spec->shadow_ram[offset + i + 1].value; 3169 else 3170 data[i + 1] = (u16)(dword >> 16 & 0xFFFF); 3171 } 3172 } 3173 3174 nvm->ops.release(hw); 3175 3176 out: 3177 if (ret_val) 3178 e_dbg("NVM read error: %d\n", ret_val); 3179 3180 return ret_val; 3181 } 3182 3183 /** 3184 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 3185 * @hw: pointer to the HW structure 3186 * @offset: The offset (in bytes) of the word(s) to read. 3187 * @words: Size of data to read in words 3188 * @data: Pointer to the word(s) to read at offset. 3189 * 3190 * Reads a word(s) from the NVM using the flash access registers. 3191 **/ 3192 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3193 u16 *data) 3194 { 3195 struct e1000_nvm_info *nvm = &hw->nvm; 3196 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3197 u32 act_offset; 3198 s32 ret_val = 0; 3199 u32 bank = 0; 3200 u16 i, word; 3201 3202 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3203 (words == 0)) { 3204 e_dbg("nvm parameter(s) out of bounds\n"); 3205 ret_val = -E1000_ERR_NVM; 3206 goto out; 3207 } 3208 3209 nvm->ops.acquire(hw); 3210 3211 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3212 if (ret_val) { 3213 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3214 bank = 0; 3215 } 3216 3217 act_offset = (bank) ? nvm->flash_bank_size : 0; 3218 act_offset += offset; 3219 3220 ret_val = 0; 3221 for (i = 0; i < words; i++) { 3222 if (dev_spec->shadow_ram[offset + i].modified) { 3223 data[i] = dev_spec->shadow_ram[offset + i].value; 3224 } else { 3225 ret_val = e1000_read_flash_word_ich8lan(hw, 3226 act_offset + i, 3227 &word); 3228 if (ret_val) 3229 break; 3230 data[i] = word; 3231 } 3232 } 3233 3234 nvm->ops.release(hw); 3235 3236 out: 3237 if (ret_val) 3238 e_dbg("NVM read error: %d\n", ret_val); 3239 3240 return ret_val; 3241 } 3242 3243 /** 3244 * e1000_flash_cycle_init_ich8lan - Initialize flash 3245 * @hw: pointer to the HW structure 3246 * 3247 * This function does initial flash setup so that a new read/write/erase cycle 3248 * can be started. 3249 **/ 3250 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 3251 { 3252 union ich8_hws_flash_status hsfsts; 3253 s32 ret_val = -E1000_ERR_NVM; 3254 3255 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3256 3257 /* Check if the flash descriptor is valid */ 3258 if (!hsfsts.hsf_status.fldesvalid) { 3259 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n"); 3260 return -E1000_ERR_NVM; 3261 } 3262 3263 /* Clear FCERR and DAEL in hw status by writing 1 */ 3264 hsfsts.hsf_status.flcerr = 1; 3265 hsfsts.hsf_status.dael = 1; 3266 if (hw->mac.type == e1000_pch_spt) 3267 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3268 else 3269 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3270 3271 /* Either we should have a hardware SPI cycle in progress 3272 * bit to check against, in order to start a new cycle or 3273 * FDONE bit should be changed in the hardware so that it 3274 * is 1 after hardware reset, which can then be used as an 3275 * indication whether a cycle is in progress or has been 3276 * completed. 3277 */ 3278 3279 if (!hsfsts.hsf_status.flcinprog) { 3280 /* There is no cycle running at present, 3281 * so we can start a cycle. 3282 * Begin by setting Flash Cycle Done. 3283 */ 3284 hsfsts.hsf_status.flcdone = 1; 3285 if (hw->mac.type == e1000_pch_spt) 3286 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3287 else 3288 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3289 ret_val = 0; 3290 } else { 3291 s32 i; 3292 3293 /* Otherwise poll for sometime so the current 3294 * cycle has a chance to end before giving up. 3295 */ 3296 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 3297 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3298 if (!hsfsts.hsf_status.flcinprog) { 3299 ret_val = 0; 3300 break; 3301 } 3302 udelay(1); 3303 } 3304 if (!ret_val) { 3305 /* Successful in waiting for previous cycle to timeout, 3306 * now set the Flash Cycle Done. 3307 */ 3308 hsfsts.hsf_status.flcdone = 1; 3309 if (hw->mac.type == e1000_pch_spt) 3310 ew32flash(ICH_FLASH_HSFSTS, 3311 hsfsts.regval & 0xFFFF); 3312 else 3313 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3314 } else { 3315 e_dbg("Flash controller busy, cannot get access\n"); 3316 } 3317 } 3318 3319 return ret_val; 3320 } 3321 3322 /** 3323 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 3324 * @hw: pointer to the HW structure 3325 * @timeout: maximum time to wait for completion 3326 * 3327 * This function starts a flash cycle and waits for its completion. 3328 **/ 3329 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 3330 { 3331 union ich8_hws_flash_ctrl hsflctl; 3332 union ich8_hws_flash_status hsfsts; 3333 u32 i = 0; 3334 3335 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 3336 if (hw->mac.type == e1000_pch_spt) 3337 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3338 else 3339 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3340 hsflctl.hsf_ctrl.flcgo = 1; 3341 3342 if (hw->mac.type == e1000_pch_spt) 3343 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 3344 else 3345 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3346 3347 /* wait till FDONE bit is set to 1 */ 3348 do { 3349 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3350 if (hsfsts.hsf_status.flcdone) 3351 break; 3352 udelay(1); 3353 } while (i++ < timeout); 3354 3355 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) 3356 return 0; 3357 3358 return -E1000_ERR_NVM; 3359 } 3360 3361 /** 3362 * e1000_read_flash_dword_ich8lan - Read dword from flash 3363 * @hw: pointer to the HW structure 3364 * @offset: offset to data location 3365 * @data: pointer to the location for storing the data 3366 * 3367 * Reads the flash dword at offset into data. Offset is converted 3368 * to bytes before read. 3369 **/ 3370 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, 3371 u32 *data) 3372 { 3373 /* Must convert word offset into bytes. */ 3374 offset <<= 1; 3375 return e1000_read_flash_data32_ich8lan(hw, offset, data); 3376 } 3377 3378 /** 3379 * e1000_read_flash_word_ich8lan - Read word from flash 3380 * @hw: pointer to the HW structure 3381 * @offset: offset to data location 3382 * @data: pointer to the location for storing the data 3383 * 3384 * Reads the flash word at offset into data. Offset is converted 3385 * to bytes before read. 3386 **/ 3387 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 3388 u16 *data) 3389 { 3390 /* Must convert offset into bytes. */ 3391 offset <<= 1; 3392 3393 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 3394 } 3395 3396 /** 3397 * e1000_read_flash_byte_ich8lan - Read byte from flash 3398 * @hw: pointer to the HW structure 3399 * @offset: The offset of the byte to read. 3400 * @data: Pointer to a byte to store the value read. 3401 * 3402 * Reads a single byte from the NVM using the flash access registers. 3403 **/ 3404 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3405 u8 *data) 3406 { 3407 s32 ret_val; 3408 u16 word = 0; 3409 3410 /* In SPT, only 32 bits access is supported, 3411 * so this function should not be called. 3412 */ 3413 if (hw->mac.type == e1000_pch_spt) 3414 return -E1000_ERR_NVM; 3415 else 3416 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 3417 3418 if (ret_val) 3419 return ret_val; 3420 3421 *data = (u8)word; 3422 3423 return 0; 3424 } 3425 3426 /** 3427 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 3428 * @hw: pointer to the HW structure 3429 * @offset: The offset (in bytes) of the byte or word to read. 3430 * @size: Size of data to read, 1=byte 2=word 3431 * @data: Pointer to the word to store the value read. 3432 * 3433 * Reads a byte or word from the NVM using the flash access registers. 3434 **/ 3435 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 3436 u8 size, u16 *data) 3437 { 3438 union ich8_hws_flash_status hsfsts; 3439 union ich8_hws_flash_ctrl hsflctl; 3440 u32 flash_linear_addr; 3441 u32 flash_data = 0; 3442 s32 ret_val = -E1000_ERR_NVM; 3443 u8 count = 0; 3444 3445 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 3446 return -E1000_ERR_NVM; 3447 3448 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3449 hw->nvm.flash_base_addr); 3450 3451 do { 3452 udelay(1); 3453 /* Steps */ 3454 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3455 if (ret_val) 3456 break; 3457 3458 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3459 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3460 hsflctl.hsf_ctrl.fldbcount = size - 1; 3461 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3462 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3463 3464 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3465 3466 ret_val = 3467 e1000_flash_cycle_ich8lan(hw, 3468 ICH_FLASH_READ_COMMAND_TIMEOUT); 3469 3470 /* Check if FCERR is set to 1, if set to 1, clear it 3471 * and try the whole sequence a few more times, else 3472 * read in (shift in) the Flash Data0, the order is 3473 * least significant byte first msb to lsb 3474 */ 3475 if (!ret_val) { 3476 flash_data = er32flash(ICH_FLASH_FDATA0); 3477 if (size == 1) 3478 *data = (u8)(flash_data & 0x000000FF); 3479 else if (size == 2) 3480 *data = (u16)(flash_data & 0x0000FFFF); 3481 break; 3482 } else { 3483 /* If we've gotten here, then things are probably 3484 * completely hosed, but if the error condition is 3485 * detected, it won't hurt to give it another try... 3486 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3487 */ 3488 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3489 if (hsfsts.hsf_status.flcerr) { 3490 /* Repeat for some time before giving up. */ 3491 continue; 3492 } else if (!hsfsts.hsf_status.flcdone) { 3493 e_dbg("Timeout error - flash cycle did not complete.\n"); 3494 break; 3495 } 3496 } 3497 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3498 3499 return ret_val; 3500 } 3501 3502 /** 3503 * e1000_read_flash_data32_ich8lan - Read dword from NVM 3504 * @hw: pointer to the HW structure 3505 * @offset: The offset (in bytes) of the dword to read. 3506 * @data: Pointer to the dword to store the value read. 3507 * 3508 * Reads a byte or word from the NVM using the flash access registers. 3509 **/ 3510 3511 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 3512 u32 *data) 3513 { 3514 union ich8_hws_flash_status hsfsts; 3515 union ich8_hws_flash_ctrl hsflctl; 3516 u32 flash_linear_addr; 3517 s32 ret_val = -E1000_ERR_NVM; 3518 u8 count = 0; 3519 3520 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || 3521 hw->mac.type != e1000_pch_spt) 3522 return -E1000_ERR_NVM; 3523 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3524 hw->nvm.flash_base_addr); 3525 3526 do { 3527 udelay(1); 3528 /* Steps */ 3529 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3530 if (ret_val) 3531 break; 3532 /* In SPT, This register is in Lan memory space, not flash. 3533 * Therefore, only 32 bit access is supported 3534 */ 3535 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3536 3537 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3538 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 3539 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3540 /* In SPT, This register is in Lan memory space, not flash. 3541 * Therefore, only 32 bit access is supported 3542 */ 3543 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16); 3544 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3545 3546 ret_val = 3547 e1000_flash_cycle_ich8lan(hw, 3548 ICH_FLASH_READ_COMMAND_TIMEOUT); 3549 3550 /* Check if FCERR is set to 1, if set to 1, clear it 3551 * and try the whole sequence a few more times, else 3552 * read in (shift in) the Flash Data0, the order is 3553 * least significant byte first msb to lsb 3554 */ 3555 if (!ret_val) { 3556 *data = er32flash(ICH_FLASH_FDATA0); 3557 break; 3558 } else { 3559 /* If we've gotten here, then things are probably 3560 * completely hosed, but if the error condition is 3561 * detected, it won't hurt to give it another try... 3562 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3563 */ 3564 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3565 if (hsfsts.hsf_status.flcerr) { 3566 /* Repeat for some time before giving up. */ 3567 continue; 3568 } else if (!hsfsts.hsf_status.flcdone) { 3569 e_dbg("Timeout error - flash cycle did not complete.\n"); 3570 break; 3571 } 3572 } 3573 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3574 3575 return ret_val; 3576 } 3577 3578 /** 3579 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 3580 * @hw: pointer to the HW structure 3581 * @offset: The offset (in bytes) of the word(s) to write. 3582 * @words: Size of data to write in words 3583 * @data: Pointer to the word(s) to write at offset. 3584 * 3585 * Writes a byte or word to the NVM using the flash access registers. 3586 **/ 3587 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3588 u16 *data) 3589 { 3590 struct e1000_nvm_info *nvm = &hw->nvm; 3591 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3592 u16 i; 3593 3594 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3595 (words == 0)) { 3596 e_dbg("nvm parameter(s) out of bounds\n"); 3597 return -E1000_ERR_NVM; 3598 } 3599 3600 nvm->ops.acquire(hw); 3601 3602 for (i = 0; i < words; i++) { 3603 dev_spec->shadow_ram[offset + i].modified = true; 3604 dev_spec->shadow_ram[offset + i].value = data[i]; 3605 } 3606 3607 nvm->ops.release(hw); 3608 3609 return 0; 3610 } 3611 3612 /** 3613 * e1000_update_nvm_checksum_spt - Update the checksum for NVM 3614 * @hw: pointer to the HW structure 3615 * 3616 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3617 * which writes the checksum to the shadow ram. The changes in the shadow 3618 * ram are then committed to the EEPROM by processing each bank at a time 3619 * checking for the modified bit and writing only the pending changes. 3620 * After a successful commit, the shadow ram is cleared and is ready for 3621 * future writes. 3622 **/ 3623 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) 3624 { 3625 struct e1000_nvm_info *nvm = &hw->nvm; 3626 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3627 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3628 s32 ret_val; 3629 u32 dword = 0; 3630 3631 ret_val = e1000e_update_nvm_checksum_generic(hw); 3632 if (ret_val) 3633 goto out; 3634 3635 if (nvm->type != e1000_nvm_flash_sw) 3636 goto out; 3637 3638 nvm->ops.acquire(hw); 3639 3640 /* We're writing to the opposite bank so if we're on bank 1, 3641 * write to bank 0 etc. We also need to erase the segment that 3642 * is going to be written 3643 */ 3644 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3645 if (ret_val) { 3646 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3647 bank = 0; 3648 } 3649 3650 if (bank == 0) { 3651 new_bank_offset = nvm->flash_bank_size; 3652 old_bank_offset = 0; 3653 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3654 if (ret_val) 3655 goto release; 3656 } else { 3657 old_bank_offset = nvm->flash_bank_size; 3658 new_bank_offset = 0; 3659 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 3660 if (ret_val) 3661 goto release; 3662 } 3663 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) { 3664 /* Determine whether to write the value stored 3665 * in the other NVM bank or a modified value stored 3666 * in the shadow RAM 3667 */ 3668 ret_val = e1000_read_flash_dword_ich8lan(hw, 3669 i + old_bank_offset, 3670 &dword); 3671 3672 if (dev_spec->shadow_ram[i].modified) { 3673 dword &= 0xffff0000; 3674 dword |= (dev_spec->shadow_ram[i].value & 0xffff); 3675 } 3676 if (dev_spec->shadow_ram[i + 1].modified) { 3677 dword &= 0x0000ffff; 3678 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) 3679 << 16); 3680 } 3681 if (ret_val) 3682 break; 3683 3684 /* If the word is 0x13, then make sure the signature bits 3685 * (15:14) are 11b until the commit has completed. 3686 * This will allow us to write 10b which indicates the 3687 * signature is valid. We want to do this after the write 3688 * has completed so that we don't mark the segment valid 3689 * while the write is still in progress 3690 */ 3691 if (i == E1000_ICH_NVM_SIG_WORD - 1) 3692 dword |= E1000_ICH_NVM_SIG_MASK << 16; 3693 3694 /* Convert offset to bytes. */ 3695 act_offset = (i + new_bank_offset) << 1; 3696 3697 usleep_range(100, 200); 3698 3699 /* Write the data to the new bank. Offset in words */ 3700 act_offset = i + new_bank_offset; 3701 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, 3702 dword); 3703 if (ret_val) 3704 break; 3705 } 3706 3707 /* Don't bother writing the segment valid bits if sector 3708 * programming failed. 3709 */ 3710 if (ret_val) { 3711 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 3712 e_dbg("Flash commit failed.\n"); 3713 goto release; 3714 } 3715 3716 /* Finally validate the new segment by setting bit 15:14 3717 * to 10b in word 0x13 , this can be done without an 3718 * erase as well since these bits are 11 to start with 3719 * and we need to change bit 14 to 0b 3720 */ 3721 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 3722 3723 /*offset in words but we read dword */ 3724 --act_offset; 3725 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 3726 3727 if (ret_val) 3728 goto release; 3729 3730 dword &= 0xBFFFFFFF; 3731 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 3732 3733 if (ret_val) 3734 goto release; 3735 3736 /* And invalidate the previously valid segment by setting 3737 * its signature word (0x13) high_byte to 0b. This can be 3738 * done without an erase because flash erase sets all bits 3739 * to 1's. We can write 1's to 0's without an erase 3740 */ 3741 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 3742 3743 /* offset in words but we read dword */ 3744 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; 3745 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 3746 3747 if (ret_val) 3748 goto release; 3749 3750 dword &= 0x00FFFFFF; 3751 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 3752 3753 if (ret_val) 3754 goto release; 3755 3756 /* Great! Everything worked, we can now clear the cached entries. */ 3757 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 3758 dev_spec->shadow_ram[i].modified = false; 3759 dev_spec->shadow_ram[i].value = 0xFFFF; 3760 } 3761 3762 release: 3763 nvm->ops.release(hw); 3764 3765 /* Reload the EEPROM, or else modifications will not appear 3766 * until after the next adapter reset. 3767 */ 3768 if (!ret_val) { 3769 nvm->ops.reload(hw); 3770 usleep_range(10000, 20000); 3771 } 3772 3773 out: 3774 if (ret_val) 3775 e_dbg("NVM update error: %d\n", ret_val); 3776 3777 return ret_val; 3778 } 3779 3780 /** 3781 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 3782 * @hw: pointer to the HW structure 3783 * 3784 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3785 * which writes the checksum to the shadow ram. The changes in the shadow 3786 * ram are then committed to the EEPROM by processing each bank at a time 3787 * checking for the modified bit and writing only the pending changes. 3788 * After a successful commit, the shadow ram is cleared and is ready for 3789 * future writes. 3790 **/ 3791 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 3792 { 3793 struct e1000_nvm_info *nvm = &hw->nvm; 3794 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3795 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3796 s32 ret_val; 3797 u16 data = 0; 3798 3799 ret_val = e1000e_update_nvm_checksum_generic(hw); 3800 if (ret_val) 3801 goto out; 3802 3803 if (nvm->type != e1000_nvm_flash_sw) 3804 goto out; 3805 3806 nvm->ops.acquire(hw); 3807 3808 /* We're writing to the opposite bank so if we're on bank 1, 3809 * write to bank 0 etc. We also need to erase the segment that 3810 * is going to be written 3811 */ 3812 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3813 if (ret_val) { 3814 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3815 bank = 0; 3816 } 3817 3818 if (bank == 0) { 3819 new_bank_offset = nvm->flash_bank_size; 3820 old_bank_offset = 0; 3821 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3822 if (ret_val) 3823 goto release; 3824 } else { 3825 old_bank_offset = nvm->flash_bank_size; 3826 new_bank_offset = 0; 3827 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 3828 if (ret_val) 3829 goto release; 3830 } 3831 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 3832 if (dev_spec->shadow_ram[i].modified) { 3833 data = dev_spec->shadow_ram[i].value; 3834 } else { 3835 ret_val = e1000_read_flash_word_ich8lan(hw, i + 3836 old_bank_offset, 3837 &data); 3838 if (ret_val) 3839 break; 3840 } 3841 3842 /* If the word is 0x13, then make sure the signature bits 3843 * (15:14) are 11b until the commit has completed. 3844 * This will allow us to write 10b which indicates the 3845 * signature is valid. We want to do this after the write 3846 * has completed so that we don't mark the segment valid 3847 * while the write is still in progress 3848 */ 3849 if (i == E1000_ICH_NVM_SIG_WORD) 3850 data |= E1000_ICH_NVM_SIG_MASK; 3851 3852 /* Convert offset to bytes. */ 3853 act_offset = (i + new_bank_offset) << 1; 3854 3855 usleep_range(100, 200); 3856 /* Write the bytes to the new bank. */ 3857 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 3858 act_offset, 3859 (u8)data); 3860 if (ret_val) 3861 break; 3862 3863 usleep_range(100, 200); 3864 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 3865 act_offset + 1, 3866 (u8)(data >> 8)); 3867 if (ret_val) 3868 break; 3869 } 3870 3871 /* Don't bother writing the segment valid bits if sector 3872 * programming failed. 3873 */ 3874 if (ret_val) { 3875 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 3876 e_dbg("Flash commit failed.\n"); 3877 goto release; 3878 } 3879 3880 /* Finally validate the new segment by setting bit 15:14 3881 * to 10b in word 0x13 , this can be done without an 3882 * erase as well since these bits are 11 to start with 3883 * and we need to change bit 14 to 0b 3884 */ 3885 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 3886 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 3887 if (ret_val) 3888 goto release; 3889 3890 data &= 0xBFFF; 3891 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 3892 act_offset * 2 + 1, 3893 (u8)(data >> 8)); 3894 if (ret_val) 3895 goto release; 3896 3897 /* And invalidate the previously valid segment by setting 3898 * its signature word (0x13) high_byte to 0b. This can be 3899 * done without an erase because flash erase sets all bits 3900 * to 1's. We can write 1's to 0's without an erase 3901 */ 3902 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 3903 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 3904 if (ret_val) 3905 goto release; 3906 3907 /* Great! Everything worked, we can now clear the cached entries. */ 3908 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 3909 dev_spec->shadow_ram[i].modified = false; 3910 dev_spec->shadow_ram[i].value = 0xFFFF; 3911 } 3912 3913 release: 3914 nvm->ops.release(hw); 3915 3916 /* Reload the EEPROM, or else modifications will not appear 3917 * until after the next adapter reset. 3918 */ 3919 if (!ret_val) { 3920 nvm->ops.reload(hw); 3921 usleep_range(10000, 20000); 3922 } 3923 3924 out: 3925 if (ret_val) 3926 e_dbg("NVM update error: %d\n", ret_val); 3927 3928 return ret_val; 3929 } 3930 3931 /** 3932 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 3933 * @hw: pointer to the HW structure 3934 * 3935 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 3936 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 3937 * calculated, in which case we need to calculate the checksum and set bit 6. 3938 **/ 3939 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 3940 { 3941 s32 ret_val; 3942 u16 data; 3943 u16 word; 3944 u16 valid_csum_mask; 3945 3946 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, 3947 * the checksum needs to be fixed. This bit is an indication that 3948 * the NVM was prepared by OEM software and did not calculate 3949 * the checksum...a likely scenario. 3950 */ 3951 switch (hw->mac.type) { 3952 case e1000_pch_lpt: 3953 case e1000_pch_spt: 3954 word = NVM_COMPAT; 3955 valid_csum_mask = NVM_COMPAT_VALID_CSUM; 3956 break; 3957 default: 3958 word = NVM_FUTURE_INIT_WORD1; 3959 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; 3960 break; 3961 } 3962 3963 ret_val = e1000_read_nvm(hw, word, 1, &data); 3964 if (ret_val) 3965 return ret_val; 3966 3967 if (!(data & valid_csum_mask)) { 3968 data |= valid_csum_mask; 3969 ret_val = e1000_write_nvm(hw, word, 1, &data); 3970 if (ret_val) 3971 return ret_val; 3972 ret_val = e1000e_update_nvm_checksum(hw); 3973 if (ret_val) 3974 return ret_val; 3975 } 3976 3977 return e1000e_validate_nvm_checksum_generic(hw); 3978 } 3979 3980 /** 3981 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only 3982 * @hw: pointer to the HW structure 3983 * 3984 * To prevent malicious write/erase of the NVM, set it to be read-only 3985 * so that the hardware ignores all write/erase cycles of the NVM via 3986 * the flash control registers. The shadow-ram copy of the NVM will 3987 * still be updated, however any updates to this copy will not stick 3988 * across driver reloads. 3989 **/ 3990 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) 3991 { 3992 struct e1000_nvm_info *nvm = &hw->nvm; 3993 union ich8_flash_protected_range pr0; 3994 union ich8_hws_flash_status hsfsts; 3995 u32 gfpreg; 3996 3997 nvm->ops.acquire(hw); 3998 3999 gfpreg = er32flash(ICH_FLASH_GFPREG); 4000 4001 /* Write-protect GbE Sector of NVM */ 4002 pr0.regval = er32flash(ICH_FLASH_PR0); 4003 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; 4004 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); 4005 pr0.range.wpe = true; 4006 ew32flash(ICH_FLASH_PR0, pr0.regval); 4007 4008 /* Lock down a subset of GbE Flash Control Registers, e.g. 4009 * PR0 to prevent the write-protection from being lifted. 4010 * Once FLOCKDN is set, the registers protected by it cannot 4011 * be written until FLOCKDN is cleared by a hardware reset. 4012 */ 4013 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4014 hsfsts.hsf_status.flockdn = true; 4015 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); 4016 4017 nvm->ops.release(hw); 4018 } 4019 4020 /** 4021 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 4022 * @hw: pointer to the HW structure 4023 * @offset: The offset (in bytes) of the byte/word to read. 4024 * @size: Size of data to read, 1=byte 2=word 4025 * @data: The byte(s) to write to the NVM. 4026 * 4027 * Writes one/two bytes to the NVM using the flash access registers. 4028 **/ 4029 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 4030 u8 size, u16 data) 4031 { 4032 union ich8_hws_flash_status hsfsts; 4033 union ich8_hws_flash_ctrl hsflctl; 4034 u32 flash_linear_addr; 4035 u32 flash_data = 0; 4036 s32 ret_val; 4037 u8 count = 0; 4038 4039 if (hw->mac.type == e1000_pch_spt) { 4040 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4041 return -E1000_ERR_NVM; 4042 } else { 4043 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4044 return -E1000_ERR_NVM; 4045 } 4046 4047 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4048 hw->nvm.flash_base_addr); 4049 4050 do { 4051 udelay(1); 4052 /* Steps */ 4053 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4054 if (ret_val) 4055 break; 4056 /* In SPT, This register is in Lan memory space, not 4057 * flash. Therefore, only 32 bit access is supported 4058 */ 4059 if (hw->mac.type == e1000_pch_spt) 4060 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 4061 else 4062 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4063 4064 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 4065 hsflctl.hsf_ctrl.fldbcount = size - 1; 4066 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4067 /* In SPT, This register is in Lan memory space, 4068 * not flash. Therefore, only 32 bit access is 4069 * supported 4070 */ 4071 if (hw->mac.type == e1000_pch_spt) 4072 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4073 else 4074 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4075 4076 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4077 4078 if (size == 1) 4079 flash_data = (u32)data & 0x00FF; 4080 else 4081 flash_data = (u32)data; 4082 4083 ew32flash(ICH_FLASH_FDATA0, flash_data); 4084 4085 /* check if FCERR is set to 1 , if set to 1, clear it 4086 * and try the whole sequence a few more times else done 4087 */ 4088 ret_val = 4089 e1000_flash_cycle_ich8lan(hw, 4090 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4091 if (!ret_val) 4092 break; 4093 4094 /* If we're here, then things are most likely 4095 * completely hosed, but if the error condition 4096 * is detected, it won't hurt to give it another 4097 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4098 */ 4099 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4100 if (hsfsts.hsf_status.flcerr) 4101 /* Repeat for some time before giving up. */ 4102 continue; 4103 if (!hsfsts.hsf_status.flcdone) { 4104 e_dbg("Timeout error - flash cycle did not complete.\n"); 4105 break; 4106 } 4107 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4108 4109 return ret_val; 4110 } 4111 4112 /** 4113 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM 4114 * @hw: pointer to the HW structure 4115 * @offset: The offset (in bytes) of the dwords to read. 4116 * @data: The 4 bytes to write to the NVM. 4117 * 4118 * Writes one/two/four bytes to the NVM using the flash access registers. 4119 **/ 4120 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 4121 u32 data) 4122 { 4123 union ich8_hws_flash_status hsfsts; 4124 union ich8_hws_flash_ctrl hsflctl; 4125 u32 flash_linear_addr; 4126 s32 ret_val; 4127 u8 count = 0; 4128 4129 if (hw->mac.type == e1000_pch_spt) { 4130 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 4131 return -E1000_ERR_NVM; 4132 } 4133 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4134 hw->nvm.flash_base_addr); 4135 do { 4136 udelay(1); 4137 /* Steps */ 4138 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4139 if (ret_val) 4140 break; 4141 4142 /* In SPT, This register is in Lan memory space, not 4143 * flash. Therefore, only 32 bit access is supported 4144 */ 4145 if (hw->mac.type == e1000_pch_spt) 4146 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) 4147 >> 16; 4148 else 4149 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4150 4151 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 4152 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4153 4154 /* In SPT, This register is in Lan memory space, 4155 * not flash. Therefore, only 32 bit access is 4156 * supported 4157 */ 4158 if (hw->mac.type == e1000_pch_spt) 4159 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4160 else 4161 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4162 4163 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4164 4165 ew32flash(ICH_FLASH_FDATA0, data); 4166 4167 /* check if FCERR is set to 1 , if set to 1, clear it 4168 * and try the whole sequence a few more times else done 4169 */ 4170 ret_val = 4171 e1000_flash_cycle_ich8lan(hw, 4172 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4173 4174 if (!ret_val) 4175 break; 4176 4177 /* If we're here, then things are most likely 4178 * completely hosed, but if the error condition 4179 * is detected, it won't hurt to give it another 4180 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4181 */ 4182 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4183 4184 if (hsfsts.hsf_status.flcerr) 4185 /* Repeat for some time before giving up. */ 4186 continue; 4187 if (!hsfsts.hsf_status.flcdone) { 4188 e_dbg("Timeout error - flash cycle did not complete.\n"); 4189 break; 4190 } 4191 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4192 4193 return ret_val; 4194 } 4195 4196 /** 4197 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 4198 * @hw: pointer to the HW structure 4199 * @offset: The index of the byte to read. 4200 * @data: The byte to write to the NVM. 4201 * 4202 * Writes a single byte to the NVM using the flash access registers. 4203 **/ 4204 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 4205 u8 data) 4206 { 4207 u16 word = (u16)data; 4208 4209 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 4210 } 4211 4212 /** 4213 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM 4214 * @hw: pointer to the HW structure 4215 * @offset: The offset of the word to write. 4216 * @dword: The dword to write to the NVM. 4217 * 4218 * Writes a single dword to the NVM using the flash access registers. 4219 * Goes through a retry algorithm before giving up. 4220 **/ 4221 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 4222 u32 offset, u32 dword) 4223 { 4224 s32 ret_val; 4225 u16 program_retries; 4226 4227 /* Must convert word offset into bytes. */ 4228 offset <<= 1; 4229 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4230 4231 if (!ret_val) 4232 return ret_val; 4233 for (program_retries = 0; program_retries < 100; program_retries++) { 4234 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset); 4235 usleep_range(100, 200); 4236 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4237 if (!ret_val) 4238 break; 4239 } 4240 if (program_retries == 100) 4241 return -E1000_ERR_NVM; 4242 4243 return 0; 4244 } 4245 4246 /** 4247 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 4248 * @hw: pointer to the HW structure 4249 * @offset: The offset of the byte to write. 4250 * @byte: The byte to write to the NVM. 4251 * 4252 * Writes a single byte to the NVM using the flash access registers. 4253 * Goes through a retry algorithm before giving up. 4254 **/ 4255 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 4256 u32 offset, u8 byte) 4257 { 4258 s32 ret_val; 4259 u16 program_retries; 4260 4261 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4262 if (!ret_val) 4263 return ret_val; 4264 4265 for (program_retries = 0; program_retries < 100; program_retries++) { 4266 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); 4267 usleep_range(100, 200); 4268 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4269 if (!ret_val) 4270 break; 4271 } 4272 if (program_retries == 100) 4273 return -E1000_ERR_NVM; 4274 4275 return 0; 4276 } 4277 4278 /** 4279 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 4280 * @hw: pointer to the HW structure 4281 * @bank: 0 for first bank, 1 for second bank, etc. 4282 * 4283 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 4284 * bank N is 4096 * N + flash_reg_addr. 4285 **/ 4286 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 4287 { 4288 struct e1000_nvm_info *nvm = &hw->nvm; 4289 union ich8_hws_flash_status hsfsts; 4290 union ich8_hws_flash_ctrl hsflctl; 4291 u32 flash_linear_addr; 4292 /* bank size is in 16bit words - adjust to bytes */ 4293 u32 flash_bank_size = nvm->flash_bank_size * 2; 4294 s32 ret_val; 4295 s32 count = 0; 4296 s32 j, iteration, sector_size; 4297 4298 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4299 4300 /* Determine HW Sector size: Read BERASE bits of hw flash status 4301 * register 4302 * 00: The Hw sector is 256 bytes, hence we need to erase 16 4303 * consecutive sectors. The start index for the nth Hw sector 4304 * can be calculated as = bank * 4096 + n * 256 4305 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 4306 * The start index for the nth Hw sector can be calculated 4307 * as = bank * 4096 4308 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 4309 * (ich9 only, otherwise error condition) 4310 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 4311 */ 4312 switch (hsfsts.hsf_status.berasesz) { 4313 case 0: 4314 /* Hw sector size 256 */ 4315 sector_size = ICH_FLASH_SEG_SIZE_256; 4316 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 4317 break; 4318 case 1: 4319 sector_size = ICH_FLASH_SEG_SIZE_4K; 4320 iteration = 1; 4321 break; 4322 case 2: 4323 sector_size = ICH_FLASH_SEG_SIZE_8K; 4324 iteration = 1; 4325 break; 4326 case 3: 4327 sector_size = ICH_FLASH_SEG_SIZE_64K; 4328 iteration = 1; 4329 break; 4330 default: 4331 return -E1000_ERR_NVM; 4332 } 4333 4334 /* Start with the base address, then add the sector offset. */ 4335 flash_linear_addr = hw->nvm.flash_base_addr; 4336 flash_linear_addr += (bank) ? flash_bank_size : 0; 4337 4338 for (j = 0; j < iteration; j++) { 4339 do { 4340 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; 4341 4342 /* Steps */ 4343 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4344 if (ret_val) 4345 return ret_val; 4346 4347 /* Write a value 11 (block Erase) in Flash 4348 * Cycle field in hw flash control 4349 */ 4350 if (hw->mac.type == e1000_pch_spt) 4351 hsflctl.regval = 4352 er32flash(ICH_FLASH_HSFSTS) >> 16; 4353 else 4354 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4355 4356 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 4357 if (hw->mac.type == e1000_pch_spt) 4358 ew32flash(ICH_FLASH_HSFSTS, 4359 hsflctl.regval << 16); 4360 else 4361 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4362 4363 /* Write the last 24 bits of an index within the 4364 * block into Flash Linear address field in Flash 4365 * Address. 4366 */ 4367 flash_linear_addr += (j * sector_size); 4368 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4369 4370 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); 4371 if (!ret_val) 4372 break; 4373 4374 /* Check if FCERR is set to 1. If 1, 4375 * clear it and try the whole sequence 4376 * a few more times else Done 4377 */ 4378 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4379 if (hsfsts.hsf_status.flcerr) 4380 /* repeat for some time before giving up */ 4381 continue; 4382 else if (!hsfsts.hsf_status.flcdone) 4383 return ret_val; 4384 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 4385 } 4386 4387 return 0; 4388 } 4389 4390 /** 4391 * e1000_valid_led_default_ich8lan - Set the default LED settings 4392 * @hw: pointer to the HW structure 4393 * @data: Pointer to the LED settings 4394 * 4395 * Reads the LED default settings from the NVM to data. If the NVM LED 4396 * settings is all 0's or F's, set the LED default to a valid LED default 4397 * setting. 4398 **/ 4399 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 4400 { 4401 s32 ret_val; 4402 4403 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 4404 if (ret_val) { 4405 e_dbg("NVM Read Error\n"); 4406 return ret_val; 4407 } 4408 4409 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 4410 *data = ID_LED_DEFAULT_ICH8LAN; 4411 4412 return 0; 4413 } 4414 4415 /** 4416 * e1000_id_led_init_pchlan - store LED configurations 4417 * @hw: pointer to the HW structure 4418 * 4419 * PCH does not control LEDs via the LEDCTL register, rather it uses 4420 * the PHY LED configuration register. 4421 * 4422 * PCH also does not have an "always on" or "always off" mode which 4423 * complicates the ID feature. Instead of using the "on" mode to indicate 4424 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()), 4425 * use "link_up" mode. The LEDs will still ID on request if there is no 4426 * link based on logic in e1000_led_[on|off]_pchlan(). 4427 **/ 4428 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 4429 { 4430 struct e1000_mac_info *mac = &hw->mac; 4431 s32 ret_val; 4432 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 4433 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 4434 u16 data, i, temp, shift; 4435 4436 /* Get default ID LED modes */ 4437 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 4438 if (ret_val) 4439 return ret_val; 4440 4441 mac->ledctl_default = er32(LEDCTL); 4442 mac->ledctl_mode1 = mac->ledctl_default; 4443 mac->ledctl_mode2 = mac->ledctl_default; 4444 4445 for (i = 0; i < 4; i++) { 4446 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 4447 shift = (i * 5); 4448 switch (temp) { 4449 case ID_LED_ON1_DEF2: 4450 case ID_LED_ON1_ON2: 4451 case ID_LED_ON1_OFF2: 4452 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4453 mac->ledctl_mode1 |= (ledctl_on << shift); 4454 break; 4455 case ID_LED_OFF1_DEF2: 4456 case ID_LED_OFF1_ON2: 4457 case ID_LED_OFF1_OFF2: 4458 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4459 mac->ledctl_mode1 |= (ledctl_off << shift); 4460 break; 4461 default: 4462 /* Do nothing */ 4463 break; 4464 } 4465 switch (temp) { 4466 case ID_LED_DEF1_ON2: 4467 case ID_LED_ON1_ON2: 4468 case ID_LED_OFF1_ON2: 4469 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4470 mac->ledctl_mode2 |= (ledctl_on << shift); 4471 break; 4472 case ID_LED_DEF1_OFF2: 4473 case ID_LED_ON1_OFF2: 4474 case ID_LED_OFF1_OFF2: 4475 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4476 mac->ledctl_mode2 |= (ledctl_off << shift); 4477 break; 4478 default: 4479 /* Do nothing */ 4480 break; 4481 } 4482 } 4483 4484 return 0; 4485 } 4486 4487 /** 4488 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 4489 * @hw: pointer to the HW structure 4490 * 4491 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 4492 * register, so the the bus width is hard coded. 4493 **/ 4494 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 4495 { 4496 struct e1000_bus_info *bus = &hw->bus; 4497 s32 ret_val; 4498 4499 ret_val = e1000e_get_bus_info_pcie(hw); 4500 4501 /* ICH devices are "PCI Express"-ish. They have 4502 * a configuration space, but do not contain 4503 * PCI Express Capability registers, so bus width 4504 * must be hardcoded. 4505 */ 4506 if (bus->width == e1000_bus_width_unknown) 4507 bus->width = e1000_bus_width_pcie_x1; 4508 4509 return ret_val; 4510 } 4511 4512 /** 4513 * e1000_reset_hw_ich8lan - Reset the hardware 4514 * @hw: pointer to the HW structure 4515 * 4516 * Does a full reset of the hardware which includes a reset of the PHY and 4517 * MAC. 4518 **/ 4519 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 4520 { 4521 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4522 u16 kum_cfg; 4523 u32 ctrl, reg; 4524 s32 ret_val; 4525 4526 /* Prevent the PCI-E bus from sticking if there is no TLP connection 4527 * on the last TLP read/write transaction when MAC is reset. 4528 */ 4529 ret_val = e1000e_disable_pcie_master(hw); 4530 if (ret_val) 4531 e_dbg("PCI-E Master disable polling has failed.\n"); 4532 4533 e_dbg("Masking off all interrupts\n"); 4534 ew32(IMC, 0xffffffff); 4535 4536 /* Disable the Transmit and Receive units. Then delay to allow 4537 * any pending transactions to complete before we hit the MAC 4538 * with the global reset. 4539 */ 4540 ew32(RCTL, 0); 4541 ew32(TCTL, E1000_TCTL_PSP); 4542 e1e_flush(); 4543 4544 usleep_range(10000, 20000); 4545 4546 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 4547 if (hw->mac.type == e1000_ich8lan) { 4548 /* Set Tx and Rx buffer allocation to 8k apiece. */ 4549 ew32(PBA, E1000_PBA_8K); 4550 /* Set Packet Buffer Size to 16k. */ 4551 ew32(PBS, E1000_PBS_16K); 4552 } 4553 4554 if (hw->mac.type == e1000_pchlan) { 4555 /* Save the NVM K1 bit setting */ 4556 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 4557 if (ret_val) 4558 return ret_val; 4559 4560 if (kum_cfg & E1000_NVM_K1_ENABLE) 4561 dev_spec->nvm_k1_enabled = true; 4562 else 4563 dev_spec->nvm_k1_enabled = false; 4564 } 4565 4566 ctrl = er32(CTRL); 4567 4568 if (!hw->phy.ops.check_reset_block(hw)) { 4569 /* Full-chip reset requires MAC and PHY reset at the same 4570 * time to make sure the interface between MAC and the 4571 * external PHY is reset. 4572 */ 4573 ctrl |= E1000_CTRL_PHY_RST; 4574 4575 /* Gate automatic PHY configuration by hardware on 4576 * non-managed 82579 4577 */ 4578 if ((hw->mac.type == e1000_pch2lan) && 4579 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 4580 e1000_gate_hw_phy_config_ich8lan(hw, true); 4581 } 4582 ret_val = e1000_acquire_swflag_ich8lan(hw); 4583 e_dbg("Issuing a global reset to ich8lan\n"); 4584 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 4585 /* cannot issue a flush here because it hangs the hardware */ 4586 msleep(20); 4587 4588 /* Set Phy Config Counter to 50msec */ 4589 if (hw->mac.type == e1000_pch2lan) { 4590 reg = er32(FEXTNVM3); 4591 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 4592 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 4593 ew32(FEXTNVM3, reg); 4594 } 4595 4596 if (!ret_val) 4597 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 4598 4599 if (ctrl & E1000_CTRL_PHY_RST) { 4600 ret_val = hw->phy.ops.get_cfg_done(hw); 4601 if (ret_val) 4602 return ret_val; 4603 4604 ret_val = e1000_post_phy_reset_ich8lan(hw); 4605 if (ret_val) 4606 return ret_val; 4607 } 4608 4609 /* For PCH, this write will make sure that any noise 4610 * will be detected as a CRC error and be dropped rather than show up 4611 * as a bad packet to the DMA engine. 4612 */ 4613 if (hw->mac.type == e1000_pchlan) 4614 ew32(CRC_OFFSET, 0x65656565); 4615 4616 ew32(IMC, 0xffffffff); 4617 er32(ICR); 4618 4619 reg = er32(KABGTXD); 4620 reg |= E1000_KABGTXD_BGSQLBIAS; 4621 ew32(KABGTXD, reg); 4622 4623 return 0; 4624 } 4625 4626 /** 4627 * e1000_init_hw_ich8lan - Initialize the hardware 4628 * @hw: pointer to the HW structure 4629 * 4630 * Prepares the hardware for transmit and receive by doing the following: 4631 * - initialize hardware bits 4632 * - initialize LED identification 4633 * - setup receive address registers 4634 * - setup flow control 4635 * - setup transmit descriptors 4636 * - clear statistics 4637 **/ 4638 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 4639 { 4640 struct e1000_mac_info *mac = &hw->mac; 4641 u32 ctrl_ext, txdctl, snoop; 4642 s32 ret_val; 4643 u16 i; 4644 4645 e1000_initialize_hw_bits_ich8lan(hw); 4646 4647 /* Initialize identification LED */ 4648 ret_val = mac->ops.id_led_init(hw); 4649 /* An error is not fatal and we should not stop init due to this */ 4650 if (ret_val) 4651 e_dbg("Error initializing identification LED\n"); 4652 4653 /* Setup the receive address. */ 4654 e1000e_init_rx_addrs(hw, mac->rar_entry_count); 4655 4656 /* Zero out the Multicast HASH table */ 4657 e_dbg("Zeroing the MTA\n"); 4658 for (i = 0; i < mac->mta_reg_count; i++) 4659 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 4660 4661 /* The 82578 Rx buffer will stall if wakeup is enabled in host and 4662 * the ME. Disable wakeup by clearing the host wakeup bit. 4663 * Reset the phy after disabling host wakeup to reset the Rx buffer. 4664 */ 4665 if (hw->phy.type == e1000_phy_82578) { 4666 e1e_rphy(hw, BM_PORT_GEN_CFG, &i); 4667 i &= ~BM_WUC_HOST_WU_BIT; 4668 e1e_wphy(hw, BM_PORT_GEN_CFG, i); 4669 ret_val = e1000_phy_hw_reset_ich8lan(hw); 4670 if (ret_val) 4671 return ret_val; 4672 } 4673 4674 /* Setup link and flow control */ 4675 ret_val = mac->ops.setup_link(hw); 4676 4677 /* Set the transmit descriptor write-back policy for both queues */ 4678 txdctl = er32(TXDCTL(0)); 4679 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 4680 E1000_TXDCTL_FULL_TX_DESC_WB); 4681 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 4682 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 4683 ew32(TXDCTL(0), txdctl); 4684 txdctl = er32(TXDCTL(1)); 4685 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 4686 E1000_TXDCTL_FULL_TX_DESC_WB); 4687 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 4688 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 4689 ew32(TXDCTL(1), txdctl); 4690 4691 /* ICH8 has opposite polarity of no_snoop bits. 4692 * By default, we should use snoop behavior. 4693 */ 4694 if (mac->type == e1000_ich8lan) 4695 snoop = PCIE_ICH8_SNOOP_ALL; 4696 else 4697 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 4698 e1000e_set_pcie_no_snoop(hw, snoop); 4699 4700 ctrl_ext = er32(CTRL_EXT); 4701 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 4702 ew32(CTRL_EXT, ctrl_ext); 4703 4704 /* Clear all of the statistics registers (clear on read). It is 4705 * important that we do this after we have tried to establish link 4706 * because the symbol error count will increment wildly if there 4707 * is no link. 4708 */ 4709 e1000_clear_hw_cntrs_ich8lan(hw); 4710 4711 return ret_val; 4712 } 4713 4714 /** 4715 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 4716 * @hw: pointer to the HW structure 4717 * 4718 * Sets/Clears required hardware bits necessary for correctly setting up the 4719 * hardware for transmit and receive. 4720 **/ 4721 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 4722 { 4723 u32 reg; 4724 4725 /* Extended Device Control */ 4726 reg = er32(CTRL_EXT); 4727 reg |= (1 << 22); 4728 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 4729 if (hw->mac.type >= e1000_pchlan) 4730 reg |= E1000_CTRL_EXT_PHYPDEN; 4731 ew32(CTRL_EXT, reg); 4732 4733 /* Transmit Descriptor Control 0 */ 4734 reg = er32(TXDCTL(0)); 4735 reg |= (1 << 22); 4736 ew32(TXDCTL(0), reg); 4737 4738 /* Transmit Descriptor Control 1 */ 4739 reg = er32(TXDCTL(1)); 4740 reg |= (1 << 22); 4741 ew32(TXDCTL(1), reg); 4742 4743 /* Transmit Arbitration Control 0 */ 4744 reg = er32(TARC(0)); 4745 if (hw->mac.type == e1000_ich8lan) 4746 reg |= (1 << 28) | (1 << 29); 4747 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 4748 ew32(TARC(0), reg); 4749 4750 /* Transmit Arbitration Control 1 */ 4751 reg = er32(TARC(1)); 4752 if (er32(TCTL) & E1000_TCTL_MULR) 4753 reg &= ~(1 << 28); 4754 else 4755 reg |= (1 << 28); 4756 reg |= (1 << 24) | (1 << 26) | (1 << 30); 4757 ew32(TARC(1), reg); 4758 4759 /* Device Status */ 4760 if (hw->mac.type == e1000_ich8lan) { 4761 reg = er32(STATUS); 4762 reg &= ~(1 << 31); 4763 ew32(STATUS, reg); 4764 } 4765 4766 /* work-around descriptor data corruption issue during nfs v2 udp 4767 * traffic, just disable the nfs filtering capability 4768 */ 4769 reg = er32(RFCTL); 4770 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 4771 4772 /* Disable IPv6 extension header parsing because some malformed 4773 * IPv6 headers can hang the Rx. 4774 */ 4775 if (hw->mac.type == e1000_ich8lan) 4776 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 4777 ew32(RFCTL, reg); 4778 4779 /* Enable ECC on Lynxpoint */ 4780 if ((hw->mac.type == e1000_pch_lpt) || 4781 (hw->mac.type == e1000_pch_spt)) { 4782 reg = er32(PBECCSTS); 4783 reg |= E1000_PBECCSTS_ECC_ENABLE; 4784 ew32(PBECCSTS, reg); 4785 4786 reg = er32(CTRL); 4787 reg |= E1000_CTRL_MEHE; 4788 ew32(CTRL, reg); 4789 } 4790 } 4791 4792 /** 4793 * e1000_setup_link_ich8lan - Setup flow control and link settings 4794 * @hw: pointer to the HW structure 4795 * 4796 * Determines which flow control settings to use, then configures flow 4797 * control. Calls the appropriate media-specific link configuration 4798 * function. Assuming the adapter has a valid link partner, a valid link 4799 * should be established. Assumes the hardware has previously been reset 4800 * and the transmitter and receiver are not enabled. 4801 **/ 4802 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 4803 { 4804 s32 ret_val; 4805 4806 if (hw->phy.ops.check_reset_block(hw)) 4807 return 0; 4808 4809 /* ICH parts do not have a word in the NVM to determine 4810 * the default flow control setting, so we explicitly 4811 * set it to full. 4812 */ 4813 if (hw->fc.requested_mode == e1000_fc_default) { 4814 /* Workaround h/w hang when Tx flow control enabled */ 4815 if (hw->mac.type == e1000_pchlan) 4816 hw->fc.requested_mode = e1000_fc_rx_pause; 4817 else 4818 hw->fc.requested_mode = e1000_fc_full; 4819 } 4820 4821 /* Save off the requested flow control mode for use later. Depending 4822 * on the link partner's capabilities, we may or may not use this mode. 4823 */ 4824 hw->fc.current_mode = hw->fc.requested_mode; 4825 4826 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 4827 4828 /* Continue to configure the copper link. */ 4829 ret_val = hw->mac.ops.setup_physical_interface(hw); 4830 if (ret_val) 4831 return ret_val; 4832 4833 ew32(FCTTV, hw->fc.pause_time); 4834 if ((hw->phy.type == e1000_phy_82578) || 4835 (hw->phy.type == e1000_phy_82579) || 4836 (hw->phy.type == e1000_phy_i217) || 4837 (hw->phy.type == e1000_phy_82577)) { 4838 ew32(FCRTV_PCH, hw->fc.refresh_time); 4839 4840 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 4841 hw->fc.pause_time); 4842 if (ret_val) 4843 return ret_val; 4844 } 4845 4846 return e1000e_set_fc_watermarks(hw); 4847 } 4848 4849 /** 4850 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 4851 * @hw: pointer to the HW structure 4852 * 4853 * Configures the kumeran interface to the PHY to wait the appropriate time 4854 * when polling the PHY, then call the generic setup_copper_link to finish 4855 * configuring the copper link. 4856 **/ 4857 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 4858 { 4859 u32 ctrl; 4860 s32 ret_val; 4861 u16 reg_data; 4862 4863 ctrl = er32(CTRL); 4864 ctrl |= E1000_CTRL_SLU; 4865 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 4866 ew32(CTRL, ctrl); 4867 4868 /* Set the mac to wait the maximum time between each iteration 4869 * and increase the max iterations when polling the phy; 4870 * this fixes erroneous timeouts at 10Mbps. 4871 */ 4872 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); 4873 if (ret_val) 4874 return ret_val; 4875 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 4876 ®_data); 4877 if (ret_val) 4878 return ret_val; 4879 reg_data |= 0x3F; 4880 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 4881 reg_data); 4882 if (ret_val) 4883 return ret_val; 4884 4885 switch (hw->phy.type) { 4886 case e1000_phy_igp_3: 4887 ret_val = e1000e_copper_link_setup_igp(hw); 4888 if (ret_val) 4889 return ret_val; 4890 break; 4891 case e1000_phy_bm: 4892 case e1000_phy_82578: 4893 ret_val = e1000e_copper_link_setup_m88(hw); 4894 if (ret_val) 4895 return ret_val; 4896 break; 4897 case e1000_phy_82577: 4898 case e1000_phy_82579: 4899 ret_val = e1000_copper_link_setup_82577(hw); 4900 if (ret_val) 4901 return ret_val; 4902 break; 4903 case e1000_phy_ife: 4904 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); 4905 if (ret_val) 4906 return ret_val; 4907 4908 reg_data &= ~IFE_PMC_AUTO_MDIX; 4909 4910 switch (hw->phy.mdix) { 4911 case 1: 4912 reg_data &= ~IFE_PMC_FORCE_MDIX; 4913 break; 4914 case 2: 4915 reg_data |= IFE_PMC_FORCE_MDIX; 4916 break; 4917 case 0: 4918 default: 4919 reg_data |= IFE_PMC_AUTO_MDIX; 4920 break; 4921 } 4922 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); 4923 if (ret_val) 4924 return ret_val; 4925 break; 4926 default: 4927 break; 4928 } 4929 4930 return e1000e_setup_copper_link(hw); 4931 } 4932 4933 /** 4934 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface 4935 * @hw: pointer to the HW structure 4936 * 4937 * Calls the PHY specific link setup function and then calls the 4938 * generic setup_copper_link to finish configuring the link for 4939 * Lynxpoint PCH devices 4940 **/ 4941 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) 4942 { 4943 u32 ctrl; 4944 s32 ret_val; 4945 4946 ctrl = er32(CTRL); 4947 ctrl |= E1000_CTRL_SLU; 4948 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 4949 ew32(CTRL, ctrl); 4950 4951 ret_val = e1000_copper_link_setup_82577(hw); 4952 if (ret_val) 4953 return ret_val; 4954 4955 return e1000e_setup_copper_link(hw); 4956 } 4957 4958 /** 4959 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 4960 * @hw: pointer to the HW structure 4961 * @speed: pointer to store current link speed 4962 * @duplex: pointer to store the current link duplex 4963 * 4964 * Calls the generic get_speed_and_duplex to retrieve the current link 4965 * information and then calls the Kumeran lock loss workaround for links at 4966 * gigabit speeds. 4967 **/ 4968 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 4969 u16 *duplex) 4970 { 4971 s32 ret_val; 4972 4973 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); 4974 if (ret_val) 4975 return ret_val; 4976 4977 if ((hw->mac.type == e1000_ich8lan) && 4978 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { 4979 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 4980 } 4981 4982 return ret_val; 4983 } 4984 4985 /** 4986 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 4987 * @hw: pointer to the HW structure 4988 * 4989 * Work-around for 82566 Kumeran PCS lock loss: 4990 * On link status change (i.e. PCI reset, speed change) and link is up and 4991 * speed is gigabit- 4992 * 0) if workaround is optionally disabled do nothing 4993 * 1) wait 1ms for Kumeran link to come up 4994 * 2) check Kumeran Diagnostic register PCS lock loss bit 4995 * 3) if not set the link is locked (all is good), otherwise... 4996 * 4) reset the PHY 4997 * 5) repeat up to 10 times 4998 * Note: this is only called for IGP3 copper when speed is 1gb. 4999 **/ 5000 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 5001 { 5002 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5003 u32 phy_ctrl; 5004 s32 ret_val; 5005 u16 i, data; 5006 bool link; 5007 5008 if (!dev_spec->kmrn_lock_loss_workaround_enabled) 5009 return 0; 5010 5011 /* Make sure link is up before proceeding. If not just return. 5012 * Attempting this while link is negotiating fouled up link 5013 * stability 5014 */ 5015 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 5016 if (!link) 5017 return 0; 5018 5019 for (i = 0; i < 10; i++) { 5020 /* read once to clear */ 5021 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5022 if (ret_val) 5023 return ret_val; 5024 /* and again to get new status */ 5025 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5026 if (ret_val) 5027 return ret_val; 5028 5029 /* check for PCS lock */ 5030 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5031 return 0; 5032 5033 /* Issue PHY reset */ 5034 e1000_phy_hw_reset(hw); 5035 mdelay(5); 5036 } 5037 /* Disable GigE link negotiation */ 5038 phy_ctrl = er32(PHY_CTRL); 5039 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 5040 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5041 ew32(PHY_CTRL, phy_ctrl); 5042 5043 /* Call gig speed drop workaround on Gig disable before accessing 5044 * any PHY registers 5045 */ 5046 e1000e_gig_downshift_workaround_ich8lan(hw); 5047 5048 /* unable to acquire PCS lock */ 5049 return -E1000_ERR_PHY; 5050 } 5051 5052 /** 5053 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 5054 * @hw: pointer to the HW structure 5055 * @state: boolean value used to set the current Kumeran workaround state 5056 * 5057 * If ICH8, set the current Kumeran workaround state (enabled - true 5058 * /disabled - false). 5059 **/ 5060 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 5061 bool state) 5062 { 5063 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5064 5065 if (hw->mac.type != e1000_ich8lan) { 5066 e_dbg("Workaround applies to ICH8 only.\n"); 5067 return; 5068 } 5069 5070 dev_spec->kmrn_lock_loss_workaround_enabled = state; 5071 } 5072 5073 /** 5074 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 5075 * @hw: pointer to the HW structure 5076 * 5077 * Workaround for 82566 power-down on D3 entry: 5078 * 1) disable gigabit link 5079 * 2) write VR power-down enable 5080 * 3) read it back 5081 * Continue if successful, else issue LCD reset and repeat 5082 **/ 5083 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 5084 { 5085 u32 reg; 5086 u16 data; 5087 u8 retry = 0; 5088 5089 if (hw->phy.type != e1000_phy_igp_3) 5090 return; 5091 5092 /* Try the workaround twice (if needed) */ 5093 do { 5094 /* Disable link */ 5095 reg = er32(PHY_CTRL); 5096 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 5097 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5098 ew32(PHY_CTRL, reg); 5099 5100 /* Call gig speed drop workaround on Gig disable before 5101 * accessing any PHY registers 5102 */ 5103 if (hw->mac.type == e1000_ich8lan) 5104 e1000e_gig_downshift_workaround_ich8lan(hw); 5105 5106 /* Write VR power-down enable */ 5107 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5108 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5109 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); 5110 5111 /* Read it back and test */ 5112 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5113 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5114 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 5115 break; 5116 5117 /* Issue PHY reset and repeat at most one more time */ 5118 reg = er32(CTRL); 5119 ew32(CTRL, reg | E1000_CTRL_PHY_RST); 5120 retry++; 5121 } while (retry); 5122 } 5123 5124 /** 5125 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working 5126 * @hw: pointer to the HW structure 5127 * 5128 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 5129 * LPLU, Gig disable, MDIC PHY reset): 5130 * 1) Set Kumeran Near-end loopback 5131 * 2) Clear Kumeran Near-end loopback 5132 * Should only be called for ICH8[m] devices with any 1G Phy. 5133 **/ 5134 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 5135 { 5136 s32 ret_val; 5137 u16 reg_data; 5138 5139 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) 5140 return; 5141 5142 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5143 ®_data); 5144 if (ret_val) 5145 return; 5146 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 5147 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5148 reg_data); 5149 if (ret_val) 5150 return; 5151 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 5152 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); 5153 } 5154 5155 /** 5156 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx 5157 * @hw: pointer to the HW structure 5158 * 5159 * During S0 to Sx transition, it is possible the link remains at gig 5160 * instead of negotiating to a lower speed. Before going to Sx, set 5161 * 'Gig Disable' to force link speed negotiation to a lower speed based on 5162 * the LPLU setting in the NVM or custom setting. For PCH and newer parts, 5163 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also 5164 * needs to be written. 5165 * Parts that support (and are linked to a partner which support) EEE in 5166 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power 5167 * than 10Mbps w/o EEE. 5168 **/ 5169 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 5170 { 5171 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5172 u32 phy_ctrl; 5173 s32 ret_val; 5174 5175 phy_ctrl = er32(PHY_CTRL); 5176 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; 5177 5178 if (hw->phy.type == e1000_phy_i217) { 5179 u16 phy_reg, device_id = hw->adapter->pdev->device; 5180 5181 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 5182 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 5183 (device_id == E1000_DEV_ID_PCH_I218_LM3) || 5184 (device_id == E1000_DEV_ID_PCH_I218_V3) || 5185 (hw->mac.type == e1000_pch_spt)) { 5186 u32 fextnvm6 = er32(FEXTNVM6); 5187 5188 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 5189 } 5190 5191 ret_val = hw->phy.ops.acquire(hw); 5192 if (ret_val) 5193 goto out; 5194 5195 if (!dev_spec->eee_disable) { 5196 u16 eee_advert; 5197 5198 ret_val = 5199 e1000_read_emi_reg_locked(hw, 5200 I217_EEE_ADVERTISEMENT, 5201 &eee_advert); 5202 if (ret_val) 5203 goto release; 5204 5205 /* Disable LPLU if both link partners support 100BaseT 5206 * EEE and 100Full is advertised on both ends of the 5207 * link, and enable Auto Enable LPI since there will 5208 * be no driver to enable LPI while in Sx. 5209 */ 5210 if ((eee_advert & I82579_EEE_100_SUPPORTED) && 5211 (dev_spec->eee_lp_ability & 5212 I82579_EEE_100_SUPPORTED) && 5213 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { 5214 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | 5215 E1000_PHY_CTRL_NOND0A_LPLU); 5216 5217 /* Set Auto Enable LPI after link up */ 5218 e1e_rphy_locked(hw, 5219 I217_LPI_GPIO_CTRL, &phy_reg); 5220 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5221 e1e_wphy_locked(hw, 5222 I217_LPI_GPIO_CTRL, phy_reg); 5223 } 5224 } 5225 5226 /* For i217 Intel Rapid Start Technology support, 5227 * when the system is going into Sx and no manageability engine 5228 * is present, the driver must configure proxy to reset only on 5229 * power good. LPI (Low Power Idle) state must also reset only 5230 * on power good, as well as the MTA (Multicast table array). 5231 * The SMBus release must also be disabled on LCD reset. 5232 */ 5233 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5234 /* Enable proxy to reset only on power good. */ 5235 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); 5236 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 5237 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); 5238 5239 /* Set bit enable LPI (EEE) to reset only on 5240 * power good. 5241 */ 5242 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); 5243 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; 5244 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); 5245 5246 /* Disable the SMB release on LCD reset. */ 5247 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5248 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; 5249 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5250 } 5251 5252 /* Enable MTA to reset for Intel Rapid Start Technology 5253 * Support 5254 */ 5255 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5256 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; 5257 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5258 5259 release: 5260 hw->phy.ops.release(hw); 5261 } 5262 out: 5263 ew32(PHY_CTRL, phy_ctrl); 5264 5265 if (hw->mac.type == e1000_ich8lan) 5266 e1000e_gig_downshift_workaround_ich8lan(hw); 5267 5268 if (hw->mac.type >= e1000_pchlan) { 5269 e1000_oem_bits_config_ich8lan(hw, false); 5270 5271 /* Reset PHY to activate OEM bits on 82577/8 */ 5272 if (hw->mac.type == e1000_pchlan) 5273 e1000e_phy_hw_reset_generic(hw); 5274 5275 ret_val = hw->phy.ops.acquire(hw); 5276 if (ret_val) 5277 return; 5278 e1000_write_smbus_addr(hw); 5279 hw->phy.ops.release(hw); 5280 } 5281 } 5282 5283 /** 5284 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 5285 * @hw: pointer to the HW structure 5286 * 5287 * During Sx to S0 transitions on non-managed devices or managed devices 5288 * on which PHY resets are not blocked, if the PHY registers cannot be 5289 * accessed properly by the s/w toggle the LANPHYPC value to power cycle 5290 * the PHY. 5291 * On i217, setup Intel Rapid Start Technology. 5292 **/ 5293 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 5294 { 5295 s32 ret_val; 5296 5297 if (hw->mac.type < e1000_pch2lan) 5298 return; 5299 5300 ret_val = e1000_init_phy_workarounds_pchlan(hw); 5301 if (ret_val) { 5302 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val); 5303 return; 5304 } 5305 5306 /* For i217 Intel Rapid Start Technology support when the system 5307 * is transitioning from Sx and no manageability engine is present 5308 * configure SMBus to restore on reset, disable proxy, and enable 5309 * the reset on MTA (Multicast table array). 5310 */ 5311 if (hw->phy.type == e1000_phy_i217) { 5312 u16 phy_reg; 5313 5314 ret_val = hw->phy.ops.acquire(hw); 5315 if (ret_val) { 5316 e_dbg("Failed to setup iRST\n"); 5317 return; 5318 } 5319 5320 /* Clear Auto Enable LPI after link up */ 5321 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); 5322 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5323 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); 5324 5325 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5326 /* Restore clear on SMB if no manageability engine 5327 * is present 5328 */ 5329 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5330 if (ret_val) 5331 goto release; 5332 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; 5333 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5334 5335 /* Disable Proxy */ 5336 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); 5337 } 5338 /* Enable reset on MTA */ 5339 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5340 if (ret_val) 5341 goto release; 5342 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; 5343 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5344 release: 5345 if (ret_val) 5346 e_dbg("Error %d in resume workarounds\n", ret_val); 5347 hw->phy.ops.release(hw); 5348 } 5349 } 5350 5351 /** 5352 * e1000_cleanup_led_ich8lan - Restore the default LED operation 5353 * @hw: pointer to the HW structure 5354 * 5355 * Return the LED back to the default configuration. 5356 **/ 5357 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 5358 { 5359 if (hw->phy.type == e1000_phy_ife) 5360 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); 5361 5362 ew32(LEDCTL, hw->mac.ledctl_default); 5363 return 0; 5364 } 5365 5366 /** 5367 * e1000_led_on_ich8lan - Turn LEDs on 5368 * @hw: pointer to the HW structure 5369 * 5370 * Turn on the LEDs. 5371 **/ 5372 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 5373 { 5374 if (hw->phy.type == e1000_phy_ife) 5375 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5376 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 5377 5378 ew32(LEDCTL, hw->mac.ledctl_mode2); 5379 return 0; 5380 } 5381 5382 /** 5383 * e1000_led_off_ich8lan - Turn LEDs off 5384 * @hw: pointer to the HW structure 5385 * 5386 * Turn off the LEDs. 5387 **/ 5388 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 5389 { 5390 if (hw->phy.type == e1000_phy_ife) 5391 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5392 (IFE_PSCL_PROBE_MODE | 5393 IFE_PSCL_PROBE_LEDS_OFF)); 5394 5395 ew32(LEDCTL, hw->mac.ledctl_mode1); 5396 return 0; 5397 } 5398 5399 /** 5400 * e1000_setup_led_pchlan - Configures SW controllable LED 5401 * @hw: pointer to the HW structure 5402 * 5403 * This prepares the SW controllable LED for use. 5404 **/ 5405 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 5406 { 5407 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); 5408 } 5409 5410 /** 5411 * e1000_cleanup_led_pchlan - Restore the default LED operation 5412 * @hw: pointer to the HW structure 5413 * 5414 * Return the LED back to the default configuration. 5415 **/ 5416 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 5417 { 5418 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); 5419 } 5420 5421 /** 5422 * e1000_led_on_pchlan - Turn LEDs on 5423 * @hw: pointer to the HW structure 5424 * 5425 * Turn on the LEDs. 5426 **/ 5427 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) 5428 { 5429 u16 data = (u16)hw->mac.ledctl_mode2; 5430 u32 i, led; 5431 5432 /* If no link, then turn LED on by setting the invert bit 5433 * for each LED that's mode is "link_up" in ledctl_mode2. 5434 */ 5435 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5436 for (i = 0; i < 3; i++) { 5437 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5438 if ((led & E1000_PHY_LED0_MODE_MASK) != 5439 E1000_LEDCTL_MODE_LINK_UP) 5440 continue; 5441 if (led & E1000_PHY_LED0_IVRT) 5442 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5443 else 5444 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5445 } 5446 } 5447 5448 return e1e_wphy(hw, HV_LED_CONFIG, data); 5449 } 5450 5451 /** 5452 * e1000_led_off_pchlan - Turn LEDs off 5453 * @hw: pointer to the HW structure 5454 * 5455 * Turn off the LEDs. 5456 **/ 5457 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) 5458 { 5459 u16 data = (u16)hw->mac.ledctl_mode1; 5460 u32 i, led; 5461 5462 /* If no link, then turn LED off by clearing the invert bit 5463 * for each LED that's mode is "link_up" in ledctl_mode1. 5464 */ 5465 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5466 for (i = 0; i < 3; i++) { 5467 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5468 if ((led & E1000_PHY_LED0_MODE_MASK) != 5469 E1000_LEDCTL_MODE_LINK_UP) 5470 continue; 5471 if (led & E1000_PHY_LED0_IVRT) 5472 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5473 else 5474 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5475 } 5476 } 5477 5478 return e1e_wphy(hw, HV_LED_CONFIG, data); 5479 } 5480 5481 /** 5482 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 5483 * @hw: pointer to the HW structure 5484 * 5485 * Read appropriate register for the config done bit for completion status 5486 * and configure the PHY through s/w for EEPROM-less parts. 5487 * 5488 * NOTE: some silicon which is EEPROM-less will fail trying to read the 5489 * config done bit, so only an error is logged and continues. If we were 5490 * to return with error, EEPROM-less silicon would not be able to be reset 5491 * or change link. 5492 **/ 5493 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 5494 { 5495 s32 ret_val = 0; 5496 u32 bank = 0; 5497 u32 status; 5498 5499 e1000e_get_cfg_done_generic(hw); 5500 5501 /* Wait for indication from h/w that it has completed basic config */ 5502 if (hw->mac.type >= e1000_ich10lan) { 5503 e1000_lan_init_done_ich8lan(hw); 5504 } else { 5505 ret_val = e1000e_get_auto_rd_done(hw); 5506 if (ret_val) { 5507 /* When auto config read does not complete, do not 5508 * return with an error. This can happen in situations 5509 * where there is no eeprom and prevents getting link. 5510 */ 5511 e_dbg("Auto Read Done did not complete\n"); 5512 ret_val = 0; 5513 } 5514 } 5515 5516 /* Clear PHY Reset Asserted bit */ 5517 status = er32(STATUS); 5518 if (status & E1000_STATUS_PHYRA) 5519 ew32(STATUS, status & ~E1000_STATUS_PHYRA); 5520 else 5521 e_dbg("PHY Reset Asserted not set - needs delay\n"); 5522 5523 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 5524 if (hw->mac.type <= e1000_ich9lan) { 5525 if (!(er32(EECD) & E1000_EECD_PRES) && 5526 (hw->phy.type == e1000_phy_igp_3)) { 5527 e1000e_phy_init_script_igp3(hw); 5528 } 5529 } else { 5530 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 5531 /* Maybe we should do a basic PHY config */ 5532 e_dbg("EEPROM not present\n"); 5533 ret_val = -E1000_ERR_CONFIG; 5534 } 5535 } 5536 5537 return ret_val; 5538 } 5539 5540 /** 5541 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 5542 * @hw: pointer to the HW structure 5543 * 5544 * In the case of a PHY power down to save power, or to turn off link during a 5545 * driver unload, or wake on lan is not enabled, remove the link. 5546 **/ 5547 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 5548 { 5549 /* If the management interface is not enabled, then power down */ 5550 if (!(hw->mac.ops.check_mng_mode(hw) || 5551 hw->phy.ops.check_reset_block(hw))) 5552 e1000_power_down_phy_copper(hw); 5553 } 5554 5555 /** 5556 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 5557 * @hw: pointer to the HW structure 5558 * 5559 * Clears hardware counters specific to the silicon family and calls 5560 * clear_hw_cntrs_generic to clear all general purpose counters. 5561 **/ 5562 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 5563 { 5564 u16 phy_data; 5565 s32 ret_val; 5566 5567 e1000e_clear_hw_cntrs_base(hw); 5568 5569 er32(ALGNERRC); 5570 er32(RXERRC); 5571 er32(TNCRS); 5572 er32(CEXTERR); 5573 er32(TSCTC); 5574 er32(TSCTFC); 5575 5576 er32(MGTPRC); 5577 er32(MGTPDC); 5578 er32(MGTPTC); 5579 5580 er32(IAC); 5581 er32(ICRXOC); 5582 5583 /* Clear PHY statistics registers */ 5584 if ((hw->phy.type == e1000_phy_82578) || 5585 (hw->phy.type == e1000_phy_82579) || 5586 (hw->phy.type == e1000_phy_i217) || 5587 (hw->phy.type == e1000_phy_82577)) { 5588 ret_val = hw->phy.ops.acquire(hw); 5589 if (ret_val) 5590 return; 5591 ret_val = hw->phy.ops.set_page(hw, 5592 HV_STATS_PAGE << IGP_PAGE_SHIFT); 5593 if (ret_val) 5594 goto release; 5595 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 5596 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 5597 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 5598 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 5599 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 5600 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 5601 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 5602 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 5603 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 5604 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 5605 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 5606 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 5607 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 5608 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 5609 release: 5610 hw->phy.ops.release(hw); 5611 } 5612 } 5613 5614 static const struct e1000_mac_operations ich8_mac_ops = { 5615 /* check_mng_mode dependent on mac type */ 5616 .check_for_link = e1000_check_for_copper_link_ich8lan, 5617 /* cleanup_led dependent on mac type */ 5618 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, 5619 .get_bus_info = e1000_get_bus_info_ich8lan, 5620 .set_lan_id = e1000_set_lan_id_single_port, 5621 .get_link_up_info = e1000_get_link_up_info_ich8lan, 5622 /* led_on dependent on mac type */ 5623 /* led_off dependent on mac type */ 5624 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 5625 .reset_hw = e1000_reset_hw_ich8lan, 5626 .init_hw = e1000_init_hw_ich8lan, 5627 .setup_link = e1000_setup_link_ich8lan, 5628 .setup_physical_interface = e1000_setup_copper_link_ich8lan, 5629 /* id_led_init dependent on mac type */ 5630 .config_collision_dist = e1000e_config_collision_dist_generic, 5631 .rar_set = e1000e_rar_set_generic, 5632 .rar_get_count = e1000e_rar_get_count_generic, 5633 }; 5634 5635 static const struct e1000_phy_operations ich8_phy_ops = { 5636 .acquire = e1000_acquire_swflag_ich8lan, 5637 .check_reset_block = e1000_check_reset_block_ich8lan, 5638 .commit = NULL, 5639 .get_cfg_done = e1000_get_cfg_done_ich8lan, 5640 .get_cable_length = e1000e_get_cable_length_igp_2, 5641 .read_reg = e1000e_read_phy_reg_igp, 5642 .release = e1000_release_swflag_ich8lan, 5643 .reset = e1000_phy_hw_reset_ich8lan, 5644 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, 5645 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, 5646 .write_reg = e1000e_write_phy_reg_igp, 5647 }; 5648 5649 static const struct e1000_nvm_operations ich8_nvm_ops = { 5650 .acquire = e1000_acquire_nvm_ich8lan, 5651 .read = e1000_read_nvm_ich8lan, 5652 .release = e1000_release_nvm_ich8lan, 5653 .reload = e1000e_reload_nvm_generic, 5654 .update = e1000_update_nvm_checksum_ich8lan, 5655 .valid_led_default = e1000_valid_led_default_ich8lan, 5656 .validate = e1000_validate_nvm_checksum_ich8lan, 5657 .write = e1000_write_nvm_ich8lan, 5658 }; 5659 5660 static const struct e1000_nvm_operations spt_nvm_ops = { 5661 .acquire = e1000_acquire_nvm_ich8lan, 5662 .release = e1000_release_nvm_ich8lan, 5663 .read = e1000_read_nvm_spt, 5664 .update = e1000_update_nvm_checksum_spt, 5665 .reload = e1000e_reload_nvm_generic, 5666 .valid_led_default = e1000_valid_led_default_ich8lan, 5667 .validate = e1000_validate_nvm_checksum_ich8lan, 5668 .write = e1000_write_nvm_ich8lan, 5669 }; 5670 5671 const struct e1000_info e1000_ich8_info = { 5672 .mac = e1000_ich8lan, 5673 .flags = FLAG_HAS_WOL 5674 | FLAG_IS_ICH 5675 | FLAG_HAS_CTRLEXT_ON_LOAD 5676 | FLAG_HAS_AMT 5677 | FLAG_HAS_FLASH 5678 | FLAG_APME_IN_WUC, 5679 .pba = 8, 5680 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN, 5681 .get_variants = e1000_get_variants_ich8lan, 5682 .mac_ops = &ich8_mac_ops, 5683 .phy_ops = &ich8_phy_ops, 5684 .nvm_ops = &ich8_nvm_ops, 5685 }; 5686 5687 const struct e1000_info e1000_ich9_info = { 5688 .mac = e1000_ich9lan, 5689 .flags = FLAG_HAS_JUMBO_FRAMES 5690 | FLAG_IS_ICH 5691 | FLAG_HAS_WOL 5692 | FLAG_HAS_CTRLEXT_ON_LOAD 5693 | FLAG_HAS_AMT 5694 | FLAG_HAS_FLASH 5695 | FLAG_APME_IN_WUC, 5696 .pba = 18, 5697 .max_hw_frame_size = DEFAULT_JUMBO, 5698 .get_variants = e1000_get_variants_ich8lan, 5699 .mac_ops = &ich8_mac_ops, 5700 .phy_ops = &ich8_phy_ops, 5701 .nvm_ops = &ich8_nvm_ops, 5702 }; 5703 5704 const struct e1000_info e1000_ich10_info = { 5705 .mac = e1000_ich10lan, 5706 .flags = FLAG_HAS_JUMBO_FRAMES 5707 | FLAG_IS_ICH 5708 | FLAG_HAS_WOL 5709 | FLAG_HAS_CTRLEXT_ON_LOAD 5710 | FLAG_HAS_AMT 5711 | FLAG_HAS_FLASH 5712 | FLAG_APME_IN_WUC, 5713 .pba = 18, 5714 .max_hw_frame_size = DEFAULT_JUMBO, 5715 .get_variants = e1000_get_variants_ich8lan, 5716 .mac_ops = &ich8_mac_ops, 5717 .phy_ops = &ich8_phy_ops, 5718 .nvm_ops = &ich8_nvm_ops, 5719 }; 5720 5721 const struct e1000_info e1000_pch_info = { 5722 .mac = e1000_pchlan, 5723 .flags = FLAG_IS_ICH 5724 | FLAG_HAS_WOL 5725 | FLAG_HAS_CTRLEXT_ON_LOAD 5726 | FLAG_HAS_AMT 5727 | FLAG_HAS_FLASH 5728 | FLAG_HAS_JUMBO_FRAMES 5729 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ 5730 | FLAG_APME_IN_WUC, 5731 .flags2 = FLAG2_HAS_PHY_STATS, 5732 .pba = 26, 5733 .max_hw_frame_size = 4096, 5734 .get_variants = e1000_get_variants_ich8lan, 5735 .mac_ops = &ich8_mac_ops, 5736 .phy_ops = &ich8_phy_ops, 5737 .nvm_ops = &ich8_nvm_ops, 5738 }; 5739 5740 const struct e1000_info e1000_pch2_info = { 5741 .mac = e1000_pch2lan, 5742 .flags = FLAG_IS_ICH 5743 | FLAG_HAS_WOL 5744 | FLAG_HAS_HW_TIMESTAMP 5745 | FLAG_HAS_CTRLEXT_ON_LOAD 5746 | FLAG_HAS_AMT 5747 | FLAG_HAS_FLASH 5748 | FLAG_HAS_JUMBO_FRAMES 5749 | FLAG_APME_IN_WUC, 5750 .flags2 = FLAG2_HAS_PHY_STATS 5751 | FLAG2_HAS_EEE, 5752 .pba = 26, 5753 .max_hw_frame_size = 9022, 5754 .get_variants = e1000_get_variants_ich8lan, 5755 .mac_ops = &ich8_mac_ops, 5756 .phy_ops = &ich8_phy_ops, 5757 .nvm_ops = &ich8_nvm_ops, 5758 }; 5759 5760 const struct e1000_info e1000_pch_lpt_info = { 5761 .mac = e1000_pch_lpt, 5762 .flags = FLAG_IS_ICH 5763 | FLAG_HAS_WOL 5764 | FLAG_HAS_HW_TIMESTAMP 5765 | FLAG_HAS_CTRLEXT_ON_LOAD 5766 | FLAG_HAS_AMT 5767 | FLAG_HAS_FLASH 5768 | FLAG_HAS_JUMBO_FRAMES 5769 | FLAG_APME_IN_WUC, 5770 .flags2 = FLAG2_HAS_PHY_STATS 5771 | FLAG2_HAS_EEE, 5772 .pba = 26, 5773 .max_hw_frame_size = 9022, 5774 .get_variants = e1000_get_variants_ich8lan, 5775 .mac_ops = &ich8_mac_ops, 5776 .phy_ops = &ich8_phy_ops, 5777 .nvm_ops = &ich8_nvm_ops, 5778 }; 5779 5780 const struct e1000_info e1000_pch_spt_info = { 5781 .mac = e1000_pch_spt, 5782 .flags = FLAG_IS_ICH 5783 | FLAG_HAS_WOL 5784 | FLAG_HAS_HW_TIMESTAMP 5785 | FLAG_HAS_CTRLEXT_ON_LOAD 5786 | FLAG_HAS_AMT 5787 | FLAG_HAS_FLASH 5788 | FLAG_HAS_JUMBO_FRAMES 5789 | FLAG_APME_IN_WUC, 5790 .flags2 = FLAG2_HAS_PHY_STATS 5791 | FLAG2_HAS_EEE, 5792 .pba = 26, 5793 .max_hw_frame_size = 9022, 5794 .get_variants = e1000_get_variants_ich8lan, 5795 .mac_ops = &ich8_mac_ops, 5796 .phy_ops = &ich8_phy_ops, 5797 .nvm_ops = &spt_nvm_ops, 5798 }; 5799