xref: /linux/drivers/net/ethernet/hisilicon/hns3/hnae3.h (revision c04259442395a6d9648e8dd105e9058726b2451a)
1d71d8381SJian Shen // SPDX-License-Identifier: GPL-2.0+
2d71d8381SJian Shen // Copyright (c) 2016-2017 Hisilicon Limited.
338caee9dSSalil 
438caee9dSSalil #ifndef __HNAE3_H
538caee9dSSalil #define __HNAE3_H
638caee9dSSalil 
738caee9dSSalil /* Names used in this framework:
838caee9dSSalil  *      ae handle (handle):
938caee9dSSalil  *        a set of queues provided by AE
1038caee9dSSalil  *      ring buffer queue (rbq):
1138caee9dSSalil  *        the channel between upper layer and the AE, can do tx and rx
1238caee9dSSalil  *      ring:
1338caee9dSSalil  *        a tx or rx channel within a rbq
1438caee9dSSalil  *      ring description (desc):
1538caee9dSSalil  *        an element in the ring with packet information
1638caee9dSSalil  *      buffer:
1738caee9dSSalil  *        a memory region referred by desc with the full packet payload
1838caee9dSSalil  *
1938caee9dSSalil  * "num" means a static number set as a parameter, "count" mean a dynamic
2038caee9dSSalil  *   number set while running
2138caee9dSSalil  * "cb" means control block
2238caee9dSSalil  */
2338caee9dSSalil 
2438caee9dSSalil #include <linux/acpi.h>
25cacde272SYunsheng Lin #include <linux/dcbnl.h>
2638caee9dSSalil #include <linux/delay.h>
2738caee9dSSalil #include <linux/device.h>
2838caee9dSSalil #include <linux/module.h>
2938caee9dSSalil #include <linux/netdevice.h>
3038caee9dSSalil #include <linux/pci.h>
3138caee9dSSalil #include <linux/types.h>
3238caee9dSSalil 
333c7624d8SXi Wang #define HNAE3_MOD_VERSION "1.0"
343c7624d8SXi Wang 
3538caee9dSSalil /* Device IDs */
3638caee9dSSalil #define HNAE3_DEV_ID_GE				0xA220
3738caee9dSSalil #define HNAE3_DEV_ID_25GE			0xA221
3838caee9dSSalil #define HNAE3_DEV_ID_25GE_RDMA			0xA222
3938caee9dSSalil #define HNAE3_DEV_ID_25GE_RDMA_MACSEC		0xA223
4038caee9dSSalil #define HNAE3_DEV_ID_50GE_RDMA			0xA224
4138caee9dSSalil #define HNAE3_DEV_ID_50GE_RDMA_MACSEC		0xA225
4238caee9dSSalil #define HNAE3_DEV_ID_100G_RDMA_MACSEC		0xA226
4338caee9dSSalil #define HNAE3_DEV_ID_100G_VF			0xA22E
4438caee9dSSalil #define HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF	0xA22F
4538caee9dSSalil 
4638caee9dSSalil #define HNAE3_CLASS_NAME_SIZE 16
4738caee9dSSalil 
4838caee9dSSalil #define HNAE3_DEV_INITED_B			0x0
49e92a0843SYunsheng Lin #define HNAE3_DEV_SUPPORT_ROCE_B		0x1
502daf4a65SYunsheng Lin #define HNAE3_DEV_SUPPORT_DCB_B			0x2
5190b99b09SPeng Li #define HNAE3_KNIC_CLIENT_INITED_B		0x3
5290b99b09SPeng Li #define HNAE3_UNIC_CLIENT_INITED_B		0x4
5390b99b09SPeng Li #define HNAE3_ROCE_CLIENT_INITED_B		0x5
54d695964dSJian Shen #define HNAE3_DEV_SUPPORT_FD_B			0x6
55b26a6feaSPeng Li #define HNAE3_DEV_SUPPORT_GRO_B			0x7
562daf4a65SYunsheng Lin 
572daf4a65SYunsheng Lin #define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\
582daf4a65SYunsheng Lin 		BIT(HNAE3_DEV_SUPPORT_ROCE_B))
59e92a0843SYunsheng Lin 
60e92a0843SYunsheng Lin #define hnae3_dev_roce_supported(hdev) \
61e4e87715SPeng Li 	hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)
6238caee9dSSalil 
632daf4a65SYunsheng Lin #define hnae3_dev_dcb_supported(hdev) \
64e4e87715SPeng Li 	hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B)
652daf4a65SYunsheng Lin 
66d695964dSJian Shen #define hnae3_dev_fd_supported(hdev) \
67d695964dSJian Shen 	hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B)
68d695964dSJian Shen 
69b26a6feaSPeng Li #define hnae3_dev_gro_supported(hdev) \
70b26a6feaSPeng Li 	hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B)
71b26a6feaSPeng Li 
7238caee9dSSalil #define ring_ptr_move_fw(ring, p) \
7338caee9dSSalil 	((ring)->p = ((ring)->p + 1) % (ring)->desc_num)
7438caee9dSSalil #define ring_ptr_move_bw(ring, p) \
7538caee9dSSalil 	((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num)
7638caee9dSSalil 
7738caee9dSSalil enum hns_desc_type {
7838caee9dSSalil 	DESC_TYPE_SKB,
7938caee9dSSalil 	DESC_TYPE_PAGE,
8038caee9dSSalil };
8138caee9dSSalil 
8238caee9dSSalil struct hnae3_handle;
8338caee9dSSalil 
8438caee9dSSalil struct hnae3_queue {
8538caee9dSSalil 	void __iomem *io_base;
8638caee9dSSalil 	struct hnae3_ae_algo *ae_algo;
8738caee9dSSalil 	struct hnae3_handle *handle;
8838caee9dSSalil 	int tqp_index;	/* index in a handle */
8938caee9dSSalil 	u32 buf_size;	/* size for hnae_desc->addr, preset by AE */
90*c0425944SPeng Li 	u16 tx_desc_num;/* total number of tx desc */
91*c0425944SPeng Li 	u16 rx_desc_num;/* total number of rx desc */
9238caee9dSSalil };
9338caee9dSSalil 
9438caee9dSSalil /*hnae3 loop mode*/
9538caee9dSSalil enum hnae3_loop {
96eb66d503SFuyun Liang 	HNAE3_LOOP_APP,
974dc13b96SFuyun Liang 	HNAE3_LOOP_SERIAL_SERDES,
984dc13b96SFuyun Liang 	HNAE3_LOOP_PARALLEL_SERDES,
99a7b687b3SFuyun Liang 	HNAE3_LOOP_PHY,
100a7b687b3SFuyun Liang 	HNAE3_LOOP_NONE,
10138caee9dSSalil };
10238caee9dSSalil 
10338caee9dSSalil enum hnae3_client_type {
10438caee9dSSalil 	HNAE3_CLIENT_KNIC,
10538caee9dSSalil 	HNAE3_CLIENT_UNIC,
10638caee9dSSalil 	HNAE3_CLIENT_ROCE,
10738caee9dSSalil };
10838caee9dSSalil 
10938caee9dSSalil enum hnae3_dev_type {
11038caee9dSSalil 	HNAE3_DEV_KNIC,
11138caee9dSSalil 	HNAE3_DEV_UNIC,
11238caee9dSSalil };
11338caee9dSSalil 
11438caee9dSSalil /* mac media type */
11538caee9dSSalil enum hnae3_media_type {
11638caee9dSSalil 	HNAE3_MEDIA_TYPE_UNKNOWN,
11738caee9dSSalil 	HNAE3_MEDIA_TYPE_FIBER,
11838caee9dSSalil 	HNAE3_MEDIA_TYPE_COPPER,
11938caee9dSSalil 	HNAE3_MEDIA_TYPE_BACKPLANE,
120c136b884SPeng Li 	HNAE3_MEDIA_TYPE_NONE,
12138caee9dSSalil };
12238caee9dSSalil 
1234ed340abSLipeng enum hnae3_reset_notify_type {
1244ed340abSLipeng 	HNAE3_UP_CLIENT,
1254ed340abSLipeng 	HNAE3_DOWN_CLIENT,
1264ed340abSLipeng 	HNAE3_INIT_CLIENT,
1274ed340abSLipeng 	HNAE3_UNINIT_CLIENT,
1281f609492SYunsheng Lin 	HNAE3_RESTORE_CLIENT,
1294ed340abSLipeng };
1304ed340abSLipeng 
1314ed340abSLipeng enum hnae3_reset_type {
1326d4c3981SSalil Mehta 	HNAE3_VF_RESET,
133dea846e8SHuazhong Tan 	HNAE3_VF_FUNC_RESET,
134aa5c4f17SHuazhong Tan 	HNAE3_VF_PF_FUNC_RESET,
135436667d2SSalil Mehta 	HNAE3_VF_FULL_RESET,
1366b9a97eeSHuazhong Tan 	HNAE3_FLR_RESET,
1374ed340abSLipeng 	HNAE3_FUNC_RESET,
1384ed340abSLipeng 	HNAE3_CORE_RESET,
1394ed340abSLipeng 	HNAE3_GLOBAL_RESET,
1404ed340abSLipeng 	HNAE3_IMP_RESET,
141f6162d44SSalil Mehta 	HNAE3_UNKNOWN_RESET,
1424ed340abSLipeng 	HNAE3_NONE_RESET,
1434ed340abSLipeng };
1444ed340abSLipeng 
1456b9a97eeSHuazhong Tan enum hnae3_flr_state {
1466b9a97eeSHuazhong Tan 	HNAE3_FLR_DOWN,
1476b9a97eeSHuazhong Tan 	HNAE3_FLR_DONE,
1486b9a97eeSHuazhong Tan };
1496b9a97eeSHuazhong Tan 
15038caee9dSSalil struct hnae3_vector_info {
15138caee9dSSalil 	u8 __iomem *io_addr;
15238caee9dSSalil 	int vector;
15338caee9dSSalil };
15438caee9dSSalil 
15538caee9dSSalil #define HNAE3_RING_TYPE_B 0
15638caee9dSSalil #define HNAE3_RING_TYPE_TX 0
15738caee9dSSalil #define HNAE3_RING_TYPE_RX 1
15811af96a4SFuyun Liang #define HNAE3_RING_GL_IDX_S 0
15911af96a4SFuyun Liang #define HNAE3_RING_GL_IDX_M GENMASK(1, 0)
16011af96a4SFuyun Liang #define HNAE3_RING_GL_RX 0
16111af96a4SFuyun Liang #define HNAE3_RING_GL_TX 1
16238caee9dSSalil 
16338caee9dSSalil struct hnae3_ring_chain_node {
16438caee9dSSalil 	struct hnae3_ring_chain_node *next;
16538caee9dSSalil 	u32 tqp_index;
16638caee9dSSalil 	u32 flag;
16711af96a4SFuyun Liang 	u32 int_gl_idx;
16838caee9dSSalil };
16938caee9dSSalil 
17038caee9dSSalil #define HNAE3_IS_TX_RING(node) \
17138caee9dSSalil 	(((node)->flag & (1 << HNAE3_RING_TYPE_B)) == HNAE3_RING_TYPE_TX)
17238caee9dSSalil 
17338caee9dSSalil struct hnae3_client_ops {
17438caee9dSSalil 	int (*init_instance)(struct hnae3_handle *handle);
17538caee9dSSalil 	void (*uninit_instance)(struct hnae3_handle *handle, bool reset);
17638caee9dSSalil 	void (*link_status_change)(struct hnae3_handle *handle, bool state);
177cacde272SYunsheng Lin 	int (*setup_tc)(struct hnae3_handle *handle, u8 tc);
1784ed340abSLipeng 	int (*reset_notify)(struct hnae3_handle *handle,
1794ed340abSLipeng 			    enum hnae3_reset_notify_type type);
1804d60291bSHuazhong Tan 	enum hnae3_reset_type (*process_hw_error)(struct hnae3_handle *handle);
18138caee9dSSalil };
18238caee9dSSalil 
18338caee9dSSalil #define HNAE3_CLIENT_NAME_LENGTH 16
18438caee9dSSalil struct hnae3_client {
18538caee9dSSalil 	char name[HNAE3_CLIENT_NAME_LENGTH];
18638caee9dSSalil 	unsigned long state;
18738caee9dSSalil 	enum hnae3_client_type type;
18838caee9dSSalil 	const struct hnae3_client_ops *ops;
18938caee9dSSalil 	struct list_head node;
19038caee9dSSalil };
19138caee9dSSalil 
19238caee9dSSalil struct hnae3_ae_dev {
19338caee9dSSalil 	struct pci_dev *pdev;
19438caee9dSSalil 	const struct hnae3_ae_ops *ops;
19538caee9dSSalil 	struct list_head node;
19638caee9dSSalil 	u32 flag;
19738caee9dSSalil 	enum hnae3_dev_type dev_type;
1986871af29SJian Shen 	enum hnae3_reset_type reset_type;
19938caee9dSSalil 	void *priv;
20038caee9dSSalil };
20138caee9dSSalil 
20238caee9dSSalil /* This struct defines the operation on the handle.
20338caee9dSSalil  *
20438caee9dSSalil  * init_ae_dev(): (mandatory)
20538caee9dSSalil  *   Get PF configure from pci_dev and initialize PF hardware
20638caee9dSSalil  * uninit_ae_dev()
20738caee9dSSalil  *   Disable PF device and release PF resource
20838caee9dSSalil  * register_client
20938caee9dSSalil  *   Register client to ae_dev
21038caee9dSSalil  * unregister_client()
21138caee9dSSalil  *   Unregister client from ae_dev
21238caee9dSSalil  * start()
21338caee9dSSalil  *   Enable the hardware
21438caee9dSSalil  * stop()
21538caee9dSSalil  *   Disable the hardware
216a6d818e3SYunsheng Lin  * start_client()
217a6d818e3SYunsheng Lin  *   Inform the hclge that client has been started
218a6d818e3SYunsheng Lin  * stop_client()
219a6d818e3SYunsheng Lin  *   Inform the hclge that client has been stopped
22038caee9dSSalil  * get_status()
22138caee9dSSalil  *   Get the carrier state of the back channel of the handle, 1 for ok, 0 for
22238caee9dSSalil  *   non-ok
22338caee9dSSalil  * get_ksettings_an_result()
22438caee9dSSalil  *   Get negotiation status,speed and duplex
22538caee9dSSalil  * update_speed_duplex_h()
22638caee9dSSalil  *   Update hardware speed and duplex
22738caee9dSSalil  * get_media_type()
22838caee9dSSalil  *   Get media type of MAC
22938caee9dSSalil  * adjust_link()
23038caee9dSSalil  *   Adjust link status
23138caee9dSSalil  * set_loopback()
23238caee9dSSalil  *   Set loopback
23338caee9dSSalil  * set_promisc_mode
23438caee9dSSalil  *   Set promisc mode
23538caee9dSSalil  * set_mtu()
23638caee9dSSalil  *   set mtu
23738caee9dSSalil  * get_pauseparam()
23838caee9dSSalil  *   get tx and rx of pause frame use
23938caee9dSSalil  * set_pauseparam()
24038caee9dSSalil  *   set tx and rx of pause frame use
24138caee9dSSalil  * set_autoneg()
24238caee9dSSalil  *   set auto autonegotiation of pause frame use
24338caee9dSSalil  * get_autoneg()
24438caee9dSSalil  *   get auto autonegotiation of pause frame use
24538caee9dSSalil  * get_coalesce_usecs()
24638caee9dSSalil  *   get usecs to delay a TX interrupt after a packet is sent
24738caee9dSSalil  * get_rx_max_coalesced_frames()
24838caee9dSSalil  *   get Maximum number of packets to be sent before a TX interrupt.
24938caee9dSSalil  * set_coalesce_usecs()
25038caee9dSSalil  *   set usecs to delay a TX interrupt after a packet is sent
25138caee9dSSalil  * set_coalesce_frames()
25238caee9dSSalil  *   set Maximum number of packets to be sent before a TX interrupt.
25338caee9dSSalil  * get_mac_addr()
25438caee9dSSalil  *   get mac address
25538caee9dSSalil  * set_mac_addr()
25638caee9dSSalil  *   set mac address
25738caee9dSSalil  * add_uc_addr
25838caee9dSSalil  *   Add unicast addr to mac table
25938caee9dSSalil  * rm_uc_addr
26038caee9dSSalil  *   Remove unicast addr from mac table
26138caee9dSSalil  * set_mc_addr()
26238caee9dSSalil  *   Set multicast address
26338caee9dSSalil  * add_mc_addr
26438caee9dSSalil  *   Add multicast address to mac table
26538caee9dSSalil  * rm_mc_addr
26638caee9dSSalil  *   Remove multicast address from mac table
26738caee9dSSalil  * update_stats()
26838caee9dSSalil  *   Update Old network device statistics
26938caee9dSSalil  * get_ethtool_stats()
27038caee9dSSalil  *   Get ethtool network device statistics
27138caee9dSSalil  * get_strings()
27238caee9dSSalil  *   Get a set of strings that describe the requested objects
27338caee9dSSalil  * get_sset_count()
27438caee9dSSalil  *   Get number of strings that @get_strings will write
27538caee9dSSalil  * update_led_status()
27638caee9dSSalil  *   Update the led status
27738caee9dSSalil  * set_led_id()
27838caee9dSSalil  *   Set led id
27938caee9dSSalil  * get_regs()
28038caee9dSSalil  *   Get regs dump
28138caee9dSSalil  * get_regs_len()
28238caee9dSSalil  *   Get the len of the regs dump
28338caee9dSSalil  * get_rss_key_size()
28438caee9dSSalil  *   Get rss key size
28538caee9dSSalil  * get_rss_indir_size()
28638caee9dSSalil  *   Get rss indirection table size
28738caee9dSSalil  * get_rss()
28838caee9dSSalil  *   Get rss table
28938caee9dSSalil  * set_rss()
29038caee9dSSalil  *   Set rss table
29138caee9dSSalil  * get_tc_size()
29238caee9dSSalil  *   Get tc size of handle
29338caee9dSSalil  * get_vector()
29438caee9dSSalil  *   Get vector number and vector information
2950d3e6631SYunsheng Lin  * put_vector()
2960d3e6631SYunsheng Lin  *   Put the vector in hdev
29738caee9dSSalil  * map_ring_to_vector()
29838caee9dSSalil  *   Map rings to vector
29938caee9dSSalil  * unmap_ring_from_vector()
30038caee9dSSalil  *   Unmap rings from vector
30138caee9dSSalil  * reset_queue()
30238caee9dSSalil  *   Reset queue
30338caee9dSSalil  * get_fw_version()
30438caee9dSSalil  *   Get firmware version
30538caee9dSSalil  * get_mdix_mode()
30638caee9dSSalil  *   Get media typr of phy
307391b5e93SJian Shen  * enable_vlan_filter()
308391b5e93SJian Shen  *   Enable vlan filter
30938caee9dSSalil  * set_vlan_filter()
31038caee9dSSalil  *   Set vlan filter config of Ports
31138caee9dSSalil  * set_vf_vlan_filter()
31238caee9dSSalil  *   Set vlan filter config of vf
313052ece6dSPeng Li  * enable_hw_strip_rxvtag()
314052ece6dSPeng Li  *   Enable/disable hardware strip vlan tag of packets received
3155c9f6b39SPeng Li  * set_gro_en
3165c9f6b39SPeng Li  *   Enable/disable HW GRO
31738caee9dSSalil  */
31838caee9dSSalil struct hnae3_ae_ops {
31938caee9dSSalil 	int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev);
32038caee9dSSalil 	void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev);
3216b9a97eeSHuazhong Tan 	void (*flr_prepare)(struct hnae3_ae_dev *ae_dev);
3226b9a97eeSHuazhong Tan 	void (*flr_done)(struct hnae3_ae_dev *ae_dev);
32338caee9dSSalil 	int (*init_client_instance)(struct hnae3_client *client,
32438caee9dSSalil 				    struct hnae3_ae_dev *ae_dev);
32538caee9dSSalil 	void (*uninit_client_instance)(struct hnae3_client *client,
32638caee9dSSalil 				       struct hnae3_ae_dev *ae_dev);
32738caee9dSSalil 	int (*start)(struct hnae3_handle *handle);
32838caee9dSSalil 	void (*stop)(struct hnae3_handle *handle);
329a6d818e3SYunsheng Lin 	int (*client_start)(struct hnae3_handle *handle);
330a6d818e3SYunsheng Lin 	void (*client_stop)(struct hnae3_handle *handle);
33138caee9dSSalil 	int (*get_status)(struct hnae3_handle *handle);
33238caee9dSSalil 	void (*get_ksettings_an_result)(struct hnae3_handle *handle,
33338caee9dSSalil 					u8 *auto_neg, u32 *speed, u8 *duplex);
33438caee9dSSalil 
33538caee9dSSalil 	int (*update_speed_duplex_h)(struct hnae3_handle *handle);
33638caee9dSSalil 	int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed,
33738caee9dSSalil 				   u8 duplex);
33838caee9dSSalil 
33938caee9dSSalil 	void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type);
34038caee9dSSalil 	void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex);
34138caee9dSSalil 	int (*set_loopback)(struct hnae3_handle *handle,
34238caee9dSSalil 			    enum hnae3_loop loop_mode, bool en);
34338caee9dSSalil 
3447fa6be4fSHuazhong Tan 	int (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc,
3453b75c3dfSPeng Li 				bool en_mc_pmc);
34638caee9dSSalil 	int (*set_mtu)(struct hnae3_handle *handle, int new_mtu);
34738caee9dSSalil 
34838caee9dSSalil 	void (*get_pauseparam)(struct hnae3_handle *handle,
34938caee9dSSalil 			       u32 *auto_neg, u32 *rx_en, u32 *tx_en);
35038caee9dSSalil 	int (*set_pauseparam)(struct hnae3_handle *handle,
35138caee9dSSalil 			      u32 auto_neg, u32 rx_en, u32 tx_en);
35238caee9dSSalil 
35338caee9dSSalil 	int (*set_autoneg)(struct hnae3_handle *handle, bool enable);
35438caee9dSSalil 	int (*get_autoneg)(struct hnae3_handle *handle);
35538caee9dSSalil 
35638caee9dSSalil 	void (*get_coalesce_usecs)(struct hnae3_handle *handle,
35738caee9dSSalil 				   u32 *tx_usecs, u32 *rx_usecs);
35838caee9dSSalil 	void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle,
35938caee9dSSalil 					    u32 *tx_frames, u32 *rx_frames);
36038caee9dSSalil 	int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout);
36138caee9dSSalil 	int (*set_coalesce_frames)(struct hnae3_handle *handle,
36238caee9dSSalil 				   u32 coalesce_frames);
36338caee9dSSalil 	void (*get_coalesce_range)(struct hnae3_handle *handle,
36438caee9dSSalil 				   u32 *tx_frames_low, u32 *rx_frames_low,
36538caee9dSSalil 				   u32 *tx_frames_high, u32 *rx_frames_high,
36638caee9dSSalil 				   u32 *tx_usecs_low, u32 *rx_usecs_low,
36738caee9dSSalil 				   u32 *tx_usecs_high, u32 *rx_usecs_high);
36838caee9dSSalil 
36938caee9dSSalil 	void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p);
37059098055SFuyun Liang 	int (*set_mac_addr)(struct hnae3_handle *handle, void *p,
37159098055SFuyun Liang 			    bool is_first);
37226483246SXi Wang 	int (*do_ioctl)(struct hnae3_handle *handle,
37326483246SXi Wang 			struct ifreq *ifr, int cmd);
37438caee9dSSalil 	int (*add_uc_addr)(struct hnae3_handle *handle,
37538caee9dSSalil 			   const unsigned char *addr);
37638caee9dSSalil 	int (*rm_uc_addr)(struct hnae3_handle *handle,
37738caee9dSSalil 			  const unsigned char *addr);
37838caee9dSSalil 	int (*set_mc_addr)(struct hnae3_handle *handle, void *addr);
37938caee9dSSalil 	int (*add_mc_addr)(struct hnae3_handle *handle,
38038caee9dSSalil 			   const unsigned char *addr);
38138caee9dSSalil 	int (*rm_mc_addr)(struct hnae3_handle *handle,
38238caee9dSSalil 			  const unsigned char *addr);
38338caee9dSSalil 	void (*set_tso_stats)(struct hnae3_handle *handle, int enable);
38438caee9dSSalil 	void (*update_stats)(struct hnae3_handle *handle,
38538caee9dSSalil 			     struct net_device_stats *net_stats);
38638caee9dSSalil 	void (*get_stats)(struct hnae3_handle *handle, u64 *data);
38738caee9dSSalil 
38838caee9dSSalil 	void (*get_strings)(struct hnae3_handle *handle,
38938caee9dSSalil 			    u32 stringset, u8 *data);
39038caee9dSSalil 	int (*get_sset_count)(struct hnae3_handle *handle, int stringset);
39138caee9dSSalil 
39277b34110SFuyun Liang 	void (*get_regs)(struct hnae3_handle *handle, u32 *version,
39377b34110SFuyun Liang 			 void *data);
39438caee9dSSalil 	int (*get_regs_len)(struct hnae3_handle *handle);
39538caee9dSSalil 
39638caee9dSSalil 	u32 (*get_rss_key_size)(struct hnae3_handle *handle);
39738caee9dSSalil 	u32 (*get_rss_indir_size)(struct hnae3_handle *handle);
39838caee9dSSalil 	int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key,
39938caee9dSSalil 		       u8 *hfunc);
40038caee9dSSalil 	int (*set_rss)(struct hnae3_handle *handle, const u32 *indir,
40138caee9dSSalil 		       const u8 *key, const u8 hfunc);
402f7db940aSLipeng 	int (*set_rss_tuple)(struct hnae3_handle *handle,
403f7db940aSLipeng 			     struct ethtool_rxnfc *cmd);
40407d29954SLipeng 	int (*get_rss_tuple)(struct hnae3_handle *handle,
40507d29954SLipeng 			     struct ethtool_rxnfc *cmd);
40638caee9dSSalil 
40738caee9dSSalil 	int (*get_tc_size)(struct hnae3_handle *handle);
40838caee9dSSalil 
40938caee9dSSalil 	int (*get_vector)(struct hnae3_handle *handle, u16 vector_num,
41038caee9dSSalil 			  struct hnae3_vector_info *vector_info);
4110d3e6631SYunsheng Lin 	int (*put_vector)(struct hnae3_handle *handle, int vector_num);
41238caee9dSSalil 	int (*map_ring_to_vector)(struct hnae3_handle *handle,
41338caee9dSSalil 				  int vector_num,
41438caee9dSSalil 				  struct hnae3_ring_chain_node *vr_chain);
41538caee9dSSalil 	int (*unmap_ring_from_vector)(struct hnae3_handle *handle,
41638caee9dSSalil 				      int vector_num,
41738caee9dSSalil 				      struct hnae3_ring_chain_node *vr_chain);
41838caee9dSSalil 
4197fa6be4fSHuazhong Tan 	int (*reset_queue)(struct hnae3_handle *handle, u16 queue_id);
42038caee9dSSalil 	u32 (*get_fw_version)(struct hnae3_handle *handle);
42138caee9dSSalil 	void (*get_mdix_mode)(struct hnae3_handle *handle,
42238caee9dSSalil 			      u8 *tp_mdix_ctrl, u8 *tp_mdix);
42338caee9dSSalil 
424391b5e93SJian Shen 	void (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable);
42538caee9dSSalil 	int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto,
42638caee9dSSalil 			       u16 vlan_id, bool is_kill);
42738caee9dSSalil 	int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid,
42838caee9dSSalil 				  u16 vlan, u8 qos, __be16 proto);
429052ece6dSPeng Li 	int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable);
4306ae4e733SShiju Jose 	void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle);
431720bd583SHuazhong Tan 	void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev,
432720bd583SHuazhong Tan 					  enum hnae3_reset_type rst_type);
433482d2e9cSPeng Li 	void (*get_channels)(struct hnae3_handle *handle,
434482d2e9cSPeng Li 			     struct ethtool_channels *ch);
43509f2af64SPeng Li 	void (*get_tqps_and_rss_info)(struct hnae3_handle *h,
4360d43bf45SHuazhong Tan 				      u16 *alloc_tqps, u16 *max_rss_size);
43790c68a41SYunsheng Lin 	int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num,
43890c68a41SYunsheng Lin 			    bool rxfh_configured);
439f34ffffdSPeng Li 	void (*get_flowctrl_adv)(struct hnae3_handle *handle,
440f34ffffdSPeng Li 				 u32 *flowctrl_adv);
44107f8e940SJian Shen 	int (*set_led_id)(struct hnae3_handle *handle,
44207f8e940SJian Shen 			  enum ethtool_phys_id_state status);
4430979aa0bSFuyun Liang 	void (*get_link_mode)(struct hnae3_handle *handle,
4440979aa0bSFuyun Liang 			      unsigned long *supported,
4450979aa0bSFuyun Liang 			      unsigned long *advertising);
446dd74f815SJian Shen 	int (*add_fd_entry)(struct hnae3_handle *handle,
447dd74f815SJian Shen 			    struct ethtool_rxnfc *cmd);
448dd74f815SJian Shen 	int (*del_fd_entry)(struct hnae3_handle *handle,
449dd74f815SJian Shen 			    struct ethtool_rxnfc *cmd);
4506871af29SJian Shen 	void (*del_all_fd_entries)(struct hnae3_handle *handle,
4516871af29SJian Shen 				   bool clear_list);
45205c2314fSJian Shen 	int (*get_fd_rule_cnt)(struct hnae3_handle *handle,
45305c2314fSJian Shen 			       struct ethtool_rxnfc *cmd);
45405c2314fSJian Shen 	int (*get_fd_rule_info)(struct hnae3_handle *handle,
45505c2314fSJian Shen 				struct ethtool_rxnfc *cmd);
45605c2314fSJian Shen 	int (*get_fd_all_rules)(struct hnae3_handle *handle,
45705c2314fSJian Shen 				struct ethtool_rxnfc *cmd, u32 *rule_locs);
4586871af29SJian Shen 	int (*restore_fd_rules)(struct hnae3_handle *handle);
459c17852a8SJian Shen 	void (*enable_fd)(struct hnae3_handle *handle, bool enable);
4603c666b58Sliuzhongzhu 	int (*dbg_run_cmd)(struct hnae3_handle *handle, char *cmd_buf);
461381c356eSShiju Jose 	pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev);
4624d60291bSHuazhong Tan 	bool (*get_hw_reset_stat)(struct hnae3_handle *handle);
4634d60291bSHuazhong Tan 	bool (*ae_dev_resetting)(struct hnae3_handle *handle);
4644d60291bSHuazhong Tan 	unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle);
4651731be4cSYonglong Liu 	int (*set_gro_en)(struct hnae3_handle *handle, bool enable);
4660c29d191Sliuzhongzhu 	u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id);
4678cdb992fSJian Shen 	void (*set_timer_task)(struct hnae3_handle *handle, bool enable);
468c8a8045bSHuazhong Tan 	int (*mac_connect_phy)(struct hnae3_handle *handle);
469c8a8045bSHuazhong Tan 	void (*mac_disconnect_phy)(struct hnae3_handle *handle);
47038caee9dSSalil };
47138caee9dSSalil 
472cacde272SYunsheng Lin struct hnae3_dcb_ops {
473cacde272SYunsheng Lin 	/* IEEE 802.1Qaz std */
474cacde272SYunsheng Lin 	int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *);
475cacde272SYunsheng Lin 	int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *);
476cacde272SYunsheng Lin 	int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *);
477cacde272SYunsheng Lin 	int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *);
478cacde272SYunsheng Lin 
479cacde272SYunsheng Lin 	/* DCBX configuration */
480cacde272SYunsheng Lin 	u8   (*getdcbx)(struct hnae3_handle *);
481cacde272SYunsheng Lin 	u8   (*setdcbx)(struct hnae3_handle *, u8);
482cacde272SYunsheng Lin 
48330d240dfSYunsheng Lin 	int (*setup_tc)(struct hnae3_handle *, u8, u8 *);
484cacde272SYunsheng Lin };
485cacde272SYunsheng Lin 
48638caee9dSSalil struct hnae3_ae_algo {
48738caee9dSSalil 	const struct hnae3_ae_ops *ops;
48838caee9dSSalil 	struct list_head node;
48938caee9dSSalil 	const struct pci_device_id *pdev_id_table;
49038caee9dSSalil };
49138caee9dSSalil 
49238caee9dSSalil #define HNAE3_INT_NAME_LEN        (IFNAMSIZ + 16)
49338caee9dSSalil #define HNAE3_ITR_COUNTDOWN_START 100
49438caee9dSSalil 
49538caee9dSSalil struct hnae3_tc_info {
49638caee9dSSalil 	u16	tqp_offset;	/* TQP offset from base TQP */
49738caee9dSSalil 	u16	tqp_count;	/* Total TQPs */
49838caee9dSSalil 	u8	tc;		/* TC index */
49938caee9dSSalil 	bool	enable;		/* If this TC is enable or not */
50038caee9dSSalil };
50138caee9dSSalil 
50238caee9dSSalil #define HNAE3_MAX_TC		8
503c5795c53SYunsheng Lin #define HNAE3_MAX_USER_PRIO	8
50438caee9dSSalil struct hnae3_knic_private_info {
50538caee9dSSalil 	struct net_device *netdev; /* Set by KNIC client when init instance */
50638caee9dSSalil 	u16 rss_size;		   /* Allocated RSS queues */
507672ad0edSHuazhong Tan 	u16 req_rss_size;
50838caee9dSSalil 	u16 rx_buf_len;
509*c0425944SPeng Li 	u16 num_tx_desc;
510*c0425944SPeng Li 	u16 num_rx_desc;
51138caee9dSSalil 
51238caee9dSSalil 	u8 num_tc;		   /* Total number of enabled TCs */
513c5795c53SYunsheng Lin 	u8 prio_tc[HNAE3_MAX_USER_PRIO];  /* TC indexed by prio */
51438caee9dSSalil 	struct hnae3_tc_info tc_info[HNAE3_MAX_TC]; /* Idx of array is HW TC */
51538caee9dSSalil 
51638caee9dSSalil 	u16 num_tqps;		  /* total number of TQPs in this handle */
51738caee9dSSalil 	struct hnae3_queue **tqp;  /* array base of all TQPs in this instance */
518cacde272SYunsheng Lin 	const struct hnae3_dcb_ops *dcb_ops;
5197e96adc4SFuyun Liang 
5207e96adc4SFuyun Liang 	u16 int_rl_setting;
521232fc64bSPeng Li 	enum pkt_hash_types rss_type;
52238caee9dSSalil };
52338caee9dSSalil 
52438caee9dSSalil struct hnae3_roce_private_info {
52538caee9dSSalil 	struct net_device *netdev;
52638caee9dSSalil 	void __iomem *roce_io_base;
52738caee9dSSalil 	int base_vector;
52838caee9dSSalil 	int num_vectors;
5294d60291bSHuazhong Tan 
5304d60291bSHuazhong Tan 	/* The below attributes defined for RoCE client, hnae3 gives
5314d60291bSHuazhong Tan 	 * initial values to them, and RoCE client can modify and use
5324d60291bSHuazhong Tan 	 * them.
5334d60291bSHuazhong Tan 	 */
5344d60291bSHuazhong Tan 	unsigned long reset_state;
5354d60291bSHuazhong Tan 	unsigned long instance_state;
5364d60291bSHuazhong Tan 	unsigned long state;
53738caee9dSSalil };
53838caee9dSSalil 
53938caee9dSSalil struct hnae3_unic_private_info {
54038caee9dSSalil 	struct net_device *netdev;
54138caee9dSSalil 	u16 rx_buf_len;
542*c0425944SPeng Li 	u16 num_tx_desc;
543*c0425944SPeng Li 	u16 num_rx_desc;
544*c0425944SPeng Li 
54538caee9dSSalil 	u16 num_tqps;	/* total number of tqps in this handle */
54638caee9dSSalil 	struct hnae3_queue **tqp;  /* array base of all TQPs of this instance */
54738caee9dSSalil };
54838caee9dSSalil 
549eb66d503SFuyun Liang #define HNAE3_SUPPORT_APP_LOOPBACK    BIT(0)
550424eb834SSalil Mehta #define HNAE3_SUPPORT_PHY_LOOPBACK    BIT(1)
5514dc13b96SFuyun Liang #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK	BIT(2)
552424eb834SSalil Mehta #define HNAE3_SUPPORT_VF	      BIT(3)
5534dc13b96SFuyun Liang #define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK	BIT(4)
55438caee9dSSalil 
555c60edc17SJian Shen #define HNAE3_USER_UPE		BIT(0)	/* unicast promisc enabled by user */
556c60edc17SJian Shen #define HNAE3_USER_MPE		BIT(1)	/* mulitcast promisc enabled by user */
557c60edc17SJian Shen #define HNAE3_BPE		BIT(2)	/* broadcast promisc enable */
558c60edc17SJian Shen #define HNAE3_OVERFLOW_UPE	BIT(3)	/* unicast mac vlan overflow */
559c60edc17SJian Shen #define HNAE3_OVERFLOW_MPE	BIT(4)	/* multicast mac vlan overflow */
560c60edc17SJian Shen #define HNAE3_VLAN_FLTR		BIT(5)	/* enable vlan filter */
561c60edc17SJian Shen #define HNAE3_UPE		(HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE)
562c60edc17SJian Shen #define HNAE3_MPE		(HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE)
563c60edc17SJian Shen 
56438caee9dSSalil struct hnae3_handle {
56538caee9dSSalil 	struct hnae3_client *client;
56638caee9dSSalil 	struct pci_dev *pdev;
56738caee9dSSalil 	void *priv;
56838caee9dSSalil 	struct hnae3_ae_algo *ae_algo;  /* the class who provides this handle */
56938caee9dSSalil 	u64 flags; /* Indicate the capabilities for this handle*/
57038caee9dSSalil 
57138caee9dSSalil 	union {
57238caee9dSSalil 		struct net_device *netdev; /* first member */
57338caee9dSSalil 		struct hnae3_knic_private_info kinfo;
57438caee9dSSalil 		struct hnae3_unic_private_info uinfo;
57538caee9dSSalil 		struct hnae3_roce_private_info rinfo;
57638caee9dSSalil 	};
57738caee9dSSalil 
57838caee9dSSalil 	u32 numa_node_mask;	/* for multi-chip support */
579c60edc17SJian Shen 
580c60edc17SJian Shen 	u8 netdev_flags;
581b2292360Sliuzhongzhu 	struct dentry *hnae3_dbgfs;
58238caee9dSSalil };
58338caee9dSSalil 
584e4e87715SPeng Li #define hnae3_set_field(origin, mask, shift, val) \
58538caee9dSSalil 	do { \
58638caee9dSSalil 		(origin) &= (~(mask)); \
58738caee9dSSalil 		(origin) |= ((val) << (shift)) & (mask); \
58838caee9dSSalil 	} while (0)
589e4e87715SPeng Li #define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift))
59038caee9dSSalil 
591e4e87715SPeng Li #define hnae3_set_bit(origin, shift, val) \
592e4e87715SPeng Li 	hnae3_set_field((origin), (0x1 << (shift)), (shift), (val))
593e4e87715SPeng Li #define hnae3_get_bit(origin, shift) \
594e4e87715SPeng Li 	hnae3_get_field((origin), (0x1 << (shift)), (shift))
59538caee9dSSalil 
59674354140SHuazhong Tan int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev);
59738caee9dSSalil void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev);
59838caee9dSSalil 
59938caee9dSSalil void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo);
600854cf33aSFuyun Liang void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo);
60138caee9dSSalil 
60238caee9dSSalil void hnae3_unregister_client(struct hnae3_client *client);
60338caee9dSSalil int hnae3_register_client(struct hnae3_client *client);
604d9f28fc2SJian Shen 
605d9f28fc2SJian Shen void hnae3_set_client_init_flag(struct hnae3_client *client,
606d9f28fc2SJian Shen 				struct hnae3_ae_dev *ae_dev, int inited);
60738caee9dSSalil #endif
608