12ef17216SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0+ */
2d71d8381SJian Shen // Copyright (c) 2016-2017 Hisilicon Limited.
338caee9dSSalil
438caee9dSSalil #ifndef __HNAE3_H
538caee9dSSalil #define __HNAE3_H
638caee9dSSalil
738caee9dSSalil /* Names used in this framework:
838caee9dSSalil * ae handle (handle):
938caee9dSSalil * a set of queues provided by AE
1038caee9dSSalil * ring buffer queue (rbq):
1138caee9dSSalil * the channel between upper layer and the AE, can do tx and rx
1238caee9dSSalil * ring:
1338caee9dSSalil * a tx or rx channel within a rbq
1438caee9dSSalil * ring description (desc):
1538caee9dSSalil * an element in the ring with packet information
1638caee9dSSalil * buffer:
1738caee9dSSalil * a memory region referred by desc with the full packet payload
1838caee9dSSalil *
1938caee9dSSalil * "num" means a static number set as a parameter, "count" mean a dynamic
2038caee9dSSalil * number set while running
2138caee9dSSalil * "cb" means control block
2238caee9dSSalil */
2338caee9dSSalil
2438caee9dSSalil #include <linux/acpi.h>
25cacde272SYunsheng Lin #include <linux/dcbnl.h>
2638caee9dSSalil #include <linux/delay.h>
2738caee9dSSalil #include <linux/device.h>
28cc69837fSJakub Kicinski #include <linux/ethtool.h>
2938caee9dSSalil #include <linux/module.h>
3038caee9dSSalil #include <linux/netdevice.h>
3138caee9dSSalil #include <linux/pci.h>
325a5c9091SJian Shen #include <linux/pkt_sched.h>
3338caee9dSSalil #include <linux/types.h>
34b27d0232SHao Lan #include <linux/bitmap.h>
355a5c9091SJian Shen #include <net/pkt_cls.h>
369adafe2bSVladimir Oltean #include <net/pkt_sched.h>
3738caee9dSSalil
383c7624d8SXi Wang #define HNAE3_MOD_VERSION "1.0"
393c7624d8SXi Wang
40580a05f9SYonglong Liu #define HNAE3_MIN_VECTOR_NUM 2 /* first one for misc, another for IO */
41580a05f9SYonglong Liu
42295ba232SGuangbin Huang /* Device version */
43295ba232SGuangbin Huang #define HNAE3_DEVICE_VERSION_V1 0x00020
44295ba232SGuangbin Huang #define HNAE3_DEVICE_VERSION_V2 0x00021
45295ba232SGuangbin Huang #define HNAE3_DEVICE_VERSION_V3 0x00030
46295ba232SGuangbin Huang
47295ba232SGuangbin Huang #define HNAE3_PCI_REVISION_BIT_SIZE 8
48295ba232SGuangbin Huang
4938caee9dSSalil /* Device IDs */
5038caee9dSSalil #define HNAE3_DEV_ID_GE 0xA220
5138caee9dSSalil #define HNAE3_DEV_ID_25GE 0xA221
5238caee9dSSalil #define HNAE3_DEV_ID_25GE_RDMA 0xA222
5338caee9dSSalil #define HNAE3_DEV_ID_25GE_RDMA_MACSEC 0xA223
5438caee9dSSalil #define HNAE3_DEV_ID_50GE_RDMA 0xA224
5538caee9dSSalil #define HNAE3_DEV_ID_50GE_RDMA_MACSEC 0xA225
5638caee9dSSalil #define HNAE3_DEV_ID_100G_RDMA_MACSEC 0xA226
57ae6f010cSGuangbin Huang #define HNAE3_DEV_ID_200G_RDMA 0xA228
58c155e22bSGuangbin Huang #define HNAE3_DEV_ID_VF 0xA22E
59c155e22bSGuangbin Huang #define HNAE3_DEV_ID_RDMA_DCB_PFC_VF 0xA22F
6038caee9dSSalil
6138caee9dSSalil #define HNAE3_CLASS_NAME_SIZE 16
6238caee9dSSalil
6338caee9dSSalil #define HNAE3_DEV_INITED_B 0x0
64e92a0843SYunsheng Lin #define HNAE3_DEV_SUPPORT_ROCE_B 0x1
652daf4a65SYunsheng Lin #define HNAE3_DEV_SUPPORT_DCB_B 0x2
6690b99b09SPeng Li #define HNAE3_KNIC_CLIENT_INITED_B 0x3
6790b99b09SPeng Li #define HNAE3_UNIC_CLIENT_INITED_B 0x4
6890b99b09SPeng Li #define HNAE3_ROCE_CLIENT_INITED_B 0x5
692daf4a65SYunsheng Lin
702daf4a65SYunsheng Lin #define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) | \
712daf4a65SYunsheng Lin BIT(HNAE3_DEV_SUPPORT_ROCE_B))
72e92a0843SYunsheng Lin
73e92a0843SYunsheng Lin #define hnae3_dev_roce_supported(hdev) \
74eddd9860SGuojia Liao hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)
7538caee9dSSalil
762daf4a65SYunsheng Lin #define hnae3_dev_dcb_supported(hdev) \
77eddd9860SGuojia Liao hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B)
782daf4a65SYunsheng Lin
794cc86cb5SGuangbin Huang enum HNAE3_DEV_CAP_BITS {
804cc86cb5SGuangbin Huang HNAE3_DEV_SUPPORT_FD_B,
814cc86cb5SGuangbin Huang HNAE3_DEV_SUPPORT_GRO_B,
824cc86cb5SGuangbin Huang HNAE3_DEV_SUPPORT_FEC_B,
834cc86cb5SGuangbin Huang HNAE3_DEV_SUPPORT_UDP_GSO_B,
844cc86cb5SGuangbin Huang HNAE3_DEV_SUPPORT_QB_B,
854cc86cb5SGuangbin Huang HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B,
864cc86cb5SGuangbin Huang HNAE3_DEV_SUPPORT_PTP_B,
874cc86cb5SGuangbin Huang HNAE3_DEV_SUPPORT_INT_QL_B,
8866d52f3bSHuazhong Tan HNAE3_DEV_SUPPORT_HW_TX_CSUM_B,
894cc86cb5SGuangbin Huang HNAE3_DEV_SUPPORT_TX_PUSH_B,
904cc86cb5SGuangbin Huang HNAE3_DEV_SUPPORT_PHY_IMP_B,
914cc86cb5SGuangbin Huang HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B,
924cc86cb5SGuangbin Huang HNAE3_DEV_SUPPORT_HW_PAD_B,
934cc86cb5SGuangbin Huang HNAE3_DEV_SUPPORT_STASH_B,
943e281621SHuazhong Tan HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B,
95e8194f32SYufeng Mo HNAE3_DEV_SUPPORT_PAUSE_B,
96e65e9f5cSJiaran Zhang HNAE3_DEV_SUPPORT_RAS_IMP_B,
9779664077SHuazhong Tan HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
982ba30662SJian Shen HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B,
992ba30662SJian Shen HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,
1005c56ff48SGuangbin Huang HNAE3_DEV_SUPPORT_MC_MAC_MNG_B,
101286c61e7SYufeng Mo HNAE3_DEV_SUPPORT_CQ_B,
1022cb343b9SHao Lan HNAE3_DEV_SUPPORT_FEC_STATS_B,
1030f032f93SHao Chen HNAE3_DEV_SUPPORT_LANE_NUM_B,
1043b064f54SHao Lan HNAE3_DEV_SUPPORT_WOL_B,
1056d233612SHao Lan HNAE3_DEV_SUPPORT_TM_FLUSH_B,
106f1bc63aaSJie Wang HNAE3_DEV_SUPPORT_VF_FAULT_B,
1078a4bda8cSPeiyang Wang HNAE3_DEV_SUPPORT_ERR_MOD_GEN_REG_B,
1084cc86cb5SGuangbin Huang };
1094cc86cb5SGuangbin Huang
110507e46aeSGuangbin Huang #define hnae3_ae_dev_fd_supported(ae_dev) \
111507e46aeSGuangbin Huang test_bit(HNAE3_DEV_SUPPORT_FD_B, (ae_dev)->caps)
112d695964dSJian Shen
113507e46aeSGuangbin Huang #define hnae3_ae_dev_gro_supported(ae_dev) \
114507e46aeSGuangbin Huang test_bit(HNAE3_DEV_SUPPORT_GRO_B, (ae_dev)->caps)
115b26a6feaSPeng Li
11674ba23a1SGuangbin Huang #define hnae3_dev_fec_supported(hdev) \
1174cc86cb5SGuangbin Huang test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps)
1184cc86cb5SGuangbin Huang
1194cc86cb5SGuangbin Huang #define hnae3_dev_udp_gso_supported(hdev) \
1204cc86cb5SGuangbin Huang test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps)
1214cc86cb5SGuangbin Huang
1224cc86cb5SGuangbin Huang #define hnae3_dev_qb_supported(hdev) \
1234cc86cb5SGuangbin Huang test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps)
1244cc86cb5SGuangbin Huang
1254cc86cb5SGuangbin Huang #define hnae3_dev_fd_forward_tc_supported(hdev) \
1264cc86cb5SGuangbin Huang test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps)
1274cc86cb5SGuangbin Huang
1284cc86cb5SGuangbin Huang #define hnae3_dev_ptp_supported(hdev) \
1294cc86cb5SGuangbin Huang test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps)
1304cc86cb5SGuangbin Huang
1314cc86cb5SGuangbin Huang #define hnae3_dev_int_ql_supported(hdev) \
1324cc86cb5SGuangbin Huang test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps)
1334cc86cb5SGuangbin Huang
13466d52f3bSHuazhong Tan #define hnae3_dev_hw_csum_supported(hdev) \
13566d52f3bSHuazhong Tan test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, (hdev)->ae_dev->caps)
1364cc86cb5SGuangbin Huang
1374cc86cb5SGuangbin Huang #define hnae3_dev_tx_push_supported(hdev) \
1384cc86cb5SGuangbin Huang test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps)
1394cc86cb5SGuangbin Huang
1404cc86cb5SGuangbin Huang #define hnae3_dev_phy_imp_supported(hdev) \
1414cc86cb5SGuangbin Huang test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps)
1424cc86cb5SGuangbin Huang
143e65e9f5cSJiaran Zhang #define hnae3_dev_ras_imp_supported(hdev) \
144e65e9f5cSJiaran Zhang test_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, (hdev)->ae_dev->caps)
145e65e9f5cSJiaran Zhang
1464cc86cb5SGuangbin Huang #define hnae3_dev_tqp_txrx_indep_supported(hdev) \
1474cc86cb5SGuangbin Huang test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps)
1484cc86cb5SGuangbin Huang
1494cc86cb5SGuangbin Huang #define hnae3_dev_hw_pad_supported(hdev) \
1504cc86cb5SGuangbin Huang test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps)
1514cc86cb5SGuangbin Huang
1524cc86cb5SGuangbin Huang #define hnae3_dev_stash_supported(hdev) \
1534cc86cb5SGuangbin Huang test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps)
15474ba23a1SGuangbin Huang
155e8194f32SYufeng Mo #define hnae3_dev_pause_supported(hdev) \
156e8194f32SYufeng Mo test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, (hdev)->ae_dev->caps)
157e8194f32SYufeng Mo
158dbaae5bbSGuangbin Huang #define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) \
159dbaae5bbSGuangbin Huang test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (ae_dev)->caps)
160dbaae5bbSGuangbin Huang
16179664077SHuazhong Tan #define hnae3_ae_dev_rxd_adv_layout_supported(ae_dev) \
16279664077SHuazhong Tan test_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, (ae_dev)->caps)
16379664077SHuazhong Tan
1645c56ff48SGuangbin Huang #define hnae3_ae_dev_mc_mac_mng_supported(ae_dev) \
1655c56ff48SGuangbin Huang test_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, (ae_dev)->caps)
1665c56ff48SGuangbin Huang
167286c61e7SYufeng Mo #define hnae3_ae_dev_cq_supported(ae_dev) \
168286c61e7SYufeng Mo test_bit(HNAE3_DEV_SUPPORT_CQ_B, (ae_dev)->caps)
169286c61e7SYufeng Mo
1702cb343b9SHao Lan #define hnae3_ae_dev_fec_stats_supported(ae_dev) \
1712cb343b9SHao Lan test_bit(HNAE3_DEV_SUPPORT_FEC_STATS_B, (ae_dev)->caps)
1722cb343b9SHao Lan
1730f032f93SHao Chen #define hnae3_ae_dev_lane_num_supported(ae_dev) \
1740f032f93SHao Chen test_bit(HNAE3_DEV_SUPPORT_LANE_NUM_B, (ae_dev)->caps)
1750f032f93SHao Chen
1763b064f54SHao Lan #define hnae3_ae_dev_wol_supported(ae_dev) \
1773b064f54SHao Lan test_bit(HNAE3_DEV_SUPPORT_WOL_B, (ae_dev)->caps)
1783b064f54SHao Lan
1796d233612SHao Lan #define hnae3_ae_dev_tm_flush_supported(hdev) \
1806d233612SHao Lan test_bit(HNAE3_DEV_SUPPORT_TM_FLUSH_B, (hdev)->ae_dev->caps)
1816d233612SHao Lan
182f1bc63aaSJie Wang #define hnae3_ae_dev_vf_fault_supported(ae_dev) \
183f1bc63aaSJie Wang test_bit(HNAE3_DEV_SUPPORT_VF_FAULT_B, (ae_dev)->caps)
184f1bc63aaSJie Wang
1858a4bda8cSPeiyang Wang #define hnae3_ae_dev_gen_reg_dfx_supported(hdev) \
1868a4bda8cSPeiyang Wang test_bit(HNAE3_DEV_SUPPORT_ERR_MOD_GEN_REG_B, (hdev)->ae_dev->caps)
1878a4bda8cSPeiyang Wang
18832e6d104SJian Shen enum HNAE3_PF_CAP_BITS {
18932e6d104SJian Shen HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,
19032e6d104SJian Shen };
19138caee9dSSalil #define ring_ptr_move_fw(ring, p) \
19238caee9dSSalil ((ring)->p = ((ring)->p + 1) % (ring)->desc_num)
19338caee9dSSalil #define ring_ptr_move_bw(ring, p) \
19438caee9dSSalil ((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num)
19538caee9dSSalil
19638caee9dSSalil struct hnae3_handle;
19738caee9dSSalil
19838caee9dSSalil struct hnae3_queue {
19938caee9dSSalil void __iomem *io_base;
20087a9b2fdSYufeng Mo void __iomem *mem_base;
20138caee9dSSalil struct hnae3_ae_algo *ae_algo;
20238caee9dSSalil struct hnae3_handle *handle;
20338caee9dSSalil int tqp_index; /* index in a handle */
20438caee9dSSalil u32 buf_size; /* size for hnae_desc->addr, preset by AE */
205c0425944SPeng Li u16 tx_desc_num; /* total number of tx desc */
206c0425944SPeng Li u16 rx_desc_num; /* total number of rx desc */
20738caee9dSSalil };
20838caee9dSSalil
209615466ceSYufeng Mo struct hns3_mac_stats {
210615466ceSYufeng Mo u64 tx_pause_cnt;
211615466ceSYufeng Mo u64 rx_pause_cnt;
212615466ceSYufeng Mo };
213615466ceSYufeng Mo
21438caee9dSSalil /* hnae3 loop mode */
21538caee9dSSalil enum hnae3_loop {
21604b6ba14SYonglong Liu HNAE3_LOOP_EXTERNAL,
217eb66d503SFuyun Liang HNAE3_LOOP_APP,
2184dc13b96SFuyun Liang HNAE3_LOOP_SERIAL_SERDES,
2194dc13b96SFuyun Liang HNAE3_LOOP_PARALLEL_SERDES,
220a7b687b3SFuyun Liang HNAE3_LOOP_PHY,
221a7b687b3SFuyun Liang HNAE3_LOOP_NONE,
22238caee9dSSalil };
22338caee9dSSalil
22438caee9dSSalil enum hnae3_client_type {
22538caee9dSSalil HNAE3_CLIENT_KNIC,
22638caee9dSSalil HNAE3_CLIENT_ROCE,
22738caee9dSSalil };
22838caee9dSSalil
22938caee9dSSalil /* mac media type */
23038caee9dSSalil enum hnae3_media_type {
23138caee9dSSalil HNAE3_MEDIA_TYPE_UNKNOWN,
23238caee9dSSalil HNAE3_MEDIA_TYPE_FIBER,
23338caee9dSSalil HNAE3_MEDIA_TYPE_COPPER,
23438caee9dSSalil HNAE3_MEDIA_TYPE_BACKPLANE,
235c136b884SPeng Li HNAE3_MEDIA_TYPE_NONE,
23638caee9dSSalil };
23738caee9dSSalil
23888d10bd6SJian Shen /* must be consistent with definition in firmware */
23988d10bd6SJian Shen enum hnae3_module_type {
24088d10bd6SJian Shen HNAE3_MODULE_TYPE_UNKNOWN = 0x00,
24188d10bd6SJian Shen HNAE3_MODULE_TYPE_FIBRE_LR = 0x01,
24288d10bd6SJian Shen HNAE3_MODULE_TYPE_FIBRE_SR = 0x02,
24388d10bd6SJian Shen HNAE3_MODULE_TYPE_AOC = 0x03,
24488d10bd6SJian Shen HNAE3_MODULE_TYPE_CR = 0x04,
24588d10bd6SJian Shen HNAE3_MODULE_TYPE_KR = 0x05,
24688d10bd6SJian Shen HNAE3_MODULE_TYPE_TP = 0x06,
24788d10bd6SJian Shen };
24888d10bd6SJian Shen
2497e6ec914SJian Shen enum hnae3_fec_mode {
2507e6ec914SJian Shen HNAE3_FEC_AUTO = 0,
2517e6ec914SJian Shen HNAE3_FEC_BASER,
2527e6ec914SJian Shen HNAE3_FEC_RS,
2535c4f7284SHao Lan HNAE3_FEC_LLRS,
25408aa17a0SGuangbin Huang HNAE3_FEC_NONE,
2557e6ec914SJian Shen HNAE3_FEC_USER_DEF,
2567e6ec914SJian Shen };
2577e6ec914SJian Shen
2584ed340abSLipeng enum hnae3_reset_notify_type {
2594ed340abSLipeng HNAE3_UP_CLIENT,
2604ed340abSLipeng HNAE3_DOWN_CLIENT,
2614ed340abSLipeng HNAE3_INIT_CLIENT,
2624ed340abSLipeng HNAE3_UNINIT_CLIENT,
2634ed340abSLipeng };
2644ed340abSLipeng
265a83d2961SWeihang Li enum hnae3_hw_error_type {
266a83d2961SWeihang Li HNAE3_PPU_POISON_ERROR,
267a83d2961SWeihang Li HNAE3_CMDQ_ECC_ERROR,
268a83d2961SWeihang Li HNAE3_IMP_RD_POISON_ERROR,
2696cd131ddSYufeng Mo HNAE3_ROCEE_AXI_RESP_ERROR,
270a83d2961SWeihang Li };
271a83d2961SWeihang Li
2724ed340abSLipeng enum hnae3_reset_type {
2736d4c3981SSalil Mehta HNAE3_VF_RESET,
274dea846e8SHuazhong Tan HNAE3_VF_FUNC_RESET,
275aa5c4f17SHuazhong Tan HNAE3_VF_PF_FUNC_RESET,
276436667d2SSalil Mehta HNAE3_VF_FULL_RESET,
2776b9a97eeSHuazhong Tan HNAE3_FLR_RESET,
2784ed340abSLipeng HNAE3_FUNC_RESET,
2794ed340abSLipeng HNAE3_GLOBAL_RESET,
2804ed340abSLipeng HNAE3_IMP_RESET,
2814ed340abSLipeng HNAE3_NONE_RESET,
2828a45c4f9SJie Wang HNAE3_VF_EXP_RESET,
2837061867bSHuazhong Tan HNAE3_MAX_RESET,
2844ed340abSLipeng };
2854ed340abSLipeng
286741fca16SJian Shen enum hnae3_port_base_vlan_state {
287741fca16SJian Shen HNAE3_PORT_BASE_VLAN_DISABLE,
288741fca16SJian Shen HNAE3_PORT_BASE_VLAN_ENABLE,
289741fca16SJian Shen HNAE3_PORT_BASE_VLAN_MODIFY,
290741fca16SJian Shen HNAE3_PORT_BASE_VLAN_NOCHANGE,
291741fca16SJian Shen };
292741fca16SJian Shen
2935e69ea7eSYufeng Mo enum hnae3_dbg_cmd {
2945e69ea7eSYufeng Mo HNAE3_DBG_CMD_TM_NODES,
2955e69ea7eSYufeng Mo HNAE3_DBG_CMD_TM_PRI,
2965e69ea7eSYufeng Mo HNAE3_DBG_CMD_TM_QSET,
2977679f28eSGuangbin Huang HNAE3_DBG_CMD_TM_MAP,
298cad7c215SGuangbin Huang HNAE3_DBG_CMD_TM_PG,
299cad7c215SGuangbin Huang HNAE3_DBG_CMD_TM_PORT,
3000e32038dSGuangbin Huang HNAE3_DBG_CMD_TC_SCH_INFO,
3016571ec2eSGuangbin Huang HNAE3_DBG_CMD_QOS_PAUSE_CFG,
30228d3badaSGuangbin Huang HNAE3_DBG_CMD_QOS_PRI_MAP,
303fddc02ebSGuangbin Huang HNAE3_DBG_CMD_QOS_DSCP_MAP,
30495b19586SGuangbin Huang HNAE3_DBG_CMD_QOS_BUF_CFG,
305c929bc2aSJiaran Zhang HNAE3_DBG_CMD_DEV_INFO,
30677e91848SHuazhong Tan HNAE3_DBG_CMD_TX_BD,
30777e91848SHuazhong Tan HNAE3_DBG_CMD_RX_BD,
3081556ea91SHuazhong Tan HNAE3_DBG_CMD_MAC_UC,
3091556ea91SHuazhong Tan HNAE3_DBG_CMD_MAC_MC,
3108ddfd9c4SYufeng Mo HNAE3_DBG_CMD_MNG_TBL,
311d658ff34SYufeng Mo HNAE3_DBG_CMD_LOOPBACK,
312b34c157fSHuazhong Tan HNAE3_DBG_CMD_PTP_INFO,
3139149ca0fSJiaran Zhang HNAE3_DBG_CMD_INTERRUPT_INFO,
3141a7ff828SJiaran Zhang HNAE3_DBG_CMD_RESET_INFO,
3150b198b0dSJiaran Zhang HNAE3_DBG_CMD_IMP_INFO,
316e76e6886SJiaran Zhang HNAE3_DBG_CMD_NCL_CONFIG,
317d96b0e59SYufeng Mo HNAE3_DBG_CMD_REG_BIOS_COMMON,
318d96b0e59SYufeng Mo HNAE3_DBG_CMD_REG_SSU,
319d96b0e59SYufeng Mo HNAE3_DBG_CMD_REG_IGU_EGU,
320d96b0e59SYufeng Mo HNAE3_DBG_CMD_REG_RPU,
321d96b0e59SYufeng Mo HNAE3_DBG_CMD_REG_NCSI,
322d96b0e59SYufeng Mo HNAE3_DBG_CMD_REG_RTC,
323d96b0e59SYufeng Mo HNAE3_DBG_CMD_REG_PPP,
324d96b0e59SYufeng Mo HNAE3_DBG_CMD_REG_RCB,
325d96b0e59SYufeng Mo HNAE3_DBG_CMD_REG_TQP,
326d96b0e59SYufeng Mo HNAE3_DBG_CMD_REG_MAC,
327365e860aSYufeng Mo HNAE3_DBG_CMD_REG_DCB,
3280ca821daSJian Shen HNAE3_DBG_CMD_VLAN_CONFIG,
329d2f737cfSHao Chen HNAE3_DBG_CMD_QUEUE_MAP,
330e44c495dSHao Chen HNAE3_DBG_CMD_RX_QUEUE_INFO,
331e44c495dSHao Chen HNAE3_DBG_CMD_TX_QUEUE_INFO,
332b5a0b70dSHao Chen HNAE3_DBG_CMD_FD_TCAM,
33303a92fe8SJian Shen HNAE3_DBG_CMD_FD_COUNTER,
3347b07ab06SJiaran Zhang HNAE3_DBG_CMD_MAC_TNL_STATUS,
335058c3be9SYufeng Mo HNAE3_DBG_CMD_SERV_INFO,
336d59daf6aSJian Shen HNAE3_DBG_CMD_UMV_INFO,
337850bfb91SHao Chen HNAE3_DBG_CMD_PAGE_POOL_INFO,
338c99fead7SHuazhong Tan HNAE3_DBG_CMD_COAL_INFO,
3395e69ea7eSYufeng Mo HNAE3_DBG_CMD_UNKNOWN,
3405e69ea7eSYufeng Mo };
3415e69ea7eSYufeng Mo
3420ba22bcbSGuangbin Huang enum hnae3_tc_map_mode {
3430ba22bcbSGuangbin Huang HNAE3_TC_MAP_MODE_PRIO,
3440ba22bcbSGuangbin Huang HNAE3_TC_MAP_MODE_DSCP,
3450ba22bcbSGuangbin Huang };
3460ba22bcbSGuangbin Huang
34738caee9dSSalil struct hnae3_vector_info {
34838caee9dSSalil u8 __iomem *io_addr;
34938caee9dSSalil int vector;
35038caee9dSSalil };
35138caee9dSSalil
35238caee9dSSalil #define HNAE3_RING_TYPE_B 0
35338caee9dSSalil #define HNAE3_RING_TYPE_TX 0
35438caee9dSSalil #define HNAE3_RING_TYPE_RX 1
35511af96a4SFuyun Liang #define HNAE3_RING_GL_IDX_S 0
35611af96a4SFuyun Liang #define HNAE3_RING_GL_IDX_M GENMASK(1, 0)
35711af96a4SFuyun Liang #define HNAE3_RING_GL_RX 0
35811af96a4SFuyun Liang #define HNAE3_RING_GL_TX 1
35938caee9dSSalil
36092371373SYufeng Mo #define HNAE3_FW_VERSION_BYTE3_SHIFT 24
36192371373SYufeng Mo #define HNAE3_FW_VERSION_BYTE3_MASK GENMASK(31, 24)
36292371373SYufeng Mo #define HNAE3_FW_VERSION_BYTE2_SHIFT 16
36392371373SYufeng Mo #define HNAE3_FW_VERSION_BYTE2_MASK GENMASK(23, 16)
36492371373SYufeng Mo #define HNAE3_FW_VERSION_BYTE1_SHIFT 8
36592371373SYufeng Mo #define HNAE3_FW_VERSION_BYTE1_MASK GENMASK(15, 8)
36692371373SYufeng Mo #define HNAE3_FW_VERSION_BYTE0_SHIFT 0
36792371373SYufeng Mo #define HNAE3_FW_VERSION_BYTE0_MASK GENMASK(7, 0)
36892371373SYufeng Mo
369a1e5de0dSHao Chen #define HNAE3_SCC_VERSION_BYTE3_SHIFT 24
370a1e5de0dSHao Chen #define HNAE3_SCC_VERSION_BYTE3_MASK GENMASK(31, 24)
371a1e5de0dSHao Chen #define HNAE3_SCC_VERSION_BYTE2_SHIFT 16
372a1e5de0dSHao Chen #define HNAE3_SCC_VERSION_BYTE2_MASK GENMASK(23, 16)
373a1e5de0dSHao Chen #define HNAE3_SCC_VERSION_BYTE1_SHIFT 8
374a1e5de0dSHao Chen #define HNAE3_SCC_VERSION_BYTE1_MASK GENMASK(15, 8)
375a1e5de0dSHao Chen #define HNAE3_SCC_VERSION_BYTE0_SHIFT 0
376a1e5de0dSHao Chen #define HNAE3_SCC_VERSION_BYTE0_MASK GENMASK(7, 0)
377a1e5de0dSHao Chen
37838caee9dSSalil struct hnae3_ring_chain_node {
37938caee9dSSalil struct hnae3_ring_chain_node *next;
38038caee9dSSalil u32 tqp_index;
38138caee9dSSalil u32 flag;
38211af96a4SFuyun Liang u32 int_gl_idx;
38338caee9dSSalil };
38438caee9dSSalil
38538caee9dSSalil #define HNAE3_IS_TX_RING(node) \
3869393eb50SYufeng Mo (((node)->flag & 1 << HNAE3_RING_TYPE_B) == HNAE3_RING_TYPE_TX)
38738caee9dSSalil
388af2aedc5SGuangbin Huang /* device specification info from firmware */
389af2aedc5SGuangbin Huang struct hnae3_dev_specs {
390af2aedc5SGuangbin Huang u32 mac_entry_num; /* number of mac-vlan table entry */
391af2aedc5SGuangbin Huang u32 mng_entry_num; /* number of manager table entry */
392d9c7d20dSGuangbin Huang u32 max_tm_rate;
393af2aedc5SGuangbin Huang u16 rss_ind_tbl_size;
394af2aedc5SGuangbin Huang u16 rss_key_size;
395af2aedc5SGuangbin Huang u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */
396ab16b49cSHuazhong Tan u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */
397af2aedc5SGuangbin Huang u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */
398e070c8b9SYufeng Mo u16 max_frm_size;
3993f094bd1SGuangbin Huang u16 max_qset_num;
400e435a6b5SGuangbin Huang u16 umv_size;
4015c56ff48SGuangbin Huang u16 mc_mac_size;
4024e4c03f6SGuangbin Huang u32 mac_stats_num;
40336122201SJijie Shao u8 tnl_num;
4040448825bSHao Lan u8 hilink_version;
405af2aedc5SGuangbin Huang };
406af2aedc5SGuangbin Huang
40738caee9dSSalil struct hnae3_client_ops {
40838caee9dSSalil int (*init_instance)(struct hnae3_handle *handle);
40938caee9dSSalil void (*uninit_instance)(struct hnae3_handle *handle, bool reset);
41038caee9dSSalil void (*link_status_change)(struct hnae3_handle *handle, bool state);
4114ed340abSLipeng int (*reset_notify)(struct hnae3_handle *handle,
4124ed340abSLipeng enum hnae3_reset_notify_type type);
413a83d2961SWeihang Li void (*process_hw_error)(struct hnae3_handle *handle,
414a83d2961SWeihang Li enum hnae3_hw_error_type);
41538caee9dSSalil };
41638caee9dSSalil
41738caee9dSSalil #define HNAE3_CLIENT_NAME_LENGTH 16
41838caee9dSSalil struct hnae3_client {
41938caee9dSSalil char name[HNAE3_CLIENT_NAME_LENGTH];
42038caee9dSSalil unsigned long state;
42138caee9dSSalil enum hnae3_client_type type;
42238caee9dSSalil const struct hnae3_client_ops *ops;
42338caee9dSSalil struct list_head node;
42438caee9dSSalil };
42538caee9dSSalil
4264cc86cb5SGuangbin Huang #define HNAE3_DEV_CAPS_MAX_NUM 96
42738caee9dSSalil struct hnae3_ae_dev {
42838caee9dSSalil struct pci_dev *pdev;
42938caee9dSSalil const struct hnae3_ae_ops *ops;
43038caee9dSSalil struct list_head node;
43138caee9dSSalil u32 flag;
432123297b7SShiju Jose unsigned long hw_err_reset_req;
433af2aedc5SGuangbin Huang struct hnae3_dev_specs dev_specs;
434295ba232SGuangbin Huang u32 dev_version;
435b27d0232SHao Lan DECLARE_BITMAP(caps, HNAE3_DEV_CAPS_MAX_NUM);
43638caee9dSSalil void *priv;
43738caee9dSSalil };
43838caee9dSSalil
43938caee9dSSalil /* This struct defines the operation on the handle.
44038caee9dSSalil *
44138caee9dSSalil * init_ae_dev(): (mandatory)
44238caee9dSSalil * Get PF configure from pci_dev and initialize PF hardware
44338caee9dSSalil * uninit_ae_dev()
44438caee9dSSalil * Disable PF device and release PF resource
44538caee9dSSalil * register_client
44638caee9dSSalil * Register client to ae_dev
44738caee9dSSalil * unregister_client()
44838caee9dSSalil * Unregister client from ae_dev
44938caee9dSSalil * start()
45038caee9dSSalil * Enable the hardware
45138caee9dSSalil * stop()
45238caee9dSSalil * Disable the hardware
453a6d818e3SYunsheng Lin * start_client()
454a6d818e3SYunsheng Lin * Inform the hclge that client has been started
455a6d818e3SYunsheng Lin * stop_client()
456a6d818e3SYunsheng Lin * Inform the hclge that client has been stopped
45738caee9dSSalil * get_status()
45838caee9dSSalil * Get the carrier state of the back channel of the handle, 1 for ok, 0 for
45938caee9dSSalil * non-ok
46038caee9dSSalil * get_ksettings_an_result()
46138caee9dSSalil * Get negotiation status,speed and duplex
46238caee9dSSalil * get_media_type()
46338caee9dSSalil * Get media type of MAC
46422f48e24SJian Shen * check_port_speed()
46522f48e24SJian Shen * Check target speed whether is supported
46638caee9dSSalil * adjust_link()
46738caee9dSSalil * Adjust link status
46838caee9dSSalil * set_loopback()
46938caee9dSSalil * Set loopback
47038caee9dSSalil * set_promisc_mode
47138caee9dSSalil * Set promisc mode
472c631c696SJian Shen * request_update_promisc_mode
473c631c696SJian Shen * request to hclge(vf) to update promisc mode
47438caee9dSSalil * set_mtu()
47538caee9dSSalil * set mtu
47638caee9dSSalil * get_pauseparam()
47738caee9dSSalil * get tx and rx of pause frame use
47838caee9dSSalil * set_pauseparam()
47938caee9dSSalil * set tx and rx of pause frame use
48038caee9dSSalil * set_autoneg()
48138caee9dSSalil * set auto autonegotiation of pause frame use
48238caee9dSSalil * get_autoneg()
48338caee9dSSalil * get auto autonegotiation of pause frame use
48422f48e24SJian Shen * restart_autoneg()
48522f48e24SJian Shen * restart autonegotiation
4867786a996SJian Shen * halt_autoneg()
4877786a996SJian Shen * halt/resume autonegotiation when autonegotiation on
48838caee9dSSalil * get_coalesce_usecs()
48938caee9dSSalil * get usecs to delay a TX interrupt after a packet is sent
49038caee9dSSalil * get_rx_max_coalesced_frames()
49138caee9dSSalil * get Maximum number of packets to be sent before a TX interrupt.
49238caee9dSSalil * set_coalesce_usecs()
49338caee9dSSalil * set usecs to delay a TX interrupt after a packet is sent
49438caee9dSSalil * set_coalesce_frames()
49538caee9dSSalil * set Maximum number of packets to be sent before a TX interrupt.
49638caee9dSSalil * get_mac_addr()
49738caee9dSSalil * get mac address
49838caee9dSSalil * set_mac_addr()
49938caee9dSSalil * set mac address
50038caee9dSSalil * add_uc_addr
50138caee9dSSalil * Add unicast addr to mac table
50238caee9dSSalil * rm_uc_addr
50338caee9dSSalil * Remove unicast addr from mac table
50438caee9dSSalil * set_mc_addr()
50538caee9dSSalil * Set multicast address
50638caee9dSSalil * add_mc_addr
50738caee9dSSalil * Add multicast address to mac table
50838caee9dSSalil * rm_mc_addr
50938caee9dSSalil * Remove multicast address from mac table
51038caee9dSSalil * update_stats()
51138caee9dSSalil * Update Old network device statistics
512615466ceSYufeng Mo * get_mac_stats()
513615466ceSYufeng Mo * get mac pause statistics including tx_cnt and rx_cnt
51438caee9dSSalil * get_ethtool_stats()
51538caee9dSSalil * Get ethtool network device statistics
51638caee9dSSalil * get_strings()
51738caee9dSSalil * Get a set of strings that describe the requested objects
51838caee9dSSalil * get_sset_count()
51938caee9dSSalil * Get number of strings that @get_strings will write
52038caee9dSSalil * update_led_status()
52138caee9dSSalil * Update the led status
52238caee9dSSalil * set_led_id()
52338caee9dSSalil * Set led id
52438caee9dSSalil * get_regs()
52538caee9dSSalil * Get regs dump
52638caee9dSSalil * get_regs_len()
52738caee9dSSalil * Get the len of the regs dump
52838caee9dSSalil * get_rss_key_size()
52938caee9dSSalil * Get rss key size
53038caee9dSSalil * get_rss()
53138caee9dSSalil * Get rss table
53238caee9dSSalil * set_rss()
53338caee9dSSalil * Set rss table
53438caee9dSSalil * get_tc_size()
53538caee9dSSalil * Get tc size of handle
53638caee9dSSalil * get_vector()
53738caee9dSSalil * Get vector number and vector information
5380d3e6631SYunsheng Lin * put_vector()
5390d3e6631SYunsheng Lin * Put the vector in hdev
54038caee9dSSalil * map_ring_to_vector()
54138caee9dSSalil * Map rings to vector
54238caee9dSSalil * unmap_ring_from_vector()
54338caee9dSSalil * Unmap rings from vector
54438caee9dSSalil * reset_queue()
54538caee9dSSalil * Reset queue
54638caee9dSSalil * get_fw_version()
54738caee9dSSalil * Get firmware version
54838caee9dSSalil * get_mdix_mode()
54938caee9dSSalil * Get media typr of phy
550391b5e93SJian Shen * enable_vlan_filter()
551391b5e93SJian Shen * Enable vlan filter
55238caee9dSSalil * set_vlan_filter()
55338caee9dSSalil * Set vlan filter config of Ports
55438caee9dSSalil * set_vf_vlan_filter()
55538caee9dSSalil * Set vlan filter config of vf
556052ece6dSPeng Li * enable_hw_strip_rxvtag()
557052ece6dSPeng Li * Enable/disable hardware strip vlan tag of packets received
5585c9f6b39SPeng Li * set_gro_en
5595c9f6b39SPeng Li * Enable/disable HW GRO
560d93ed94fSJian Shen * add_arfs_entry
561d93ed94fSJian Shen * Check the 5-tuples of flow, and create flow director rule
5626430f744SYufeng Mo * get_vf_config
5636430f744SYufeng Mo * Get the VF configuration setting by the host
5646430f744SYufeng Mo * set_vf_link_state
5656430f744SYufeng Mo * Set VF link status
56622044f95SJian Shen * set_vf_spoofchk
56722044f95SJian Shen * Enable/disable spoof check for specified vf
568e196ec75SJian Shen * set_vf_trust
569e196ec75SJian Shen * Enable/disable trust for specified vf, if the vf being trusted, then
570e196ec75SJian Shen * it can enable promisc mode
571ee9e4424SYonglong Liu * set_vf_rate
572ee9e4424SYonglong Liu * Set the max tx rate of specified vf.
5738e6de441SHuazhong Tan * set_vf_mac
5748e6de441SHuazhong Tan * Configure the default MAC for specified VF
575cb10228dSYonglong Liu * get_module_eeprom
576cb10228dSYonglong Liu * Get the optical module eeprom info.
5770205ec04SJian Shen * add_cls_flower
5780205ec04SJian Shen * Add clsflower rule
5790205ec04SJian Shen * del_cls_flower
5800205ec04SJian Shen * Delete clsflower rule
5810205ec04SJian Shen * cls_flower_active
5820205ec04SJian Shen * Check if any cls flower rule exist
58304987ca1SGuangbin Huang * dbg_read_cmd
58404987ca1SGuangbin Huang * Execute debugfs read command.
5850bf5eb78SHuazhong Tan * set_tx_hwts_info
5860bf5eb78SHuazhong Tan * Save information for 1588 tx packet
5870bf5eb78SHuazhong Tan * get_rx_hwts
5880bf5eb78SHuazhong Tan * Get 1588 rx hwstamp
5890bf5eb78SHuazhong Tan * get_ts_info
5900bf5eb78SHuazhong Tan * Get phc info
591671cb8cbSPeng Li * clean_vf_config
592671cb8cbSPeng Li * Clean residual vf info after disable sriov
5933b064f54SHao Lan * get_wol
5943b064f54SHao Lan * Get wake on lan info
5953b064f54SHao Lan * set_wol
5963b064f54SHao Lan * Config wake on lan
59738caee9dSSalil */
59838caee9dSSalil struct hnae3_ae_ops {
59938caee9dSSalil int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev);
60038caee9dSSalil void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev);
601bb1890d5SJiaran Zhang void (*reset_prepare)(struct hnae3_ae_dev *ae_dev,
602bb1890d5SJiaran Zhang enum hnae3_reset_type rst_type);
603bb1890d5SJiaran Zhang void (*reset_done)(struct hnae3_ae_dev *ae_dev);
60438caee9dSSalil int (*init_client_instance)(struct hnae3_client *client,
60538caee9dSSalil struct hnae3_ae_dev *ae_dev);
60638caee9dSSalil void (*uninit_client_instance)(struct hnae3_client *client,
60738caee9dSSalil struct hnae3_ae_dev *ae_dev);
60838caee9dSSalil int (*start)(struct hnae3_handle *handle);
60938caee9dSSalil void (*stop)(struct hnae3_handle *handle);
610a6d818e3SYunsheng Lin int (*client_start)(struct hnae3_handle *handle);
611a6d818e3SYunsheng Lin void (*client_stop)(struct hnae3_handle *handle);
61238caee9dSSalil int (*get_status)(struct hnae3_handle *handle);
61338caee9dSSalil void (*get_ksettings_an_result)(struct hnae3_handle *handle,
6140f032f93SHao Chen u8 *auto_neg, u32 *speed, u8 *duplex,
6150f032f93SHao Chen u32 *lane_num);
61638caee9dSSalil
61738caee9dSSalil int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed,
6180f032f93SHao Chen u8 duplex, u8 lane_num);
61938caee9dSSalil
62088d10bd6SJian Shen void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type,
62188d10bd6SJian Shen u8 *module_type);
62222f48e24SJian Shen int (*check_port_speed)(struct hnae3_handle *handle, u32 speed);
6232cb343b9SHao Lan void (*get_fec_stats)(struct hnae3_handle *handle,
6242cb343b9SHao Lan struct ethtool_fec_stats *fec_stats);
6257e6ec914SJian Shen void (*get_fec)(struct hnae3_handle *handle, u8 *fec_ability,
6267e6ec914SJian Shen u8 *fec_mode);
6277e6ec914SJian Shen int (*set_fec)(struct hnae3_handle *handle, u32 fec_mode);
62838caee9dSSalil void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex);
62938caee9dSSalil int (*set_loopback)(struct hnae3_handle *handle,
63038caee9dSSalil enum hnae3_loop loop_mode, bool en);
63138caee9dSSalil
6327fa6be4fSHuazhong Tan int (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc,
6333b75c3dfSPeng Li bool en_mc_pmc);
634c631c696SJian Shen void (*request_update_promisc_mode)(struct hnae3_handle *handle);
63538caee9dSSalil int (*set_mtu)(struct hnae3_handle *handle, int new_mtu);
63638caee9dSSalil
63738caee9dSSalil void (*get_pauseparam)(struct hnae3_handle *handle,
63838caee9dSSalil u32 *auto_neg, u32 *rx_en, u32 *tx_en);
63938caee9dSSalil int (*set_pauseparam)(struct hnae3_handle *handle,
64038caee9dSSalil u32 auto_neg, u32 rx_en, u32 tx_en);
64138caee9dSSalil
64238caee9dSSalil int (*set_autoneg)(struct hnae3_handle *handle, bool enable);
64338caee9dSSalil int (*get_autoneg)(struct hnae3_handle *handle);
64422f48e24SJian Shen int (*restart_autoneg)(struct hnae3_handle *handle);
6457786a996SJian Shen int (*halt_autoneg)(struct hnae3_handle *handle, bool halt);
64638caee9dSSalil
64738caee9dSSalil void (*get_coalesce_usecs)(struct hnae3_handle *handle,
64838caee9dSSalil u32 *tx_usecs, u32 *rx_usecs);
64938caee9dSSalil void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle,
65038caee9dSSalil u32 *tx_frames, u32 *rx_frames);
65138caee9dSSalil int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout);
65238caee9dSSalil int (*set_coalesce_frames)(struct hnae3_handle *handle,
65338caee9dSSalil u32 coalesce_frames);
65438caee9dSSalil void (*get_coalesce_range)(struct hnae3_handle *handle,
65538caee9dSSalil u32 *tx_frames_low, u32 *rx_frames_low,
65638caee9dSSalil u32 *tx_frames_high, u32 *rx_frames_high,
65738caee9dSSalil u32 *tx_usecs_low, u32 *rx_usecs_low,
65838caee9dSSalil u32 *tx_usecs_high, u32 *rx_usecs_high);
65938caee9dSSalil
66038caee9dSSalil void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p);
66176660757SJakub Kicinski int (*set_mac_addr)(struct hnae3_handle *handle, const void *p,
66259098055SFuyun Liang bool is_first);
66326483246SXi Wang int (*do_ioctl)(struct hnae3_handle *handle,
66426483246SXi Wang struct ifreq *ifr, int cmd);
66538caee9dSSalil int (*add_uc_addr)(struct hnae3_handle *handle,
66638caee9dSSalil const unsigned char *addr);
66738caee9dSSalil int (*rm_uc_addr)(struct hnae3_handle *handle,
66838caee9dSSalil const unsigned char *addr);
66938caee9dSSalil int (*set_mc_addr)(struct hnae3_handle *handle, void *addr);
67038caee9dSSalil int (*add_mc_addr)(struct hnae3_handle *handle,
67138caee9dSSalil const unsigned char *addr);
67238caee9dSSalil int (*rm_mc_addr)(struct hnae3_handle *handle,
67338caee9dSSalil const unsigned char *addr);
67438caee9dSSalil void (*set_tso_stats)(struct hnae3_handle *handle, int enable);
675ed1c6f35SPeiyang Wang void (*update_stats)(struct hnae3_handle *handle);
67638caee9dSSalil void (*get_stats)(struct hnae3_handle *handle, u64 *data);
677615466ceSYufeng Mo void (*get_mac_stats)(struct hnae3_handle *handle,
678615466ceSYufeng Mo struct hns3_mac_stats *mac_stats);
67938caee9dSSalil void (*get_strings)(struct hnae3_handle *handle,
68038caee9dSSalil u32 stringset, u8 *data);
68138caee9dSSalil int (*get_sset_count)(struct hnae3_handle *handle, int stringset);
68238caee9dSSalil
68377b34110SFuyun Liang void (*get_regs)(struct hnae3_handle *handle, u32 *version,
68477b34110SFuyun Liang void *data);
68538caee9dSSalil int (*get_regs_len)(struct hnae3_handle *handle);
68638caee9dSSalil
68738caee9dSSalil u32 (*get_rss_key_size)(struct hnae3_handle *handle);
68838caee9dSSalil int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key,
68938caee9dSSalil u8 *hfunc);
69038caee9dSSalil int (*set_rss)(struct hnae3_handle *handle, const u32 *indir,
69138caee9dSSalil const u8 *key, const u8 hfunc);
692f7db940aSLipeng int (*set_rss_tuple)(struct hnae3_handle *handle,
693f7db940aSLipeng struct ethtool_rxnfc *cmd);
69407d29954SLipeng int (*get_rss_tuple)(struct hnae3_handle *handle,
69507d29954SLipeng struct ethtool_rxnfc *cmd);
69638caee9dSSalil
69738caee9dSSalil int (*get_tc_size)(struct hnae3_handle *handle);
69838caee9dSSalil
69938caee9dSSalil int (*get_vector)(struct hnae3_handle *handle, u16 vector_num,
70038caee9dSSalil struct hnae3_vector_info *vector_info);
7010d3e6631SYunsheng Lin int (*put_vector)(struct hnae3_handle *handle, int vector_num);
70238caee9dSSalil int (*map_ring_to_vector)(struct hnae3_handle *handle,
70338caee9dSSalil int vector_num,
70438caee9dSSalil struct hnae3_ring_chain_node *vr_chain);
70538caee9dSSalil int (*unmap_ring_from_vector)(struct hnae3_handle *handle,
70638caee9dSSalil int vector_num,
70738caee9dSSalil struct hnae3_ring_chain_node *vr_chain);
70838caee9dSSalil
7098fa86551SYufeng Mo int (*reset_queue)(struct hnae3_handle *handle);
71038caee9dSSalil u32 (*get_fw_version)(struct hnae3_handle *handle);
71138caee9dSSalil void (*get_mdix_mode)(struct hnae3_handle *handle,
71238caee9dSSalil u8 *tp_mdix_ctrl, u8 *tp_mdix);
71338caee9dSSalil
7142ba30662SJian Shen int (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable);
71538caee9dSSalil int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto,
71638caee9dSSalil u16 vlan_id, bool is_kill);
71738caee9dSSalil int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid,
71838caee9dSSalil u16 vlan, u8 qos, __be16 proto);
719052ece6dSPeng Li int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable);
7206ae4e733SShiju Jose void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle);
721123297b7SShiju Jose enum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *ae_dev,
722123297b7SShiju Jose unsigned long *addr);
723720bd583SHuazhong Tan void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev,
724720bd583SHuazhong Tan enum hnae3_reset_type rst_type);
725482d2e9cSPeng Li void (*get_channels)(struct hnae3_handle *handle,
726482d2e9cSPeng Li struct ethtool_channels *ch);
72709f2af64SPeng Li void (*get_tqps_and_rss_info)(struct hnae3_handle *h,
7280d43bf45SHuazhong Tan u16 *alloc_tqps, u16 *max_rss_size);
72990c68a41SYunsheng Lin int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num,
73090c68a41SYunsheng Lin bool rxfh_configured);
731f34ffffdSPeng Li void (*get_flowctrl_adv)(struct hnae3_handle *handle,
732f34ffffdSPeng Li u32 *flowctrl_adv);
73307f8e940SJian Shen int (*set_led_id)(struct hnae3_handle *handle,
73407f8e940SJian Shen enum ethtool_phys_id_state status);
7350979aa0bSFuyun Liang void (*get_link_mode)(struct hnae3_handle *handle,
7360979aa0bSFuyun Liang unsigned long *supported,
7370979aa0bSFuyun Liang unsigned long *advertising);
738dd74f815SJian Shen int (*add_fd_entry)(struct hnae3_handle *handle,
739dd74f815SJian Shen struct ethtool_rxnfc *cmd);
740dd74f815SJian Shen int (*del_fd_entry)(struct hnae3_handle *handle,
741dd74f815SJian Shen struct ethtool_rxnfc *cmd);
74205c2314fSJian Shen int (*get_fd_rule_cnt)(struct hnae3_handle *handle,
74305c2314fSJian Shen struct ethtool_rxnfc *cmd);
74405c2314fSJian Shen int (*get_fd_rule_info)(struct hnae3_handle *handle,
74505c2314fSJian Shen struct ethtool_rxnfc *cmd);
74605c2314fSJian Shen int (*get_fd_all_rules)(struct hnae3_handle *handle,
74705c2314fSJian Shen struct ethtool_rxnfc *cmd, u32 *rule_locs);
748c17852a8SJian Shen void (*enable_fd)(struct hnae3_handle *handle, bool enable);
749d93ed94fSJian Shen int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id,
750d93ed94fSJian Shen u16 flow_id, struct flow_keys *fkeys);
7515e69ea7eSYufeng Mo int (*dbg_read_cmd)(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd,
75204987ca1SGuangbin Huang char *buf, int len);
753381c356eSShiju Jose pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev);
7544d60291bSHuazhong Tan bool (*get_hw_reset_stat)(struct hnae3_handle *handle);
7554d60291bSHuazhong Tan bool (*ae_dev_resetting)(struct hnae3_handle *handle);
7564d60291bSHuazhong Tan unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle);
7571731be4cSYonglong Liu int (*set_gro_en)(struct hnae3_handle *handle, bool enable);
7580c29d191Sliuzhongzhu u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id);
7598cdb992fSJian Shen void (*set_timer_task)(struct hnae3_handle *handle, bool enable);
760c8a8045bSHuazhong Tan int (*mac_connect_phy)(struct hnae3_handle *handle);
761c8a8045bSHuazhong Tan void (*mac_disconnect_phy)(struct hnae3_handle *handle);
7626430f744SYufeng Mo int (*get_vf_config)(struct hnae3_handle *handle, int vf,
7636430f744SYufeng Mo struct ifla_vf_info *ivf);
7646430f744SYufeng Mo int (*set_vf_link_state)(struct hnae3_handle *handle, int vf,
7656430f744SYufeng Mo int link_state);
76622044f95SJian Shen int (*set_vf_spoofchk)(struct hnae3_handle *handle, int vf,
76722044f95SJian Shen bool enable);
768e196ec75SJian Shen int (*set_vf_trust)(struct hnae3_handle *handle, int vf, bool enable);
769ee9e4424SYonglong Liu int (*set_vf_rate)(struct hnae3_handle *handle, int vf,
770ee9e4424SYonglong Liu int min_tx_rate, int max_tx_rate, bool force);
7718e6de441SHuazhong Tan int (*set_vf_mac)(struct hnae3_handle *handle, int vf, u8 *p);
772cb10228dSYonglong Liu int (*get_module_eeprom)(struct hnae3_handle *handle, u32 offset,
773cb10228dSYonglong Liu u32 len, u8 *data);
774a4de0228SHuazhong Tan bool (*get_cmdq_stat)(struct hnae3_handle *handle);
7750205ec04SJian Shen int (*add_cls_flower)(struct hnae3_handle *handle,
7760205ec04SJian Shen struct flow_cls_offload *cls_flower, int tc);
7770205ec04SJian Shen int (*del_cls_flower)(struct hnae3_handle *handle,
7780205ec04SJian Shen struct flow_cls_offload *cls_flower);
7790205ec04SJian Shen bool (*cls_flower_active)(struct hnae3_handle *handle);
780f5f2b3e4SGuangbin Huang int (*get_phy_link_ksettings)(struct hnae3_handle *handle,
781f5f2b3e4SGuangbin Huang struct ethtool_link_ksettings *cmd);
782f5f2b3e4SGuangbin Huang int (*set_phy_link_ksettings)(struct hnae3_handle *handle,
783f5f2b3e4SGuangbin Huang const struct ethtool_link_ksettings *cmd);
7840bf5eb78SHuazhong Tan bool (*set_tx_hwts_info)(struct hnae3_handle *handle,
7850bf5eb78SHuazhong Tan struct sk_buff *skb);
7860bf5eb78SHuazhong Tan void (*get_rx_hwts)(struct hnae3_handle *handle, struct sk_buff *skb,
7870bf5eb78SHuazhong Tan u32 nsec, u32 sec);
7880bf5eb78SHuazhong Tan int (*get_ts_info)(struct hnae3_handle *handle,
789*2111375bSKory Maincent struct kernel_ethtool_ts_info *info);
790f5c2b9f0SGuangbin Huang int (*get_link_diagnosis_info)(struct hnae3_handle *handle,
791f5c2b9f0SGuangbin Huang u32 *status_code);
792671cb8cbSPeng Li void (*clean_vf_config)(struct hnae3_ae_dev *ae_dev, int num_vfs);
7930ba22bcbSGuangbin Huang int (*get_dscp_prio)(struct hnae3_handle *handle, u8 dscp,
7940ba22bcbSGuangbin Huang u8 *tc_map_mode, u8 *priority);
7953b064f54SHao Lan void (*get_wol)(struct hnae3_handle *handle,
7963b064f54SHao Lan struct ethtool_wolinfo *wol);
7973b064f54SHao Lan int (*set_wol)(struct hnae3_handle *handle,
7983b064f54SHao Lan struct ethtool_wolinfo *wol);
79938caee9dSSalil };
80038caee9dSSalil
801cacde272SYunsheng Lin struct hnae3_dcb_ops {
802cacde272SYunsheng Lin /* IEEE 802.1Qaz std */
803cacde272SYunsheng Lin int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *);
804cacde272SYunsheng Lin int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *);
805cacde272SYunsheng Lin int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *);
806cacde272SYunsheng Lin int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *);
8070ba22bcbSGuangbin Huang int (*ieee_setapp)(struct hnae3_handle *h, struct dcb_app *app);
8080ba22bcbSGuangbin Huang int (*ieee_delapp)(struct hnae3_handle *h, struct dcb_app *app);
809cacde272SYunsheng Lin
810cacde272SYunsheng Lin /* DCBX configuration */
811cacde272SYunsheng Lin u8 (*getdcbx)(struct hnae3_handle *);
812cacde272SYunsheng Lin u8 (*setdcbx)(struct hnae3_handle *, u8);
813cacde272SYunsheng Lin
8145a5c9091SJian Shen int (*setup_tc)(struct hnae3_handle *handle,
8155a5c9091SJian Shen struct tc_mqprio_qopt_offload *mqprio_qopt);
816cacde272SYunsheng Lin };
817cacde272SYunsheng Lin
81838caee9dSSalil struct hnae3_ae_algo {
81938caee9dSSalil const struct hnae3_ae_ops *ops;
82038caee9dSSalil struct list_head node;
82138caee9dSSalil const struct pci_device_id *pdev_id_table;
82238caee9dSSalil };
82338caee9dSSalil
824f97c4d82SYonglong Liu #define HNAE3_INT_NAME_LEN 32
82538caee9dSSalil #define HNAE3_ITR_COUNTDOWN_START 100
82638caee9dSSalil
82738caee9dSSalil #define HNAE3_MAX_TC 8
828c5795c53SYunsheng Lin #define HNAE3_MAX_USER_PRIO 8
82935244430SJian Shen struct hnae3_tc_info {
83035244430SJian Shen u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */
83135244430SJian Shen u16 tqp_count[HNAE3_MAX_TC];
83235244430SJian Shen u16 tqp_offset[HNAE3_MAX_TC];
833e93530aeSGuangbin Huang u8 max_tc; /* Total number of TCs */
83435244430SJian Shen u8 num_tc; /* Total number of enabled TCs */
8355a5c9091SJian Shen bool mqprio_active;
83603f92287SJijie Shao bool mqprio_destroy;
837fa556494SJijie Shao bool dcb_ets_active;
83835244430SJian Shen };
83935244430SJian Shen
840dfea275eSGuangbin Huang #define HNAE3_MAX_DSCP 64
841dfea275eSGuangbin Huang #define HNAE3_PRIO_ID_INVALID 0xff
84238caee9dSSalil struct hnae3_knic_private_info {
84338caee9dSSalil struct net_device *netdev; /* Set by KNIC client when init instance */
84438caee9dSSalil u16 rss_size; /* Allocated RSS queues */
845672ad0edSHuazhong Tan u16 req_rss_size;
84638caee9dSSalil u16 rx_buf_len;
847c0425944SPeng Li u16 num_tx_desc;
848c0425944SPeng Li u16 num_rx_desc;
8491a00197bSHuazhong Tan u32 tx_spare_buf_size;
85038caee9dSSalil
85135244430SJian Shen struct hnae3_tc_info tc_info;
8520ba22bcbSGuangbin Huang u8 tc_map_mode;
853dfea275eSGuangbin Huang u8 dscp_app_cnt;
854dfea275eSGuangbin Huang u8 dscp_prio[HNAE3_MAX_DSCP];
85538caee9dSSalil
85638caee9dSSalil u16 num_tqps; /* total number of TQPs in this handle */
85738caee9dSSalil struct hnae3_queue **tqp; /* array base of all TQPs in this instance */
858cacde272SYunsheng Lin const struct hnae3_dcb_ops *dcb_ops;
8597e96adc4SFuyun Liang
8607e96adc4SFuyun Liang u16 int_rl_setting;
8619f0c6f4bSYufeng Mo void __iomem *io_base;
86238caee9dSSalil };
86338caee9dSSalil
86438caee9dSSalil struct hnae3_roce_private_info {
86538caee9dSSalil struct net_device *netdev;
86638caee9dSSalil void __iomem *roce_io_base;
86730ae7f8aSHuazhong Tan void __iomem *roce_mem_base;
86838caee9dSSalil int base_vector;
86938caee9dSSalil int num_vectors;
8704d60291bSHuazhong Tan
8714d60291bSHuazhong Tan /* The below attributes defined for RoCE client, hnae3 gives
8724d60291bSHuazhong Tan * initial values to them, and RoCE client can modify and use
8734d60291bSHuazhong Tan * them.
8744d60291bSHuazhong Tan */
8754d60291bSHuazhong Tan unsigned long reset_state;
8764d60291bSHuazhong Tan unsigned long instance_state;
8774d60291bSHuazhong Tan unsigned long state;
87838caee9dSSalil };
87938caee9dSSalil
880eb66d503SFuyun Liang #define HNAE3_SUPPORT_APP_LOOPBACK BIT(0)
881424eb834SSalil Mehta #define HNAE3_SUPPORT_PHY_LOOPBACK BIT(1)
8824dc13b96SFuyun Liang #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK BIT(2)
883424eb834SSalil Mehta #define HNAE3_SUPPORT_VF BIT(3)
8844dc13b96SFuyun Liang #define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK BIT(4)
88504b6ba14SYonglong Liu #define HNAE3_SUPPORT_EXTERNAL_LOOPBACK BIT(5)
88638caee9dSSalil
887c60edc17SJian Shen #define HNAE3_USER_UPE BIT(0) /* unicast promisc enabled by user */
888c60edc17SJian Shen #define HNAE3_USER_MPE BIT(1) /* mulitcast promisc enabled by user */
889c60edc17SJian Shen #define HNAE3_BPE BIT(2) /* broadcast promisc enable */
890c60edc17SJian Shen #define HNAE3_OVERFLOW_UPE BIT(3) /* unicast mac vlan overflow */
891c60edc17SJian Shen #define HNAE3_OVERFLOW_MPE BIT(4) /* multicast mac vlan overflow */
892c60edc17SJian Shen #define HNAE3_UPE (HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE)
893c60edc17SJian Shen #define HNAE3_MPE (HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE)
894c60edc17SJian Shen
8955e7414cdSJian Shen enum hnae3_pflag {
8965e7414cdSJian Shen HNAE3_PFLAG_LIMIT_PROMISC,
8975e7414cdSJian Shen HNAE3_PFLAG_MAX
8985e7414cdSJian Shen };
8995e7414cdSJian Shen
90038caee9dSSalil struct hnae3_handle {
90138caee9dSSalil struct hnae3_client *client;
90238caee9dSSalil struct pci_dev *pdev;
90338caee9dSSalil void *priv;
90438caee9dSSalil struct hnae3_ae_algo *ae_algo; /* the class who provides this handle */
90538caee9dSSalil u64 flags; /* Indicate the capabilities for this handle */
90638caee9dSSalil
90738caee9dSSalil union {
90838caee9dSSalil struct net_device *netdev; /* first member */
90938caee9dSSalil struct hnae3_knic_private_info kinfo;
91038caee9dSSalil struct hnae3_roce_private_info rinfo;
91138caee9dSSalil };
91238caee9dSSalil
9136639a7b9SPeiyang Wang nodemask_t numa_node_mask; /* for multi-chip support */
914c60edc17SJian Shen
91544e626f7SJian Shen enum hnae3_port_base_vlan_state port_base_vlan_state;
91644e626f7SJian Shen
917c60edc17SJian Shen u8 netdev_flags;
918b2292360Sliuzhongzhu struct dentry *hnae3_dbgfs;
9196dde452bSYufeng Mo /* protects concurrent contention between debugfs commands */
9206dde452bSYufeng Mo struct mutex dbgfs_lock;
9219c9a0421SYufeng Mo char **dbgfs_buf;
922bb87be87SYonglong Liu
923bb87be87SYonglong Liu /* Network interface message level enabled bits */
924bb87be87SYonglong Liu u32 msg_enable;
9255e7414cdSJian Shen
9265e7414cdSJian Shen unsigned long supported_pflags;
9275e7414cdSJian Shen unsigned long priv_flags;
92838caee9dSSalil };
92938caee9dSSalil
930e4e87715SPeng Li #define hnae3_set_field(origin, mask, shift, val) \
93138caee9dSSalil do { \
93238caee9dSSalil (origin) &= (~(mask)); \
93338caee9dSSalil (origin) |= ((val) << (shift)) & (mask); \
93438caee9dSSalil } while (0)
935e4e87715SPeng Li #define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift))
93638caee9dSSalil
937e4e87715SPeng Li #define hnae3_set_bit(origin, shift, val) \
9389393eb50SYufeng Mo hnae3_set_field(origin, 0x1 << (shift), shift, val)
939e4e87715SPeng Li #define hnae3_get_bit(origin, shift) \
9409393eb50SYufeng Mo hnae3_get_field(origin, 0x1 << (shift), shift)
94138caee9dSSalil
9424f331fdaSYufeng Mo #define HNAE3_FORMAT_MAC_ADDR_LEN 18
9434f331fdaSYufeng Mo #define HNAE3_FORMAT_MAC_ADDR_OFFSET_0 0
9444f331fdaSYufeng Mo #define HNAE3_FORMAT_MAC_ADDR_OFFSET_4 4
9454f331fdaSYufeng Mo #define HNAE3_FORMAT_MAC_ADDR_OFFSET_5 5
9464f331fdaSYufeng Mo
hnae3_format_mac_addr(char * format_mac_addr,const u8 * mac_addr)9474f331fdaSYufeng Mo static inline void hnae3_format_mac_addr(char *format_mac_addr,
9484f331fdaSYufeng Mo const u8 *mac_addr)
9494f331fdaSYufeng Mo {
9504f331fdaSYufeng Mo snprintf(format_mac_addr, HNAE3_FORMAT_MAC_ADDR_LEN, "%02x:**:**:**:%02x:%02x",
9514f331fdaSYufeng Mo mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_0],
9524f331fdaSYufeng Mo mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_4],
9534f331fdaSYufeng Mo mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_5]);
9544f331fdaSYufeng Mo }
9554f331fdaSYufeng Mo
95674354140SHuazhong Tan int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev);
95738caee9dSSalil void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev);
95838caee9dSSalil
9590dd8a25fSPeng Li void hnae3_unregister_ae_algo_prepare(struct hnae3_ae_algo *ae_algo);
96038caee9dSSalil void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo);
961854cf33aSFuyun Liang void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo);
96238caee9dSSalil
96338caee9dSSalil void hnae3_unregister_client(struct hnae3_client *client);
96438caee9dSSalil int hnae3_register_client(struct hnae3_client *client);
965d9f28fc2SJian Shen
966d9f28fc2SJian Shen void hnae3_set_client_init_flag(struct hnae3_client *client,
967ebaf1908SWeihang Li struct hnae3_ae_dev *ae_dev,
968ebaf1908SWeihang Li unsigned int inited);
96938caee9dSSalil #endif
970