xref: /linux/drivers/net/ethernet/chelsio/cxgb4/t4_values.h (revision 597473720f4dc69749542bfcfed4a927a43d935e)
1f612b815SHariprasad Shenai /*
2f612b815SHariprasad Shenai  * This file is part of the Chelsio T4 Ethernet driver for Linux.
3f612b815SHariprasad Shenai  *
4f612b815SHariprasad Shenai  * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
5f612b815SHariprasad Shenai  *
6f612b815SHariprasad Shenai  * This software is available to you under a choice of one of two
7f612b815SHariprasad Shenai  * licenses.  You may choose to be licensed under the terms of the GNU
8f612b815SHariprasad Shenai  * General Public License (GPL) Version 2, available from the file
9f612b815SHariprasad Shenai  * COPYING in the main directory of this source tree, or the
10f612b815SHariprasad Shenai  * OpenIB.org BSD license below:
11f612b815SHariprasad Shenai  *
12f612b815SHariprasad Shenai  *     Redistribution and use in source and binary forms, with or
13f612b815SHariprasad Shenai  *     without modification, are permitted provided that the following
14f612b815SHariprasad Shenai  *     conditions are met:
15f612b815SHariprasad Shenai  *
16f612b815SHariprasad Shenai  *      - Redistributions of source code must retain the above
17f612b815SHariprasad Shenai  *        copyright notice, this list of conditions and the following
18f612b815SHariprasad Shenai  *        disclaimer.
19f612b815SHariprasad Shenai  *
20f612b815SHariprasad Shenai  *      - Redistributions in binary form must reproduce the above
21f612b815SHariprasad Shenai  *        copyright notice, this list of conditions and the following
22f612b815SHariprasad Shenai  *        disclaimer in the documentation and/or other materials
23f612b815SHariprasad Shenai  *        provided with the distribution.
24f612b815SHariprasad Shenai  *
25f612b815SHariprasad Shenai  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26f612b815SHariprasad Shenai  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27f612b815SHariprasad Shenai  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28f612b815SHariprasad Shenai  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29f612b815SHariprasad Shenai  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30f612b815SHariprasad Shenai  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31f612b815SHariprasad Shenai  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32f612b815SHariprasad Shenai  * SOFTWARE.
33f612b815SHariprasad Shenai  */
34f612b815SHariprasad Shenai 
35f612b815SHariprasad Shenai #ifndef __T4_VALUES_H__
36f612b815SHariprasad Shenai #define __T4_VALUES_H__
37f612b815SHariprasad Shenai 
38f612b815SHariprasad Shenai /* This file contains definitions for various T4 register value hardware
39f612b815SHariprasad Shenai  * constants.  The types of values encoded here are predominantly those for
40f612b815SHariprasad Shenai  * register fields which control "modal" behavior.  For the most part, we do
41f612b815SHariprasad Shenai  * not include definitions for register fields which are simple numeric
42f612b815SHariprasad Shenai  * metrics, etc.
43f612b815SHariprasad Shenai  */
44f612b815SHariprasad Shenai 
45f612b815SHariprasad Shenai /* SGE register field values.
46f612b815SHariprasad Shenai  */
47f612b815SHariprasad Shenai 
48f612b815SHariprasad Shenai /* CONTROL1 register */
49f612b815SHariprasad Shenai #define RXPKTCPLMODE_SPLIT_X		1
50f612b815SHariprasad Shenai 
51f612b815SHariprasad Shenai #define INGPCIEBOUNDARY_SHIFT_X		5
52f612b815SHariprasad Shenai #define INGPCIEBOUNDARY_32B_X		0
53f612b815SHariprasad Shenai 
54f612b815SHariprasad Shenai #define INGPADBOUNDARY_SHIFT_X		5
55f612b815SHariprasad Shenai 
56acac5962SHariprasad Shenai #define T6_INGPADBOUNDARY_SHIFT_X	3
57bb58d079SArjun Vynipadath #define T6_INGPADBOUNDARY_8B_X		0
58acac5962SHariprasad Shenai #define T6_INGPADBOUNDARY_32B_X		2
59acac5962SHariprasad Shenai 
60bb58d079SArjun Vynipadath #define INGPADBOUNDARY_32B_X		0
61bb58d079SArjun Vynipadath 
62f612b815SHariprasad Shenai /* CONTROL2 register */
63f612b815SHariprasad Shenai #define INGPACKBOUNDARY_SHIFT_X		5
64f612b815SHariprasad Shenai #define INGPACKBOUNDARY_16B_X		0
65bb58d079SArjun Vynipadath #define INGPACKBOUNDARY_64B_X		1
66f612b815SHariprasad Shenai 
67f612b815SHariprasad Shenai /* GTS register */
68f612b815SHariprasad Shenai #define SGE_TIMERREGS			6
693a336cb1SHariprasad Shenai #define TIMERREG_COUNTER0_X		0
70f612b815SHariprasad Shenai 
711ecc7b7aSHariprasad Shenai #define FETCHBURSTMIN_64B_X		2
72edadad80SHariprasad Shenai #define FETCHBURSTMIN_128B_X		3
731ecc7b7aSHariprasad Shenai 
74*d429005fSVishal Kulkarni /* T6 and later use a single-bit encoding for FetchBurstMin */
75*d429005fSVishal Kulkarni #define FETCHBURSTMIN_64B_T6_X		0
76*d429005fSVishal Kulkarni #define FETCHBURSTMIN_128B_T6_X		1
77*d429005fSVishal Kulkarni 
783ccc6cf7SHariprasad Shenai #define FETCHBURSTMAX_256B_X		2
791ecc7b7aSHariprasad Shenai #define FETCHBURSTMAX_512B_X		3
801ecc7b7aSHariprasad Shenai 
81*d429005fSVishal Kulkarni #define HOSTFCMODE_INGRESS_QUEUE_X	1
821ecc7b7aSHariprasad Shenai #define HOSTFCMODE_STATUS_PAGE_X	2
831ecc7b7aSHariprasad Shenai 
841ecc7b7aSHariprasad Shenai #define CIDXFLUSHTHRESH_32_X		5
85*d429005fSVishal Kulkarni #define CIDXFLUSHTHRESH_128_X		7
861ecc7b7aSHariprasad Shenai 
871ecc7b7aSHariprasad Shenai #define UPDATEDELIVERY_INTERRUPT_X	1
881ecc7b7aSHariprasad Shenai 
891ecc7b7aSHariprasad Shenai #define RSPD_TYPE_FLBUF_X		0
901ecc7b7aSHariprasad Shenai #define RSPD_TYPE_CPL_X			1
911ecc7b7aSHariprasad Shenai #define RSPD_TYPE_INTR_X		2
921ecc7b7aSHariprasad Shenai 
93b8b1ae99SHariprasad Shenai /* Congestion Manager Definitions.
94b8b1ae99SHariprasad Shenai  */
95b8b1ae99SHariprasad Shenai #define CONMCTXT_CNGTPMODE_S		19
96b8b1ae99SHariprasad Shenai #define CONMCTXT_CNGTPMODE_V(x)		((x) << CONMCTXT_CNGTPMODE_S)
97b8b1ae99SHariprasad Shenai #define CONMCTXT_CNGCHMAP_S		0
98b8b1ae99SHariprasad Shenai #define CONMCTXT_CNGCHMAP_V(x)		((x) << CONMCTXT_CNGCHMAP_S)
99b8b1ae99SHariprasad Shenai #define CONMCTXT_CNGTPMODE_CHANNEL_X	2
100b8b1ae99SHariprasad Shenai #define CONMCTXT_CNGTPMODE_QUEUE_X	1
101b8b1ae99SHariprasad Shenai 
102f612b815SHariprasad Shenai /* T5 and later support a new BAR2-based doorbell mechanism for Egress Queues.
103f612b815SHariprasad Shenai  * The User Doorbells are each 128 bytes in length with a Simple Doorbell at
104f612b815SHariprasad Shenai  * offsets 8x and a Write Combining single 64-byte Egress Queue Unit
105f612b815SHariprasad Shenai  * (IDXSIZE_UNIT_X) Gather Buffer interface at offset 64.  For Ingress Queues,
106f612b815SHariprasad Shenai  * we have a Going To Sleep register at offsets 8x+4.
107f612b815SHariprasad Shenai  *
108f612b815SHariprasad Shenai  * As noted above, we have many instances of the Simple Doorbell and Going To
109f612b815SHariprasad Shenai  * Sleep registers at offsets 8x and 8x+4, respectively.  We want to use a
110f612b815SHariprasad Shenai  * non-64-byte aligned offset for the Simple Doorbell in order to attempt to
111f612b815SHariprasad Shenai  * avoid buffering of the writes to the Simple Doorbell and we want to use a
112f612b815SHariprasad Shenai  * non-contiguous offset for the Going To Sleep writes in order to avoid
113f612b815SHariprasad Shenai  * possible combining between them.
114f612b815SHariprasad Shenai  */
115f612b815SHariprasad Shenai #define SGE_UDB_SIZE		128
116f612b815SHariprasad Shenai #define SGE_UDB_KDOORBELL	8
117f612b815SHariprasad Shenai #define SGE_UDB_GTS		20
118f612b815SHariprasad Shenai #define SGE_UDB_WCDOORBELL	64
119f612b815SHariprasad Shenai 
120bf7c781dSHariprasad Shenai /* CIM register field values.
121bf7c781dSHariprasad Shenai  */
122bf7c781dSHariprasad Shenai #define X_MBOWNER_FW			1
123bf7c781dSHariprasad Shenai #define X_MBOWNER_PL			2
124bf7c781dSHariprasad Shenai 
125f061de42SHariprasad Shenai /* PCI-E definitions */
126f061de42SHariprasad Shenai #define WINDOW_SHIFT_X		10
127f061de42SHariprasad Shenai #define PCIEOFST_SHIFT_X	10
128f061de42SHariprasad Shenai 
1290d804338SHariprasad Shenai /* TP_VLAN_PRI_MAP controls which subset of fields will be present in the
1300d804338SHariprasad Shenai  * Compressed Filter Tuple for LE filters.  Each bit set in TP_VLAN_PRI_MAP
1310d804338SHariprasad Shenai  * selects for a particular field being present.  These fields, when present
1320d804338SHariprasad Shenai  * in the Compressed Filter Tuple, have the following widths in bits.
1330d804338SHariprasad Shenai  */
1340d804338SHariprasad Shenai #define FT_FCOE_W                       1
1350d804338SHariprasad Shenai #define FT_PORT_W                       3
1360d804338SHariprasad Shenai #define FT_VNIC_ID_W                    17
1370d804338SHariprasad Shenai #define FT_VLAN_W                       17
1380d804338SHariprasad Shenai #define FT_TOS_W                        8
1390d804338SHariprasad Shenai #define FT_PROTOCOL_W                   8
1400d804338SHariprasad Shenai #define FT_ETHERTYPE_W                  16
1410d804338SHariprasad Shenai #define FT_MACMATCH_W                   9
1420d804338SHariprasad Shenai #define FT_MPSHITTYPE_W                 3
1430d804338SHariprasad Shenai #define FT_FRAGMENTATION_W              1
1440d804338SHariprasad Shenai 
1450d804338SHariprasad Shenai /* Some of the Compressed Filter Tuple fields have internal structure.  These
1460d804338SHariprasad Shenai  * bit shifts/masks describe those structures.  All shifts are relative to the
1470d804338SHariprasad Shenai  * base position of the fields within the Compressed Filter Tuple
1480d804338SHariprasad Shenai  */
1490d804338SHariprasad Shenai #define FT_VLAN_VLD_S                   16
1500d804338SHariprasad Shenai #define FT_VLAN_VLD_V(x)                ((x) << FT_VLAN_VLD_S)
1510d804338SHariprasad Shenai #define FT_VLAN_VLD_F                   FT_VLAN_VLD_V(1U)
1520d804338SHariprasad Shenai 
1530d804338SHariprasad Shenai #define FT_VNID_ID_VF_S                 0
1540d804338SHariprasad Shenai #define FT_VNID_ID_VF_V(x)              ((x) << FT_VNID_ID_VF_S)
1550d804338SHariprasad Shenai 
1560d804338SHariprasad Shenai #define FT_VNID_ID_PF_S                 7
1570d804338SHariprasad Shenai #define FT_VNID_ID_PF_V(x)              ((x) << FT_VNID_ID_PF_S)
1580d804338SHariprasad Shenai 
1590d804338SHariprasad Shenai #define FT_VNID_ID_VLD_S                16
1600d804338SHariprasad Shenai #define FT_VNID_ID_VLD_V(x)             ((x) << FT_VNID_ID_VLD_S)
1610d804338SHariprasad Shenai 
162f612b815SHariprasad Shenai #endif /* __T4_VALUES_H__ */
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