1 /* 2 * Broadcom GENET MDIO routines 3 * 4 * Copyright (c) 2014 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 12 #include <linux/types.h> 13 #include <linux/delay.h> 14 #include <linux/wait.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/bitops.h> 18 #include <linux/netdevice.h> 19 #include <linux/platform_device.h> 20 #include <linux/phy.h> 21 #include <linux/phy_fixed.h> 22 #include <linux/brcmphy.h> 23 #include <linux/of.h> 24 #include <linux/of_net.h> 25 #include <linux/of_mdio.h> 26 #include <linux/platform_data/bcmgenet.h> 27 28 #include "bcmgenet.h" 29 30 /* read a value from the MII */ 31 static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location) 32 { 33 int ret; 34 struct net_device *dev = bus->priv; 35 struct bcmgenet_priv *priv = netdev_priv(dev); 36 u32 reg; 37 38 bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | 39 (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD); 40 /* Start MDIO transaction*/ 41 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); 42 reg |= MDIO_START_BUSY; 43 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD); 44 wait_event_timeout(priv->wq, 45 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) 46 & MDIO_START_BUSY), 47 HZ / 100); 48 ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); 49 50 /* Some broken devices are known not to release the line during 51 * turn-around, e.g: Broadcom BCM53125 external switches, so check for 52 * that condition here and ignore the MDIO controller read failure 53 * indication. 54 */ 55 if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (ret & MDIO_READ_FAIL)) 56 return -EIO; 57 58 return ret & 0xffff; 59 } 60 61 /* write a value to the MII */ 62 static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id, 63 int location, u16 val) 64 { 65 struct net_device *dev = bus->priv; 66 struct bcmgenet_priv *priv = netdev_priv(dev); 67 u32 reg; 68 69 bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) | 70 (location << MDIO_REG_SHIFT) | (0xffff & val)), 71 UMAC_MDIO_CMD); 72 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); 73 reg |= MDIO_START_BUSY; 74 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD); 75 wait_event_timeout(priv->wq, 76 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) & 77 MDIO_START_BUSY), 78 HZ / 100); 79 80 return 0; 81 } 82 83 /* setup netdev link state when PHY link status change and 84 * update UMAC and RGMII block when link up 85 */ 86 void bcmgenet_mii_setup(struct net_device *dev) 87 { 88 struct bcmgenet_priv *priv = netdev_priv(dev); 89 struct phy_device *phydev = priv->phydev; 90 u32 reg, cmd_bits = 0; 91 bool status_changed = false; 92 93 if (priv->old_link != phydev->link) { 94 status_changed = true; 95 priv->old_link = phydev->link; 96 } 97 98 if (phydev->link) { 99 /* check speed/duplex/pause changes */ 100 if (priv->old_speed != phydev->speed) { 101 status_changed = true; 102 priv->old_speed = phydev->speed; 103 } 104 105 if (priv->old_duplex != phydev->duplex) { 106 status_changed = true; 107 priv->old_duplex = phydev->duplex; 108 } 109 110 if (priv->old_pause != phydev->pause) { 111 status_changed = true; 112 priv->old_pause = phydev->pause; 113 } 114 115 /* done if nothing has changed */ 116 if (!status_changed) 117 return; 118 119 /* speed */ 120 if (phydev->speed == SPEED_1000) 121 cmd_bits = UMAC_SPEED_1000; 122 else if (phydev->speed == SPEED_100) 123 cmd_bits = UMAC_SPEED_100; 124 else 125 cmd_bits = UMAC_SPEED_10; 126 cmd_bits <<= CMD_SPEED_SHIFT; 127 128 /* duplex */ 129 if (phydev->duplex != DUPLEX_FULL) 130 cmd_bits |= CMD_HD_EN; 131 132 /* pause capability */ 133 if (!phydev->pause) 134 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 135 136 /* 137 * Program UMAC and RGMII block based on established 138 * link speed, duplex, and pause. The speed set in 139 * umac->cmd tell RGMII block which clock to use for 140 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). 141 * Receive clock is provided by the PHY. 142 */ 143 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 144 reg &= ~OOB_DISABLE; 145 reg |= RGMII_LINK; 146 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 147 148 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 149 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 150 CMD_HD_EN | 151 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); 152 reg |= cmd_bits; 153 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 154 } else { 155 /* done if nothing has changed */ 156 if (!status_changed) 157 return; 158 159 /* needed for MoCA fixed PHY to reflect correct link status */ 160 netif_carrier_off(dev); 161 } 162 163 phy_print_status(phydev); 164 } 165 166 void bcmgenet_mii_reset(struct net_device *dev) 167 { 168 struct bcmgenet_priv *priv = netdev_priv(dev); 169 170 if (priv->phydev) { 171 phy_init_hw(priv->phydev); 172 phy_start_aneg(priv->phydev); 173 } 174 } 175 176 void bcmgenet_phy_power_set(struct net_device *dev, bool enable) 177 { 178 struct bcmgenet_priv *priv = netdev_priv(dev); 179 u32 reg = 0; 180 181 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ 182 if (!GENET_IS_V4(priv)) 183 return; 184 185 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); 186 if (enable) { 187 reg &= ~EXT_CK25_DIS; 188 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 189 mdelay(1); 190 191 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN); 192 reg |= EXT_GPHY_RESET; 193 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 194 mdelay(1); 195 196 reg &= ~EXT_GPHY_RESET; 197 } else { 198 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | EXT_GPHY_RESET; 199 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 200 mdelay(1); 201 reg |= EXT_CK25_DIS; 202 } 203 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 204 udelay(60); 205 } 206 207 static void bcmgenet_internal_phy_setup(struct net_device *dev) 208 { 209 struct bcmgenet_priv *priv = netdev_priv(dev); 210 u32 reg; 211 212 /* Power up PHY */ 213 bcmgenet_phy_power_set(dev, true); 214 /* enable APD */ 215 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 216 reg |= EXT_PWR_DN_EN_LD; 217 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 218 bcmgenet_mii_reset(dev); 219 } 220 221 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) 222 { 223 u32 reg; 224 225 /* Speed settings are set in bcmgenet_mii_setup() */ 226 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL); 227 reg |= LED_ACT_SOURCE_MAC; 228 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL); 229 } 230 231 int bcmgenet_mii_config(struct net_device *dev, bool init) 232 { 233 struct bcmgenet_priv *priv = netdev_priv(dev); 234 struct phy_device *phydev = priv->phydev; 235 struct device *kdev = &priv->pdev->dev; 236 const char *phy_name = NULL; 237 u32 id_mode_dis = 0; 238 u32 port_ctrl; 239 u32 reg; 240 241 priv->ext_phy = !phy_is_internal(priv->phydev) && 242 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); 243 244 if (phy_is_internal(priv->phydev)) 245 priv->phy_interface = PHY_INTERFACE_MODE_NA; 246 247 switch (priv->phy_interface) { 248 case PHY_INTERFACE_MODE_NA: 249 case PHY_INTERFACE_MODE_MOCA: 250 /* Irrespective of the actually configured PHY speed (100 or 251 * 1000) GENETv4 only has an internal GPHY so we will just end 252 * up masking the Gigabit features from what we support, not 253 * switching to the EPHY 254 */ 255 if (GENET_IS_V4(priv)) 256 port_ctrl = PORT_MODE_INT_GPHY; 257 else 258 port_ctrl = PORT_MODE_INT_EPHY; 259 260 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 261 262 if (phy_is_internal(priv->phydev)) { 263 phy_name = "internal PHY"; 264 bcmgenet_internal_phy_setup(dev); 265 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 266 phy_name = "MoCA"; 267 bcmgenet_moca_phy_setup(priv); 268 } 269 break; 270 271 case PHY_INTERFACE_MODE_MII: 272 phy_name = "external MII"; 273 phydev->supported &= PHY_BASIC_FEATURES; 274 bcmgenet_sys_writel(priv, 275 PORT_MODE_EXT_EPHY, SYS_PORT_CTRL); 276 break; 277 278 case PHY_INTERFACE_MODE_REVMII: 279 phy_name = "external RvMII"; 280 /* of_mdiobus_register took care of reading the 'max-speed' 281 * PHY property for us, effectively limiting the PHY supported 282 * capabilities, use that knowledge to also configure the 283 * Reverse MII interface correctly. 284 */ 285 if ((priv->phydev->supported & PHY_BASIC_FEATURES) == 286 PHY_BASIC_FEATURES) 287 port_ctrl = PORT_MODE_EXT_RVMII_25; 288 else 289 port_ctrl = PORT_MODE_EXT_RVMII_50; 290 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 291 break; 292 293 case PHY_INTERFACE_MODE_RGMII: 294 /* RGMII_NO_ID: TXC transitions at the same time as TXD 295 * (requires PCB or receiver-side delay) 296 * RGMII: Add 2ns delay on TXC (90 degree shift) 297 * 298 * ID is implicitly disabled for 100Mbps (RG)MII operation. 299 */ 300 id_mode_dis = BIT(16); 301 /* fall through */ 302 case PHY_INTERFACE_MODE_RGMII_TXID: 303 if (id_mode_dis) 304 phy_name = "external RGMII (no delay)"; 305 else 306 phy_name = "external RGMII (TX delay)"; 307 bcmgenet_sys_writel(priv, 308 PORT_MODE_EXT_GPHY, SYS_PORT_CTRL); 309 break; 310 default: 311 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); 312 return -EINVAL; 313 } 314 315 /* This is an external PHY (xMII), so we need to enable the RGMII 316 * block for the interface to work 317 */ 318 if (priv->ext_phy) { 319 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 320 reg |= RGMII_MODE_EN | id_mode_dis; 321 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 322 } 323 324 if (init) 325 dev_info(kdev, "configuring instance for %s\n", phy_name); 326 327 return 0; 328 } 329 330 static int bcmgenet_mii_probe(struct net_device *dev) 331 { 332 struct bcmgenet_priv *priv = netdev_priv(dev); 333 struct device_node *dn = priv->pdev->dev.of_node; 334 struct phy_device *phydev; 335 u32 phy_flags; 336 int ret; 337 338 /* Communicate the integrated PHY revision */ 339 phy_flags = priv->gphy_rev; 340 341 /* Initialize link state variables that bcmgenet_mii_setup() uses */ 342 priv->old_link = -1; 343 priv->old_speed = -1; 344 priv->old_duplex = -1; 345 priv->old_pause = -1; 346 347 if (dn) { 348 if (priv->phydev) { 349 pr_info("PHY already attached\n"); 350 return 0; 351 } 352 353 /* In the case of a fixed PHY, the DT node associated 354 * to the PHY is the Ethernet MAC DT node. 355 */ 356 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { 357 ret = of_phy_register_fixed_link(dn); 358 if (ret) 359 return ret; 360 361 priv->phy_dn = of_node_get(dn); 362 } 363 364 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, 365 phy_flags, priv->phy_interface); 366 if (!phydev) { 367 pr_err("could not attach to PHY\n"); 368 return -ENODEV; 369 } 370 } else { 371 phydev = priv->phydev; 372 phydev->dev_flags = phy_flags; 373 374 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup, 375 priv->phy_interface); 376 if (ret) { 377 pr_err("could not attach to PHY\n"); 378 return -ENODEV; 379 } 380 } 381 382 priv->phydev = phydev; 383 384 /* Configure port multiplexer based on what the probed PHY device since 385 * reading the 'max-speed' property determines the maximum supported 386 * PHY speed which is needed for bcmgenet_mii_config() to configure 387 * things appropriately. 388 */ 389 ret = bcmgenet_mii_config(dev, true); 390 if (ret) { 391 phy_disconnect(priv->phydev); 392 return ret; 393 } 394 395 phydev->advertising = phydev->supported; 396 397 /* The internal PHY has its link interrupts routed to the 398 * Ethernet MAC ISRs 399 */ 400 if (phy_is_internal(priv->phydev)) 401 priv->mii_bus->irq[phydev->addr] = PHY_IGNORE_INTERRUPT; 402 else 403 priv->mii_bus->irq[phydev->addr] = PHY_POLL; 404 405 pr_info("attached PHY at address %d [%s]\n", 406 phydev->addr, phydev->drv->name); 407 408 return 0; 409 } 410 411 static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv) 412 { 413 struct mii_bus *bus; 414 415 if (priv->mii_bus) 416 return 0; 417 418 priv->mii_bus = mdiobus_alloc(); 419 if (!priv->mii_bus) { 420 pr_err("failed to allocate\n"); 421 return -ENOMEM; 422 } 423 424 bus = priv->mii_bus; 425 bus->priv = priv->dev; 426 bus->name = "bcmgenet MII bus"; 427 bus->parent = &priv->pdev->dev; 428 bus->read = bcmgenet_mii_read; 429 bus->write = bcmgenet_mii_write; 430 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", 431 priv->pdev->name, priv->pdev->id); 432 433 bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL); 434 if (!bus->irq) { 435 mdiobus_free(priv->mii_bus); 436 return -ENOMEM; 437 } 438 439 return 0; 440 } 441 442 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) 443 { 444 struct device_node *dn = priv->pdev->dev.of_node; 445 struct device *kdev = &priv->pdev->dev; 446 struct device_node *mdio_dn; 447 char *compat; 448 int ret; 449 450 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); 451 if (!compat) 452 return -ENOMEM; 453 454 mdio_dn = of_find_compatible_node(dn, NULL, compat); 455 kfree(compat); 456 if (!mdio_dn) { 457 dev_err(kdev, "unable to find MDIO bus node\n"); 458 return -ENODEV; 459 } 460 461 ret = of_mdiobus_register(priv->mii_bus, mdio_dn); 462 if (ret) { 463 dev_err(kdev, "failed to register MDIO bus\n"); 464 return ret; 465 } 466 467 /* Fetch the PHY phandle */ 468 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); 469 470 /* Get the link mode */ 471 priv->phy_interface = of_get_phy_mode(dn); 472 473 return 0; 474 } 475 476 static int bcmgenet_fixed_phy_link_update(struct net_device *dev, 477 struct fixed_phy_status *status) 478 { 479 if (dev && dev->phydev && status) 480 status->link = dev->phydev->link; 481 482 return 0; 483 } 484 485 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv) 486 { 487 struct device *kdev = &priv->pdev->dev; 488 struct bcmgenet_platform_data *pd = kdev->platform_data; 489 struct mii_bus *mdio = priv->mii_bus; 490 struct phy_device *phydev; 491 int ret; 492 493 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 494 /* 495 * Internal or external PHY with MDIO access 496 */ 497 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 498 mdio->phy_mask = ~(1 << pd->phy_address); 499 else 500 mdio->phy_mask = 0; 501 502 ret = mdiobus_register(mdio); 503 if (ret) { 504 dev_err(kdev, "failed to register MDIO bus\n"); 505 return ret; 506 } 507 508 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 509 phydev = mdio->phy_map[pd->phy_address]; 510 else 511 phydev = phy_find_first(mdio); 512 513 if (!phydev) { 514 dev_err(kdev, "failed to register PHY device\n"); 515 mdiobus_unregister(mdio); 516 return -ENODEV; 517 } 518 } else { 519 /* 520 * MoCA port or no MDIO access. 521 * Use fixed PHY to represent the link layer. 522 */ 523 struct fixed_phy_status fphy_status = { 524 .link = 1, 525 .speed = pd->phy_speed, 526 .duplex = pd->phy_duplex, 527 .pause = 0, 528 .asym_pause = 0, 529 }; 530 531 phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL); 532 if (!phydev || IS_ERR(phydev)) { 533 dev_err(kdev, "failed to register fixed PHY device\n"); 534 return -ENODEV; 535 } 536 537 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) { 538 ret = fixed_phy_set_link_update( 539 phydev, bcmgenet_fixed_phy_link_update); 540 if (!ret) 541 phydev->link = 0; 542 } 543 } 544 545 priv->phydev = phydev; 546 priv->phy_interface = pd->phy_interface; 547 548 return 0; 549 } 550 551 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) 552 { 553 struct device_node *dn = priv->pdev->dev.of_node; 554 555 if (dn) 556 return bcmgenet_mii_of_init(priv); 557 else 558 return bcmgenet_mii_pd_init(priv); 559 } 560 561 int bcmgenet_mii_init(struct net_device *dev) 562 { 563 struct bcmgenet_priv *priv = netdev_priv(dev); 564 int ret; 565 566 ret = bcmgenet_mii_alloc(priv); 567 if (ret) 568 return ret; 569 570 ret = bcmgenet_mii_bus_init(priv); 571 if (ret) 572 goto out_free; 573 574 ret = bcmgenet_mii_probe(dev); 575 if (ret) 576 goto out; 577 578 return 0; 579 580 out: 581 of_node_put(priv->phy_dn); 582 mdiobus_unregister(priv->mii_bus); 583 out_free: 584 kfree(priv->mii_bus->irq); 585 mdiobus_free(priv->mii_bus); 586 return ret; 587 } 588 589 void bcmgenet_mii_exit(struct net_device *dev) 590 { 591 struct bcmgenet_priv *priv = netdev_priv(dev); 592 593 of_node_put(priv->phy_dn); 594 mdiobus_unregister(priv->mii_bus); 595 kfree(priv->mii_bus->irq); 596 mdiobus_free(priv->mii_bus); 597 } 598