1c0c050c5SMichael Chan /* Broadcom NetXtreme-C/E network driver.
2c0c050c5SMichael Chan *
311f15ed3SMichael Chan * Copyright (c) 2014-2016 Broadcom Corporation
4894aa69aSMichael Chan * Copyright (c) 2016-2018 Broadcom Limited
5c0c050c5SMichael Chan *
6c0c050c5SMichael Chan * This program is free software; you can redistribute it and/or modify
7c0c050c5SMichael Chan * it under the terms of the GNU General Public License as published by
8c0c050c5SMichael Chan * the Free Software Foundation.
9c0c050c5SMichael Chan */
10c0c050c5SMichael Chan
11c0c050c5SMichael Chan #ifndef BNXT_H
12c0c050c5SMichael Chan #define BNXT_H
13c0c050c5SMichael Chan
14c0c050c5SMichael Chan #define DRV_MODULE_NAME "bnxt_en"
15c0c050c5SMichael Chan
16e3c0a635SLeon Romanovsky /* DO NOT CHANGE DRV_VER_* defines
17e3c0a635SLeon Romanovsky * FIXME: Delete them
18e3c0a635SLeon Romanovsky */
19c193554eSMichael Chan #define DRV_VER_MAJ 1
2031d357c0SMichael Chan #define DRV_VER_MIN 10
21397d44bfSMichael Chan #define DRV_VER_UPD 3
22c0c050c5SMichael Chan
23cc69837fSJakub Kicinski #include <linux/ethtool.h>
24282ccf6eSFlorian Westphal #include <linux/interrupt.h>
252ae7408fSSathya Perla #include <linux/rhashtable.h>
26d629522eSMichael Chan #include <linux/crash_dump.h>
27d80d88b0SAjit Khaparde #include <linux/auxiliary_bus.h>
284ab0c6a8SSathya Perla #include <net/devlink.h>
29ee5c7fb3SSathya Perla #include <net/dst_metadata.h>
3096a8604fSJesper Dangaard Brouer #include <net/xdp.h>
314f75da36STal Gilboa #include <linux/dim.h>
32c6132f6fSMichael Chan #include <linux/io-64-nonatomic-lo-hi.h>
33e07ab202SVasundhara Volam #ifdef CONFIG_TEE_BNXT_FW
34e07ab202SVasundhara Volam #include <linux/firmware/broadcom/tee_bnxt_fw.h>
35e07ab202SVasundhara Volam #endif
36282ccf6eSFlorian Westphal
37627c89d0SSriharsha Basavapatna extern struct list_head bnxt_block_cb_list;
38627c89d0SSriharsha Basavapatna
39322b87caSAndy Gospodarek struct page_pool;
40322b87caSAndy Gospodarek
41c0c050c5SMichael Chan struct tx_bd {
42c0c050c5SMichael Chan __le32 tx_bd_len_flags_type;
43c0c050c5SMichael Chan #define TX_BD_TYPE (0x3f << 0)
44c0c050c5SMichael Chan #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
45c0c050c5SMichael Chan #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
46c0c050c5SMichael Chan #define TX_BD_FLAGS_PACKET_END (1 << 6)
47c0c050c5SMichael Chan #define TX_BD_FLAGS_NO_CMPL (1 << 7)
48c0c050c5SMichael Chan #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
49c0c050c5SMichael Chan #define TX_BD_FLAGS_BD_CNT_SHIFT 8
50c0c050c5SMichael Chan #define TX_BD_FLAGS_LHINT (3 << 13)
51c0c050c5SMichael Chan #define TX_BD_FLAGS_LHINT_SHIFT 13
52c0c050c5SMichael Chan #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
53c0c050c5SMichael Chan #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
54c0c050c5SMichael Chan #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
55c0c050c5SMichael Chan #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
56c0c050c5SMichael Chan #define TX_BD_FLAGS_COAL_NOW (1 << 15)
57c0c050c5SMichael Chan #define TX_BD_LEN (0xffff << 16)
58c0c050c5SMichael Chan #define TX_BD_LEN_SHIFT 16
59c0c050c5SMichael Chan
60c0c050c5SMichael Chan u32 tx_bd_opaque;
61c0c050c5SMichael Chan __le64 tx_bd_haddr;
62c0c050c5SMichael Chan } __packed;
63c0c050c5SMichael Chan
6434eec1f2SMichael Chan #define TX_OPAQUE_IDX_MASK 0x0000ffff
6534eec1f2SMichael Chan #define TX_OPAQUE_BDS_MASK 0x00ff0000
6634eec1f2SMichael Chan #define TX_OPAQUE_BDS_SHIFT 16
675a3c585fSMichael Chan #define TX_OPAQUE_RING_MASK 0xff000000
685a3c585fSMichael Chan #define TX_OPAQUE_RING_SHIFT 24
6934eec1f2SMichael Chan
705a3c585fSMichael Chan #define SET_TX_OPAQUE(bp, txr, idx, bds) \
715a3c585fSMichael Chan (((txr)->tx_napi_idx << TX_OPAQUE_RING_SHIFT) | \
725a3c585fSMichael Chan ((bds) << TX_OPAQUE_BDS_SHIFT) | ((idx) & (bp)->tx_ring_mask))
7334eec1f2SMichael Chan
747f0a168bSMichael Chan #define TX_OPAQUE_IDX(opq) ((opq) & TX_OPAQUE_IDX_MASK)
755a3c585fSMichael Chan #define TX_OPAQUE_RING(opq) (((opq) & TX_OPAQUE_RING_MASK) >> \
765a3c585fSMichael Chan TX_OPAQUE_RING_SHIFT)
777f0a168bSMichael Chan #define TX_OPAQUE_BDS(opq) (((opq) & TX_OPAQUE_BDS_MASK) >> \
787f0a168bSMichael Chan TX_OPAQUE_BDS_SHIFT)
797f0a168bSMichael Chan #define TX_OPAQUE_PROD(bp, opq) ((TX_OPAQUE_IDX(opq) + TX_OPAQUE_BDS(opq)) &\
807f0a168bSMichael Chan (bp)->tx_ring_mask)
817f0a168bSMichael Chan
82c0c050c5SMichael Chan struct tx_bd_ext {
83c0c050c5SMichael Chan __le32 tx_bd_hsize_lflags;
84c0c050c5SMichael Chan #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
85c0c050c5SMichael Chan #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
86c0c050c5SMichael Chan #define TX_BD_FLAGS_NO_CRC (1 << 2)
87c0c050c5SMichael Chan #define TX_BD_FLAGS_STAMP (1 << 3)
88c0c050c5SMichael Chan #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
89c0c050c5SMichael Chan #define TX_BD_FLAGS_LSO (1 << 5)
90c0c050c5SMichael Chan #define TX_BD_FLAGS_IPID_FMT (1 << 6)
91c0c050c5SMichael Chan #define TX_BD_FLAGS_T_IPID (1 << 7)
92c0c050c5SMichael Chan #define TX_BD_HSIZE (0xff << 16)
93c0c050c5SMichael Chan #define TX_BD_HSIZE_SHIFT 16
94c0c050c5SMichael Chan
95c0c050c5SMichael Chan __le32 tx_bd_mss;
96c0c050c5SMichael Chan __le32 tx_bd_cfa_action;
97c0c050c5SMichael Chan #define TX_BD_CFA_ACTION (0xffff << 16)
98c0c050c5SMichael Chan #define TX_BD_CFA_ACTION_SHIFT 16
99c0c050c5SMichael Chan
100c0c050c5SMichael Chan __le32 tx_bd_cfa_meta;
101c0c050c5SMichael Chan #define TX_BD_CFA_META_MASK 0xfffffff
102c0c050c5SMichael Chan #define TX_BD_CFA_META_VID_MASK 0xfff
103c0c050c5SMichael Chan #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
104c0c050c5SMichael Chan #define TX_BD_CFA_META_PRI_SHIFT 12
105c0c050c5SMichael Chan #define TX_BD_CFA_META_TPID_MASK (3 << 16)
106c0c050c5SMichael Chan #define TX_BD_CFA_META_TPID_SHIFT 16
107c0c050c5SMichael Chan #define TX_BD_CFA_META_KEY (0xf << 28)
108c0c050c5SMichael Chan #define TX_BD_CFA_META_KEY_SHIFT 28
109c0c050c5SMichael Chan #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
110c0c050c5SMichael Chan };
111c0c050c5SMichael Chan
11283bb623cSPavan Chebbi #define BNXT_TX_PTP_IS_SET(lflags) ((lflags) & cpu_to_le32(TX_BD_FLAGS_STAMP))
11383bb623cSPavan Chebbi
114c0c050c5SMichael Chan struct rx_bd {
115c0c050c5SMichael Chan __le32 rx_bd_len_flags_type;
116c0c050c5SMichael Chan #define RX_BD_TYPE (0x3f << 0)
117c0c050c5SMichael Chan #define RX_BD_TYPE_RX_PACKET_BD 0x4
118c0c050c5SMichael Chan #define RX_BD_TYPE_RX_BUFFER_BD 0x5
119c0c050c5SMichael Chan #define RX_BD_TYPE_RX_AGG_BD 0x6
120c0c050c5SMichael Chan #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
121c0c050c5SMichael Chan #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
122c0c050c5SMichael Chan #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
123c0c050c5SMichael Chan #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
124c0c050c5SMichael Chan #define RX_BD_FLAGS_SOP (1 << 6)
125c0c050c5SMichael Chan #define RX_BD_FLAGS_EOP (1 << 7)
126c0c050c5SMichael Chan #define RX_BD_FLAGS_BUFFERS (3 << 8)
127c0c050c5SMichael Chan #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
128c0c050c5SMichael Chan #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
129c0c050c5SMichael Chan #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
130c0c050c5SMichael Chan #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
131c0c050c5SMichael Chan #define RX_BD_LEN (0xffff << 16)
132c0c050c5SMichael Chan #define RX_BD_LEN_SHIFT 16
133c0c050c5SMichael Chan
134c0c050c5SMichael Chan u32 rx_bd_opaque;
135c0c050c5SMichael Chan __le64 rx_bd_haddr;
136c0c050c5SMichael Chan };
137c0c050c5SMichael Chan
138c0c050c5SMichael Chan struct tx_cmp {
139c0c050c5SMichael Chan __le32 tx_cmp_flags_type;
140c0c050c5SMichael Chan #define CMP_TYPE (0x3f << 0)
141c0c050c5SMichael Chan #define CMP_TYPE_TX_L2_CMP 0
14213d2d3d3SMichael Chan #define CMP_TYPE_TX_L2_COAL_CMP 2
14313d2d3d3SMichael Chan #define CMP_TYPE_TX_L2_PKT_TS_CMP 4
144c0c050c5SMichael Chan #define CMP_TYPE_RX_L2_CMP 17
145c0c050c5SMichael Chan #define CMP_TYPE_RX_AGG_CMP 18
146c0c050c5SMichael Chan #define CMP_TYPE_RX_L2_TPA_START_CMP 19
147c0c050c5SMichael Chan #define CMP_TYPE_RX_L2_TPA_END_CMP 21
148218a8a71SMichael Chan #define CMP_TYPE_RX_TPA_AGG_CMP 22
14913d2d3d3SMichael Chan #define CMP_TYPE_RX_L2_V3_CMP 23
15013d2d3d3SMichael Chan #define CMP_TYPE_RX_L2_TPA_START_V3_CMP 25
151c0c050c5SMichael Chan #define CMP_TYPE_STATUS_CMP 32
152c0c050c5SMichael Chan #define CMP_TYPE_REMOTE_DRIVER_REQ 34
153c0c050c5SMichael Chan #define CMP_TYPE_REMOTE_DRIVER_RESP 36
154c0c050c5SMichael Chan #define CMP_TYPE_ERROR_STATUS 48
155441cabbbSMichael Chan #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
156441cabbbSMichael Chan #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
157441cabbbSMichael Chan #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
158441cabbbSMichael Chan #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
159441cabbbSMichael Chan #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
160c0c050c5SMichael Chan
161c0c050c5SMichael Chan #define TX_CMP_FLAGS_ERROR (1 << 6)
162c0c050c5SMichael Chan #define TX_CMP_FLAGS_PUSH (1 << 7)
163c0c050c5SMichael Chan
164c0c050c5SMichael Chan u32 tx_cmp_opaque;
165c0c050c5SMichael Chan __le32 tx_cmp_errors_v;
166c0c050c5SMichael Chan #define TX_CMP_V (1 << 0)
167c0c050c5SMichael Chan #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
168c0c050c5SMichael Chan #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
169c0c050c5SMichael Chan #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
170c0c050c5SMichael Chan #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
171c0c050c5SMichael Chan #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
172c0c050c5SMichael Chan #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
173c0c050c5SMichael Chan #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
174c0c050c5SMichael Chan #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
175c0c050c5SMichael Chan #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
176c0c050c5SMichael Chan
17713d2d3d3SMichael Chan __le32 sq_cons_idx;
17813d2d3d3SMichael Chan #define TX_CMP_SQ_CONS_IDX_MASK 0x00ffffff
179c0c050c5SMichael Chan };
180c0c050c5SMichael Chan
18113d2d3d3SMichael Chan #define TX_CMP_SQ_CONS_IDX(txcmp) \
18213d2d3d3SMichael Chan (le32_to_cpu((txcmp)->sq_cons_idx) & TX_CMP_SQ_CONS_IDX_MASK)
18313d2d3d3SMichael Chan
184be6b7ca3SMichael Chan struct tx_ts_cmp {
185be6b7ca3SMichael Chan __le32 tx_ts_cmp_flags_type;
186be6b7ca3SMichael Chan #define TX_TS_CMP_FLAGS_ERROR (1 << 6)
187be6b7ca3SMichael Chan #define TX_TS_CMP_FLAGS_TS_TYPE (1 << 7)
188be6b7ca3SMichael Chan #define TX_TS_CMP_FLAGS_TS_TYPE_PM (0 << 7)
189be6b7ca3SMichael Chan #define TX_TS_CMP_FLAGS_TS_TYPE_PA (1 << 7)
190be6b7ca3SMichael Chan #define TX_TS_CMP_FLAGS_TS_FALLBACK (1 << 8)
191be6b7ca3SMichael Chan #define TX_TS_CMP_TS_SUB_NS (0xf << 12)
192be6b7ca3SMichael Chan #define TX_TS_CMP_TS_NS_MID (0xffff << 16)
193be6b7ca3SMichael Chan #define TX_TS_CMP_TS_NS_MID_SFT 16
194be6b7ca3SMichael Chan u32 tx_ts_cmp_opaque;
195be6b7ca3SMichael Chan __le32 tx_ts_cmp_errors_v;
196be6b7ca3SMichael Chan #define TX_TS_CMP_V (1 << 0)
197be6b7ca3SMichael Chan #define TX_TS_CMP_TS_INVALID_ERR (1 << 10)
198be6b7ca3SMichael Chan __le32 tx_ts_cmp_ts_ns_lo;
199be6b7ca3SMichael Chan };
200be6b7ca3SMichael Chan
201be6b7ca3SMichael Chan #define BNXT_GET_TX_TS_48B_NS(tscmp) \
202be6b7ca3SMichael Chan (le32_to_cpu((tscmp)->tx_ts_cmp_ts_ns_lo) | \
203be6b7ca3SMichael Chan ((u64)(le32_to_cpu((tscmp)->tx_ts_cmp_flags_type) & \
204be6b7ca3SMichael Chan TX_TS_CMP_TS_NS_MID) << TX_TS_CMP_TS_NS_MID_SFT))
205be6b7ca3SMichael Chan
206be6b7ca3SMichael Chan #define BNXT_TX_TS_ERR(tscmp) \
207be6b7ca3SMichael Chan (((tscmp)->tx_ts_cmp_flags_type & cpu_to_le32(TX_TS_CMP_FLAGS_ERROR)) &&\
208be6b7ca3SMichael Chan ((tscmp)->tx_ts_cmp_errors_v & cpu_to_le32(TX_TS_CMP_TS_INVALID_ERR)))
209be6b7ca3SMichael Chan
210c0c050c5SMichael Chan struct rx_cmp {
211c0c050c5SMichael Chan __le32 rx_cmp_len_flags_type;
212c0c050c5SMichael Chan #define RX_CMP_CMP_TYPE (0x3f << 0)
213c0c050c5SMichael Chan #define RX_CMP_FLAGS_ERROR (1 << 6)
214c0c050c5SMichael Chan #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
215c0c050c5SMichael Chan #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
216c13e268cSMichael Chan #define RX_CMP_FLAGS_PKT_METADATA_PRESENT (1 << 11)
217c0c050c5SMichael Chan #define RX_CMP_FLAGS_ITYPES_SHIFT 12
2187f5515d1SPavan Chebbi #define RX_CMP_FLAGS_ITYPES_MASK 0xf000
219c0c050c5SMichael Chan #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
220c0c050c5SMichael Chan #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
221c0c050c5SMichael Chan #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
222c0c050c5SMichael Chan #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
223c0c050c5SMichael Chan #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
224c0c050c5SMichael Chan #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
225c0c050c5SMichael Chan #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
226c0c050c5SMichael Chan #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
227c0c050c5SMichael Chan #define RX_CMP_LEN (0xffff << 16)
228c0c050c5SMichael Chan #define RX_CMP_LEN_SHIFT 16
229c0c050c5SMichael Chan
230c0c050c5SMichael Chan u32 rx_cmp_opaque;
231c0c050c5SMichael Chan __le32 rx_cmp_misc_v1;
232c0c050c5SMichael Chan #define RX_CMP_V1 (1 << 0)
233c0c050c5SMichael Chan #define RX_CMP_AGG_BUFS (0x1f << 1)
234c0c050c5SMichael Chan #define RX_CMP_AGG_BUFS_SHIFT 1
235c0c050c5SMichael Chan #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
236c0c050c5SMichael Chan #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
23713d2d3d3SMichael Chan #define RX_CMP_V3_RSS_EXT_OP_LEGACY (0xf << 12)
23813d2d3d3SMichael Chan #define RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT 12
23913d2d3d3SMichael Chan #define RX_CMP_V3_RSS_EXT_OP_NEW (0xf << 8)
24013d2d3d3SMichael Chan #define RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT 8
241c0c050c5SMichael Chan #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
242c0c050c5SMichael Chan #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
24313d2d3d3SMichael Chan #define RX_CMP_SUB_NS_TS (0xf << 16)
24413d2d3d3SMichael Chan #define RX_CMP_SUB_NS_TS_SHIFT 16
24513d2d3d3SMichael Chan #define RX_CMP_METADATA1 (0xf << 28)
24613d2d3d3SMichael Chan #define RX_CMP_METADATA1_SHIFT 28
24713d2d3d3SMichael Chan #define RX_CMP_METADATA1_TPID_SEL (0x7 << 28)
24813d2d3d3SMichael Chan #define RX_CMP_METADATA1_TPID_8021Q (0x1 << 28)
24913d2d3d3SMichael Chan #define RX_CMP_METADATA1_TPID_8021AD (0x0 << 28)
25013d2d3d3SMichael Chan #define RX_CMP_METADATA1_VALID (0x8 << 28)
251c0c050c5SMichael Chan
252c0c050c5SMichael Chan __le32 rx_cmp_rss_hash;
253c0c050c5SMichael Chan };
254c0c050c5SMichael Chan
255c13e268cSMichael Chan #define BNXT_PTP_RX_TS_VALID(flags) \
256c13e268cSMichael Chan (((flags) & RX_CMP_FLAGS_ITYPES_MASK) == RX_CMP_FLAGS_ITYPE_PTP_W_TS)
257c13e268cSMichael Chan
258c13e268cSMichael Chan #define BNXT_ALL_RX_TS_VALID(flags) \
259c13e268cSMichael Chan !((flags) & RX_CMP_FLAGS_PKT_METADATA_PRESENT)
260c13e268cSMichael Chan
261c0c050c5SMichael Chan #define RX_CMP_HASH_VALID(rxcmp) \
262c0c050c5SMichael Chan ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
263c0c050c5SMichael Chan
264614388ceSMichael Chan #define RSS_PROFILE_ID_MASK 0x1f
265614388ceSMichael Chan
266c0c050c5SMichael Chan #define RX_CMP_HASH_TYPE(rxcmp) \
267614388ceSMichael Chan (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
268614388ceSMichael Chan RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
269c0c050c5SMichael Chan
27013d2d3d3SMichael Chan #define RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp) \
27113d2d3d3SMichael Chan ((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_V3_RSS_EXT_OP_LEGACY) >>\
27213d2d3d3SMichael Chan RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT)
27313d2d3d3SMichael Chan
27413d2d3d3SMichael Chan #define RX_CMP_V3_HASH_TYPE_NEW(rxcmp) \
27513d2d3d3SMichael Chan ((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_V3_RSS_EXT_OP_NEW) >>\
27613d2d3d3SMichael Chan RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT)
27713d2d3d3SMichael Chan
27813d2d3d3SMichael Chan #define RX_CMP_V3_HASH_TYPE(bp, rxcmp) \
27913d2d3d3SMichael Chan (((bp)->rss_cap & BNXT_RSS_CAP_RSS_TCAM) ? \
28013d2d3d3SMichael Chan RX_CMP_V3_HASH_TYPE_NEW(rxcmp) : \
28113d2d3d3SMichael Chan RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp))
28213d2d3d3SMichael Chan
28313d2d3d3SMichael Chan #define EXT_OP_INNER_4 0x0
28413d2d3d3SMichael Chan #define EXT_OP_OUTER_4 0x2
28513d2d3d3SMichael Chan #define EXT_OP_INNFL_3 0x8
28613d2d3d3SMichael Chan #define EXT_OP_OUTFL_3 0xa
28713d2d3d3SMichael Chan
28813d2d3d3SMichael Chan #define RX_CMP_VLAN_VALID(rxcmp) \
28913d2d3d3SMichael Chan ((rxcmp)->rx_cmp_misc_v1 & cpu_to_le32(RX_CMP_METADATA1_VALID))
29013d2d3d3SMichael Chan
29113d2d3d3SMichael Chan #define RX_CMP_VLAN_TPID_SEL(rxcmp) \
29213d2d3d3SMichael Chan (le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_METADATA1_TPID_SEL)
29313d2d3d3SMichael Chan
294c0c050c5SMichael Chan struct rx_cmp_ext {
295c0c050c5SMichael Chan __le32 rx_cmp_flags2;
296c0c050c5SMichael Chan #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
297c0c050c5SMichael Chan #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
298c0c050c5SMichael Chan #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
299c0c050c5SMichael Chan #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
300c0c050c5SMichael Chan #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
301c0c050c5SMichael Chan __le32 rx_cmp_meta_data;
302ed7bc602SMichael Chan #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff
303c0c050c5SMichael Chan #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
304c0c050c5SMichael Chan #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
305c0c050c5SMichael Chan #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
306c0c050c5SMichael Chan __le32 rx_cmp_cfa_code_errors_v2;
307c0c050c5SMichael Chan #define RX_CMP_V (1 << 0)
308c0c050c5SMichael Chan #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
309c0c050c5SMichael Chan #define RX_CMPL_ERRORS_SFT 1
310c0c050c5SMichael Chan #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
311c0c050c5SMichael Chan #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
312c0c050c5SMichael Chan #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
313c0c050c5SMichael Chan #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
314c0c050c5SMichael Chan #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
315c0c050c5SMichael Chan #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
316c0c050c5SMichael Chan #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
317c0c050c5SMichael Chan #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
318c0c050c5SMichael Chan #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
319c0c050c5SMichael Chan #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
320c0c050c5SMichael Chan #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
321c0c050c5SMichael Chan #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
322c0c050c5SMichael Chan #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
323c0c050c5SMichael Chan #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
324c0c050c5SMichael Chan #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
325c0c050c5SMichael Chan #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
326c0c050c5SMichael Chan #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
327c0c050c5SMichael Chan #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
328c0c050c5SMichael Chan #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
329c0c050c5SMichael Chan #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
330c0c050c5SMichael Chan #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
331c0c050c5SMichael Chan #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
332c0c050c5SMichael Chan #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
333c0c050c5SMichael Chan #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
334c0c050c5SMichael Chan #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
335c0c050c5SMichael Chan #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
336c0c050c5SMichael Chan #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
337c0c050c5SMichael Chan #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
338c0c050c5SMichael Chan
339c0c050c5SMichael Chan #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
340c0c050c5SMichael Chan #define RX_CMPL_CFA_CODE_SFT 16
34113d2d3d3SMichael Chan #define RX_CMPL_METADATA0_TCI_MASK (0xffff << 16)
34213d2d3d3SMichael Chan #define RX_CMPL_METADATA0_VID_MASK (0x0fff << 16)
34313d2d3d3SMichael Chan #define RX_CMPL_METADATA0_SFT 16
344c0c050c5SMichael Chan
3457f5515d1SPavan Chebbi __le32 rx_cmp_timestamp;
346c0c050c5SMichael Chan };
347c0c050c5SMichael Chan
348c0c050c5SMichael Chan #define RX_CMP_L2_ERRORS \
349c0c050c5SMichael Chan cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
350c0c050c5SMichael Chan
351c0c050c5SMichael Chan #define RX_CMP_L4_CS_BITS \
352c0c050c5SMichael Chan (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
353c0c050c5SMichael Chan
354c0c050c5SMichael Chan #define RX_CMP_L4_CS_ERR_BITS \
355c0c050c5SMichael Chan (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
356c0c050c5SMichael Chan
357c0c050c5SMichael Chan #define RX_CMP_L4_CS_OK(rxcmp1) \
358c0c050c5SMichael Chan (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
359c0c050c5SMichael Chan !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
360c0c050c5SMichael Chan
361c0c050c5SMichael Chan #define RX_CMP_ENCAP(rxcmp1) \
362c0c050c5SMichael Chan ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
363c0c050c5SMichael Chan RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
364c0c050c5SMichael Chan
365ee5c7fb3SSathya Perla #define RX_CMP_CFA_CODE(rxcmpl1) \
366ee5c7fb3SSathya Perla ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \
367ee5c7fb3SSathya Perla RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
368ee5c7fb3SSathya Perla
36913d2d3d3SMichael Chan #define RX_CMP_METADATA0_TCI(rxcmp1) \
37013d2d3d3SMichael Chan ((le32_to_cpu((rxcmp1)->rx_cmp_cfa_code_errors_v2) & \
37113d2d3d3SMichael Chan RX_CMPL_METADATA0_TCI_MASK) >> RX_CMPL_METADATA0_SFT)
37213d2d3d3SMichael Chan
373c0c050c5SMichael Chan struct rx_agg_cmp {
374c0c050c5SMichael Chan __le32 rx_agg_cmp_len_flags_type;
375c0c050c5SMichael Chan #define RX_AGG_CMP_TYPE (0x3f << 0)
376c0c050c5SMichael Chan #define RX_AGG_CMP_LEN (0xffff << 16)
377c0c050c5SMichael Chan #define RX_AGG_CMP_LEN_SHIFT 16
378c0c050c5SMichael Chan u32 rx_agg_cmp_opaque;
379c0c050c5SMichael Chan __le32 rx_agg_cmp_v;
380c0c050c5SMichael Chan #define RX_AGG_CMP_V (1 << 0)
381218a8a71SMichael Chan #define RX_AGG_CMP_AGG_ID (0xffff << 16)
382218a8a71SMichael Chan #define RX_AGG_CMP_AGG_ID_SHIFT 16
383c0c050c5SMichael Chan __le32 rx_agg_cmp_unused;
384c0c050c5SMichael Chan };
385c0c050c5SMichael Chan
386218a8a71SMichael Chan #define TPA_AGG_AGG_ID(rx_agg) \
387218a8a71SMichael Chan ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) & \
388218a8a71SMichael Chan RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
389218a8a71SMichael Chan
390c0c050c5SMichael Chan struct rx_tpa_start_cmp {
391c0c050c5SMichael Chan __le32 rx_tpa_start_cmp_len_flags_type;
392c0c050c5SMichael Chan #define RX_TPA_START_CMP_TYPE (0x3f << 0)
393c0c050c5SMichael Chan #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
394c0c050c5SMichael Chan #define RX_TPA_START_CMP_FLAGS_SHIFT 6
395218a8a71SMichael Chan #define RX_TPA_START_CMP_FLAGS_ERROR (0x1 << 6)
396c0c050c5SMichael Chan #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
397c0c050c5SMichael Chan #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
398c0c050c5SMichael Chan #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
399c0c050c5SMichael Chan #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
400c0c050c5SMichael Chan #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
401c0c050c5SMichael Chan #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
402c0c050c5SMichael Chan #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
403218a8a71SMichael Chan #define RX_TPA_START_CMP_FLAGS_TIMESTAMP (0x1 << 11)
404c0c050c5SMichael Chan #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
405c0c050c5SMichael Chan #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
406c0c050c5SMichael Chan #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
407c0c050c5SMichael Chan #define RX_TPA_START_CMP_LEN (0xffff << 16)
408c0c050c5SMichael Chan #define RX_TPA_START_CMP_LEN_SHIFT 16
409c0c050c5SMichael Chan
410c0c050c5SMichael Chan u32 rx_tpa_start_cmp_opaque;
411c0c050c5SMichael Chan __le32 rx_tpa_start_cmp_misc_v1;
412c0c050c5SMichael Chan #define RX_TPA_START_CMP_V1 (0x1 << 0)
413c0c050c5SMichael Chan #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
414c0c050c5SMichael Chan #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
41513d2d3d3SMichael Chan #define RX_TPA_START_CMP_V3_RSS_HASH_TYPE (0x1ff << 7)
41613d2d3d3SMichael Chan #define RX_TPA_START_CMP_V3_RSS_HASH_TYPE_SHIFT 7
417c0c050c5SMichael Chan #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
418c0c050c5SMichael Chan #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
419218a8a71SMichael Chan #define RX_TPA_START_CMP_AGG_ID_P5 (0xffff << 16)
420218a8a71SMichael Chan #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5 16
42113d2d3d3SMichael Chan #define RX_TPA_START_CMP_METADATA1 (0xf << 28)
42213d2d3d3SMichael Chan #define RX_TPA_START_CMP_METADATA1_SHIFT 28
42313d2d3d3SMichael Chan #define RX_TPA_START_METADATA1_TPID_SEL (0x7 << 28)
42413d2d3d3SMichael Chan #define RX_TPA_START_METADATA1_TPID_8021Q (0x1 << 28)
42513d2d3d3SMichael Chan #define RX_TPA_START_METADATA1_TPID_8021AD (0x0 << 28)
42613d2d3d3SMichael Chan #define RX_TPA_START_METADATA1_VALID (0x8 << 28)
427c0c050c5SMichael Chan
428c0c050c5SMichael Chan __le32 rx_tpa_start_cmp_rss_hash;
429c0c050c5SMichael Chan };
430c0c050c5SMichael Chan
431c0c050c5SMichael Chan #define TPA_START_HASH_VALID(rx_tpa_start) \
432c0c050c5SMichael Chan ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
433c0c050c5SMichael Chan cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
434c0c050c5SMichael Chan
435c0c050c5SMichael Chan #define TPA_START_HASH_TYPE(rx_tpa_start) \
436614388ceSMichael Chan (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
437c0c050c5SMichael Chan RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
438614388ceSMichael Chan RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
439c0c050c5SMichael Chan
44013d2d3d3SMichael Chan #define TPA_START_V3_HASH_TYPE(rx_tpa_start) \
44113d2d3d3SMichael Chan (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
44213d2d3d3SMichael Chan RX_TPA_START_CMP_V3_RSS_HASH_TYPE) >> \
44313d2d3d3SMichael Chan RX_TPA_START_CMP_V3_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
44413d2d3d3SMichael Chan
445c0c050c5SMichael Chan #define TPA_START_AGG_ID(rx_tpa_start) \
446c0c050c5SMichael Chan ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
447c0c050c5SMichael Chan RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
448c0c050c5SMichael Chan
449218a8a71SMichael Chan #define TPA_START_AGG_ID_P5(rx_tpa_start) \
450218a8a71SMichael Chan ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
451218a8a71SMichael Chan RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
452218a8a71SMichael Chan
453218a8a71SMichael Chan #define TPA_START_ERROR(rx_tpa_start) \
454218a8a71SMichael Chan ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
455218a8a71SMichael Chan cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
456218a8a71SMichael Chan
45713d2d3d3SMichael Chan #define TPA_START_VLAN_VALID(rx_tpa_start) \
45813d2d3d3SMichael Chan ((rx_tpa_start)->rx_tpa_start_cmp_misc_v1 & \
45913d2d3d3SMichael Chan cpu_to_le32(RX_TPA_START_METADATA1_VALID))
46013d2d3d3SMichael Chan
46113d2d3d3SMichael Chan #define TPA_START_VLAN_TPID_SEL(rx_tpa_start) \
46213d2d3d3SMichael Chan (le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
46313d2d3d3SMichael Chan RX_TPA_START_METADATA1_TPID_SEL)
46413d2d3d3SMichael Chan
465c0c050c5SMichael Chan struct rx_tpa_start_cmp_ext {
466c0c050c5SMichael Chan __le32 rx_tpa_start_cmp_flags2;
467c0c050c5SMichael Chan #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
468c0c050c5SMichael Chan #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
469c0c050c5SMichael Chan #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
470c0c050c5SMichael Chan #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
47194758f8dSMichael Chan #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
472218a8a71SMichael Chan #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID (0x1 << 9)
473218a8a71SMichael Chan #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT (0x3 << 10)
474218a8a71SMichael Chan #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT 10
47513d2d3d3SMichael Chan #define RX_TPA_START_CMP_V3_FLAGS2_T_IP_TYPE (0x1 << 10)
47613d2d3d3SMichael Chan #define RX_TPA_START_CMP_V3_FLAGS2_AGG_GRO (0x1 << 11)
477218a8a71SMichael Chan #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL (0xffff << 16)
478218a8a71SMichael Chan #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT 16
479c0c050c5SMichael Chan
480c0c050c5SMichael Chan __le32 rx_tpa_start_cmp_metadata;
481c0c050c5SMichael Chan __le32 rx_tpa_start_cmp_cfa_code_v2;
482c0c050c5SMichael Chan #define RX_TPA_START_CMP_V2 (0x1 << 0)
483218a8a71SMichael Chan #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
484218a8a71SMichael Chan #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT 1
485218a8a71SMichael Chan #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
486218a8a71SMichael Chan #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
487218a8a71SMichael Chan #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
488c0c050c5SMichael Chan #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
489c0c050c5SMichael Chan #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
49013d2d3d3SMichael Chan #define RX_TPA_START_CMP_METADATA0_TCI_MASK (0xffff << 16)
49113d2d3d3SMichael Chan #define RX_TPA_START_CMP_METADATA0_VID_MASK (0x0fff << 16)
49213d2d3d3SMichael Chan #define RX_TPA_START_CMP_METADATA0_SFT 16
49394758f8dSMichael Chan __le32 rx_tpa_start_cmp_hdr_info;
494c0c050c5SMichael Chan };
495c0c050c5SMichael Chan
496ee5c7fb3SSathya Perla #define TPA_START_CFA_CODE(rx_tpa_start) \
497ee5c7fb3SSathya Perla ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
498ee5c7fb3SSathya Perla RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
499ee5c7fb3SSathya Perla
50050f011b6SMichael Chan #define TPA_START_IS_IPV6(rx_tpa_start) \
50150f011b6SMichael Chan (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \
50250f011b6SMichael Chan cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
50350f011b6SMichael Chan
504218a8a71SMichael Chan #define TPA_START_ERROR_CODE(rx_tpa_start) \
505218a8a71SMichael Chan ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
506218a8a71SMichael Chan RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >> \
507218a8a71SMichael Chan RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
508218a8a71SMichael Chan
50913d2d3d3SMichael Chan #define TPA_START_METADATA0_TCI(rx_tpa_start) \
51013d2d3d3SMichael Chan ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
51113d2d3d3SMichael Chan RX_TPA_START_CMP_METADATA0_TCI_MASK) >> \
51213d2d3d3SMichael Chan RX_TPA_START_CMP_METADATA0_SFT)
51313d2d3d3SMichael Chan
514c0c050c5SMichael Chan struct rx_tpa_end_cmp {
515c0c050c5SMichael Chan __le32 rx_tpa_end_cmp_len_flags_type;
516c0c050c5SMichael Chan #define RX_TPA_END_CMP_TYPE (0x3f << 0)
517c0c050c5SMichael Chan #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
518c0c050c5SMichael Chan #define RX_TPA_END_CMP_FLAGS_SHIFT 6
519c0c050c5SMichael Chan #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
520c0c050c5SMichael Chan #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
521c0c050c5SMichael Chan #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
522c0c050c5SMichael Chan #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
523c0c050c5SMichael Chan #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
524c0c050c5SMichael Chan #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
525c0c050c5SMichael Chan #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
526c0c050c5SMichael Chan #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
527c0c050c5SMichael Chan #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
528c0c050c5SMichael Chan #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
529c0c050c5SMichael Chan #define RX_TPA_END_CMP_LEN (0xffff << 16)
530c0c050c5SMichael Chan #define RX_TPA_END_CMP_LEN_SHIFT 16
531c0c050c5SMichael Chan
532c0c050c5SMichael Chan u32 rx_tpa_end_cmp_opaque;
533c0c050c5SMichael Chan __le32 rx_tpa_end_cmp_misc_v1;
534c0c050c5SMichael Chan #define RX_TPA_END_CMP_V1 (0x1 << 0)
535c0c050c5SMichael Chan #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
536c0c050c5SMichael Chan #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
537c0c050c5SMichael Chan #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
538c0c050c5SMichael Chan #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
539c0c050c5SMichael Chan #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
540c0c050c5SMichael Chan #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
541c0c050c5SMichael Chan #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
542c0c050c5SMichael Chan #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
543218a8a71SMichael Chan #define RX_TPA_END_CMP_AGG_ID_P5 (0xffff << 16)
544218a8a71SMichael Chan #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5 16
545c0c050c5SMichael Chan
546c0c050c5SMichael Chan __le32 rx_tpa_end_cmp_tsdelta;
547c0c050c5SMichael Chan #define RX_TPA_END_GRO_TS (0x1 << 31)
548c0c050c5SMichael Chan };
549c0c050c5SMichael Chan
550c0c050c5SMichael Chan #define TPA_END_AGG_ID(rx_tpa_end) \
551c0c050c5SMichael Chan ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
552c0c050c5SMichael Chan RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
553c0c050c5SMichael Chan
554218a8a71SMichael Chan #define TPA_END_AGG_ID_P5(rx_tpa_end) \
555218a8a71SMichael Chan ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
556218a8a71SMichael Chan RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
557218a8a71SMichael Chan
558218a8a71SMichael Chan #define TPA_END_PAYLOAD_OFF(rx_tpa_end) \
559218a8a71SMichael Chan ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
560218a8a71SMichael Chan RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
561218a8a71SMichael Chan
562218a8a71SMichael Chan #define TPA_END_AGG_BUFS(rx_tpa_end) \
563218a8a71SMichael Chan ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
564218a8a71SMichael Chan RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
565218a8a71SMichael Chan
566c0c050c5SMichael Chan #define TPA_END_TPA_SEGS(rx_tpa_end) \
567c0c050c5SMichael Chan ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
568c0c050c5SMichael Chan RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
569c0c050c5SMichael Chan
570c0c050c5SMichael Chan #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
571c0c050c5SMichael Chan cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
572c0c050c5SMichael Chan RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
573c0c050c5SMichael Chan
574c0c050c5SMichael Chan #define TPA_END_GRO(rx_tpa_end) \
575c0c050c5SMichael Chan ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
576c0c050c5SMichael Chan RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
577c0c050c5SMichael Chan
578c0c050c5SMichael Chan #define TPA_END_GRO_TS(rx_tpa_end) \
579a58a3e68SMichael Chan (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
580a58a3e68SMichael Chan cpu_to_le32(RX_TPA_END_GRO_TS)))
581c0c050c5SMichael Chan
582c0c050c5SMichael Chan struct rx_tpa_end_cmp_ext {
583c0c050c5SMichael Chan __le32 rx_tpa_end_cmp_dup_acks;
584c0c050c5SMichael Chan #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
585218a8a71SMichael Chan #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5 (0xff << 16)
586218a8a71SMichael Chan #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5 16
587218a8a71SMichael Chan #define RX_TPA_END_CMP_AGG_BUFS_P5 (0xff << 24)
588218a8a71SMichael Chan #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5 24
589c0c050c5SMichael Chan
590c0c050c5SMichael Chan __le32 rx_tpa_end_cmp_seg_len;
591c0c050c5SMichael Chan #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
592c0c050c5SMichael Chan
593c0c050c5SMichael Chan __le32 rx_tpa_end_cmp_errors_v2;
594c0c050c5SMichael Chan #define RX_TPA_END_CMP_V2 (0x1 << 0)
59569c149e2SMichael Chan #define RX_TPA_END_CMP_ERRORS (0x3 << 1)
596218a8a71SMichael Chan #define RX_TPA_END_CMP_ERRORS_P5 (0x7 << 1)
597c0c050c5SMichael Chan #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
598218a8a71SMichael Chan #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
599218a8a71SMichael Chan #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
600218a8a71SMichael Chan #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
601218a8a71SMichael Chan #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR (0x4 << 1)
602218a8a71SMichael Chan #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
603c0c050c5SMichael Chan
604c0c050c5SMichael Chan u32 rx_tpa_end_cmp_start_opaque;
605c0c050c5SMichael Chan };
606c0c050c5SMichael Chan
60769c149e2SMichael Chan #define TPA_END_ERRORS(rx_tpa_end_ext) \
60869c149e2SMichael Chan ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
60969c149e2SMichael Chan cpu_to_le32(RX_TPA_END_CMP_ERRORS))
61069c149e2SMichael Chan
611218a8a71SMichael Chan #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext) \
612218a8a71SMichael Chan ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
613218a8a71SMichael Chan RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >> \
614218a8a71SMichael Chan RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
615218a8a71SMichael Chan
616218a8a71SMichael Chan #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext) \
617218a8a71SMichael Chan ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
618218a8a71SMichael Chan RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
619218a8a71SMichael Chan
620acfb50e4SVasundhara Volam #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \
621acfb50e4SVasundhara Volam (((data1) & \
622acfb50e4SVasundhara Volam ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
623acfb50e4SVasundhara Volam ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
624acfb50e4SVasundhara Volam
6258f6c5e4dSEdwin Peer #define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1) \
6268f6c5e4dSEdwin Peer (((data1) & \
6278f6c5e4dSEdwin Peer ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
6288f6c5e4dSEdwin Peer ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION)
6298f6c5e4dSEdwin Peer
630aadb0b1aSEdwin Peer #define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2) \
631aadb0b1aSEdwin Peer ((data2) & \
632aadb0b1aSEdwin Peer ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK)
633aadb0b1aSEdwin Peer
6347e914027SMichael Chan #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \
6357e914027SMichael Chan !!((data1) & \
6367e914027SMichael Chan ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
6377e914027SMichael Chan
6387e914027SMichael Chan #define EVENT_DATA1_RECOVERY_ENABLED(data1) \
6397e914027SMichael Chan !!((data1) & \
6407e914027SMichael Chan ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
6417e914027SMichael Chan
642abf90ac2SPavan Chebbi #define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \
643abf90ac2SPavan Chebbi (((data1) & \
644abf90ac2SPavan Chebbi ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\
645abf90ac2SPavan Chebbi ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT)
646abf90ac2SPavan Chebbi
647abf90ac2SPavan Chebbi #define BNXT_EVENT_INVALID_SIGNAL_DATA(data2) \
648abf90ac2SPavan Chebbi (((data2) & \
649abf90ac2SPavan Chebbi ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >>\
650abf90ac2SPavan Chebbi ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT)
651abf90ac2SPavan Chebbi
652e38287b7SMichael Chan struct nqe_cn {
653e38287b7SMichael Chan __le16 type;
654e38287b7SMichael Chan #define NQ_CN_TYPE_MASK 0x3fUL
655e38287b7SMichael Chan #define NQ_CN_TYPE_SFT 0
656e38287b7SMichael Chan #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
657e38287b7SMichael Chan #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
658a432a45bSMichael Chan #define NQ_CN_TOGGLE_MASK 0xc0UL
659a432a45bSMichael Chan #define NQ_CN_TOGGLE_SFT 6
660e38287b7SMichael Chan __le16 reserved16;
661e38287b7SMichael Chan __le32 cq_handle_low;
662e38287b7SMichael Chan __le32 v;
663e38287b7SMichael Chan #define NQ_CN_V 0x1UL
664e38287b7SMichael Chan __le32 cq_handle_high;
665e38287b7SMichael Chan };
666e38287b7SMichael Chan
6679c0b06deSMichael Chan #define BNXT_NQ_HDL_IDX_MASK 0x00ffffff
6689c0b06deSMichael Chan #define BNXT_NQ_HDL_TYPE_MASK 0xff000000
6699c0b06deSMichael Chan #define BNXT_NQ_HDL_TYPE_SHIFT 24
6709c0b06deSMichael Chan #define BNXT_NQ_HDL_TYPE_RX 0x00
6719c0b06deSMichael Chan #define BNXT_NQ_HDL_TYPE_TX 0x01
6729c0b06deSMichael Chan
6739c0b06deSMichael Chan #define BNXT_NQ_HDL_IDX(hdl) ((hdl) & BNXT_NQ_HDL_IDX_MASK)
6749c0b06deSMichael Chan #define BNXT_NQ_HDL_TYPE(hdl) (((hdl) & BNXT_NQ_HDL_TYPE_MASK) >> \
6759c0b06deSMichael Chan BNXT_NQ_HDL_TYPE_SHIFT)
6769c0b06deSMichael Chan
6779c0b06deSMichael Chan #define BNXT_SET_NQ_HDL(cpr) \
6789c0b06deSMichael Chan (((cpr)->cp_ring_type << BNXT_NQ_HDL_TYPE_SHIFT) | (cpr)->cp_idx)
6799c0b06deSMichael Chan
680a432a45bSMichael Chan #define NQE_CN_TYPE(type) ((type) & NQ_CN_TYPE_MASK)
681a432a45bSMichael Chan #define NQE_CN_TOGGLE(type) (((type) & NQ_CN_TOGGLE_MASK) >> \
682a432a45bSMichael Chan NQ_CN_TOGGLE_SFT)
683a432a45bSMichael Chan
684c0c050c5SMichael Chan #define DB_IDX_MASK 0xffffff
685c0c050c5SMichael Chan #define DB_IDX_VALID (0x1 << 26)
686c0c050c5SMichael Chan #define DB_IRQ_DIS (0x1 << 27)
687c0c050c5SMichael Chan #define DB_KEY_TX (0x0 << 28)
688c0c050c5SMichael Chan #define DB_KEY_RX (0x1 << 28)
689c0c050c5SMichael Chan #define DB_KEY_CP (0x2 << 28)
690c0c050c5SMichael Chan #define DB_KEY_ST (0x3 << 28)
691c0c050c5SMichael Chan #define DB_KEY_TX_PUSH (0x4 << 28)
692c0c050c5SMichael Chan #define DB_LONG_TX_PUSH (0x2 << 24)
693c0c050c5SMichael Chan
694e4060d30SMichael Chan #define BNXT_MIN_ROCE_CP_RINGS 2
695e4060d30SMichael Chan #define BNXT_MIN_ROCE_STAT_CTXS 1
696e4060d30SMichael Chan
697e38287b7SMichael Chan /* 64-bit doorbell */
698e38287b7SMichael Chan #define DBR_INDEX_MASK 0x0000000000ffffffULL
699a432a45bSMichael Chan #define DBR_EPOCH_MASK 0x01000000UL
700a432a45bSMichael Chan #define DBR_EPOCH_SFT 24
701a432a45bSMichael Chan #define DBR_TOGGLE_MASK 0x06000000UL
702a432a45bSMichael Chan #define DBR_TOGGLE_SFT 25
703e38287b7SMichael Chan #define DBR_XID_MASK 0x000fffff00000000ULL
704e38287b7SMichael Chan #define DBR_XID_SFT 32
705e38287b7SMichael Chan #define DBR_PATH_L2 (0x1ULL << 56)
706a432a45bSMichael Chan #define DBR_VALID (0x1ULL << 58)
707e38287b7SMichael Chan #define DBR_TYPE_SQ (0x0ULL << 60)
708e38287b7SMichael Chan #define DBR_TYPE_RQ (0x1ULL << 60)
709e38287b7SMichael Chan #define DBR_TYPE_SRQ (0x2ULL << 60)
710e38287b7SMichael Chan #define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
711e38287b7SMichael Chan #define DBR_TYPE_CQ (0x4ULL << 60)
712e38287b7SMichael Chan #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
713e38287b7SMichael Chan #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
714e38287b7SMichael Chan #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
715e38287b7SMichael Chan #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
716e38287b7SMichael Chan #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
717e38287b7SMichael Chan #define DBR_TYPE_NQ (0xaULL << 60)
718e38287b7SMichael Chan #define DBR_TYPE_NQ_ARM (0xbULL << 60)
719a432a45bSMichael Chan #define DBR_TYPE_NQ_MASK (0xeULL << 60)
720e38287b7SMichael Chan #define DBR_TYPE_NULL (0xfULL << 60)
721e38287b7SMichael Chan
722ebdf73dcSMichael Chan #define DB_PF_OFFSET_P5 0x10000
723ebdf73dcSMichael Chan #define DB_VF_OFFSET_P5 0x4000
724ebdf73dcSMichael Chan
725c0c050c5SMichael Chan #define INVALID_HW_RING_ID ((u16)-1)
726c0c050c5SMichael Chan
727c0c050c5SMichael Chan /* The hardware supports certain page sizes. Use the supported page sizes
728c0c050c5SMichael Chan * to allocate the rings.
729c0c050c5SMichael Chan */
730c0c050c5SMichael Chan #if (PAGE_SHIFT < 12)
731c0c050c5SMichael Chan #define BNXT_PAGE_SHIFT 12
732c0c050c5SMichael Chan #elif (PAGE_SHIFT <= 13)
733c0c050c5SMichael Chan #define BNXT_PAGE_SHIFT PAGE_SHIFT
734c0c050c5SMichael Chan #elif (PAGE_SHIFT < 16)
735c0c050c5SMichael Chan #define BNXT_PAGE_SHIFT 13
736c0c050c5SMichael Chan #else
737c0c050c5SMichael Chan #define BNXT_PAGE_SHIFT 16
738c0c050c5SMichael Chan #endif
739c0c050c5SMichael Chan
740c0c050c5SMichael Chan #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
741c0c050c5SMichael Chan
7422839f28bSMichael Chan /* The RXBD length is 16-bit so we can only support page sizes < 64K */
7432839f28bSMichael Chan #if (PAGE_SHIFT > 15)
7442839f28bSMichael Chan #define BNXT_RX_PAGE_SHIFT 15
7452839f28bSMichael Chan #else
7462839f28bSMichael Chan #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
7472839f28bSMichael Chan #endif
7482839f28bSMichael Chan
7492839f28bSMichael Chan #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
7502839f28bSMichael Chan
751c61fb99cSMichael Chan #define BNXT_MAX_MTU 9500
7521abeacc1SMichael Chan
7531abeacc1SMichael Chan /* First RX buffer page in XDP multi-buf mode
7541abeacc1SMichael Chan *
7551abeacc1SMichael Chan * +-------------------------------------------------------------------------+
7561abeacc1SMichael Chan * | XDP_PACKET_HEADROOM | bp->rx_buf_use_size | skb_shared_info|
7571abeacc1SMichael Chan * | (bp->rx_dma_offset) | | |
7581abeacc1SMichael Chan * +-------------------------------------------------------------------------+
7591abeacc1SMichael Chan */
7601abeacc1SMichael Chan #define BNXT_MAX_PAGE_MODE_MTU_SBUF \
761c6d30e83SMichael Chan ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
762b231c3f3SAndy Gospodarek XDP_PACKET_HEADROOM)
763b231c3f3SAndy Gospodarek #define BNXT_MAX_PAGE_MODE_MTU \
7641abeacc1SMichael Chan (BNXT_MAX_PAGE_MODE_MTU_SBUF - \
7651abeacc1SMichael Chan SKB_DATA_ALIGN((unsigned int)sizeof(struct skb_shared_info)))
766c61fb99cSMichael Chan
7674ffcd582SMichael Chan #define BNXT_MIN_PKT_SIZE 52
768c0c050c5SMichael Chan
76951dd55b5SMichael Chan #define BNXT_DEFAULT_RX_RING_SIZE 511
77051dd55b5SMichael Chan #define BNXT_DEFAULT_TX_RING_SIZE 511
771c0c050c5SMichael Chan
772c0c050c5SMichael Chan #define MAX_TPA 64
77379632e9bSMichael Chan #define MAX_TPA_P5 256
774ec4d8e7cSMichael Chan #define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1)
77579632e9bSMichael Chan #define MAX_TPA_SEGS_P5 0x3f
776c0c050c5SMichael Chan
777d0a42d6fSMichael Chan #if (BNXT_PAGE_SHIFT == 16)
778c1129b51SMichael Chan #define MAX_RX_PAGES_AGG_ENA 1
779c1129b51SMichael Chan #define MAX_RX_PAGES 4
780d0a42d6fSMichael Chan #define MAX_RX_AGG_PAGES 4
781d0a42d6fSMichael Chan #define MAX_TX_PAGES 1
782c1129b51SMichael Chan #define MAX_CP_PAGES 16
783d0a42d6fSMichael Chan #else
784c1129b51SMichael Chan #define MAX_RX_PAGES_AGG_ENA 8
785c1129b51SMichael Chan #define MAX_RX_PAGES 32
786c0c050c5SMichael Chan #define MAX_RX_AGG_PAGES 32
787c0c050c5SMichael Chan #define MAX_TX_PAGES 8
788c1129b51SMichael Chan #define MAX_CP_PAGES 128
789d0a42d6fSMichael Chan #endif
790c0c050c5SMichael Chan
791c0c050c5SMichael Chan #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
792c0c050c5SMichael Chan #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
793c0c050c5SMichael Chan #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
794c0c050c5SMichael Chan
795c0c050c5SMichael Chan #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
796c0c050c5SMichael Chan #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
797c0c050c5SMichael Chan
798c0c050c5SMichael Chan #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
799c0c050c5SMichael Chan
800c0c050c5SMichael Chan #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
801c0c050c5SMichael Chan #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
802c0c050c5SMichael Chan
803c0c050c5SMichael Chan #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
804c0c050c5SMichael Chan
805c0c050c5SMichael Chan #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
806c1129b51SMichael Chan #define BNXT_MAX_RX_DESC_CNT_JUM_ENA (RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1)
807c0c050c5SMichael Chan #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
808c0c050c5SMichael Chan #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
809c0c050c5SMichael Chan
8105bed8b07SMichael Chan /* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1. We need one extra
8115bed8b07SMichael Chan * BD because the first TX BD is always a long BD.
8125bed8b07SMichael Chan */
8135bed8b07SMichael Chan #define BNXT_MIN_TX_DESC_CNT (MAX_SKB_FRAGS + 2)
8145bed8b07SMichael Chan
815c09d2267SMichael Chan #define RX_RING(bp, x) (((x) & (bp)->rx_ring_mask) >> (BNXT_PAGE_SHIFT - 4))
816c09d2267SMichael Chan #define RX_AGG_RING(bp, x) (((x) & (bp)->rx_agg_ring_mask) >> \
817c09d2267SMichael Chan (BNXT_PAGE_SHIFT - 4))
818c0c050c5SMichael Chan #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
819c0c050c5SMichael Chan
8206d1add95SMichael Chan #define TX_RING(bp, x) (((x) & (bp)->tx_ring_mask) >> (BNXT_PAGE_SHIFT - 4))
821c0c050c5SMichael Chan #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
822c0c050c5SMichael Chan
823c0c050c5SMichael Chan #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
824c0c050c5SMichael Chan #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
825c0c050c5SMichael Chan
826c0c050c5SMichael Chan #define TX_CMP_VALID(txcmp, raw_cons) \
827c0c050c5SMichael Chan (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
828c0c050c5SMichael Chan !((raw_cons) & bp->cp_bit))
829c0c050c5SMichael Chan
830c0c050c5SMichael Chan #define RX_CMP_VALID(rxcmp1, raw_cons) \
831c0c050c5SMichael Chan (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
832c0c050c5SMichael Chan !((raw_cons) & bp->cp_bit))
833c0c050c5SMichael Chan
834c0c050c5SMichael Chan #define RX_AGG_CMP_VALID(agg, raw_cons) \
835c0c050c5SMichael Chan (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
836c0c050c5SMichael Chan !((raw_cons) & bp->cp_bit))
837c0c050c5SMichael Chan
8380fcec985SMichael Chan #define NQ_CMP_VALID(nqcmp, raw_cons) \
8390fcec985SMichael Chan (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
8400fcec985SMichael Chan
841c0c050c5SMichael Chan #define TX_CMP_TYPE(txcmp) \
842c0c050c5SMichael Chan (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
843c0c050c5SMichael Chan
844c0c050c5SMichael Chan #define RX_CMP_TYPE(rxcmp) \
845c0c050c5SMichael Chan (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
846c0c050c5SMichael Chan
847c09d2267SMichael Chan #define RING_RX(bp, idx) ((idx) & (bp)->rx_ring_mask)
848c09d2267SMichael Chan #define NEXT_RX(idx) ((idx) + 1)
849c0c050c5SMichael Chan
850c09d2267SMichael Chan #define RING_RX_AGG(bp, idx) ((idx) & (bp)->rx_agg_ring_mask)
851c09d2267SMichael Chan #define NEXT_RX_AGG(idx) ((idx) + 1)
852c0c050c5SMichael Chan
8536d1add95SMichael Chan #define RING_TX(bp, idx) ((idx) & (bp)->tx_ring_mask)
8546d1add95SMichael Chan #define NEXT_TX(idx) ((idx) + 1)
855c0c050c5SMichael Chan
856c0c050c5SMichael Chan #define ADV_RAW_CMP(idx, n) ((idx) + (n))
857c0c050c5SMichael Chan #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
858c0c050c5SMichael Chan #define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
859c0c050c5SMichael Chan #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
860c0c050c5SMichael Chan
861ff4fe81dSMichael Chan #define DFLT_HWRM_CMD_TIMEOUT 500
862760b6d33SVenkat Duvvuru
8634e5dbbdaSMichael Chan #define BNXT_RX_EVENT 1
8644e5dbbdaSMichael Chan #define BNXT_AGG_EVENT 2
86538413406SMichael Chan #define BNXT_TX_EVENT 4
866f18c2b77SAndy Gospodarek #define BNXT_REDIRECT_EVENT 8
8677f0a168bSMichael Chan #define BNXT_TX_CMP_EVENT 0x10
8684e5dbbdaSMichael Chan
869c0c050c5SMichael Chan struct bnxt_sw_tx_bd {
870f18c2b77SAndy Gospodarek union {
871c0c050c5SMichael Chan struct sk_buff *skb;
872f18c2b77SAndy Gospodarek struct xdp_frame *xdpf;
873f18c2b77SAndy Gospodarek };
874c0c050c5SMichael Chan DEFINE_DMA_UNMAP_ADDR(mapping);
875f18c2b77SAndy Gospodarek DEFINE_DMA_UNMAP_LEN(len);
876a7559bc8SAndy Gospodarek struct page *page;
877449da975SMichael Chan u8 is_ts_pkt;
878c0c050c5SMichael Chan u8 is_push;
879c1ba92a8SMichael Chan u8 action;
880c0c050c5SMichael Chan unsigned short nr_frags;
8818aa2a79eSPavan Chebbi union {
88238413406SMichael Chan u16 rx_prod;
8838aa2a79eSPavan Chebbi u16 txts_prod;
8848aa2a79eSPavan Chebbi };
88538413406SMichael Chan };
886c0c050c5SMichael Chan
887c0c050c5SMichael Chan struct bnxt_sw_rx_bd {
8886bb19474SMichael Chan void *data;
8896bb19474SMichael Chan u8 *data_ptr;
89011cd119dSMichael Chan dma_addr_t mapping;
891c0c050c5SMichael Chan };
892c0c050c5SMichael Chan
893c0c050c5SMichael Chan struct bnxt_sw_rx_agg_bd {
894c0c050c5SMichael Chan struct page *page;
89589d0a06cSMichael Chan unsigned int offset;
896c0c050c5SMichael Chan dma_addr_t mapping;
897c0c050c5SMichael Chan };
898c0c050c5SMichael Chan
8996fe19886SMichael Chan struct bnxt_ring_mem_info {
900c0c050c5SMichael Chan int nr_pages;
901c0c050c5SMichael Chan int page_size;
9024f49b2b8SMichael Chan u16 flags;
90366cca20aSMichael Chan #define BNXT_RMEM_VALID_PTE_FLAG 1
90466cca20aSMichael Chan #define BNXT_RMEM_RING_PTE_FLAG 2
9054f49b2b8SMichael Chan #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4
9064f49b2b8SMichael Chan
9074f49b2b8SMichael Chan u16 depth;
90876087d99SMichael Chan struct bnxt_ctx_mem_type *ctx_mem;
90966cca20aSMichael Chan
910c0c050c5SMichael Chan void **pg_arr;
911c0c050c5SMichael Chan dma_addr_t *dma_arr;
912c0c050c5SMichael Chan
913c0c050c5SMichael Chan __le64 *pg_tbl;
914c0c050c5SMichael Chan dma_addr_t pg_tbl_map;
915c0c050c5SMichael Chan
916c0c050c5SMichael Chan int vmem_size;
917c0c050c5SMichael Chan void **vmem;
9186fe19886SMichael Chan };
9196fe19886SMichael Chan
9206fe19886SMichael Chan struct bnxt_ring_struct {
9216fe19886SMichael Chan struct bnxt_ring_mem_info ring_mem;
922c0c050c5SMichael Chan
923c0c050c5SMichael Chan u16 fw_ring_id; /* Ring id filled by Chimp FW */
9249899bb59SMichael Chan union {
9259899bb59SMichael Chan u16 grp_idx;
9269899bb59SMichael Chan u16 map_idx; /* Used by cmpl rings */
9279899bb59SMichael Chan };
92823aefdd7SMichael Chan u32 handle;
929c0c050c5SMichael Chan u8 queue_id;
930c0c050c5SMichael Chan };
931c0c050c5SMichael Chan
932c0c050c5SMichael Chan struct tx_push_bd {
933c0c050c5SMichael Chan __le32 doorbell;
9344419dbe6SMichael Chan __le32 tx_bd_len_flags_type;
9354419dbe6SMichael Chan u32 tx_bd_opaque;
936c0c050c5SMichael Chan struct tx_bd_ext txbd2;
937c0c050c5SMichael Chan };
938c0c050c5SMichael Chan
9394419dbe6SMichael Chan struct tx_push_buffer {
9404419dbe6SMichael Chan struct tx_push_bd push_bd;
9414419dbe6SMichael Chan u32 data[25];
9424419dbe6SMichael Chan };
9434419dbe6SMichael Chan
944697197e5SMichael Chan struct bnxt_db_info {
945697197e5SMichael Chan void __iomem *doorbell;
946697197e5SMichael Chan union {
947697197e5SMichael Chan u64 db_key64;
948697197e5SMichael Chan u32 db_key32;
949697197e5SMichael Chan };
950b9e0c47eSMichael Chan u32 db_ring_mask;
951a432a45bSMichael Chan u32 db_epoch_mask;
952a432a45bSMichael Chan u8 db_epoch_shift;
953697197e5SMichael Chan };
954697197e5SMichael Chan
955a432a45bSMichael Chan #define DB_EPOCH(db, idx) (((idx) & (db)->db_epoch_mask) << \
956a432a45bSMichael Chan ((db)->db_epoch_shift))
957a432a45bSMichael Chan
958a432a45bSMichael Chan #define DB_TOGGLE(tgl) ((tgl) << DBR_TOGGLE_SFT)
959a432a45bSMichael Chan
960a432a45bSMichael Chan #define DB_RING_IDX(db, idx) (((idx) & (db)->db_ring_mask) | \
961a432a45bSMichael Chan DB_EPOCH(db, idx))
962b9e0c47eSMichael Chan
963c0c050c5SMichael Chan struct bnxt_tx_ring_info {
964b6ab4b01SMichael Chan struct bnxt_napi *bnapi;
9657845b8dfSMichael Chan struct bnxt_cp_ring_info *tx_cpr;
966c0c050c5SMichael Chan u16 tx_prod;
967c0c050c5SMichael Chan u16 tx_cons;
9687f0a168bSMichael Chan u16 tx_hw_cons;
969a960dec9SMichael Chan u16 txq_index;
9705a3c585fSMichael Chan u8 tx_napi_idx;
971e8d8c5d8SJakub Kicinski u8 kick_pending;
972697197e5SMichael Chan struct bnxt_db_info tx_db;
973c0c050c5SMichael Chan
974c0c050c5SMichael Chan struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
975c0c050c5SMichael Chan struct bnxt_sw_tx_bd *tx_buf_ring;
976c0c050c5SMichael Chan
977c0c050c5SMichael Chan dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
978c0c050c5SMichael Chan
9794419dbe6SMichael Chan struct tx_push_buffer *tx_push;
980c0c050c5SMichael Chan dma_addr_t tx_push_mapping;
9814419dbe6SMichael Chan __le64 data_mapping;
982c0c050c5SMichael Chan
983c0c050c5SMichael Chan #define BNXT_DEV_STATE_CLOSING 0x1
984c0c050c5SMichael Chan u32 dev_state;
985c0c050c5SMichael Chan
986c0c050c5SMichael Chan struct bnxt_ring_struct tx_ring_struct;
9874f81def2SPavan Chebbi /* Synchronize simultaneous xdp_xmit on same ring */
9884f81def2SPavan Chebbi spinlock_t xdp_tx_lock;
989c0c050c5SMichael Chan };
990c0c050c5SMichael Chan
99174706afaSMichael Chan #define BNXT_LEGACY_COAL_CMPL_PARAMS \
99274706afaSMichael Chan (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \
99374706afaSMichael Chan RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \
99474706afaSMichael Chan RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \
99574706afaSMichael Chan RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \
99674706afaSMichael Chan RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \
99774706afaSMichael Chan RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
99874706afaSMichael Chan RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \
99974706afaSMichael Chan RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
100074706afaSMichael Chan RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
100174706afaSMichael Chan
100274706afaSMichael Chan #define BNXT_COAL_CMPL_ENABLES \
100374706afaSMichael Chan (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
100474706afaSMichael Chan RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
100574706afaSMichael Chan RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
100674706afaSMichael Chan RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
100774706afaSMichael Chan
100874706afaSMichael Chan #define BNXT_COAL_CMPL_MIN_TMR_ENABLE \
100974706afaSMichael Chan RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
101074706afaSMichael Chan
101174706afaSMichael Chan #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \
101274706afaSMichael Chan RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
101374706afaSMichael Chan
101474706afaSMichael Chan struct bnxt_coal_cap {
101574706afaSMichael Chan u32 cmpl_params;
101674706afaSMichael Chan u32 nq_params;
101774706afaSMichael Chan u16 num_cmpl_dma_aggr_max;
101874706afaSMichael Chan u16 num_cmpl_dma_aggr_during_int_max;
101974706afaSMichael Chan u16 cmpl_aggr_dma_tmr_max;
102074706afaSMichael Chan u16 cmpl_aggr_dma_tmr_during_int_max;
102174706afaSMichael Chan u16 int_lat_tmr_min_max;
102274706afaSMichael Chan u16 int_lat_tmr_max_max;
102374706afaSMichael Chan u16 num_cmpl_aggr_int_max;
102474706afaSMichael Chan u16 timer_units;
102574706afaSMichael Chan };
102674706afaSMichael Chan
10276a8788f2SAndy Gospodarek struct bnxt_coal {
10286a8788f2SAndy Gospodarek u16 coal_ticks;
10296a8788f2SAndy Gospodarek u16 coal_ticks_irq;
10306a8788f2SAndy Gospodarek u16 coal_bufs;
10316a8788f2SAndy Gospodarek u16 coal_bufs_irq;
10326a8788f2SAndy Gospodarek /* RING_IDLE enabled when coal ticks < idle_thresh */
10336a8788f2SAndy Gospodarek u16 idle_thresh;
10346a8788f2SAndy Gospodarek u8 bufs_per_record;
10356a8788f2SAndy Gospodarek u8 budget;
1036df78ea22SMichael Chan u16 flags;
10376a8788f2SAndy Gospodarek };
10386a8788f2SAndy Gospodarek
1039c0c050c5SMichael Chan struct bnxt_tpa_info {
10406bb19474SMichael Chan void *data;
10416bb19474SMichael Chan u8 *data_ptr;
1042c0c050c5SMichael Chan dma_addr_t mapping;
1043c0c050c5SMichael Chan u16 len;
1044c0c050c5SMichael Chan unsigned short gso_type;
1045c0c050c5SMichael Chan u32 flags2;
1046c0c050c5SMichael Chan u32 metadata;
1047c0c050c5SMichael Chan enum pkt_hash_types hash_type;
1048c0c050c5SMichael Chan u32 rss_hash;
104994758f8dSMichael Chan u32 hdr_info;
105094758f8dSMichael Chan
105194758f8dSMichael Chan #define BNXT_TPA_L4_SIZE(hdr_info) \
105294758f8dSMichael Chan (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
105394758f8dSMichael Chan
105494758f8dSMichael Chan #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
105594758f8dSMichael Chan (((hdr_info) >> 18) & 0x1ff)
105694758f8dSMichael Chan
105794758f8dSMichael Chan #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
105894758f8dSMichael Chan (((hdr_info) >> 9) & 0x1ff)
105994758f8dSMichael Chan
106094758f8dSMichael Chan #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
106194758f8dSMichael Chan ((hdr_info) & 0x1ff)
10624ab0c6a8SSathya Perla
10634ab0c6a8SSathya Perla u16 cfa_code; /* cfa_code in TPA start compl */
106479632e9bSMichael Chan u8 agg_count;
106539b2e62bSMichael Chan u8 vlan_valid:1;
106639b2e62bSMichael Chan u8 cfa_code_valid:1;
106779632e9bSMichael Chan struct rx_agg_cmp *agg_arr;
1068c0c050c5SMichael Chan };
1069c0c050c5SMichael Chan
1070ec4d8e7cSMichael Chan #define BNXT_AGG_IDX_BMAP_SIZE (MAX_TPA_P5 / BITS_PER_LONG)
1071ec4d8e7cSMichael Chan
1072ec4d8e7cSMichael Chan struct bnxt_tpa_idx_map {
1073ec4d8e7cSMichael Chan u16 agg_id_tbl[1024];
1074ec4d8e7cSMichael Chan unsigned long agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
1075ec4d8e7cSMichael Chan };
1076ec4d8e7cSMichael Chan
1077c0c050c5SMichael Chan struct bnxt_rx_ring_info {
1078b6ab4b01SMichael Chan struct bnxt_napi *bnapi;
10797845b8dfSMichael Chan struct bnxt_cp_ring_info *rx_cpr;
1080c0c050c5SMichael Chan u16 rx_prod;
1081c0c050c5SMichael Chan u16 rx_agg_prod;
1082c0c050c5SMichael Chan u16 rx_sw_agg_prod;
1083376a5b86SMichael Chan u16 rx_next_cons;
1084697197e5SMichael Chan struct bnxt_db_info rx_db;
1085697197e5SMichael Chan struct bnxt_db_info rx_agg_db;
1086c0c050c5SMichael Chan
1087c6d30e83SMichael Chan struct bpf_prog *xdp_prog;
1088c6d30e83SMichael Chan
1089c0c050c5SMichael Chan struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
1090c0c050c5SMichael Chan struct bnxt_sw_rx_bd *rx_buf_ring;
1091c0c050c5SMichael Chan
1092c0c050c5SMichael Chan struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
1093c0c050c5SMichael Chan struct bnxt_sw_rx_agg_bd *rx_agg_ring;
1094c0c050c5SMichael Chan
1095c0c050c5SMichael Chan unsigned long *rx_agg_bmap;
1096c0c050c5SMichael Chan u16 rx_agg_bmap_size;
1097c0c050c5SMichael Chan
1098c0c050c5SMichael Chan dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
1099c0c050c5SMichael Chan dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
1100c0c050c5SMichael Chan
1101c0c050c5SMichael Chan struct bnxt_tpa_info *rx_tpa;
1102ec4d8e7cSMichael Chan struct bnxt_tpa_idx_map *rx_tpa_idx_map;
1103c0c050c5SMichael Chan
1104c0c050c5SMichael Chan struct bnxt_ring_struct rx_ring_struct;
1105c0c050c5SMichael Chan struct bnxt_ring_struct rx_agg_ring_struct;
110696a8604fSJesper Dangaard Brouer struct xdp_rxq_info xdp_rxq;
1107322b87caSAndy Gospodarek struct page_pool *page_pool;
1108c0c050c5SMichael Chan };
1109c0c050c5SMichael Chan
11109d8b5f05SMichael Chan struct bnxt_rx_sw_stats {
11119d8b5f05SMichael Chan u64 rx_l4_csum_errors;
11128a27d4b9SMichael Chan u64 rx_resets;
11139d8b5f05SMichael Chan u64 rx_buf_errors;
1114907fd4a2SJakub Kicinski u64 rx_oom_discards;
111540bedf7cSJakub Kicinski u64 rx_netpoll_discards;
11169d8b5f05SMichael Chan };
11179d8b5f05SMichael Chan
11188becd196SMichael Chan struct bnxt_tx_sw_stats {
11198becd196SMichael Chan u64 tx_resets;
11208becd196SMichael Chan };
11218becd196SMichael Chan
11229d8b5f05SMichael Chan struct bnxt_cmn_sw_stats {
11239d8b5f05SMichael Chan u64 missed_irqs;
11249d8b5f05SMichael Chan };
11259d8b5f05SMichael Chan
11269d8b5f05SMichael Chan struct bnxt_sw_stats {
11279d8b5f05SMichael Chan struct bnxt_rx_sw_stats rx;
11288becd196SMichael Chan struct bnxt_tx_sw_stats tx;
11299d8b5f05SMichael Chan struct bnxt_cmn_sw_stats cmn;
11309d8b5f05SMichael Chan };
11319d8b5f05SMichael Chan
11324c70dbe3SMichael Chan struct bnxt_total_ring_err_stats {
11334c70dbe3SMichael Chan u64 rx_total_l4_csum_errors;
11344c70dbe3SMichael Chan u64 rx_total_resets;
11354c70dbe3SMichael Chan u64 rx_total_buf_errors;
11364c70dbe3SMichael Chan u64 rx_total_oom_discards;
11374c70dbe3SMichael Chan u64 rx_total_netpoll_discards;
11384c70dbe3SMichael Chan u64 rx_total_ring_discards;
11398becd196SMichael Chan u64 tx_total_resets;
11404c70dbe3SMichael Chan u64 tx_total_ring_discards;
11414c70dbe3SMichael Chan u64 total_missed_irqs;
11424c70dbe3SMichael Chan };
11434c70dbe3SMichael Chan
1144177a6cdeSMichael Chan struct bnxt_stats_mem {
1145a37120b2SMichael Chan u64 *sw_stats;
1146a37120b2SMichael Chan u64 *hw_masks;
1147177a6cdeSMichael Chan void *hw_stats;
1148177a6cdeSMichael Chan dma_addr_t hw_stats_map;
1149177a6cdeSMichael Chan int len;
1150177a6cdeSMichael Chan };
1151177a6cdeSMichael Chan
1152c0c050c5SMichael Chan struct bnxt_cp_ring_info {
115350e3ab78SMichael Chan struct bnxt_napi *bnapi;
1154c0c050c5SMichael Chan u32 cp_raw_cons;
1155697197e5SMichael Chan struct bnxt_db_info cp_db;
1156c0c050c5SMichael Chan
11573675b92fSMichael Chan u8 had_work_done:1;
11580fcec985SMichael Chan u8 has_more_work:1;
1159f94471f3SMichael Chan u8 had_nqe_notify:1;
1160d846992eSMichael Chan u8 toggle;
1161f94471f3SMichael Chan
11629c0b06deSMichael Chan u8 cp_ring_type;
11639c0b06deSMichael Chan u8 cp_idx;
11643675b92fSMichael Chan
1165ffd77621SMichael Chan u32 last_cp_raw_cons;
1166ffd77621SMichael Chan
11676a8788f2SAndy Gospodarek struct bnxt_coal rx_ring_coal;
11686a8788f2SAndy Gospodarek u64 rx_packets;
11696a8788f2SAndy Gospodarek u64 rx_bytes;
11706a8788f2SAndy Gospodarek u64 event_ctr;
11716a8788f2SAndy Gospodarek
11728960b389STal Gilboa struct dim dim;
11736a8788f2SAndy Gospodarek
1174e38287b7SMichael Chan union {
117503c74487SMichael Chan struct tx_cmp **cp_desc_ring;
117603c74487SMichael Chan struct nqe_cn **nq_desc_ring;
1177e38287b7SMichael Chan };
1178c0c050c5SMichael Chan
117903c74487SMichael Chan dma_addr_t *cp_desc_mapping;
1180c0c050c5SMichael Chan
1181177a6cdeSMichael Chan struct bnxt_stats_mem stats;
1182c0c050c5SMichael Chan u32 hw_stats_ctx_id;
11839d8b5f05SMichael Chan
1184a75fbb3aSEdwin Peer struct bnxt_sw_stats *sw_stats;
1185c0c050c5SMichael Chan
1186c0c050c5SMichael Chan struct bnxt_ring_struct cp_ring_struct;
1187e38287b7SMichael Chan
1188d1eec614SMichael Chan int cp_ring_count;
1189d1eec614SMichael Chan struct bnxt_cp_ring_info *cp_ring_arr;
1190c0c050c5SMichael Chan };
1191c0c050c5SMichael Chan
11920589a1edSMichael Chan #define BNXT_MAX_QUEUE 8
11930589a1edSMichael Chan #define BNXT_MAX_TXR_PER_NAPI BNXT_MAX_QUEUE
11940589a1edSMichael Chan
11950589a1edSMichael Chan #define bnxt_for_each_napi_tx(iter, bnapi, txr) \
11960589a1edSMichael Chan for (iter = 0, txr = (bnapi)->tx_ring[0]; txr; \
11970589a1edSMichael Chan txr = (iter < BNXT_MAX_TXR_PER_NAPI - 1) ? \
11980589a1edSMichael Chan (bnapi)->tx_ring[++iter] : NULL)
11990589a1edSMichael Chan
1200c0c050c5SMichael Chan struct bnxt_napi {
1201c0c050c5SMichael Chan struct napi_struct napi;
1202c0c050c5SMichael Chan struct bnxt *bp;
1203c0c050c5SMichael Chan
1204c0c050c5SMichael Chan int index;
1205c0c050c5SMichael Chan struct bnxt_cp_ring_info cp_ring;
1206b6ab4b01SMichael Chan struct bnxt_rx_ring_info *rx_ring;
12070589a1edSMichael Chan struct bnxt_tx_ring_info *tx_ring[BNXT_MAX_TXR_PER_NAPI];
1208c0c050c5SMichael Chan
1209fa3e93e8SMichael Chan void (*tx_int)(struct bnxt *, struct bnxt_napi *,
121037b61cdaSJakub Kicinski int budget);
12113675b92fSMichael Chan u8 events;
12122b56b3d9SJakub Kicinski u8 tx_fault:1;
12133675b92fSMichael Chan
1214fa3e93e8SMichael Chan u32 flags;
1215fa3e93e8SMichael Chan #define BNXT_NAPI_FLAG_XDP 0x1
1216fa3e93e8SMichael Chan
1217fa7e2812SMichael Chan bool in_reset;
1218c0c050c5SMichael Chan };
1219c0c050c5SMichael Chan
1220*f77cdee5SEdwin Peer /* "TxRx", 2 hypens, plus maximum integer */
1221*f77cdee5SEdwin Peer #define BNXT_IRQ_NAME_EXTRA 17
1222*f77cdee5SEdwin Peer
1223c0c050c5SMichael Chan struct bnxt_irq {
1224c0c050c5SMichael Chan irq_handler_t handler;
1225c0c050c5SMichael Chan unsigned int vector;
122656f0fd80SVasundhara Volam u8 requested:1;
122756f0fd80SVasundhara Volam u8 have_cpumask:1;
1228*f77cdee5SEdwin Peer char name[IFNAMSIZ + BNXT_IRQ_NAME_EXTRA];
122956f0fd80SVasundhara Volam cpumask_var_t cpu_mask;
1230c0c050c5SMichael Chan };
1231c0c050c5SMichael Chan
1232c0c050c5SMichael Chan #define HWRM_RING_ALLOC_TX 0x1
1233c0c050c5SMichael Chan #define HWRM_RING_ALLOC_RX 0x2
1234c0c050c5SMichael Chan #define HWRM_RING_ALLOC_AGG 0x4
1235c0c050c5SMichael Chan #define HWRM_RING_ALLOC_CMPL 0x8
1236697197e5SMichael Chan #define HWRM_RING_ALLOC_NQ 0x10
1237c0c050c5SMichael Chan
1238c0c050c5SMichael Chan #define INVALID_STATS_CTX_ID -1
1239c0c050c5SMichael Chan
1240c0c050c5SMichael Chan struct bnxt_ring_grp_info {
1241c0c050c5SMichael Chan u16 fw_stats_ctx;
1242c0c050c5SMichael Chan u16 fw_grp_id;
1243c0c050c5SMichael Chan u16 rx_fw_ring_id;
1244c0c050c5SMichael Chan u16 agg_fw_ring_id;
1245c0c050c5SMichael Chan u16 cp_fw_ring_id;
1246c0c050c5SMichael Chan };
1247c0c050c5SMichael Chan
1248ef4ee64eSPavan Chebbi #define BNXT_VNIC_DEFAULT 0
124993e90104SPavan Chebbi #define BNXT_VNIC_NTUPLE 1
1250ef4ee64eSPavan Chebbi
1251c0c050c5SMichael Chan struct bnxt_vnic_info {
1252c0c050c5SMichael Chan u16 fw_vnic_id; /* returned by Chimp during alloc */
125344c6f72aSMichael Chan #define BNXT_MAX_CTX_PER_VNIC 8
125494ce9caaSPrashant Sreedharan u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
1255c0c050c5SMichael Chan u16 fw_l2_ctx_id;
1256f2878cdeSMichael Chan u16 mru;
1257c0c050c5SMichael Chan #define BNXT_MAX_UC_ADDRS 4
12581f6e77cbSMichael Chan struct bnxt_l2_filter *l2_filters[BNXT_MAX_UC_ADDRS];
1259c0c050c5SMichael Chan /* index 0 always dev_addr */
1260c0c050c5SMichael Chan u16 uc_filter_count;
1261c0c050c5SMichael Chan u8 *uc_list;
1262c0c050c5SMichael Chan
1263c0c050c5SMichael Chan u16 *fw_grp_ids;
1264c0c050c5SMichael Chan dma_addr_t rss_table_dma_addr;
1265c0c050c5SMichael Chan __le16 *rss_table;
1266c0c050c5SMichael Chan dma_addr_t rss_hash_key_dma_addr;
1267c0c050c5SMichael Chan u64 *rss_hash_key;
126834370d24SMichael Chan int rss_table_size;
126934370d24SMichael Chan #define BNXT_RSS_TABLE_ENTRIES_P5 64
127034370d24SMichael Chan #define BNXT_RSS_TABLE_SIZE_P5 (BNXT_RSS_TABLE_ENTRIES_P5 * 4)
127134370d24SMichael Chan #define BNXT_RSS_TABLE_MAX_TBL_P5 8
127234370d24SMichael Chan #define BNXT_MAX_RSS_TABLE_SIZE_P5 \
127334370d24SMichael Chan (BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
12741667cbf6SMichael Chan #define BNXT_MAX_RSS_TABLE_ENTRIES_P5 \
12751667cbf6SMichael Chan (BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
127634370d24SMichael Chan
1277c0c050c5SMichael Chan u32 rx_mask;
1278c0c050c5SMichael Chan
1279c0c050c5SMichael Chan u8 *mc_list;
1280c0c050c5SMichael Chan int mc_list_size;
1281c0c050c5SMichael Chan int mc_list_count;
1282c0c050c5SMichael Chan dma_addr_t mc_list_mapping;
1283c0c050c5SMichael Chan #define BNXT_MAX_MC_ADDRS 16
1284c0c050c5SMichael Chan
1285c0c050c5SMichael Chan u32 flags;
1286c0c050c5SMichael Chan #define BNXT_VNIC_RSS_FLAG 1
1287c0c050c5SMichael Chan #define BNXT_VNIC_RFS_FLAG 2
1288c0c050c5SMichael Chan #define BNXT_VNIC_MCAST_FLAG 4
1289c0c050c5SMichael Chan #define BNXT_VNIC_UCAST_FLAG 8
1290ae10ae74SMichael Chan #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
129193e90104SPavan Chebbi #define BNXT_VNIC_NTUPLE_FLAG 0x20
1292fea41bd7SPavan Chebbi #define BNXT_VNIC_RSSCTX_FLAG 0x40
129346e457a4SJakub Kicinski struct ethtool_rxfh_context *rss_ctx;
1294a4c11166SPavan Chebbi u32 vnic_id;
1295c0c050c5SMichael Chan };
1296c0c050c5SMichael Chan
1297fea41bd7SPavan Chebbi struct bnxt_rss_ctx {
1298fea41bd7SPavan Chebbi struct bnxt_vnic_info vnic;
1299fea41bd7SPavan Chebbi u8 index;
1300fea41bd7SPavan Chebbi };
1301fea41bd7SPavan Chebbi
1302fea41bd7SPavan Chebbi #define BNXT_MAX_ETH_RSS_CTX 32
1303b3d0083cSPavan Chebbi #define BNXT_VNIC_ID_INVALID 0xffffffff
1304fea41bd7SPavan Chebbi
1305257bbf45SMichael Chan struct bnxt_hw_rings {
1306257bbf45SMichael Chan int tx;
1307257bbf45SMichael Chan int rx;
1308257bbf45SMichael Chan int grp;
1309257bbf45SMichael Chan int cp;
1310ae8186b2SMichael Chan int cp_p5;
1311257bbf45SMichael Chan int stat;
1312257bbf45SMichael Chan int vnic;
1313438ba39bSPavan Chebbi int rss_ctx;
1314257bbf45SMichael Chan };
1315257bbf45SMichael Chan
13166a4f2947SMichael Chan struct bnxt_hw_resc {
13176a4f2947SMichael Chan u16 min_rsscos_ctxs;
13186a4f2947SMichael Chan u16 max_rsscos_ctxs;
1319438ba39bSPavan Chebbi u16 resv_rsscos_ctxs;
13206a4f2947SMichael Chan u16 min_cp_rings;
13216a4f2947SMichael Chan u16 max_cp_rings;
13226a4f2947SMichael Chan u16 resv_cp_rings;
13236a4f2947SMichael Chan u16 min_tx_rings;
13246a4f2947SMichael Chan u16 max_tx_rings;
13256a4f2947SMichael Chan u16 resv_tx_rings;
1326db4723b3SMichael Chan u16 max_tx_sch_inputs;
13276a4f2947SMichael Chan u16 min_rx_rings;
13286a4f2947SMichael Chan u16 max_rx_rings;
13296a4f2947SMichael Chan u16 resv_rx_rings;
13306a4f2947SMichael Chan u16 min_hw_ring_grps;
13316a4f2947SMichael Chan u16 max_hw_ring_grps;
13326a4f2947SMichael Chan u16 resv_hw_ring_grps;
13336a4f2947SMichael Chan u16 min_l2_ctxs;
13346a4f2947SMichael Chan u16 max_l2_ctxs;
13356a4f2947SMichael Chan u16 min_vnics;
13366a4f2947SMichael Chan u16 max_vnics;
13376a4f2947SMichael Chan u16 resv_vnics;
13386a4f2947SMichael Chan u16 min_stat_ctxs;
13396a4f2947SMichael Chan u16 max_stat_ctxs;
1340780baad4SVasundhara Volam u16 resv_stat_ctxs;
1341f7588cd8SMichael Chan u16 max_nqs;
13426a4f2947SMichael Chan u16 max_irqs;
134375720e63SMichael Chan u16 resv_irqs;
1344f42822f2SMichael Chan u32 max_encap_records;
1345f42822f2SMichael Chan u32 max_decap_records;
1346f42822f2SMichael Chan u32 max_tx_em_flows;
1347f42822f2SMichael Chan u32 max_tx_wm_flows;
1348f42822f2SMichael Chan u32 max_rx_em_flows;
1349f42822f2SMichael Chan u32 max_rx_wm_flows;
13506a4f2947SMichael Chan };
13516a4f2947SMichael Chan
1352c0c050c5SMichael Chan #if defined(CONFIG_BNXT_SRIOV)
1353c0c050c5SMichael Chan struct bnxt_vf_info {
1354c0c050c5SMichael Chan u16 fw_fid;
135591cdda40SVasundhara Volam u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */
135691cdda40SVasundhara Volam u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only
135791cdda40SVasundhara Volam * stored by PF.
135891cdda40SVasundhara Volam */
1359c0c050c5SMichael Chan u16 vlan;
13602a516444SMichael Chan u16 func_qcfg_flags;
1361c0c050c5SMichael Chan u32 flags;
1362c0c050c5SMichael Chan #define BNXT_VF_SPOOFCHK 0x2
1363c0c050c5SMichael Chan #define BNXT_VF_LINK_FORCED 0x4
1364c0c050c5SMichael Chan #define BNXT_VF_LINK_UP 0x8
1365746df139SVasundhara Volam #define BNXT_VF_TRUST 0x10
1366c0c050c5SMichael Chan u32 min_tx_rate;
1367c0c050c5SMichael Chan u32 max_tx_rate;
1368c0c050c5SMichael Chan void *hwrm_cmd_req_addr;
1369c0c050c5SMichael Chan dma_addr_t hwrm_cmd_req_dma_addr;
1370c0c050c5SMichael Chan };
1371379a80a1SMichael Chan #endif
1372c0c050c5SMichael Chan
1373c0c050c5SMichael Chan struct bnxt_pf_info {
1374c0c050c5SMichael Chan #define BNXT_FIRST_PF_FID 1
1375c0c050c5SMichael Chan #define BNXT_FIRST_VF_FID 128
1376a58a3e68SMichael Chan u16 fw_fid;
1377a58a3e68SMichael Chan u16 port_id;
1378c0c050c5SMichael Chan u8 mac_addr[ETH_ALEN];
1379c0c050c5SMichael Chan u32 first_vf_id;
1380c0c050c5SMichael Chan u16 active_vfs;
1381230d1f0dSMichael Chan u16 registered_vfs;
1382c0c050c5SMichael Chan u16 max_vfs;
1383c0c050c5SMichael Chan unsigned long *vf_event_bmap;
1384c0c050c5SMichael Chan u16 hwrm_cmd_req_pages;
13854673d664SMichael Chan u8 vf_resv_strategy;
13864673d664SMichael Chan #define BNXT_VF_RESV_STRATEGY_MAXIMAL 0
13874673d664SMichael Chan #define BNXT_VF_RESV_STRATEGY_MINIMAL 1
1388bf82736dSMichael Chan #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2
1389c0c050c5SMichael Chan void *hwrm_cmd_req_addr[4];
1390c0c050c5SMichael Chan dma_addr_t hwrm_cmd_req_dma_addr[4];
1391c0c050c5SMichael Chan struct bnxt_vf_info *vf;
1392c0c050c5SMichael Chan };
1393c0c050c5SMichael Chan
1394992d38d2SMichael Chan struct bnxt_filter_base {
1395c0c050c5SMichael Chan struct hlist_node hash;
13968336a974SPavan Chebbi struct list_head list;
1397c0c050c5SMichael Chan __le64 filter_id;
1398992d38d2SMichael Chan u8 type;
1399992d38d2SMichael Chan #define BNXT_FLTR_TYPE_NTUPLE 1
1400992d38d2SMichael Chan #define BNXT_FLTR_TYPE_L2 2
1401992d38d2SMichael Chan u8 flags;
1402992d38d2SMichael Chan #define BNXT_ACT_DROP 1
1403992d38d2SMichael Chan #define BNXT_ACT_RING_DST 2
1404992d38d2SMichael Chan #define BNXT_ACT_FUNC_DST 4
1405c029bc30SMichael Chan #define BNXT_ACT_NO_AGING 8
14062f4f9fe5SPavan Chebbi #define BNXT_ACT_RSS_CTX 0x10
1407c0c050c5SMichael Chan u16 sw_id;
1408c0c050c5SMichael Chan u16 rxq;
1409992d38d2SMichael Chan u16 fw_vnic_id;
1410992d38d2SMichael Chan u16 vf_idx;
1411c0c050c5SMichael Chan unsigned long state;
1412c0c050c5SMichael Chan #define BNXT_FLTR_VALID 0
1413ee908d05SMichael Chan #define BNXT_FLTR_INSERTED 1
141480cfde29SMichael Chan #define BNXT_FLTR_FW_DELETED 2
14151f6e77cbSMichael Chan
14161f6e77cbSMichael Chan struct rcu_head rcu;
1417c0c050c5SMichael Chan };
1418c0c050c5SMichael Chan
1419c8d129c4SEdwin Peer struct bnxt_flow_masks {
1420c8d129c4SEdwin Peer struct flow_dissector_key_ports ports;
1421c8d129c4SEdwin Peer struct flow_dissector_key_addrs addrs;
1422c8d129c4SEdwin Peer };
1423c8d129c4SEdwin Peer
1424c8d129c4SEdwin Peer extern const struct bnxt_flow_masks BNXT_FLOW_MASK_NONE;
1425c8d129c4SEdwin Peer extern const struct bnxt_flow_masks BNXT_FLOW_IPV6_MASK_ALL;
1426c8d129c4SEdwin Peer extern const struct bnxt_flow_masks BNXT_FLOW_IPV4_MASK_ALL;
1427c8d129c4SEdwin Peer
1428992d38d2SMichael Chan struct bnxt_ntuple_filter {
1429be40b4e9SPavan Chebbi /* base filter must be the first member */
1430992d38d2SMichael Chan struct bnxt_filter_base base;
1431992d38d2SMichael Chan struct flow_keys fkeys;
1432c8d129c4SEdwin Peer struct bnxt_flow_masks fmasks;
1433bfeabf7eSMichael Chan struct bnxt_l2_filter *l2_fltr;
1434992d38d2SMichael Chan u32 flow_id;
1435992d38d2SMichael Chan };
1436992d38d2SMichael Chan
14371f6e77cbSMichael Chan struct bnxt_l2_key {
14381f6e77cbSMichael Chan union {
14391f6e77cbSMichael Chan struct {
14401f6e77cbSMichael Chan u8 dst_mac_addr[ETH_ALEN];
14411f6e77cbSMichael Chan u16 vlan;
14421f6e77cbSMichael Chan };
14431f6e77cbSMichael Chan u32 filter_key;
14441f6e77cbSMichael Chan };
14451f6e77cbSMichael Chan };
14461f6e77cbSMichael Chan
1447d3c98285SPavan Chebbi struct bnxt_ipv4_tuple {
1448d3c98285SPavan Chebbi struct flow_dissector_key_ipv4_addrs v4addrs;
1449d3c98285SPavan Chebbi struct flow_dissector_key_ports ports;
1450d3c98285SPavan Chebbi };
1451d3c98285SPavan Chebbi
1452d3c98285SPavan Chebbi struct bnxt_ipv6_tuple {
1453d3c98285SPavan Chebbi struct flow_dissector_key_ipv6_addrs v6addrs;
1454d3c98285SPavan Chebbi struct flow_dissector_key_ports ports;
1455d3c98285SPavan Chebbi };
1456d3c98285SPavan Chebbi
14571f6e77cbSMichael Chan #define BNXT_L2_KEY_SIZE (sizeof(struct bnxt_l2_key) / 4)
14581f6e77cbSMichael Chan
14591f6e77cbSMichael Chan struct bnxt_l2_filter {
1460be40b4e9SPavan Chebbi /* base filter must be the first member */
14611f6e77cbSMichael Chan struct bnxt_filter_base base;
14621f6e77cbSMichael Chan struct bnxt_l2_key l2_key;
14631f6e77cbSMichael Chan atomic_t refcnt;
14641f6e77cbSMichael Chan };
14651f6e77cbSMichael Chan
14667d9df38cSMichael Chan /* Compat version of hwrm_port_phy_qcfg_output capped at 96 bytes. The
14677d9df38cSMichael Chan * first 95 bytes are identical to hwrm_port_phy_qcfg_output in bnxt_hsi.h.
14687d9df38cSMichael Chan * The last valid byte in the compat version is different.
14697d9df38cSMichael Chan */
14707d9df38cSMichael Chan struct hwrm_port_phy_qcfg_output_compat {
14717d9df38cSMichael Chan __le16 error_code;
14727d9df38cSMichael Chan __le16 req_type;
14737d9df38cSMichael Chan __le16 seq_id;
14747d9df38cSMichael Chan __le16 resp_len;
14757d9df38cSMichael Chan u8 link;
14767d9df38cSMichael Chan u8 active_fec_signal_mode;
14777d9df38cSMichael Chan __le16 link_speed;
14787d9df38cSMichael Chan u8 duplex_cfg;
14797d9df38cSMichael Chan u8 pause;
14807d9df38cSMichael Chan __le16 support_speeds;
14817d9df38cSMichael Chan __le16 force_link_speed;
14827d9df38cSMichael Chan u8 auto_mode;
14837d9df38cSMichael Chan u8 auto_pause;
14847d9df38cSMichael Chan __le16 auto_link_speed;
14857d9df38cSMichael Chan __le16 auto_link_speed_mask;
14867d9df38cSMichael Chan u8 wirespeed;
14877d9df38cSMichael Chan u8 lpbk;
14887d9df38cSMichael Chan u8 force_pause;
14897d9df38cSMichael Chan u8 module_status;
14907d9df38cSMichael Chan __le32 preemphasis;
14917d9df38cSMichael Chan u8 phy_maj;
14927d9df38cSMichael Chan u8 phy_min;
14937d9df38cSMichael Chan u8 phy_bld;
14947d9df38cSMichael Chan u8 phy_type;
14957d9df38cSMichael Chan u8 media_type;
14967d9df38cSMichael Chan u8 xcvr_pkg_type;
14977d9df38cSMichael Chan u8 eee_config_phy_addr;
14987d9df38cSMichael Chan u8 parallel_detect;
14997d9df38cSMichael Chan __le16 link_partner_adv_speeds;
15007d9df38cSMichael Chan u8 link_partner_adv_auto_mode;
15017d9df38cSMichael Chan u8 link_partner_adv_pause;
15027d9df38cSMichael Chan __le16 adv_eee_link_speed_mask;
15037d9df38cSMichael Chan __le16 link_partner_adv_eee_link_speed_mask;
15047d9df38cSMichael Chan __le32 xcvr_identifier_type_tx_lpi_timer;
15057d9df38cSMichael Chan __le16 fec_cfg;
15067d9df38cSMichael Chan u8 duplex_state;
15077d9df38cSMichael Chan u8 option_flags;
15087d9df38cSMichael Chan char phy_vendor_name[16];
15097d9df38cSMichael Chan char phy_vendor_partnumber[16];
15107d9df38cSMichael Chan __le16 support_pam4_speeds;
15117d9df38cSMichael Chan __le16 force_pam4_link_speed;
15127d9df38cSMichael Chan __le16 auto_pam4_link_speed_mask;
15137d9df38cSMichael Chan u8 link_partner_pam4_adv_speeds;
15147d9df38cSMichael Chan u8 valid;
15157d9df38cSMichael Chan };
15167d9df38cSMichael Chan
1517c0c050c5SMichael Chan struct bnxt_link_info {
151803efbec0SMichael Chan u8 phy_type;
1519c0c050c5SMichael Chan u8 media_type;
1520c0c050c5SMichael Chan u8 transceiver;
1521c0c050c5SMichael Chan u8 phy_addr;
1522c0c050c5SMichael Chan u8 phy_link_status;
1523c0c050c5SMichael Chan #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
1524c0c050c5SMichael Chan #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
1525c0c050c5SMichael Chan #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
1526c0c050c5SMichael Chan u8 wire_speed;
15273128e811SMichael Chan u8 phy_state;
15283128e811SMichael Chan #define BNXT_PHY_STATE_ENABLED 0
15293128e811SMichael Chan #define BNXT_PHY_STATE_DISABLED 1
15303128e811SMichael Chan
15310f5a4841SEdwin Peer u8 link_state;
15320f5a4841SEdwin Peer #define BNXT_LINK_STATE_UNKNOWN 0
15330f5a4841SEdwin Peer #define BNXT_LINK_STATE_DOWN 1
15340f5a4841SEdwin Peer #define BNXT_LINK_STATE_UP 2
15350f5a4841SEdwin Peer #define BNXT_LINK_IS_UP(bp) ((bp)->link_info.link_state == BNXT_LINK_STATE_UP)
153630c0bb63SMichael Chan u8 active_lanes;
1537c0c050c5SMichael Chan u8 duplex;
1538acb20054SMichael Chan #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1539acb20054SMichael Chan #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1540c0c050c5SMichael Chan u8 pause;
1541c0c050c5SMichael Chan #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
1542c0c050c5SMichael Chan #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
1543c0c050c5SMichael Chan #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1544c0c050c5SMichael Chan PORT_PHY_QCFG_RESP_PAUSE_TX)
15453277360eSMichael Chan u8 lp_pause;
1546c0c050c5SMichael Chan u8 auto_pause_setting;
1547c0c050c5SMichael Chan u8 force_pause_setting;
1548c0c050c5SMichael Chan u8 duplex_setting;
1549c0c050c5SMichael Chan u8 auto_mode;
1550c0c050c5SMichael Chan #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
1551c0c050c5SMichael Chan (mode) <= BNXT_LINK_AUTO_MSK)
1552c0c050c5SMichael Chan #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1553c0c050c5SMichael Chan #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1554c0c050c5SMichael Chan #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1555c0c050c5SMichael Chan #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
155611f15ed3SMichael Chan #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1557c0c050c5SMichael Chan #define PHY_VER_LEN 3
1558c0c050c5SMichael Chan u8 phy_ver[PHY_VER_LEN];
1559c0c050c5SMichael Chan u16 link_speed;
1560c0c050c5SMichael Chan #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1561c0c050c5SMichael Chan #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1562c0c050c5SMichael Chan #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1563c0c050c5SMichael Chan #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1564c0c050c5SMichael Chan #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1565c0c050c5SMichael Chan #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1566c0c050c5SMichael Chan #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1567c0c050c5SMichael Chan #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1568c0c050c5SMichael Chan #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
156938a21b34SDeepak Khungar #define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1570581bce7bSMichael Chan #define BNXT_LINK_SPEED_200GB PORT_PHY_QCFG_RESP_LINK_SPEED_200GB
157130c0bb63SMichael Chan #define BNXT_LINK_SPEED_400GB PORT_PHY_QCFG_RESP_LINK_SPEED_400GB
1572c0c050c5SMichael Chan u16 support_speeds;
1573d058426eSEdwin Peer u16 support_pam4_speeds;
157430c0bb63SMichael Chan u16 support_speeds2;
157530c0bb63SMichael Chan
157668515a18SMichael Chan u16 auto_link_speeds; /* fw adv setting */
1577c0c050c5SMichael Chan #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1578c0c050c5SMichael Chan #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1579c0c050c5SMichael Chan #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1580c0c050c5SMichael Chan #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1581c0c050c5SMichael Chan #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1582c0c050c5SMichael Chan #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1583c0c050c5SMichael Chan #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1584c0c050c5SMichael Chan #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1585c0c050c5SMichael Chan #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
158638a21b34SDeepak Khungar #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1587d058426eSEdwin Peer u16 auto_pam4_link_speeds;
1588d058426eSEdwin Peer #define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G
1589d058426eSEdwin Peer #define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G
1590d058426eSEdwin Peer #define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G
159130c0bb63SMichael Chan u16 auto_link_speeds2;
159230c0bb63SMichael Chan #define BNXT_LINK_SPEEDS2_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB
159330c0bb63SMichael Chan #define BNXT_LINK_SPEEDS2_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB
159430c0bb63SMichael Chan #define BNXT_LINK_SPEEDS2_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB
159530c0bb63SMichael Chan #define BNXT_LINK_SPEEDS2_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB
159630c0bb63SMichael Chan #define BNXT_LINK_SPEEDS2_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB
159730c0bb63SMichael Chan #define BNXT_LINK_SPEEDS2_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB
159830c0bb63SMichael Chan #define BNXT_LINK_SPEEDS2_MSK_50GB_PAM4 \
159930c0bb63SMichael Chan PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56
160030c0bb63SMichael Chan #define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4 \
160130c0bb63SMichael Chan PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56
160230c0bb63SMichael Chan #define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4 \
160330c0bb63SMichael Chan PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56
160430c0bb63SMichael Chan #define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4 \
160530c0bb63SMichael Chan PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56
160630c0bb63SMichael Chan #define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112 \
160730c0bb63SMichael Chan PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112
160830c0bb63SMichael Chan #define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112 \
160930c0bb63SMichael Chan PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112
161030c0bb63SMichael Chan #define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112 \
161130c0bb63SMichael Chan PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112
161230c0bb63SMichael Chan
161393ed8117SMichael Chan u16 support_auto_speeds;
1614d058426eSEdwin Peer u16 support_pam4_auto_speeds;
161530c0bb63SMichael Chan u16 support_auto_speeds2;
161630c0bb63SMichael Chan
16173277360eSMichael Chan u16 lp_auto_link_speeds;
1618d058426eSEdwin Peer u16 lp_auto_pam4_link_speeds;
1619c0c050c5SMichael Chan u16 force_link_speed;
1620d058426eSEdwin Peer u16 force_pam4_link_speed;
162130c0bb63SMichael Chan u16 force_link_speed2;
162230c0bb63SMichael Chan #define BNXT_LINK_SPEED_50GB_PAM4 \
162330c0bb63SMichael Chan PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56
162430c0bb63SMichael Chan #define BNXT_LINK_SPEED_100GB_PAM4 \
162530c0bb63SMichael Chan PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56
162630c0bb63SMichael Chan #define BNXT_LINK_SPEED_200GB_PAM4 \
162730c0bb63SMichael Chan PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56
162830c0bb63SMichael Chan #define BNXT_LINK_SPEED_400GB_PAM4 \
162930c0bb63SMichael Chan PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56
163030c0bb63SMichael Chan #define BNXT_LINK_SPEED_100GB_PAM4_112 \
163130c0bb63SMichael Chan PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112
163230c0bb63SMichael Chan #define BNXT_LINK_SPEED_200GB_PAM4_112 \
163330c0bb63SMichael Chan PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112
163430c0bb63SMichael Chan #define BNXT_LINK_SPEED_400GB_PAM4_112 \
163530c0bb63SMichael Chan PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112
163630c0bb63SMichael Chan
1637c0c050c5SMichael Chan u32 preemphasis;
163842ee18feSAjit Khaparde u8 module_status;
16398b277589SMichael Chan u8 active_fec_sig_mode;
1640e70c752fSMichael Chan u16 fec_cfg;
16418b277589SMichael Chan #define BNXT_FEC_NONE PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
16428b277589SMichael Chan #define BNXT_FEC_AUTONEG_CAP PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
1643e70c752fSMichael Chan #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
16448b277589SMichael Chan #define BNXT_FEC_ENC_BASE_R_CAP \
16458b277589SMichael Chan PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
1646e70c752fSMichael Chan #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
16478b277589SMichael Chan #define BNXT_FEC_ENC_RS_CAP \
16488b277589SMichael Chan PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
16498b277589SMichael Chan #define BNXT_FEC_ENC_LLRS_CAP \
16508b277589SMichael Chan (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED | \
16518b277589SMichael Chan PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)
16528b277589SMichael Chan #define BNXT_FEC_ENC_RS \
16538b277589SMichael Chan (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED | \
16548b277589SMichael Chan PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED | \
16558b277589SMichael Chan PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)
16568b277589SMichael Chan #define BNXT_FEC_ENC_LLRS \
16578b277589SMichael Chan (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED | \
16588b277589SMichael Chan PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)
1659c0c050c5SMichael Chan
1660c0c050c5SMichael Chan /* copy of requested setting from ethtool cmd */
1661c0c050c5SMichael Chan u8 autoneg;
1662c0c050c5SMichael Chan #define BNXT_AUTONEG_SPEED 1
1663c0c050c5SMichael Chan #define BNXT_AUTONEG_FLOW_CTRL 2
1664d058426eSEdwin Peer u8 req_signal_mode;
1665d058426eSEdwin Peer #define BNXT_SIG_MODE_NRZ PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ
1666d058426eSEdwin Peer #define BNXT_SIG_MODE_PAM4 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
166730c0bb63SMichael Chan #define BNXT_SIG_MODE_PAM4_112 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112
1668ecdad2a6SEdwin Peer #define BNXT_SIG_MODE_MAX (PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST + 1)
1669c0c050c5SMichael Chan u8 req_duplex;
1670c0c050c5SMichael Chan u8 req_flow_ctrl;
1671c0c050c5SMichael Chan u16 req_link_speed;
167268515a18SMichael Chan u16 advertising; /* user adv setting */
1673d058426eSEdwin Peer u16 advertising_pam4;
1674c0c050c5SMichael Chan bool force_link_chng;
16754bb13abfSMichael Chan
1676a1ef4a79SMichael Chan bool phy_retry;
1677a1ef4a79SMichael Chan unsigned long phy_retry_expires;
1678a1ef4a79SMichael Chan
1679c0c050c5SMichael Chan /* a copy of phy_qcfg output used to report link
1680c0c050c5SMichael Chan * info to VF
1681c0c050c5SMichael Chan */
1682c0c050c5SMichael Chan struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1683c0c050c5SMichael Chan };
1684c0c050c5SMichael Chan
1685ccd6a9dcSMichael Chan #define BNXT_FEC_RS544_ON \
1686ccd6a9dcSMichael Chan (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE | \
1687ccd6a9dcSMichael Chan PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)
1688ccd6a9dcSMichael Chan
1689ccd6a9dcSMichael Chan #define BNXT_FEC_RS544_OFF \
1690ccd6a9dcSMichael Chan (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE | \
1691ccd6a9dcSMichael Chan PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)
1692ccd6a9dcSMichael Chan
1693ccd6a9dcSMichael Chan #define BNXT_FEC_RS272_ON \
1694ccd6a9dcSMichael Chan (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE | \
1695ccd6a9dcSMichael Chan PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)
1696ccd6a9dcSMichael Chan
1697ccd6a9dcSMichael Chan #define BNXT_FEC_RS272_OFF \
1698ccd6a9dcSMichael Chan (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE | \
1699ccd6a9dcSMichael Chan PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)
1700ccd6a9dcSMichael Chan
1701ccd6a9dcSMichael Chan #define BNXT_PAM4_SUPPORTED(link_info) \
1702ccd6a9dcSMichael Chan ((link_info)->support_pam4_speeds)
1703ccd6a9dcSMichael Chan
1704ccd6a9dcSMichael Chan #define BNXT_FEC_RS_ON(link_info) \
1705ccd6a9dcSMichael Chan (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
1706ccd6a9dcSMichael Chan PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1707ccd6a9dcSMichael Chan (BNXT_PAM4_SUPPORTED(link_info) ? \
1708ccd6a9dcSMichael Chan (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))
1709ccd6a9dcSMichael Chan
1710ccd6a9dcSMichael Chan #define BNXT_FEC_LLRS_ON \
1711ccd6a9dcSMichael Chan (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
1712ccd6a9dcSMichael Chan PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1713ccd6a9dcSMichael Chan BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)
1714ccd6a9dcSMichael Chan
1715ccd6a9dcSMichael Chan #define BNXT_FEC_RS_OFF(link_info) \
1716ccd6a9dcSMichael Chan (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE | \
1717ccd6a9dcSMichael Chan (BNXT_PAM4_SUPPORTED(link_info) ? \
1718ccd6a9dcSMichael Chan (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))
1719ccd6a9dcSMichael Chan
1720ccd6a9dcSMichael Chan #define BNXT_FEC_BASE_R_ON(link_info) \
1721ccd6a9dcSMichael Chan (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE | \
1722ccd6a9dcSMichael Chan BNXT_FEC_RS_OFF(link_info))
1723ccd6a9dcSMichael Chan
1724ccd6a9dcSMichael Chan #define BNXT_FEC_ALL_OFF(link_info) \
1725ccd6a9dcSMichael Chan (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1726ccd6a9dcSMichael Chan BNXT_FEC_RS_OFF(link_info))
1727ccd6a9dcSMichael Chan
1728c0c050c5SMichael Chan struct bnxt_queue_info {
1729c0c050c5SMichael Chan u8 queue_id;
1730c0c050c5SMichael Chan u8 queue_profile;
1731c0c050c5SMichael Chan };
1732c0c050c5SMichael Chan
17335ad2cbeeSMichael Chan #define BNXT_MAX_LED 4
17345ad2cbeeSMichael Chan
17355ad2cbeeSMichael Chan struct bnxt_led_info {
17365ad2cbeeSMichael Chan u8 led_id;
17375ad2cbeeSMichael Chan u8 led_type;
17385ad2cbeeSMichael Chan u8 led_group_id;
17395ad2cbeeSMichael Chan u8 unused;
17405ad2cbeeSMichael Chan __le16 led_state_caps;
17415ad2cbeeSMichael Chan #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
17425ad2cbeeSMichael Chan cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
17435ad2cbeeSMichael Chan
17445ad2cbeeSMichael Chan __le16 led_color_caps;
17455ad2cbeeSMichael Chan };
17465ad2cbeeSMichael Chan
1747eb513658SMichael Chan #define BNXT_MAX_TEST 8
1748eb513658SMichael Chan
1749eb513658SMichael Chan struct bnxt_test_info {
1750eb513658SMichael Chan u8 offline_mask;
1751eb513658SMichael Chan u16 timeout;
1752eb513658SMichael Chan char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1753eb513658SMichael Chan };
1754eb513658SMichael Chan
1755b5d600b0SVasundhara Volam #define CHIMP_REG_VIEW_ADDR \
17561c7fd6eeSRandy Schacher ((bp->flags & BNXT_FLAG_CHIP_P5_PLUS) ? 0x80000000 : 0xb1000000)
1757b5d600b0SVasundhara Volam
17582e9ee398SVenkat Duvvuru #define BNXT_GRCPF_REG_CHIMP_COMM 0x0
17592e9ee398SVenkat Duvvuru #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
176011809490SJeffrey Huang #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
176111809490SJeffrey Huang
1762d1cbd165SMichael Chan #define BNXT_GRC_REG_STATUS_P5 0x520
1763d1cbd165SMichael Chan
1764760b6d33SVenkat Duvvuru #define BNXT_GRCPF_REG_KONG_COMM 0xA00
1765760b6d33SVenkat Duvvuru #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00
1766760b6d33SVenkat Duvvuru
1767d1cbd165SMichael Chan #define BNXT_GRC_REG_CHIP_NUM 0x48
1768d1cbd165SMichael Chan #define BNXT_GRC_REG_BASE 0x260000
1769d1cbd165SMichael Chan
1770ae5c42f0SMichael Chan #define BNXT_TS_REG_TIMESYNC_TS0_LOWER 0x640180c
1771ae5c42f0SMichael Chan #define BNXT_TS_REG_TIMESYNC_TS0_UPPER 0x6401810
1772ae5c42f0SMichael Chan
17739ffbd677SMichael Chan #define BNXT_GRC_BASE_MASK 0xfffff000
17749ffbd677SMichael Chan #define BNXT_GRC_OFFSET_MASK 0x00000ffc
17759ffbd677SMichael Chan
17765a84acbeSSathya Perla struct bnxt_tc_flow_stats {
17775a84acbeSSathya Perla u64 packets;
17785a84acbeSSathya Perla u64 bytes;
17795a84acbeSSathya Perla };
17805a84acbeSSathya Perla
1781627c89d0SSriharsha Basavapatna #ifdef CONFIG_BNXT_FLOWER_OFFLOAD
1782627c89d0SSriharsha Basavapatna struct bnxt_flower_indr_block_cb_priv {
1783627c89d0SSriharsha Basavapatna struct net_device *tunnel_netdev;
1784627c89d0SSriharsha Basavapatna struct bnxt *bp;
1785627c89d0SSriharsha Basavapatna struct list_head list;
1786627c89d0SSriharsha Basavapatna };
1787627c89d0SSriharsha Basavapatna #endif
1788627c89d0SSriharsha Basavapatna
17892ae7408fSSathya Perla struct bnxt_tc_info {
17902ae7408fSSathya Perla bool enabled;
17912ae7408fSSathya Perla
17922ae7408fSSathya Perla /* hash table to store TC offloaded flows */
17932ae7408fSSathya Perla struct rhashtable flow_table;
17942ae7408fSSathya Perla struct rhashtable_params flow_ht_params;
17952ae7408fSSathya Perla
17962ae7408fSSathya Perla /* hash table to store L2 keys of TC flows */
17972ae7408fSSathya Perla struct rhashtable l2_table;
17982ae7408fSSathya Perla struct rhashtable_params l2_ht_params;
17998c95f773SSathya Perla /* hash table to store L2 keys for TC tunnel decap */
18008c95f773SSathya Perla struct rhashtable decap_l2_table;
18018c95f773SSathya Perla struct rhashtable_params decap_l2_ht_params;
18028c95f773SSathya Perla /* hash table to store tunnel decap entries */
18038c95f773SSathya Perla struct rhashtable decap_table;
18048c95f773SSathya Perla struct rhashtable_params decap_ht_params;
18058c95f773SSathya Perla /* hash table to store tunnel encap entries */
18068c95f773SSathya Perla struct rhashtable encap_table;
18078c95f773SSathya Perla struct rhashtable_params encap_ht_params;
18082ae7408fSSathya Perla
18092ae7408fSSathya Perla /* lock to atomically add/del an l2 node when a flow is
18102ae7408fSSathya Perla * added or deleted.
18112ae7408fSSathya Perla */
18122ae7408fSSathya Perla struct mutex lock;
18132ae7408fSSathya Perla
18145a84acbeSSathya Perla /* Fields used for batching stats query */
18155a84acbeSSathya Perla struct rhashtable_iter iter;
18165a84acbeSSathya Perla #define BNXT_FLOW_STATS_BATCH_MAX 10
18175a84acbeSSathya Perla struct bnxt_tc_stats_batch {
18185a84acbeSSathya Perla void *flow_node;
18195a84acbeSSathya Perla struct bnxt_tc_flow_stats hw_stats;
18205a84acbeSSathya Perla } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
18215a84acbeSSathya Perla
18222ae7408fSSathya Perla /* Stat counter mask (width) */
18232ae7408fSSathya Perla u64 bytes_mask;
18242ae7408fSSathya Perla u64 packets_mask;
18252ae7408fSSathya Perla };
18262ae7408fSSathya Perla
18274ab0c6a8SSathya Perla struct bnxt_vf_rep_stats {
18284ab0c6a8SSathya Perla u64 packets;
18294ab0c6a8SSathya Perla u64 bytes;
18304ab0c6a8SSathya Perla u64 dropped;
18314ab0c6a8SSathya Perla };
18324ab0c6a8SSathya Perla
18334ab0c6a8SSathya Perla struct bnxt_vf_rep {
18344ab0c6a8SSathya Perla struct bnxt *bp;
18354ab0c6a8SSathya Perla struct net_device *dev;
1836ee5c7fb3SSathya Perla struct metadata_dst *dst;
18374ab0c6a8SSathya Perla u16 vf_idx;
18384ab0c6a8SSathya Perla u16 tx_cfa_action;
18394ab0c6a8SSathya Perla u16 rx_cfa_code;
18404ab0c6a8SSathya Perla
18414ab0c6a8SSathya Perla struct bnxt_vf_rep_stats rx_stats;
18424ab0c6a8SSathya Perla struct bnxt_vf_rep_stats tx_stats;
18434ab0c6a8SSathya Perla };
18444ab0c6a8SSathya Perla
184566cca20aSMichael Chan #define PTU_PTE_VALID 0x1UL
184666cca20aSMichael Chan #define PTU_PTE_LAST 0x2UL
184766cca20aSMichael Chan #define PTU_PTE_NEXT_TO_LAST 0x4UL
184866cca20aSMichael Chan
184998f04cf0SMichael Chan #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
185008fe9d18SMichael Chan #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
185198f04cf0SMichael Chan
185298f04cf0SMichael Chan struct bnxt_ctx_pg_info {
185398f04cf0SMichael Chan u32 entries;
185408fe9d18SMichael Chan u32 nr_pages;
185598f04cf0SMichael Chan void *ctx_pg_arr[MAX_CTX_PAGES];
185698f04cf0SMichael Chan dma_addr_t ctx_dma_arr[MAX_CTX_PAGES];
185798f04cf0SMichael Chan struct bnxt_ring_mem_info ring_mem;
185808fe9d18SMichael Chan struct bnxt_ctx_pg_info **ctx_pg_tbl;
185998f04cf0SMichael Chan };
186098f04cf0SMichael Chan
1861a029a2feSMichael Chan #define BNXT_MAX_TQM_SP_RINGS 1
1862a029a2feSMichael Chan #define BNXT_MAX_TQM_FP_RINGS 8
1863a029a2feSMichael Chan #define BNXT_MAX_TQM_RINGS \
1864a029a2feSMichael Chan (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
1865a029a2feSMichael Chan
186616db6323SMichael Chan #define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256
186716db6323SMichael Chan
1868702279d2SMichael Chan #define BNXT_SET_CTX_PAGE_ATTR(attr) \
1869702279d2SMichael Chan do { \
1870702279d2SMichael Chan if (BNXT_PAGE_SIZE == 0x2000) \
1871702279d2SMichael Chan attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K; \
1872702279d2SMichael Chan else if (BNXT_PAGE_SIZE == 0x10000) \
1873702279d2SMichael Chan attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K; \
1874702279d2SMichael Chan else \
1875702279d2SMichael Chan attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K; \
1876702279d2SMichael Chan } while (0)
1877702279d2SMichael Chan
187876087d99SMichael Chan struct bnxt_ctx_mem_type {
187976087d99SMichael Chan u16 type;
188076087d99SMichael Chan u16 entry_size;
188176087d99SMichael Chan u32 flags;
1882236e237fSMichael Chan #define BNXT_CTX_MEM_TYPE_VALID FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID
188376087d99SMichael Chan u32 instance_bmap;
188476087d99SMichael Chan u8 init_value;
188576087d99SMichael Chan u8 entry_multiple;
188676087d99SMichael Chan u16 init_offset;
188776087d99SMichael Chan #define BNXT_CTX_INIT_INVALID_OFFSET 0xffff
188876087d99SMichael Chan u32 max_entries;
188976087d99SMichael Chan u32 min_entries;
189076087d99SMichael Chan u8 last:1;
189176087d99SMichael Chan u8 split_entry_cnt;
189276087d99SMichael Chan #define BNXT_MAX_SPLIT_ENTRY 4
189376087d99SMichael Chan union {
189476087d99SMichael Chan struct {
189576087d99SMichael Chan u32 qp_l2_entries;
189676087d99SMichael Chan u32 qp_qp1_entries;
189776087d99SMichael Chan u32 qp_fast_qpmd_entries;
189876087d99SMichael Chan };
189976087d99SMichael Chan u32 srq_l2_entries;
190076087d99SMichael Chan u32 cq_l2_entries;
190176087d99SMichael Chan u32 vnic_entries;
190276087d99SMichael Chan struct {
190376087d99SMichael Chan u32 mrav_av_entries;
190476087d99SMichael Chan u32 mrav_num_entries_units;
190576087d99SMichael Chan };
190676087d99SMichael Chan u32 split[BNXT_MAX_SPLIT_ENTRY];
190776087d99SMichael Chan };
1908035c5761SMichael Chan struct bnxt_ctx_pg_info *pg_info;
190976087d99SMichael Chan };
191076087d99SMichael Chan
191176087d99SMichael Chan #define BNXT_CTX_MRAV_AV_SPLIT_ENTRY 0
191276087d99SMichael Chan
191376087d99SMichael Chan #define BNXT_CTX_QP FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP
191476087d99SMichael Chan #define BNXT_CTX_SRQ FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ
191576087d99SMichael Chan #define BNXT_CTX_CQ FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ
191676087d99SMichael Chan #define BNXT_CTX_VNIC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC
191776087d99SMichael Chan #define BNXT_CTX_STAT FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT
191876087d99SMichael Chan #define BNXT_CTX_STQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING
191976087d99SMichael Chan #define BNXT_CTX_FTQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING
192076087d99SMichael Chan #define BNXT_CTX_MRAV FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV
192176087d99SMichael Chan #define BNXT_CTX_TIM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM
192276087d99SMichael Chan #define BNXT_CTX_TKC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TKC
192376087d99SMichael Chan #define BNXT_CTX_RKC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RKC
192476087d99SMichael Chan #define BNXT_CTX_MTQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING
192576087d99SMichael Chan #define BNXT_CTX_SQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW
192676087d99SMichael Chan #define BNXT_CTX_RQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW
192776087d99SMichael Chan #define BNXT_CTX_SRQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW
192876087d99SMichael Chan #define BNXT_CTX_CQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW
192976087d99SMichael Chan #define BNXT_CTX_QTKC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_TKC
193076087d99SMichael Chan #define BNXT_CTX_QRKC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_RKC
193176087d99SMichael Chan #define BNXT_CTX_TBLSC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE
193276087d99SMichael Chan #define BNXT_CTX_XPAR FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION
193376087d99SMichael Chan
193476087d99SMichael Chan #define BNXT_CTX_MAX (BNXT_CTX_TIM + 1)
193508b386b1SMichael Chan #define BNXT_CTX_L2_MAX (BNXT_CTX_FTQM + 1)
193676087d99SMichael Chan #define BNXT_CTX_V2_MAX (BNXT_CTX_XPAR + 1)
193776087d99SMichael Chan #define BNXT_CTX_INV ((u16)-1)
193876087d99SMichael Chan
193998f04cf0SMichael Chan struct bnxt_ctx_mem_info {
1940ac3158cbSMichael Chan u8 tqm_fp_rings_count;
194198f04cf0SMichael Chan
194298f04cf0SMichael Chan u32 flags;
194398f04cf0SMichael Chan #define BNXT_CTX_FLAG_INITED 0x01
19446a4d0774SMichael Chan struct bnxt_ctx_mem_type ctx_arr[BNXT_CTX_V2_MAX];
194598f04cf0SMichael Chan };
194698f04cf0SMichael Chan
19478cc95cebSEdwin Peer enum bnxt_health_severity {
19488cc95cebSEdwin Peer SEVERITY_NORMAL = 0,
19498cc95cebSEdwin Peer SEVERITY_WARNING,
19508cc95cebSEdwin Peer SEVERITY_RECOVERABLE,
19518cc95cebSEdwin Peer SEVERITY_FATAL,
19528cc95cebSEdwin Peer };
19538cc95cebSEdwin Peer
19548cc95cebSEdwin Peer enum bnxt_health_remedy {
19558cc95cebSEdwin Peer REMEDY_DEVLINK_RECOVER,
19568cc95cebSEdwin Peer REMEDY_POWER_CYCLE_DEVICE,
19578cc95cebSEdwin Peer REMEDY_POWER_CYCLE_HOST,
19588cc95cebSEdwin Peer REMEDY_FW_UPDATE,
19598cc95cebSEdwin Peer REMEDY_HW_REPLACE,
19608cc95cebSEdwin Peer };
19618cc95cebSEdwin Peer
196207f83d72SMichael Chan struct bnxt_fw_health {
196307f83d72SMichael Chan u32 flags;
196407f83d72SMichael Chan u32 polling_dsecs;
196507f83d72SMichael Chan u32 master_func_wait_dsecs;
196607f83d72SMichael Chan u32 normal_func_wait_dsecs;
196707f83d72SMichael Chan u32 post_reset_wait_dsecs;
196807f83d72SMichael Chan u32 post_reset_max_wait_dsecs;
196907f83d72SMichael Chan u32 regs[4];
197007f83d72SMichael Chan u32 mapped_regs[4];
197107f83d72SMichael Chan #define BNXT_FW_HEALTH_REG 0
197207f83d72SMichael Chan #define BNXT_FW_HEARTBEAT_REG 1
197307f83d72SMichael Chan #define BNXT_FW_RESET_CNT_REG 2
197407f83d72SMichael Chan #define BNXT_FW_RESET_INPROG_REG 3
197507f83d72SMichael Chan u32 fw_reset_inprog_reg_mask;
197607f83d72SMichael Chan u32 last_fw_heartbeat;
197707f83d72SMichael Chan u32 last_fw_reset_cnt;
197807f83d72SMichael Chan u8 enabled:1;
19791596847dSEdwin Peer u8 primary:1;
1980ba02629fSEdwin Peer u8 status_reliable:1;
19818cc95cebSEdwin Peer u8 resets_reliable:1;
198207f83d72SMichael Chan u8 tmr_multiplier;
198307f83d72SMichael Chan u8 tmr_counter;
198407f83d72SMichael Chan u8 fw_reset_seq_cnt;
198507f83d72SMichael Chan u32 fw_reset_seq_regs[16];
198607f83d72SMichael Chan u32 fw_reset_seq_vals[16];
198707f83d72SMichael Chan u32 fw_reset_seq_delay_msec[16];
1988df97b34dSMichael Chan u32 echo_req_data1;
1989df97b34dSMichael Chan u32 echo_req_data2;
19906763c779SVasundhara Volam struct devlink_health_reporter *fw_reporter;
19918cc95cebSEdwin Peer /* Protects severity and remedy */
19928cc95cebSEdwin Peer struct mutex lock;
19938cc95cebSEdwin Peer enum bnxt_health_severity severity;
19948cc95cebSEdwin Peer enum bnxt_health_remedy remedy;
19958cc95cebSEdwin Peer u32 arrests;
19968cc95cebSEdwin Peer u32 discoveries;
19978cc95cebSEdwin Peer u32 survivals;
19988cc95cebSEdwin Peer u32 fatalities;
19998cc95cebSEdwin Peer u32 diagnoses;
2000657a33c8SVasundhara Volam };
2001657a33c8SVasundhara Volam
200207f83d72SMichael Chan #define BNXT_FW_HEALTH_REG_TYPE_MASK 3
200307f83d72SMichael Chan #define BNXT_FW_HEALTH_REG_TYPE_CFG 0
200407f83d72SMichael Chan #define BNXT_FW_HEALTH_REG_TYPE_GRC 1
200507f83d72SMichael Chan #define BNXT_FW_HEALTH_REG_TYPE_BAR0 2
200607f83d72SMichael Chan #define BNXT_FW_HEALTH_REG_TYPE_BAR1 3
200707f83d72SMichael Chan
200807f83d72SMichael Chan #define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
200907f83d72SMichael Chan #define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
201007f83d72SMichael Chan
20119ffbd677SMichael Chan #define BNXT_FW_HEALTH_WIN_BASE 0x3000
20129ffbd677SMichael Chan #define BNXT_FW_HEALTH_WIN_MAP_OFF 8
20139ffbd677SMichael Chan
2014ba02629fSEdwin Peer #define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \
2015ba02629fSEdwin Peer ((reg) & BNXT_GRC_OFFSET_MASK))
2016ba02629fSEdwin Peer
2017fe1b8535SMichael Chan #define BNXT_FW_STATUS_HEALTH_MSK 0xffff
20186763c779SVasundhara Volam #define BNXT_FW_STATUS_HEALTHY 0x8000
20194037eb71SVasundhara Volam #define BNXT_FW_STATUS_SHUTDOWN 0x100000
2020861aae78SMichael Chan #define BNXT_FW_STATUS_RECOVERING 0x400000
20216763c779SVasundhara Volam
2022fe1b8535SMichael Chan #define BNXT_FW_IS_HEALTHY(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\
2023fe1b8535SMichael Chan BNXT_FW_STATUS_HEALTHY)
2024fe1b8535SMichael Chan
2025fe1b8535SMichael Chan #define BNXT_FW_IS_BOOTING(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \
2026fe1b8535SMichael Chan BNXT_FW_STATUS_HEALTHY)
2027fe1b8535SMichael Chan
2028fe1b8535SMichael Chan #define BNXT_FW_IS_ERR(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \
2029fe1b8535SMichael Chan BNXT_FW_STATUS_HEALTHY)
2030fe1b8535SMichael Chan
2031861aae78SMichael Chan #define BNXT_FW_IS_RECOVERING(sts) (BNXT_FW_IS_ERR(sts) && \
2032861aae78SMichael Chan ((sts) & BNXT_FW_STATUS_RECOVERING))
2033861aae78SMichael Chan
2034d1cbd165SMichael Chan #define BNXT_FW_RETRY 5
20355d06eb5cSVasundhara Volam #define BNXT_FW_IF_RETRY 10
20360cf736a1SVikas Gupta #define BNXT_FW_SLOT_RESET_RETRY 4
2037d1cbd165SMichael Chan
2038d80d88b0SAjit Khaparde struct bnxt_aux_priv {
2039d80d88b0SAjit Khaparde struct auxiliary_device aux_dev;
2040d80d88b0SAjit Khaparde struct bnxt_en_dev *edev;
2041d80d88b0SAjit Khaparde int id;
2042d80d88b0SAjit Khaparde };
2043d80d88b0SAjit Khaparde
2044c7dd4a5bSEdwin Peer enum board_idx {
2045c7dd4a5bSEdwin Peer BCM57301,
2046c7dd4a5bSEdwin Peer BCM57302,
2047c7dd4a5bSEdwin Peer BCM57304,
2048c7dd4a5bSEdwin Peer BCM57417_NPAR,
2049c7dd4a5bSEdwin Peer BCM58700,
2050c7dd4a5bSEdwin Peer BCM57311,
2051c7dd4a5bSEdwin Peer BCM57312,
2052c7dd4a5bSEdwin Peer BCM57402,
2053c7dd4a5bSEdwin Peer BCM57404,
2054c7dd4a5bSEdwin Peer BCM57406,
2055c7dd4a5bSEdwin Peer BCM57402_NPAR,
2056c7dd4a5bSEdwin Peer BCM57407,
2057c7dd4a5bSEdwin Peer BCM57412,
2058c7dd4a5bSEdwin Peer BCM57414,
2059c7dd4a5bSEdwin Peer BCM57416,
2060c7dd4a5bSEdwin Peer BCM57417,
2061c7dd4a5bSEdwin Peer BCM57412_NPAR,
2062c7dd4a5bSEdwin Peer BCM57314,
2063c7dd4a5bSEdwin Peer BCM57417_SFP,
2064c7dd4a5bSEdwin Peer BCM57416_SFP,
2065c7dd4a5bSEdwin Peer BCM57404_NPAR,
2066c7dd4a5bSEdwin Peer BCM57406_NPAR,
2067c7dd4a5bSEdwin Peer BCM57407_SFP,
2068c7dd4a5bSEdwin Peer BCM57407_NPAR,
2069c7dd4a5bSEdwin Peer BCM57414_NPAR,
2070c7dd4a5bSEdwin Peer BCM57416_NPAR,
2071c7dd4a5bSEdwin Peer BCM57452,
2072c7dd4a5bSEdwin Peer BCM57454,
2073c7dd4a5bSEdwin Peer BCM5745x_NPAR,
2074c7dd4a5bSEdwin Peer BCM57508,
2075c7dd4a5bSEdwin Peer BCM57504,
2076c7dd4a5bSEdwin Peer BCM57502,
2077c7dd4a5bSEdwin Peer BCM57508_NPAR,
2078c7dd4a5bSEdwin Peer BCM57504_NPAR,
2079c7dd4a5bSEdwin Peer BCM57502_NPAR,
20802012a6abSMichael Chan BCM57608,
20812012a6abSMichael Chan BCM57604,
20822012a6abSMichael Chan BCM57602,
20832012a6abSMichael Chan BCM57601,
2084c7dd4a5bSEdwin Peer BCM58802,
2085c7dd4a5bSEdwin Peer BCM58804,
2086c7dd4a5bSEdwin Peer BCM58808,
2087c7dd4a5bSEdwin Peer NETXTREME_E_VF,
2088c7dd4a5bSEdwin Peer NETXTREME_C_VF,
2089c7dd4a5bSEdwin Peer NETXTREME_S_VF,
2090c7dd4a5bSEdwin Peer NETXTREME_C_VF_HV,
2091c7dd4a5bSEdwin Peer NETXTREME_E_VF_HV,
2092c7dd4a5bSEdwin Peer NETXTREME_E_P5_VF,
2093c7dd4a5bSEdwin Peer NETXTREME_E_P5_VF_HV,
209454d0b84fSAjit Khaparde NETXTREME_E_P7_VF,
2095c7dd4a5bSEdwin Peer };
2096c7dd4a5bSEdwin Peer
2097c0c050c5SMichael Chan struct bnxt {
2098c0c050c5SMichael Chan void __iomem *bar0;
2099c0c050c5SMichael Chan void __iomem *bar1;
2100c0c050c5SMichael Chan void __iomem *bar2;
2101c0c050c5SMichael Chan
2102c0c050c5SMichael Chan u32 reg_base;
2103659c805cSMichael Chan u16 chip_num;
2104659c805cSMichael Chan #define CHIP_NUM_57301 0x16c8
2105659c805cSMichael Chan #define CHIP_NUM_57302 0x16c9
2106659c805cSMichael Chan #define CHIP_NUM_57304 0x16ca
21073e8060faSPrashant Sreedharan #define CHIP_NUM_58700 0x16cd
2108659c805cSMichael Chan #define CHIP_NUM_57402 0x16d0
2109659c805cSMichael Chan #define CHIP_NUM_57404 0x16d1
2110659c805cSMichael Chan #define CHIP_NUM_57406 0x16d2
21113284f9e1SMichael Chan #define CHIP_NUM_57407 0x16d5
2112659c805cSMichael Chan
2113659c805cSMichael Chan #define CHIP_NUM_57311 0x16ce
2114659c805cSMichael Chan #define CHIP_NUM_57312 0x16cf
2115659c805cSMichael Chan #define CHIP_NUM_57314 0x16df
21163284f9e1SMichael Chan #define CHIP_NUM_57317 0x16e0
2117659c805cSMichael Chan #define CHIP_NUM_57412 0x16d6
2118659c805cSMichael Chan #define CHIP_NUM_57414 0x16d7
2119659c805cSMichael Chan #define CHIP_NUM_57416 0x16d8
2120659c805cSMichael Chan #define CHIP_NUM_57417 0x16d9
21213284f9e1SMichael Chan #define CHIP_NUM_57412L 0x16da
21223284f9e1SMichael Chan #define CHIP_NUM_57414L 0x16db
21233284f9e1SMichael Chan
21243284f9e1SMichael Chan #define CHIP_NUM_5745X 0xd730
2125fb4cd81eSMichael Chan #define CHIP_NUM_57452 0xc452
2126fb4cd81eSMichael Chan #define CHIP_NUM_57454 0xc454
2127659c805cSMichael Chan
21281dc88b97SMichael Chan #define CHIP_NUM_57508 0x1750
21291dc88b97SMichael Chan #define CHIP_NUM_57504 0x1751
21301dc88b97SMichael Chan #define CHIP_NUM_57502 0x1752
2131e38287b7SMichael Chan
2132a432a45bSMichael Chan #define CHIP_NUM_57608 0x1760
2133a432a45bSMichael Chan
21344a58139bSRay Jui #define CHIP_NUM_58802 0xd802
21358ed693b7SRay Jui #define CHIP_NUM_58804 0xd804
21364a58139bSRay Jui #define CHIP_NUM_58808 0xd808
21374a58139bSRay Jui
21385313845fSMichael Chan u8 chip_rev;
21395313845fSMichael Chan
2140659c805cSMichael Chan #define BNXT_CHIP_NUM_5730X(chip_num) \
2141659c805cSMichael Chan ((chip_num) >= CHIP_NUM_57301 && \
2142659c805cSMichael Chan (chip_num) <= CHIP_NUM_57304)
2143659c805cSMichael Chan
2144659c805cSMichael Chan #define BNXT_CHIP_NUM_5740X(chip_num) \
21453284f9e1SMichael Chan (((chip_num) >= CHIP_NUM_57402 && \
21463284f9e1SMichael Chan (chip_num) <= CHIP_NUM_57406) || \
21473284f9e1SMichael Chan (chip_num) == CHIP_NUM_57407)
2148659c805cSMichael Chan
2149659c805cSMichael Chan #define BNXT_CHIP_NUM_5731X(chip_num) \
2150659c805cSMichael Chan ((chip_num) == CHIP_NUM_57311 || \
2151659c805cSMichael Chan (chip_num) == CHIP_NUM_57312 || \
21523284f9e1SMichael Chan (chip_num) == CHIP_NUM_57314 || \
21533284f9e1SMichael Chan (chip_num) == CHIP_NUM_57317)
2154659c805cSMichael Chan
2155659c805cSMichael Chan #define BNXT_CHIP_NUM_5741X(chip_num) \
2156659c805cSMichael Chan ((chip_num) >= CHIP_NUM_57412 && \
21573284f9e1SMichael Chan (chip_num) <= CHIP_NUM_57414L)
21583284f9e1SMichael Chan
21593284f9e1SMichael Chan #define BNXT_CHIP_NUM_58700(chip_num) \
21603284f9e1SMichael Chan ((chip_num) == CHIP_NUM_58700)
21613284f9e1SMichael Chan
21623284f9e1SMichael Chan #define BNXT_CHIP_NUM_5745X(chip_num) \
2163fb4cd81eSMichael Chan ((chip_num) == CHIP_NUM_5745X || \
2164fb4cd81eSMichael Chan (chip_num) == CHIP_NUM_57452 || \
2165fb4cd81eSMichael Chan (chip_num) == CHIP_NUM_57454)
2166fb4cd81eSMichael Chan
2167659c805cSMichael Chan
2168659c805cSMichael Chan #define BNXT_CHIP_NUM_57X0X(chip_num) \
2169659c805cSMichael Chan (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
2170659c805cSMichael Chan
2171659c805cSMichael Chan #define BNXT_CHIP_NUM_57X1X(chip_num) \
2172659c805cSMichael Chan (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
2173c0c050c5SMichael Chan
21744a58139bSRay Jui #define BNXT_CHIP_NUM_588XX(chip_num) \
21754a58139bSRay Jui ((chip_num) == CHIP_NUM_58802 || \
21768ed693b7SRay Jui (chip_num) == CHIP_NUM_58804 || \
21774a58139bSRay Jui (chip_num) == CHIP_NUM_58808)
21784a58139bSRay Jui
2179a0d0fd70SVasundhara Volam #define BNXT_VPD_FLD_LEN 32
2180a0d0fd70SVasundhara Volam char board_partno[BNXT_VPD_FLD_LEN];
2181a0d0fd70SVasundhara Volam char board_serialno[BNXT_VPD_FLD_LEN];
2182a0d0fd70SVasundhara Volam
2183c0c050c5SMichael Chan struct net_device *dev;
2184c0c050c5SMichael Chan struct pci_dev *pdev;
2185c0c050c5SMichael Chan
2186c0c050c5SMichael Chan atomic_t intr_sem;
2187c0c050c5SMichael Chan
2188c0c050c5SMichael Chan u32 flags;
21891c7fd6eeSRandy Schacher #define BNXT_FLAG_CHIP_P5_PLUS 0x1
2190c0c050c5SMichael Chan #define BNXT_FLAG_VF 0x2
2191c0c050c5SMichael Chan #define BNXT_FLAG_LRO 0x4
2192d1611c3aSMichael Chan #ifdef CONFIG_INET
2193c0c050c5SMichael Chan #define BNXT_FLAG_GRO 0x8
2194d1611c3aSMichael Chan #else
2195d1611c3aSMichael Chan /* Cannot support hardware GRO if CONFIG_INET is not set */
2196d1611c3aSMichael Chan #define BNXT_FLAG_GRO 0x0
2197d1611c3aSMichael Chan #endif
2198c0c050c5SMichael Chan #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
2199c0c050c5SMichael Chan #define BNXT_FLAG_JUMBO 0x10
2200c0c050c5SMichael Chan #define BNXT_FLAG_STRIP_VLAN 0x20
2201c0c050c5SMichael Chan #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
2202c0c050c5SMichael Chan BNXT_FLAG_LRO)
2203c0c050c5SMichael Chan #define BNXT_FLAG_RFS 0x100
22046e6c5a57SMichael Chan #define BNXT_FLAG_SHARED_RINGS 0x200
22053bdf56c4SMichael Chan #define BNXT_FLAG_PORT_STATS 0x400
2206c1ef146aSMichael Chan #define BNXT_FLAG_WOL_CAP 0x4000
2207e4060d30SMichael Chan #define BNXT_FLAG_ROCEV1_CAP 0x8000
2208e4060d30SMichael Chan #define BNXT_FLAG_ROCEV2_CAP 0x10000
2209e4060d30SMichael Chan #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \
2210e4060d30SMichael Chan BNXT_FLAG_ROCEV2_CAP)
2211bdbd1eb5SMichael Chan #define BNXT_FLAG_NO_AGG_RINGS 0x20000
2212c61fb99cSMichael Chan #define BNXT_FLAG_RX_PAGE_MODE 0x40000
2213a432a45bSMichael Chan #define BNXT_FLAG_CHIP_P7 0x80000
22149e54e322SDeepak Khungar #define BNXT_FLAG_MULTI_HOST 0x100000
2215d061b241SMichael Chan #define BNXT_FLAG_DSN_VALID 0x200000
2216434c975aSMichael Chan #define BNXT_FLAG_DOUBLE_DB 0x400000
2217feeef68fSMichael Chan #define BNXT_FLAG_UDP_GSO_CAP 0x800000
22183e8060faSPrashant Sreedharan #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
22196a8788f2SAndy Gospodarek #define BNXT_FLAG_DIM 0x2000000
2220abe93ad2SMichael Chan #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000
22216dea3ebeSMichael Chan #define BNXT_FLAG_TX_COAL_CMPL 0x8000000
222200db3cbaSVasundhara Volam #define BNXT_FLAG_PORT_STATS_EXT 0x10000000
22236e6c5a57SMichael Chan
2224c0c050c5SMichael Chan #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
2225c0c050c5SMichael Chan BNXT_FLAG_RFS | \
2226c0c050c5SMichael Chan BNXT_FLAG_STRIP_VLAN)
2227c0c050c5SMichael Chan
2228c0c050c5SMichael Chan #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
2229c0c050c5SMichael Chan #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
2230567b2abeSSatish Baddipadige #define BNXT_NPAR(bp) ((bp)->port_partition_type)
22319e54e322SDeepak Khungar #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
22329e54e322SDeepak Khungar #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
2233b0d28207SMichael Chan #define BNXT_SH_PORT_CFG_OK(bp) (BNXT_PF(bp) && \
2234b0d28207SMichael Chan ((bp)->phy_flags & BNXT_PHY_FL_SHARED_PORT_CFG))
22353128e811SMichael Chan #define BNXT_PHY_CFG_ABLE(bp) ((BNXT_SINGLE_PF(bp) || \
2236b0d28207SMichael Chan BNXT_SH_PORT_CFG_OK(bp)) && \
22373128e811SMichael Chan (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
22383e8060faSPrashant Sreedharan #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
2239c61fb99cSMichael Chan #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
2240e38287b7SMichael Chan #define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \
22411c7fd6eeSRandy Schacher (!((bp)->flags & BNXT_FLAG_CHIP_P5_PLUS) ||\
22427c380918SMichael Chan (bp)->max_tpa_v2) && !is_kdump_kernel())
224332861236SAndy Gospodarek #define BNXT_RX_JUMBO_MODE(bp) ((bp)->flags & BNXT_FLAG_JUMBO)
2244c0c050c5SMichael Chan
2245a432a45bSMichael Chan #define BNXT_CHIP_P7(bp) \
2246a432a45bSMichael Chan ((bp)->chip_num == CHIP_NUM_57608)
22479d6b648cSMichael Chan
22481c7fd6eeSRandy Schacher #define BNXT_CHIP_P5(bp) \
22491dc88b97SMichael Chan ((bp)->chip_num == CHIP_NUM_57508 || \
22501dc88b97SMichael Chan (bp)->chip_num == CHIP_NUM_57504 || \
22511dc88b97SMichael Chan (bp)->chip_num == CHIP_NUM_57502)
2252e38287b7SMichael Chan
22539d6b648cSMichael Chan /* Chip class phase 5 */
22541c7fd6eeSRandy Schacher #define BNXT_CHIP_P5_PLUS(bp) \
2255a432a45bSMichael Chan (BNXT_CHIP_P5(bp) || BNXT_CHIP_P7(bp))
22569d6b648cSMichael Chan
2257e38287b7SMichael Chan /* Chip class phase 4.x */
2258e38287b7SMichael Chan #define BNXT_CHIP_P4(bp) \
22593284f9e1SMichael Chan (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
22603284f9e1SMichael Chan BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
22614a58139bSRay Jui BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
22623284f9e1SMichael Chan (BNXT_CHIP_NUM_58700((bp)->chip_num) && \
22633284f9e1SMichael Chan !BNXT_CHIP_TYPE_NITRO_A0(bp)))
22643284f9e1SMichael Chan
22654d588d32SPavan Chebbi /* Chip class phase 3.x */
22664d588d32SPavan Chebbi #define BNXT_CHIP_P3(bp) \
22674d588d32SPavan Chebbi (BNXT_CHIP_NUM_57X0X((bp)->chip_num) || \
22684d588d32SPavan Chebbi BNXT_CHIP_TYPE_NITRO_A0(bp))
22694d588d32SPavan Chebbi
2270e38287b7SMichael Chan #define BNXT_CHIP_P4_PLUS(bp) \
22711c7fd6eeSRandy Schacher (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5_PLUS(bp))
2272e38287b7SMichael Chan
22734d588d32SPavan Chebbi #define BNXT_CHIP_P5_AND_MINUS(bp) \
22744d588d32SPavan Chebbi (BNXT_CHIP_P3(bp) || BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
22754d588d32SPavan Chebbi
2276d80d88b0SAjit Khaparde struct bnxt_aux_priv *aux_priv;
2277a588e458SMichael Chan struct bnxt_en_dev *edev;
2278a588e458SMichael Chan
2279c0c050c5SMichael Chan struct bnxt_napi **bnapi;
2280c0c050c5SMichael Chan
2281b6ab4b01SMichael Chan struct bnxt_rx_ring_info *rx_ring;
2282b6ab4b01SMichael Chan struct bnxt_tx_ring_info *tx_ring;
2283a960dec9SMichael Chan u16 *tx_ring_map;
2284b6ab4b01SMichael Chan
2285309369c9SMichael Chan struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int,
2286309369c9SMichael Chan struct sk_buff *);
2287309369c9SMichael Chan
22886bb19474SMichael Chan struct sk_buff * (*rx_skb_func)(struct bnxt *,
22896bb19474SMichael Chan struct bnxt_rx_ring_info *,
22906bb19474SMichael Chan u16, void *, u8 *, dma_addr_t,
22916bb19474SMichael Chan unsigned int);
22926bb19474SMichael Chan
229379632e9bSMichael Chan u16 max_tpa_v2;
229479632e9bSMichael Chan u16 max_tpa;
2295c0c050c5SMichael Chan u32 rx_buf_size;
2296c0c050c5SMichael Chan u32 rx_buf_use_size; /* useable size */
2297b3dba77cSMichael Chan u16 rx_offset;
2298b3dba77cSMichael Chan u16 rx_dma_offset;
2299745fc05cSMichael Chan enum dma_data_direction rx_dir;
2300c0c050c5SMichael Chan u32 rx_ring_size;
2301c0c050c5SMichael Chan u32 rx_agg_ring_size;
2302c0c050c5SMichael Chan u32 rx_copy_thresh;
2303c0c050c5SMichael Chan u32 rx_ring_mask;
2304c0c050c5SMichael Chan u32 rx_agg_ring_mask;
2305c0c050c5SMichael Chan int rx_nr_pages;
2306c0c050c5SMichael Chan int rx_agg_nr_pages;
2307c0c050c5SMichael Chan int rx_nr_rings;
2308c0c050c5SMichael Chan int rsscos_nr_ctxs;
2309c0c050c5SMichael Chan
2310c0c050c5SMichael Chan u32 tx_ring_size;
2311c0c050c5SMichael Chan u32 tx_ring_mask;
2312c0c050c5SMichael Chan int tx_nr_pages;
2313c0c050c5SMichael Chan int tx_nr_rings;
2314c0c050c5SMichael Chan int tx_nr_rings_per_tc;
23155f449249SMichael Chan int tx_nr_rings_xdp;
2316c0c050c5SMichael Chan
2317c0c050c5SMichael Chan int tx_wake_thresh;
2318c0c050c5SMichael Chan int tx_push_thresh;
2319c0c050c5SMichael Chan int tx_push_size;
2320c0c050c5SMichael Chan
2321c0c050c5SMichael Chan u32 cp_ring_size;
2322c0c050c5SMichael Chan u32 cp_ring_mask;
2323c0c050c5SMichael Chan u32 cp_bit;
2324c0c050c5SMichael Chan int cp_nr_pages;
2325c0c050c5SMichael Chan int cp_nr_rings;
2326c0c050c5SMichael Chan
2327b81a90d3SMichael Chan /* grp_info indexed by completion ring index */
2328c0c050c5SMichael Chan struct bnxt_ring_grp_info *grp_info;
2329c0c050c5SMichael Chan struct bnxt_vnic_info *vnic_info;
2330fea41bd7SPavan Chebbi u32 num_rss_ctx;
2331c0c050c5SMichael Chan int nr_vnics;
233273afb518SJakub Kicinski u32 *rss_indir_tbl;
23331667cbf6SMichael Chan u16 rss_indir_tbl_entries;
233487da7f79SMichael Chan u32 rss_hash_cfg;
233598a4322bSEdwin Peer u32 rss_hash_delta;
23368243345bSAjit Khaparde u32 rss_cap;
23378243345bSAjit Khaparde #define BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA BIT(0)
23388243345bSAjit Khaparde #define BNXT_RSS_CAP_UDP_RSS_CAP BIT(1)
23398243345bSAjit Khaparde #define BNXT_RSS_CAP_NEW_RSS_CAP BIT(2)
234013d2d3d3SMichael Chan #define BNXT_RSS_CAP_RSS_TCAM BIT(3)
23410c36211bSAjit Khaparde #define BNXT_RSS_CAP_AH_V4_RSS_CAP BIT(4)
23420c36211bSAjit Khaparde #define BNXT_RSS_CAP_AH_V6_RSS_CAP BIT(5)
23430c36211bSAjit Khaparde #define BNXT_RSS_CAP_ESP_V4_RSS_CAP BIT(6)
23440c36211bSAjit Khaparde #define BNXT_RSS_CAP_ESP_V6_RSS_CAP BIT(7)
2345fea41bd7SPavan Chebbi #define BNXT_RSS_CAP_MULTI_RSS_CTX BIT(8)
2346c0c050c5SMichael Chan
23475de1fce3SPavan Chebbi u8 rss_hash_key[HW_HASH_KEY_SIZE];
23485de1fce3SPavan Chebbi u8 rss_hash_key_valid:1;
23495de1fce3SPavan Chebbi u8 rss_hash_key_updated:1;
23505de1fce3SPavan Chebbi
23517eb9bb3aSMichael Chan u16 max_mtu;
2352b7bfcb4cSMichael Chan u16 tso_max_segs;
2353c0c050c5SMichael Chan u8 max_tc;
235487c374deSMichael Chan u8 max_lltc; /* lossless TCs */
2355c0c050c5SMichael Chan struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
23562e8ef77eSMichael Chan u8 tc_to_qidx[BNXT_MAX_QUEUE];
235798f04cf0SMichael Chan u8 q_ids[BNXT_MAX_QUEUE];
235898f04cf0SMichael Chan u8 max_q;
2359467739baSMichael Chan u8 num_tc;
2360c0c050c5SMichael Chan
2361c0c050c5SMichael Chan unsigned int current_interval;
23623bdf56c4SMichael Chan #define BNXT_TIMER_INTERVAL HZ
2363c0c050c5SMichael Chan
2364c0c050c5SMichael Chan struct timer_list timer;
2365c0c050c5SMichael Chan
2366caefe526SMichael Chan unsigned long state;
2367caefe526SMichael Chan #define BNXT_STATE_OPEN 0
23684cebdcecSMichael Chan #define BNXT_STATE_IN_SP_TASK 1
2369f9b76ebdSMichael Chan #define BNXT_STATE_READ_STATS 2
2370ec5d31e3SMichael Chan #define BNXT_STATE_FW_RESET_DET 3
23713bc7d4a3SMichael Chan #define BNXT_STATE_IN_FW_RESET 4
2372ec5d31e3SMichael Chan #define BNXT_STATE_ABORT_ERR 5
2373b4fff207SMichael Chan #define BNXT_STATE_FW_FATAL_COND 6
2374bdb38602SVasundhara Volam #define BNXT_STATE_DRV_REGISTERED 7
2375f75d9a0aSVasundhara Volam #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8
2376e340a5c4SMichael Chan #define BNXT_STATE_NAPI_DISABLED 9
2377662c9b22SEdwin Peer #define BNXT_STATE_L2_FILTER_RETRY 10
23788f6c5e4dSEdwin Peer #define BNXT_STATE_FW_ACTIVATE 11
2379aadb0b1aSEdwin Peer #define BNXT_STATE_RECOVER 12
2380aadb0b1aSEdwin Peer #define BNXT_STATE_FW_NON_FATAL_COND 13
23818f6c5e4dSEdwin Peer #define BNXT_STATE_FW_ACTIVATE_RESET 14
2382cfcab3b3SMichael Chan #define BNXT_STATE_HALF_OPEN 15 /* For offline ethtool tests */
2383c0c050c5SMichael Chan
2384b340dc68SVasundhara Volam #define BNXT_NO_FW_ACCESS(bp) \
2385b340dc68SVasundhara Volam (test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) || \
2386b340dc68SVasundhara Volam pci_channel_offline((bp)->pdev))
2387b340dc68SVasundhara Volam
2388c0c050c5SMichael Chan struct bnxt_irq *irq_tbl;
23897809592dSMichael Chan int total_irqs;
23902e4592dcSVikas Gupta int ulp_num_msix_want;
2391c0c050c5SMichael Chan u8 mac_addr[ETH_ALEN];
2392c0c050c5SMichael Chan
23937df4ae9fSMichael Chan #ifdef CONFIG_BNXT_DCB
23947df4ae9fSMichael Chan struct ieee_pfc *ieee_pfc;
23957df4ae9fSMichael Chan struct ieee_ets *ieee_ets;
23967df4ae9fSMichael Chan u8 dcbx_cap;
23977df4ae9fSMichael Chan u8 default_pri;
2398afdc8a84SMichael Chan u8 max_dscp_value;
23997df4ae9fSMichael Chan #endif /* CONFIG_BNXT_DCB */
24007df4ae9fSMichael Chan
2401c0c050c5SMichael Chan u32 msg_enable;
2402c0c050c5SMichael Chan
2403a3a4e300SPavan Chebbi u64 fw_cap;
2404a3a4e300SPavan Chebbi #define BNXT_FW_CAP_SHORT_CMD BIT_ULL(0)
2405a3a4e300SPavan Chebbi #define BNXT_FW_CAP_LLDP_AGENT BIT_ULL(1)
2406a3a4e300SPavan Chebbi #define BNXT_FW_CAP_DCBX_AGENT BIT_ULL(2)
2407a3a4e300SPavan Chebbi #define BNXT_FW_CAP_NEW_RM BIT_ULL(3)
2408a3a4e300SPavan Chebbi #define BNXT_FW_CAP_IF_CHANGE BIT_ULL(4)
2409a3a4e300SPavan Chebbi #define BNXT_FW_CAP_KONG_MB_CHNL BIT_ULL(7)
2410a3a4e300SPavan Chebbi #define BNXT_FW_CAP_OVS_64BIT_HANDLE BIT_ULL(10)
2411a3a4e300SPavan Chebbi #define BNXT_FW_CAP_TRUSTED_VF BIT_ULL(11)
2412a3a4e300SPavan Chebbi #define BNXT_FW_CAP_ERROR_RECOVERY BIT_ULL(13)
2413a3a4e300SPavan Chebbi #define BNXT_FW_CAP_PKG_VER BIT_ULL(14)
2414a3a4e300SPavan Chebbi #define BNXT_FW_CAP_CFA_ADV_FLOW BIT_ULL(15)
2415a3a4e300SPavan Chebbi #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 BIT_ULL(16)
2416a3a4e300SPavan Chebbi #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED BIT_ULL(17)
2417a3a4e300SPavan Chebbi #define BNXT_FW_CAP_EXT_STATS_SUPPORTED BIT_ULL(18)
24181d294b4fSMichael Chan #define BNXT_FW_CAP_TX_TS_CMP BIT_ULL(19)
2419a3a4e300SPavan Chebbi #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT_ULL(20)
2420a3a4e300SPavan Chebbi #define BNXT_FW_CAP_HOT_RESET BIT_ULL(21)
2421a3a4e300SPavan Chebbi #define BNXT_FW_CAP_PTP_RTC BIT_ULL(22)
2422a3a4e300SPavan Chebbi #define BNXT_FW_CAP_RX_ALL_PKT_TS BIT_ULL(23)
2423a3a4e300SPavan Chebbi #define BNXT_FW_CAP_VLAN_RX_STRIP BIT_ULL(24)
2424a3a4e300SPavan Chebbi #define BNXT_FW_CAP_VLAN_TX_INSERT BIT_ULL(25)
2425a3a4e300SPavan Chebbi #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED BIT_ULL(26)
2426a3a4e300SPavan Chebbi #define BNXT_FW_CAP_LIVEPATCH BIT_ULL(27)
2427a3a4e300SPavan Chebbi #define BNXT_FW_CAP_PTP_PPS BIT_ULL(28)
2428a3a4e300SPavan Chebbi #define BNXT_FW_CAP_HOT_RESET_IF BIT_ULL(29)
2429a3a4e300SPavan Chebbi #define BNXT_FW_CAP_RING_MONITOR BIT_ULL(30)
2430a3a4e300SPavan Chebbi #define BNXT_FW_CAP_DBG_QCAPS BIT_ULL(31)
2431edc52873SPavan Chebbi #define BNXT_FW_CAP_PTP BIT_ULL(32)
2432cd13244fSKalesh AP #define BNXT_FW_CAP_THRESHOLD_TEMP_SUPPORTED BIT_ULL(33)
2433e76d44feSSreekanth Reddy #define BNXT_FW_CAP_DFLT_VLAN_TPID_PCP BIT_ULL(34)
2434cbdbf0aaSVikas Gupta #define BNXT_FW_CAP_PRE_RESV_VNICS BIT_ULL(35)
24356a4d0774SMichael Chan #define BNXT_FW_CAP_BACKING_STORE_V2 BIT_ULL(36)
243696009633SMichael Chan #define BNXT_FW_CAP_VNIC_TUNNEL_TPA BIT_ULL(37)
24379ba0e561SVikas Gupta #define BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO BIT_ULL(38)
2438532c034eSPavan Chebbi #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V3 BIT_ULL(39)
24396e360862SMichael Chan #define BNXT_FW_CAP_VNIC_RE_FLUSH BIT_ULL(40)
244080194db9SVasundhara Volam
244180194db9SVasundhara Volam u32 fw_dbg_cap;
244297381a18SMichael Chan
244397381a18SMichael Chan #define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
2444131db499SVadim Fedorenko #define BNXT_PTP_USE_RTC(bp) (!BNXT_MH(bp) && \
2445131db499SVadim Fedorenko ((bp)->fw_cap & BNXT_FW_CAP_PTP_RTC))
2446532c034eSPavan Chebbi #define BNXT_SUPPORTS_NTUPLE_VNIC(bp) \
2447532c034eSPavan Chebbi (BNXT_PF(bp) && ((bp)->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V3))
2448532c034eSPavan Chebbi
2449fea41bd7SPavan Chebbi #define BNXT_SUPPORTS_MULTI_RSS_CTX(bp) \
2450fea41bd7SPavan Chebbi (BNXT_PF(bp) && BNXT_SUPPORTS_NTUPLE_VNIC(bp) && \
2451fea41bd7SPavan Chebbi ((bp)->rss_cap & BNXT_RSS_CAP_MULTI_RSS_CTX))
245297cbf3d0SDavid Wei #define BNXT_SUPPORTS_QUEUE_API(bp) \
245397cbf3d0SDavid Wei (BNXT_PF(bp) && BNXT_SUPPORTS_NTUPLE_VNIC(bp) && \
245497cbf3d0SDavid Wei ((bp)->fw_cap & BNXT_FW_CAP_VNIC_RE_FLUSH))
2455fea41bd7SPavan Chebbi
245611f15ed3SMichael Chan u32 hwrm_spec_code;
2457c0c050c5SMichael Chan u16 hwrm_cmd_seq;
2458760b6d33SVenkat Duvvuru u16 hwrm_cmd_kong_seq;
2459f9ff5782SEdwin Peer struct dma_pool *hwrm_dma_pool;
246068f684e2SEdwin Peer struct hlist_head hwrm_pending_list;
24613bdf56c4SMichael Chan
2462b8875ca3SMichael Chan struct rtnl_link_stats64 net_stats_prev;
2463177a6cdeSMichael Chan struct bnxt_stats_mem port_stats;
2464177a6cdeSMichael Chan struct bnxt_stats_mem rx_port_stats_ext;
2465177a6cdeSMichael Chan struct bnxt_stats_mem tx_port_stats_ext;
246636e53349SMichael Chan u16 fw_rx_stats_ext_size;
246736e53349SMichael Chan u16 fw_tx_stats_ext_size;
24684e748506SMichael Chan u16 hw_ring_stats_size;
2469a24ec322SMichael Chan u8 pri2cos_idx[8];
2470e37fed79SMichael Chan u8 pri2cos_valid;
24713bdf56c4SMichael Chan
24724c70dbe3SMichael Chan struct bnxt_total_ring_err_stats ring_err_stats_prev;
24734c70dbe3SMichael Chan
2474e6ef2699SMichael Chan u16 hwrm_max_req_len;
24751dfddc41SMichael Chan u16 hwrm_max_ext_req_len;
2476bce9a0b7SEdwin Peer unsigned int hwrm_cmd_timeout;
2477bce9a0b7SEdwin Peer unsigned int hwrm_cmd_max_timeout;
2478c0c050c5SMichael Chan struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
2479c0c050c5SMichael Chan struct hwrm_ver_get_output ver_resp;
2480c0c050c5SMichael Chan #define FW_VER_STR_LEN 32
2481c0c050c5SMichael Chan #define BC_HWRM_STR_LEN 21
2482c0c050c5SMichael Chan #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
2483c0c050c5SMichael Chan char fw_ver_str[FW_VER_STR_LEN];
2484b7a444f0SVasundhara Volam char hwrm_ver_supp[FW_VER_STR_LEN];
24854933f675SVasundhara Volam char nvm_cfg_ver[FW_VER_STR_LEN];
2486d0ad2ea2SMichael Chan u64 fw_ver_code;
2487d0ad2ea2SMichael Chan #define BNXT_FW_VER_CODE(maj, min, bld, rsv) \
2488d0ad2ea2SMichael Chan ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
2489fed7edd1SMichael Chan #define BNXT_FW_MAJ(bp) ((bp)->fw_ver_code >> 48)
2490cbdbf0aaSVikas Gupta #define BNXT_FW_BLD(bp) (((bp)->fw_ver_code >> 16) & 0xffff)
2491d0ad2ea2SMichael Chan
2492442a35a5SJakub Kicinski u16 vxlan_fw_dst_port_id;
2493442a35a5SJakub Kicinski u16 nge_fw_dst_port_id;
249477b0fff5SMichael Chan u16 vxlan_gpe_fw_dst_port_id;
24951698d600SMichael Chan __be16 vxlan_port;
24961698d600SMichael Chan __be16 nge_port;
249777b0fff5SMichael Chan __be16 vxlan_gpe_port;
2498567b2abeSSatish Baddipadige u8 port_partition_type;
2499d5430d31SMichael Chan u8 port_count;
250032e8239cSMichael Chan u16 br_mode;
2501dfc9c94aSMichael Chan
250274706afaSMichael Chan struct bnxt_coal_cap coal_cap;
250318775aa8SMichael Chan struct bnxt_coal rx_coal;
250418775aa8SMichael Chan struct bnxt_coal tx_coal;
2505c0c050c5SMichael Chan
250651f30785SMichael Chan u32 stats_coal_ticks;
250751f30785SMichael Chan #define BNXT_DEF_STATS_COAL_TICKS 1000000
250851f30785SMichael Chan #define BNXT_MIN_STATS_COAL_TICKS 250000
250951f30785SMichael Chan #define BNXT_MAX_STATS_COAL_TICKS 1000000
251051f30785SMichael Chan
2511c0c050c5SMichael Chan struct work_struct sp_task;
2512c0c050c5SMichael Chan unsigned long sp_event;
2513c0c050c5SMichael Chan #define BNXT_RX_MASK_SP_EVENT 0
2514c0c050c5SMichael Chan #define BNXT_RX_NTP_FLTR_SP_EVENT 1
2515c0c050c5SMichael Chan #define BNXT_LINK_CHNG_SP_EVENT 2
2516c5d7774dSJeffrey Huang #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
2517c5d7774dSJeffrey Huang #define BNXT_RESET_TASK_SP_EVENT 6
2518c5d7774dSJeffrey Huang #define BNXT_RST_RING_SP_EVENT 7
251919241368SJeffrey Huang #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
25203bdf56c4SMichael Chan #define BNXT_PERIODIC_STATS_SP_EVENT 9
25214bb13abfSMichael Chan #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
2522fc0f1929SMichael Chan #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
2523286ef9d6SMichael Chan #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
25245a84acbeSSathya Perla #define BNXT_FLOW_STATS_SP_EVENT 15
2525a1ef4a79SMichael Chan #define BNXT_UPDATE_PHY_SP_EVENT 16
2526ffd77621SMichael Chan #define BNXT_RING_COAL_NOW_SP_EVENT 17
25272151fe08SMichael Chan #define BNXT_FW_RESET_NOTIFY_SP_EVENT 18
2528acfb50e4SVasundhara Volam #define BNXT_FW_EXCEPTION_SP_EVENT 19
2529b1613e78SMichael Chan #define BNXT_LINK_CFG_CHANGE_SP_EVENT 21
253055862094SKalesh AP #define BNXT_THERMAL_THRESHOLD_SP_EVENT 22
2531df97b34dSMichael Chan #define BNXT_FW_ECHO_REQUEST_SP_EVENT 23
25323c163f35SKalesh AP #define BNXT_RESTART_ULP_SP_EVENT 24
25332151fe08SMichael Chan
2534230d1f0dSMichael Chan struct delayed_work fw_reset_task;
2535230d1f0dSMichael Chan int fw_reset_state;
2536230d1f0dSMichael Chan #define BNXT_FW_RESET_STATE_POLL_VF 1
2537230d1f0dSMichael Chan #define BNXT_FW_RESET_STATE_RESET_FW 2
2538230d1f0dSMichael Chan #define BNXT_FW_RESET_STATE_ENABLE_DEV 3
2539230d1f0dSMichael Chan #define BNXT_FW_RESET_STATE_POLL_FW 4
2540230d1f0dSMichael Chan #define BNXT_FW_RESET_STATE_OPENING 5
25414037eb71SVasundhara Volam #define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6
2542230d1f0dSMichael Chan
25432151fe08SMichael Chan u16 fw_reset_min_dsecs;
25442151fe08SMichael Chan #define BNXT_DFLT_FW_RST_MIN_DSECS 20
25452151fe08SMichael Chan u16 fw_reset_max_dsecs;
25462151fe08SMichael Chan #define BNXT_DFLT_FW_RST_MAX_DSECS 60
25472151fe08SMichael Chan unsigned long fw_reset_timestamp;
2548c0c050c5SMichael Chan
254907f83d72SMichael Chan struct bnxt_fw_health *fw_health;
255007f83d72SMichael Chan
25516a4f2947SMichael Chan struct bnxt_hw_resc hw_resc;
2552379a80a1SMichael Chan struct bnxt_pf_info pf;
255398f04cf0SMichael Chan struct bnxt_ctx_mem_info *ctx;
2554c0c050c5SMichael Chan #ifdef CONFIG_BNXT_SRIOV
2555c0c050c5SMichael Chan int nr_vfs;
2556c0c050c5SMichael Chan struct bnxt_vf_info vf;
2557c0c050c5SMichael Chan wait_queue_head_t sriov_cfg_wait;
2558c0c050c5SMichael Chan bool sriov_cfg;
2559c0c050c5SMichael Chan #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
2560c0c050c5SMichael Chan #endif
2561c0c050c5SMichael Chan
2562c6132f6fSMichael Chan #if BITS_PER_LONG == 32
2563697197e5SMichael Chan /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
2564697197e5SMichael Chan spinlock_t db_lock;
2565697197e5SMichael Chan #endif
2566d3c16475SHongguang Gao int db_offset; /* db_offset within db_size */
25678ae24738SMichael Chan int db_size;
2568697197e5SMichael Chan
2569c0c050c5SMichael Chan #define BNXT_NTP_FLTR_MAX_FLTR 4096
257096c9bedcSMichael Chan #define BNXT_MAX_FLTR (BNXT_NTP_FLTR_MAX_FLTR + BNXT_L2_FLTR_MAX_FLTR)
2571c0c050c5SMichael Chan #define BNXT_NTP_FLTR_HASH_SIZE 512
2572c0c050c5SMichael Chan #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
2573c0c050c5SMichael Chan struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
2574c0c050c5SMichael Chan spinlock_t ntp_fltr_lock; /* for hash table add, del */
2575c0c050c5SMichael Chan
2576c0c050c5SMichael Chan unsigned long *ntp_fltr_bmap;
2577c0c050c5SMichael Chan int ntp_fltr_count;
2578f42822f2SMichael Chan int max_fltr;
2579c0c050c5SMichael Chan
25801f6e77cbSMichael Chan #define BNXT_L2_FLTR_MAX_FLTR 1024
25811f6e77cbSMichael Chan #define BNXT_L2_FLTR_HASH_SIZE 32
25821f6e77cbSMichael Chan #define BNXT_L2_FLTR_HASH_MASK (BNXT_L2_FLTR_HASH_SIZE - 1)
25831f6e77cbSMichael Chan struct hlist_head l2_fltr_hash_tbl[BNXT_L2_FLTR_HASH_SIZE];
25841f6e77cbSMichael Chan
25851f6e77cbSMichael Chan u32 hash_seed;
2586d3c98285SPavan Chebbi u64 toeplitz_prefix;
25871f6e77cbSMichael Chan
25888336a974SPavan Chebbi struct list_head usr_fltr_list;
25898336a974SPavan Chebbi
2590e2dc9b6eSMichael Chan /* To protect link related settings during link changes and
2591e2dc9b6eSMichael Chan * ethtool settings changes.
2592e2dc9b6eSMichael Chan */
2593e2dc9b6eSMichael Chan struct mutex link_lock;
2594c0c050c5SMichael Chan struct bnxt_link_info link_info;
2595d80a5233SHeiner Kallweit struct ethtool_keee eee;
2596170ce013SMichael Chan u32 lpi_tmr_lo;
2597170ce013SMichael Chan u32 lpi_tmr_hi;
25985ad2cbeeSMichael Chan
25999a3bc77eSMichael Chan /* copied from flags and flags2 in hwrm_port_phy_qcaps_output */
26009a3bc77eSMichael Chan u32 phy_flags;
2601b0d28207SMichael Chan #define BNXT_PHY_FL_EEE_CAP PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED
2602b0d28207SMichael Chan #define BNXT_PHY_FL_EXT_LPBK PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED
2603b0d28207SMichael Chan #define BNXT_PHY_FL_AN_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED
2604b0d28207SMichael Chan #define BNXT_PHY_FL_SHARED_PORT_CFG PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED
2605b0d28207SMichael Chan #define BNXT_PHY_FL_PORT_STATS_NO_RESET PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET
2606b0d28207SMichael Chan #define BNXT_PHY_FL_NO_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED
2607d5ca9905SMichael Chan #define BNXT_PHY_FL_FW_MANAGED_LKDN PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN
2608dade5e15SMichael Chan #define BNXT_PHY_FL_NO_FCS PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS
26099a3bc77eSMichael Chan #define BNXT_PHY_FL_NO_PAUSE (PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED << 8)
26109a3bc77eSMichael Chan #define BNXT_PHY_FL_NO_PFC (PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED << 8)
26117ef3d390SVikas Gupta #define BNXT_PHY_FL_BANK_SEL (PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED << 8)
261230c0bb63SMichael Chan #define BNXT_PHY_FL_SPEEDS2 (PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED << 8)
2613b0d28207SMichael Chan
2614eb513658SMichael Chan u8 num_tests;
2615eb513658SMichael Chan struct bnxt_test_info *test_info;
2616eb513658SMichael Chan
2617c1ef146aSMichael Chan u8 wol_filter_id;
2618c1ef146aSMichael Chan u8 wol;
2619c1ef146aSMichael Chan
26205ad2cbeeSMichael Chan u8 num_leds;
26215ad2cbeeSMichael Chan struct bnxt_led_info leds[BNXT_MAX_LED];
26220b0eacf3SVasundhara Volam u16 dump_flag;
26230b0eacf3SVasundhara Volam #define BNXT_DUMP_LIVE 0
26240b0eacf3SVasundhara Volam #define BNXT_DUMP_CRASH 1
2625c6d30e83SMichael Chan
2626c6d30e83SMichael Chan struct bpf_prog *xdp_prog;
26274ab0c6a8SSathya Perla
2628ae5c42f0SMichael Chan struct bnxt_ptp_cfg *ptp_cfg;
262966ed81dcSPavan Chebbi u8 ptp_all_rx_tstamp;
2630ae5c42f0SMichael Chan
26314ab0c6a8SSathya Perla /* devlink interface and vf-rep structs */
26324ab0c6a8SSathya Perla struct devlink *dl;
2633782a624dSVasundhara Volam struct devlink_port dl_port;
26344ab0c6a8SSathya Perla enum devlink_eswitch_mode eswitch_mode;
26354ab0c6a8SSathya Perla struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */
26364ab0c6a8SSathya Perla u16 *cfa_code_map; /* cfa_code -> vf_idx map */
2637b014232fSVasundhara Volam u8 dsn[8];
2638cd66358eSSathya Perla struct bnxt_tc_info *tc_info;
2639627c89d0SSriharsha Basavapatna struct list_head tc_indr_block_list;
2640cabfb09dSAndy Gospodarek struct dentry *debugfs_pdev;
2641cd13244fSKalesh AP #ifdef CONFIG_BNXT_HWMON
2642cde49a42SVasundhara Volam struct device *hwmon_dev;
2643cd13244fSKalesh AP u8 warn_thresh_temp;
2644cd13244fSKalesh AP u8 crit_thresh_temp;
2645cd13244fSKalesh AP u8 fatal_thresh_temp;
2646cd13244fSKalesh AP u8 shutdown_thresh_temp;
2647cd13244fSKalesh AP #endif
264855862094SKalesh AP u32 thermal_threshold_type;
2649c7dd4a5bSEdwin Peer enum board_idx board_idx;
2650c33626d8SVikas Gupta
2651c33626d8SVikas Gupta struct bnxt_ctx_pg_info *fw_crash_mem;
2652c33626d8SVikas Gupta u32 fw_crash_len;
2653c0c050c5SMichael Chan };
2654c0c050c5SMichael Chan
26559d6b648cSMichael Chan #define BNXT_NUM_RX_RING_STATS 8
26569d6b648cSMichael Chan #define BNXT_NUM_TX_RING_STATS 8
26579d6b648cSMichael Chan #define BNXT_NUM_TPA_RING_STATS 4
26589d6b648cSMichael Chan #define BNXT_NUM_TPA_RING_STATS_P5 5
2659a432a45bSMichael Chan #define BNXT_NUM_TPA_RING_STATS_P7 6
26609d6b648cSMichael Chan
26619d6b648cSMichael Chan #define BNXT_RING_STATS_SIZE_P5 \
26629d6b648cSMichael Chan ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
26639d6b648cSMichael Chan BNXT_NUM_TPA_RING_STATS_P5) * 8)
26649d6b648cSMichael Chan
2665a432a45bSMichael Chan #define BNXT_RING_STATS_SIZE_P7 \
26669d6b648cSMichael Chan ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
2667a432a45bSMichael Chan BNXT_NUM_TPA_RING_STATS_P7) * 8)
26689d6b648cSMichael Chan
2669a0c30621SMichael Chan #define BNXT_GET_RING_STATS64(sw, counter) \
2670a0c30621SMichael Chan (*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
2671a0c30621SMichael Chan
2672a0c30621SMichael Chan #define BNXT_GET_RX_PORT_STATS64(sw, counter) \
2673a0c30621SMichael Chan (*((sw) + offsetof(struct rx_port_stats, counter) / 8))
2674a0c30621SMichael Chan
2675a0c30621SMichael Chan #define BNXT_GET_TX_PORT_STATS64(sw, counter) \
2676a0c30621SMichael Chan (*((sw) + offsetof(struct tx_port_stats, counter) / 8))
2677a0c30621SMichael Chan
267824c93443SMichael Chan #define BNXT_PORT_STATS_SIZE \
267924c93443SMichael Chan (sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)
268024c93443SMichael Chan
268124c93443SMichael Chan #define BNXT_TX_PORT_STATS_BYTE_OFFSET \
268224c93443SMichael Chan (sizeof(struct rx_port_stats) + 512)
268324c93443SMichael Chan
2684c77192f2SMichael Chan #define BNXT_RX_STATS_OFFSET(counter) \
2685c77192f2SMichael Chan (offsetof(struct rx_port_stats, counter) / 8)
2686c77192f2SMichael Chan
2687c77192f2SMichael Chan #define BNXT_TX_STATS_OFFSET(counter) \
2688c77192f2SMichael Chan ((offsetof(struct tx_port_stats, counter) + \
268924c93443SMichael Chan BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)
2690c77192f2SMichael Chan
269100db3cbaSVasundhara Volam #define BNXT_RX_STATS_EXT_OFFSET(counter) \
269200db3cbaSVasundhara Volam (offsetof(struct rx_port_stats_ext, counter) / 8)
269300db3cbaSVasundhara Volam
269421e70778SMichael Chan #define BNXT_RX_STATS_EXT_NUM_LEGACY \
269521e70778SMichael Chan BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)
269621e70778SMichael Chan
269736e53349SMichael Chan #define BNXT_TX_STATS_EXT_OFFSET(counter) \
269836e53349SMichael Chan (offsetof(struct tx_port_stats_ext, counter) / 8)
269936e53349SMichael Chan
2700a196e96bSEdwin Peer #define BNXT_HW_FEATURE_VLAN_ALL_RX \
2701a196e96bSEdwin Peer (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
2702a196e96bSEdwin Peer #define BNXT_HW_FEATURE_VLAN_ALL_TX \
2703a196e96bSEdwin Peer (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)
2704a196e96bSEdwin Peer
270542ee18feSAjit Khaparde #define I2C_DEV_ADDR_A0 0xa0
270642ee18feSAjit Khaparde #define I2C_DEV_ADDR_A2 0xa2
27077328a23cSVasundhara Volam #define SFF_DIAG_SUPPORT_OFFSET 0x5c
270842ee18feSAjit Khaparde #define SFF_MODULE_ID_SFP 0x3
270942ee18feSAjit Khaparde #define SFF_MODULE_ID_QSFP 0xc
271042ee18feSAjit Khaparde #define SFF_MODULE_ID_QSFP_PLUS 0xd
271142ee18feSAjit Khaparde #define SFF_MODULE_ID_QSFP28 0x11
271242ee18feSAjit Khaparde #define BNXT_MAX_PHY_I2C_RESP_SIZE 64
271342ee18feSAjit Khaparde
bnxt_tx_avail(struct bnxt * bp,const struct bnxt_tx_ring_info * txr)271436647b20SJakub Kicinski static inline u32 bnxt_tx_avail(struct bnxt *bp,
271536647b20SJakub Kicinski const struct bnxt_tx_ring_info *txr)
271638413406SMichael Chan {
271736647b20SJakub Kicinski u32 used = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons);
271838413406SMichael Chan
271936647b20SJakub Kicinski return bp->tx_ring_size - (used & bp->tx_ring_mask);
272038413406SMichael Chan }
272138413406SMichael Chan
bnxt_writeq(struct bnxt * bp,u64 val,volatile void __iomem * addr)2722c6132f6fSMichael Chan static inline void bnxt_writeq(struct bnxt *bp, u64 val,
2723c6132f6fSMichael Chan volatile void __iomem *addr)
2724c6132f6fSMichael Chan {
2725c6132f6fSMichael Chan #if BITS_PER_LONG == 32
2726c6132f6fSMichael Chan spin_lock(&bp->db_lock);
2727c6132f6fSMichael Chan lo_hi_writeq(val, addr);
2728c6132f6fSMichael Chan spin_unlock(&bp->db_lock);
2729c6132f6fSMichael Chan #else
2730c6132f6fSMichael Chan writeq(val, addr);
2731697197e5SMichael Chan #endif
2732c6132f6fSMichael Chan }
2733c6132f6fSMichael Chan
bnxt_writeq_relaxed(struct bnxt * bp,u64 val,volatile void __iomem * addr)2734c6132f6fSMichael Chan static inline void bnxt_writeq_relaxed(struct bnxt *bp, u64 val,
2735c6132f6fSMichael Chan volatile void __iomem *addr)
2736c6132f6fSMichael Chan {
2737c6132f6fSMichael Chan #if BITS_PER_LONG == 32
2738c6132f6fSMichael Chan spin_lock(&bp->db_lock);
2739c6132f6fSMichael Chan lo_hi_writeq_relaxed(val, addr);
2740c6132f6fSMichael Chan spin_unlock(&bp->db_lock);
2741c6132f6fSMichael Chan #else
2742c6132f6fSMichael Chan writeq_relaxed(val, addr);
2743c6132f6fSMichael Chan #endif
2744c6132f6fSMichael Chan }
2745697197e5SMichael Chan
2746fd141fa4SSinan Kaya /* For TX and RX ring doorbells with no ordering guarantee*/
bnxt_db_write_relaxed(struct bnxt * bp,struct bnxt_db_info * db,u32 idx)2747697197e5SMichael Chan static inline void bnxt_db_write_relaxed(struct bnxt *bp,
2748697197e5SMichael Chan struct bnxt_db_info *db, u32 idx)
2749fd141fa4SSinan Kaya {
27501c7fd6eeSRandy Schacher if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
2751b9e0c47eSMichael Chan bnxt_writeq_relaxed(bp, db->db_key64 | DB_RING_IDX(db, idx),
2752b9e0c47eSMichael Chan db->doorbell);
2753697197e5SMichael Chan } else {
2754b9e0c47eSMichael Chan u32 db_val = db->db_key32 | DB_RING_IDX(db, idx);
2755697197e5SMichael Chan
2756697197e5SMichael Chan writel_relaxed(db_val, db->doorbell);
2757fd141fa4SSinan Kaya if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2758697197e5SMichael Chan writel_relaxed(db_val, db->doorbell);
2759697197e5SMichael Chan }
2760fd141fa4SSinan Kaya }
2761fd141fa4SSinan Kaya
2762434c975aSMichael Chan /* For TX and RX ring doorbells */
bnxt_db_write(struct bnxt * bp,struct bnxt_db_info * db,u32 idx)2763697197e5SMichael Chan static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
2764697197e5SMichael Chan u32 idx)
2765434c975aSMichael Chan {
27661c7fd6eeSRandy Schacher if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
2767b9e0c47eSMichael Chan bnxt_writeq(bp, db->db_key64 | DB_RING_IDX(db, idx),
2768b9e0c47eSMichael Chan db->doorbell);
2769697197e5SMichael Chan } else {
2770b9e0c47eSMichael Chan u32 db_val = db->db_key32 | DB_RING_IDX(db, idx);
2771697197e5SMichael Chan
2772697197e5SMichael Chan writel(db_val, db->doorbell);
2773434c975aSMichael Chan if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2774697197e5SMichael Chan writel(db_val, db->doorbell);
2775697197e5SMichael Chan }
2776434c975aSMichael Chan }
2777434c975aSMichael Chan
27789f536391SMichael Chan /* Must hold rtnl_lock */
bnxt_sriov_cfg(struct bnxt * bp)27799f536391SMichael Chan static inline bool bnxt_sriov_cfg(struct bnxt *bp)
27809f536391SMichael Chan {
27819f536391SMichael Chan #if defined(CONFIG_BNXT_SRIOV)
27829f536391SMichael Chan return BNXT_PF(bp) && (bp->pf.active_vfs || bp->sriov_cfg);
27839f536391SMichael Chan #else
27849f536391SMichael Chan return false;
27859f536391SMichael Chan #endif
27869f536391SMichael Chan }
27879f536391SMichael Chan
278838413406SMichael Chan extern const u16 bnxt_lhint_arr[];
278938413406SMichael Chan
279038413406SMichael Chan int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
279138413406SMichael Chan u16 prod, gfp_t gfp);
2792c6d30e83SMichael Chan void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
27937e914027SMichael Chan u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
2794c6d30e83SMichael Chan void bnxt_set_tpa_flags(struct bnxt *bp);
2795c0c050c5SMichael Chan void bnxt_set_ring_params(struct bnxt *);
2796c61fb99cSMichael Chan int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
27978336a974SPavan Chebbi void bnxt_insert_usr_fltr(struct bnxt *bp, struct bnxt_filter_base *fltr);
27988336a974SPavan Chebbi void bnxt_del_one_usr_fltr(struct bnxt *bp, struct bnxt_filter_base *fltr);
27992e882468SVasundhara Volam int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,
28002e882468SVasundhara Volam int bmap_size, bool async_only);
2801228ea8c1SEdwin Peer int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp);
28021f6e77cbSMichael Chan void bnxt_del_l2_filter(struct bnxt *bp, struct bnxt_l2_filter *fltr);
2803e462998aSMichael Chan struct bnxt_l2_filter *bnxt_alloc_new_l2_filter(struct bnxt *bp,
2804e462998aSMichael Chan struct bnxt_l2_key *key,
2805e462998aSMichael Chan u16 flags);
280696c9bedcSMichael Chan int bnxt_hwrm_l2_filter_free(struct bnxt *bp, struct bnxt_l2_filter *fltr);
280796c9bedcSMichael Chan int bnxt_hwrm_l2_filter_alloc(struct bnxt *bp, struct bnxt_l2_filter *fltr);
28084faeadfdSMichael Chan int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
28094faeadfdSMichael Chan struct bnxt_ntuple_filter *fltr);
2810c029bc30SMichael Chan int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
2811c029bc30SMichael Chan struct bnxt_ntuple_filter *fltr);
2812b3d0083cSPavan Chebbi int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2813b3d0083cSPavan Chebbi u32 tpa_flags);
2814300c1918SMichael Chan void bnxt_fill_ipv6_mask(__be32 mask[4]);
281546e457a4SJakub Kicinski void bnxt_set_dflt_rss_indir_tbl(struct bnxt *bp,
281646e457a4SJakub Kicinski struct ethtool_rxfh_context *rss_ctx);
2817f9f6a3fbSMichael Chan int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);
2818a4c11166SPavan Chebbi int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic);
2819b3d0083cSPavan Chebbi int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2820b3d0083cSPavan Chebbi unsigned int start_rx_ring_idx,
2821b3d0083cSPavan Chebbi unsigned int nr_rings);
2822391be5c2SMichael Chan int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
2823b16b6891SMichael Chan int bnxt_nq_rings_in_use(struct bnxt *bp);
2824c0c050c5SMichael Chan int bnxt_hwrm_set_coal(struct bnxt *);
2825228ea8c1SEdwin Peer void bnxt_free_ctx_mem(struct bnxt *bp);
2826f5b29c6aSMichael Chan int bnxt_num_tx_to_cp(struct bnxt *bp, int tx);
2827e4060d30SMichael Chan unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
2828c027c6b4SVasundhara Volam unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
2829e4060d30SMichael Chan unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
2830e916b081SMichael Chan unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
28311b3f0b75SMichael Chan int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
28327df4ae9fSMichael Chan void bnxt_tx_disable(struct bnxt *bp);
28337df4ae9fSMichael Chan void bnxt_tx_enable(struct bnxt *bp);
28342b56b3d9SJakub Kicinski void bnxt_sched_reset_txr(struct bnxt *bp, struct bnxt_tx_ring_info *txr,
28357f0a168bSMichael Chan u16 curr);
2836228ea8c1SEdwin Peer void bnxt_report_link(struct bnxt *bp);
2837ccd6a9dcSMichael Chan int bnxt_update_link(struct bnxt *bp, bool chng_link_state);
2838c0c050c5SMichael Chan int bnxt_hwrm_set_pause(struct bnxt *);
2839939f7f0cSMichael Chan int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
2840d900aaddSEdwin Peer int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset);
28415282db6cSMichael Chan int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
28425282db6cSMichael Chan int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
2843db4723b3SMichael Chan int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
2844c5b744d3SKashyap Desai int bnxt_hwrm_func_qcaps(struct bnxt *bp);
28455ac67d8bSRob Swindell int bnxt_hwrm_fw_set_time(struct bnxt *);
2846f2878cdeSMichael Chan int bnxt_hwrm_vnic_update(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2847f2878cdeSMichael Chan u8 valid);
2848a4c11166SPavan Chebbi int bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic);
2849b3d0083cSPavan Chebbi int __bnxt_setup_vnic_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic);
2850fea41bd7SPavan Chebbi void bnxt_del_one_rss_ctx(struct bnxt *bp, struct bnxt_rss_ctx *rss_ctx,
2851fea41bd7SPavan Chebbi bool all);
2852c0c050c5SMichael Chan int bnxt_open_nic(struct bnxt *, bool, bool);
2853f7dc1ea6SMichael Chan int bnxt_half_open_nic(struct bnxt *bp);
2854f7dc1ea6SMichael Chan void bnxt_half_close_nic(struct bnxt *bp);
2855228ea8c1SEdwin Peer void bnxt_reenable_sriov(struct bnxt *bp);
2856bd6781c1SKalesh AP void bnxt_close_nic(struct bnxt *, bool, bool);
28574c70dbe3SMichael Chan void bnxt_get_ring_err_stats(struct bnxt *bp,
28584c70dbe3SMichael Chan struct bnxt_total_ring_err_stats *stats);
28590895926fSPavan Chebbi bool bnxt_rfs_capable(struct bnxt *bp, bool new_rss_ctx);
2860b5d600b0SVasundhara Volam int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
2861b5d600b0SVasundhara Volam u32 *reg_buf);
2862d1db9e16SMichael Chan void bnxt_fw_exception(struct bnxt *bp);
2863230d1f0dSMichael Chan void bnxt_fw_reset(struct bnxt *bp);
286498fdbe73SMichael Chan int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
28653b6b34dfSMichael Chan int tx_xdp);
2866228ea8c1SEdwin Peer int bnxt_fw_init_one(struct bnxt *bp);
2867892a662fSEdwin Peer bool bnxt_hwrm_reset_permitted(struct bnxt *bp);
2868c5e3deb8SMichael Chan int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
286959cde76fSMichael Chan struct bnxt_ntuple_filter *bnxt_lookup_ntp_filter_from_idx(struct bnxt *bp,
287059cde76fSMichael Chan struct bnxt_ntuple_filter *fltr, u32 idx);
287159cde76fSMichael Chan u32 bnxt_get_ntp_filter_idx(struct bnxt *bp, struct flow_keys *fkeys,
287259cde76fSMichael Chan const struct sk_buff *skb);
287359cde76fSMichael Chan int bnxt_insert_ntp_filter(struct bnxt *bp, struct bnxt_ntuple_filter *fltr,
287459cde76fSMichael Chan u32 idx);
28754faeadfdSMichael Chan void bnxt_del_ntp_filter(struct bnxt *bp, struct bnxt_ntuple_filter *fltr);
28766e6c5a57SMichael Chan int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
287780fcaf46SMichael Chan int bnxt_restore_pf_fw_resources(struct bnxt *bp);
287852d5254aSFlorian Fainelli int bnxt_get_port_parent_id(struct net_device *dev,
287952d5254aSFlorian Fainelli struct netdev_phys_item_id *ppid);
28806a8788f2SAndy Gospodarek void bnxt_dim_work(struct work_struct *work);
28816a8788f2SAndy Gospodarek int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
2882c7dd4a5bSEdwin Peer void bnxt_print_device_info(struct bnxt *bp);
2883c0c050c5SMichael Chan #endif
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