1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2015 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 10 #include <linux/module.h> 11 12 #include <linux/stringify.h> 13 #include <linux/kernel.h> 14 #include <linux/timer.h> 15 #include <linux/errno.h> 16 #include <linux/ioport.h> 17 #include <linux/slab.h> 18 #include <linux/vmalloc.h> 19 #include <linux/interrupt.h> 20 #include <linux/pci.h> 21 #include <linux/netdevice.h> 22 #include <linux/etherdevice.h> 23 #include <linux/skbuff.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/bitops.h> 26 #include <linux/io.h> 27 #include <linux/irq.h> 28 #include <linux/delay.h> 29 #include <asm/byteorder.h> 30 #include <asm/page.h> 31 #include <linux/time.h> 32 #include <linux/mii.h> 33 #include <linux/if.h> 34 #include <linux/if_vlan.h> 35 #include <net/ip.h> 36 #include <net/tcp.h> 37 #include <net/udp.h> 38 #include <net/checksum.h> 39 #include <net/ip6_checksum.h> 40 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE) 41 #include <net/vxlan.h> 42 #endif 43 #ifdef CONFIG_NET_RX_BUSY_POLL 44 #include <net/busy_poll.h> 45 #endif 46 #include <linux/workqueue.h> 47 #include <linux/prefetch.h> 48 #include <linux/cache.h> 49 #include <linux/log2.h> 50 #include <linux/aer.h> 51 #include <linux/bitmap.h> 52 #include <linux/cpu_rmap.h> 53 54 #include "bnxt_hsi.h" 55 #include "bnxt.h" 56 #include "bnxt_sriov.h" 57 #include "bnxt_ethtool.h" 58 59 #define BNXT_TX_TIMEOUT (5 * HZ) 60 61 static const char version[] = 62 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n"; 63 64 MODULE_LICENSE("GPL"); 65 MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); 66 MODULE_VERSION(DRV_MODULE_VERSION); 67 68 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) 69 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD 70 #define BNXT_RX_COPY_THRESH 256 71 72 #define BNXT_TX_PUSH_THRESH 164 73 74 enum board_idx { 75 BCM57301, 76 BCM57302, 77 BCM57304, 78 BCM57402, 79 BCM57404, 80 BCM57406, 81 BCM57304_VF, 82 BCM57404_VF, 83 }; 84 85 /* indexed by enum above */ 86 static const struct { 87 char *name; 88 } board_info[] = { 89 { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" }, 90 { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" }, 91 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" }, 92 { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" }, 93 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" }, 94 { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" }, 95 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" }, 96 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" }, 97 }; 98 99 static const struct pci_device_id bnxt_pci_tbl[] = { 100 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, 101 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, 102 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, 103 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, 104 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, 105 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, 106 #ifdef CONFIG_BNXT_SRIOV 107 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = BCM57304_VF }, 108 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = BCM57404_VF }, 109 #endif 110 { 0 } 111 }; 112 113 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); 114 115 static const u16 bnxt_vf_req_snif[] = { 116 HWRM_FUNC_CFG, 117 HWRM_PORT_PHY_QCFG, 118 HWRM_CFA_L2_FILTER_ALLOC, 119 }; 120 121 static bool bnxt_vf_pciid(enum board_idx idx) 122 { 123 return (idx == BCM57304_VF || idx == BCM57404_VF); 124 } 125 126 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) 127 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) 128 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) 129 130 #define BNXT_CP_DB_REARM(db, raw_cons) \ 131 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db) 132 133 #define BNXT_CP_DB(db, raw_cons) \ 134 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db) 135 136 #define BNXT_CP_DB_IRQ_DIS(db) \ 137 writel(DB_CP_IRQ_DIS_FLAGS, db) 138 139 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr) 140 { 141 /* Tell compiler to fetch tx indices from memory. */ 142 barrier(); 143 144 return bp->tx_ring_size - 145 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask); 146 } 147 148 static const u16 bnxt_lhint_arr[] = { 149 TX_BD_FLAGS_LHINT_512_AND_SMALLER, 150 TX_BD_FLAGS_LHINT_512_TO_1023, 151 TX_BD_FLAGS_LHINT_1024_TO_2047, 152 TX_BD_FLAGS_LHINT_1024_TO_2047, 153 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 154 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 155 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 156 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 157 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 158 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 159 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 160 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 161 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 162 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 163 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 164 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 165 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 166 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 167 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 168 }; 169 170 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) 171 { 172 struct bnxt *bp = netdev_priv(dev); 173 struct tx_bd *txbd; 174 struct tx_bd_ext *txbd1; 175 struct netdev_queue *txq; 176 int i; 177 dma_addr_t mapping; 178 unsigned int length, pad = 0; 179 u32 len, free_size, vlan_tag_flags, cfa_action, flags; 180 u16 prod, last_frag; 181 struct pci_dev *pdev = bp->pdev; 182 struct bnxt_tx_ring_info *txr; 183 struct bnxt_sw_tx_bd *tx_buf; 184 185 i = skb_get_queue_mapping(skb); 186 if (unlikely(i >= bp->tx_nr_rings)) { 187 dev_kfree_skb_any(skb); 188 return NETDEV_TX_OK; 189 } 190 191 txr = &bp->tx_ring[i]; 192 txq = netdev_get_tx_queue(dev, i); 193 prod = txr->tx_prod; 194 195 free_size = bnxt_tx_avail(bp, txr); 196 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { 197 netif_tx_stop_queue(txq); 198 return NETDEV_TX_BUSY; 199 } 200 201 length = skb->len; 202 len = skb_headlen(skb); 203 last_frag = skb_shinfo(skb)->nr_frags; 204 205 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 206 207 txbd->tx_bd_opaque = prod; 208 209 tx_buf = &txr->tx_buf_ring[prod]; 210 tx_buf->skb = skb; 211 tx_buf->nr_frags = last_frag; 212 213 vlan_tag_flags = 0; 214 cfa_action = 0; 215 if (skb_vlan_tag_present(skb)) { 216 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | 217 skb_vlan_tag_get(skb); 218 /* Currently supports 8021Q, 8021AD vlan offloads 219 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated 220 */ 221 if (skb->vlan_proto == htons(ETH_P_8021Q)) 222 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; 223 } 224 225 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) { 226 struct tx_push_buffer *tx_push_buf = txr->tx_push; 227 struct tx_push_bd *tx_push = &tx_push_buf->push_bd; 228 struct tx_bd_ext *tx_push1 = &tx_push->txbd2; 229 void *pdata = tx_push_buf->data; 230 u64 *end; 231 int j, push_len; 232 233 /* Set COAL_NOW to be ready quickly for the next push */ 234 tx_push->tx_bd_len_flags_type = 235 cpu_to_le32((length << TX_BD_LEN_SHIFT) | 236 TX_BD_TYPE_LONG_TX_BD | 237 TX_BD_FLAGS_LHINT_512_AND_SMALLER | 238 TX_BD_FLAGS_COAL_NOW | 239 TX_BD_FLAGS_PACKET_END | 240 (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); 241 242 if (skb->ip_summed == CHECKSUM_PARTIAL) 243 tx_push1->tx_bd_hsize_lflags = 244 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 245 else 246 tx_push1->tx_bd_hsize_lflags = 0; 247 248 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 249 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action); 250 251 end = pdata + length; 252 end = PTR_ALIGN(end, 8) - 1; 253 *end = 0; 254 255 skb_copy_from_linear_data(skb, pdata, len); 256 pdata += len; 257 for (j = 0; j < last_frag; j++) { 258 skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; 259 void *fptr; 260 261 fptr = skb_frag_address_safe(frag); 262 if (!fptr) 263 goto normal_tx; 264 265 memcpy(pdata, fptr, skb_frag_size(frag)); 266 pdata += skb_frag_size(frag); 267 } 268 269 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type; 270 txbd->tx_bd_haddr = txr->data_mapping; 271 prod = NEXT_TX(prod); 272 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 273 memcpy(txbd, tx_push1, sizeof(*txbd)); 274 prod = NEXT_TX(prod); 275 tx_push->doorbell = 276 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); 277 txr->tx_prod = prod; 278 279 netdev_tx_sent_queue(txq, skb->len); 280 281 push_len = (length + sizeof(*tx_push) + 7) / 8; 282 if (push_len > 16) { 283 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16); 284 __iowrite64_copy(txr->tx_doorbell + 4, tx_push_buf + 1, 285 push_len - 16); 286 } else { 287 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 288 push_len); 289 } 290 291 tx_buf->is_push = 1; 292 goto tx_done; 293 } 294 295 normal_tx: 296 if (length < BNXT_MIN_PKT_SIZE) { 297 pad = BNXT_MIN_PKT_SIZE - length; 298 if (skb_pad(skb, pad)) { 299 /* SKB already freed. */ 300 tx_buf->skb = NULL; 301 return NETDEV_TX_OK; 302 } 303 length = BNXT_MIN_PKT_SIZE; 304 } 305 306 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); 307 308 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) { 309 dev_kfree_skb_any(skb); 310 tx_buf->skb = NULL; 311 return NETDEV_TX_OK; 312 } 313 314 dma_unmap_addr_set(tx_buf, mapping, mapping); 315 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | 316 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); 317 318 txbd->tx_bd_haddr = cpu_to_le64(mapping); 319 320 prod = NEXT_TX(prod); 321 txbd1 = (struct tx_bd_ext *) 322 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 323 324 txbd1->tx_bd_hsize_lflags = 0; 325 if (skb_is_gso(skb)) { 326 u32 hdr_len; 327 328 if (skb->encapsulation) 329 hdr_len = skb_inner_network_offset(skb) + 330 skb_inner_network_header_len(skb) + 331 inner_tcp_hdrlen(skb); 332 else 333 hdr_len = skb_transport_offset(skb) + 334 tcp_hdrlen(skb); 335 336 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO | 337 TX_BD_FLAGS_T_IPID | 338 (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); 339 length = skb_shinfo(skb)->gso_size; 340 txbd1->tx_bd_mss = cpu_to_le32(length); 341 length += hdr_len; 342 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 343 txbd1->tx_bd_hsize_lflags = 344 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 345 txbd1->tx_bd_mss = 0; 346 } 347 348 length >>= 9; 349 flags |= bnxt_lhint_arr[length]; 350 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 351 352 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 353 txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action); 354 for (i = 0; i < last_frag; i++) { 355 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 356 357 prod = NEXT_TX(prod); 358 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 359 360 len = skb_frag_size(frag); 361 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, 362 DMA_TO_DEVICE); 363 364 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) 365 goto tx_dma_error; 366 367 tx_buf = &txr->tx_buf_ring[prod]; 368 dma_unmap_addr_set(tx_buf, mapping, mapping); 369 370 txbd->tx_bd_haddr = cpu_to_le64(mapping); 371 372 flags = len << TX_BD_LEN_SHIFT; 373 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 374 } 375 376 flags &= ~TX_BD_LEN; 377 txbd->tx_bd_len_flags_type = 378 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | 379 TX_BD_FLAGS_PACKET_END); 380 381 netdev_tx_sent_queue(txq, skb->len); 382 383 /* Sync BD data before updating doorbell */ 384 wmb(); 385 386 prod = NEXT_TX(prod); 387 txr->tx_prod = prod; 388 389 writel(DB_KEY_TX | prod, txr->tx_doorbell); 390 writel(DB_KEY_TX | prod, txr->tx_doorbell); 391 392 tx_done: 393 394 mmiowb(); 395 396 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { 397 netif_tx_stop_queue(txq); 398 399 /* netif_tx_stop_queue() must be done before checking 400 * tx index in bnxt_tx_avail() below, because in 401 * bnxt_tx_int(), we update tx index before checking for 402 * netif_tx_queue_stopped(). 403 */ 404 smp_mb(); 405 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) 406 netif_tx_wake_queue(txq); 407 } 408 return NETDEV_TX_OK; 409 410 tx_dma_error: 411 last_frag = i; 412 413 /* start back at beginning and unmap skb */ 414 prod = txr->tx_prod; 415 tx_buf = &txr->tx_buf_ring[prod]; 416 tx_buf->skb = NULL; 417 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 418 skb_headlen(skb), PCI_DMA_TODEVICE); 419 prod = NEXT_TX(prod); 420 421 /* unmap remaining mapped pages */ 422 for (i = 0; i < last_frag; i++) { 423 prod = NEXT_TX(prod); 424 tx_buf = &txr->tx_buf_ring[prod]; 425 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 426 skb_frag_size(&skb_shinfo(skb)->frags[i]), 427 PCI_DMA_TODEVICE); 428 } 429 430 dev_kfree_skb_any(skb); 431 return NETDEV_TX_OK; 432 } 433 434 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) 435 { 436 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 437 int index = txr - &bp->tx_ring[0]; 438 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index); 439 u16 cons = txr->tx_cons; 440 struct pci_dev *pdev = bp->pdev; 441 int i; 442 unsigned int tx_bytes = 0; 443 444 for (i = 0; i < nr_pkts; i++) { 445 struct bnxt_sw_tx_bd *tx_buf; 446 struct sk_buff *skb; 447 int j, last; 448 449 tx_buf = &txr->tx_buf_ring[cons]; 450 cons = NEXT_TX(cons); 451 skb = tx_buf->skb; 452 tx_buf->skb = NULL; 453 454 if (tx_buf->is_push) { 455 tx_buf->is_push = 0; 456 goto next_tx_int; 457 } 458 459 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 460 skb_headlen(skb), PCI_DMA_TODEVICE); 461 last = tx_buf->nr_frags; 462 463 for (j = 0; j < last; j++) { 464 cons = NEXT_TX(cons); 465 tx_buf = &txr->tx_buf_ring[cons]; 466 dma_unmap_page( 467 &pdev->dev, 468 dma_unmap_addr(tx_buf, mapping), 469 skb_frag_size(&skb_shinfo(skb)->frags[j]), 470 PCI_DMA_TODEVICE); 471 } 472 473 next_tx_int: 474 cons = NEXT_TX(cons); 475 476 tx_bytes += skb->len; 477 dev_kfree_skb_any(skb); 478 } 479 480 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes); 481 txr->tx_cons = cons; 482 483 /* Need to make the tx_cons update visible to bnxt_start_xmit() 484 * before checking for netif_tx_queue_stopped(). Without the 485 * memory barrier, there is a small possibility that bnxt_start_xmit() 486 * will miss it and cause the queue to be stopped forever. 487 */ 488 smp_mb(); 489 490 if (unlikely(netif_tx_queue_stopped(txq)) && 491 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) { 492 __netif_tx_lock(txq, smp_processor_id()); 493 if (netif_tx_queue_stopped(txq) && 494 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh && 495 txr->dev_state != BNXT_DEV_STATE_CLOSING) 496 netif_tx_wake_queue(txq); 497 __netif_tx_unlock(txq); 498 } 499 } 500 501 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping, 502 gfp_t gfp) 503 { 504 u8 *data; 505 struct pci_dev *pdev = bp->pdev; 506 507 data = kmalloc(bp->rx_buf_size, gfp); 508 if (!data) 509 return NULL; 510 511 *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET, 512 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); 513 514 if (dma_mapping_error(&pdev->dev, *mapping)) { 515 kfree(data); 516 data = NULL; 517 } 518 return data; 519 } 520 521 static inline int bnxt_alloc_rx_data(struct bnxt *bp, 522 struct bnxt_rx_ring_info *rxr, 523 u16 prod, gfp_t gfp) 524 { 525 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 526 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; 527 u8 *data; 528 dma_addr_t mapping; 529 530 data = __bnxt_alloc_rx_data(bp, &mapping, gfp); 531 if (!data) 532 return -ENOMEM; 533 534 rx_buf->data = data; 535 dma_unmap_addr_set(rx_buf, mapping, mapping); 536 537 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 538 539 return 0; 540 } 541 542 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, 543 u8 *data) 544 { 545 u16 prod = rxr->rx_prod; 546 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 547 struct rx_bd *cons_bd, *prod_bd; 548 549 prod_rx_buf = &rxr->rx_buf_ring[prod]; 550 cons_rx_buf = &rxr->rx_buf_ring[cons]; 551 552 prod_rx_buf->data = data; 553 554 dma_unmap_addr_set(prod_rx_buf, mapping, 555 dma_unmap_addr(cons_rx_buf, mapping)); 556 557 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 558 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; 559 560 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; 561 } 562 563 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 564 { 565 u16 next, max = rxr->rx_agg_bmap_size; 566 567 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); 568 if (next >= max) 569 next = find_first_zero_bit(rxr->rx_agg_bmap, max); 570 return next; 571 } 572 573 static inline int bnxt_alloc_rx_page(struct bnxt *bp, 574 struct bnxt_rx_ring_info *rxr, 575 u16 prod, gfp_t gfp) 576 { 577 struct rx_bd *rxbd = 578 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 579 struct bnxt_sw_rx_agg_bd *rx_agg_buf; 580 struct pci_dev *pdev = bp->pdev; 581 struct page *page; 582 dma_addr_t mapping; 583 u16 sw_prod = rxr->rx_sw_agg_prod; 584 585 page = alloc_page(gfp); 586 if (!page) 587 return -ENOMEM; 588 589 mapping = dma_map_page(&pdev->dev, page, 0, PAGE_SIZE, 590 PCI_DMA_FROMDEVICE); 591 if (dma_mapping_error(&pdev->dev, mapping)) { 592 __free_page(page); 593 return -EIO; 594 } 595 596 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 597 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 598 599 __set_bit(sw_prod, rxr->rx_agg_bmap); 600 rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; 601 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); 602 603 rx_agg_buf->page = page; 604 rx_agg_buf->mapping = mapping; 605 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 606 rxbd->rx_bd_opaque = sw_prod; 607 return 0; 608 } 609 610 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons, 611 u32 agg_bufs) 612 { 613 struct bnxt *bp = bnapi->bp; 614 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 615 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 616 u16 prod = rxr->rx_agg_prod; 617 u16 sw_prod = rxr->rx_sw_agg_prod; 618 u32 i; 619 620 for (i = 0; i < agg_bufs; i++) { 621 u16 cons; 622 struct rx_agg_cmp *agg; 623 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; 624 struct rx_bd *prod_bd; 625 struct page *page; 626 627 agg = (struct rx_agg_cmp *) 628 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 629 cons = agg->rx_agg_cmp_opaque; 630 __clear_bit(cons, rxr->rx_agg_bmap); 631 632 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 633 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 634 635 __set_bit(sw_prod, rxr->rx_agg_bmap); 636 prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; 637 cons_rx_buf = &rxr->rx_agg_ring[cons]; 638 639 /* It is possible for sw_prod to be equal to cons, so 640 * set cons_rx_buf->page to NULL first. 641 */ 642 page = cons_rx_buf->page; 643 cons_rx_buf->page = NULL; 644 prod_rx_buf->page = page; 645 646 prod_rx_buf->mapping = cons_rx_buf->mapping; 647 648 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 649 650 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); 651 prod_bd->rx_bd_opaque = sw_prod; 652 653 prod = NEXT_RX_AGG(prod); 654 sw_prod = NEXT_RX_AGG(sw_prod); 655 cp_cons = NEXT_CMP(cp_cons); 656 } 657 rxr->rx_agg_prod = prod; 658 rxr->rx_sw_agg_prod = sw_prod; 659 } 660 661 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, 662 struct bnxt_rx_ring_info *rxr, u16 cons, 663 u16 prod, u8 *data, dma_addr_t dma_addr, 664 unsigned int len) 665 { 666 int err; 667 struct sk_buff *skb; 668 669 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 670 if (unlikely(err)) { 671 bnxt_reuse_rx_data(rxr, cons, data); 672 return NULL; 673 } 674 675 skb = build_skb(data, 0); 676 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, 677 PCI_DMA_FROMDEVICE); 678 if (!skb) { 679 kfree(data); 680 return NULL; 681 } 682 683 skb_reserve(skb, BNXT_RX_OFFSET); 684 skb_put(skb, len); 685 return skb; 686 } 687 688 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi, 689 struct sk_buff *skb, u16 cp_cons, 690 u32 agg_bufs) 691 { 692 struct pci_dev *pdev = bp->pdev; 693 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 694 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 695 u16 prod = rxr->rx_agg_prod; 696 u32 i; 697 698 for (i = 0; i < agg_bufs; i++) { 699 u16 cons, frag_len; 700 struct rx_agg_cmp *agg; 701 struct bnxt_sw_rx_agg_bd *cons_rx_buf; 702 struct page *page; 703 dma_addr_t mapping; 704 705 agg = (struct rx_agg_cmp *) 706 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 707 cons = agg->rx_agg_cmp_opaque; 708 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & 709 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; 710 711 cons_rx_buf = &rxr->rx_agg_ring[cons]; 712 skb_fill_page_desc(skb, i, cons_rx_buf->page, 0, frag_len); 713 __clear_bit(cons, rxr->rx_agg_bmap); 714 715 /* It is possible for bnxt_alloc_rx_page() to allocate 716 * a sw_prod index that equals the cons index, so we 717 * need to clear the cons entry now. 718 */ 719 mapping = dma_unmap_addr(cons_rx_buf, mapping); 720 page = cons_rx_buf->page; 721 cons_rx_buf->page = NULL; 722 723 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { 724 struct skb_shared_info *shinfo; 725 unsigned int nr_frags; 726 727 shinfo = skb_shinfo(skb); 728 nr_frags = --shinfo->nr_frags; 729 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL); 730 731 dev_kfree_skb(skb); 732 733 cons_rx_buf->page = page; 734 735 /* Update prod since possibly some pages have been 736 * allocated already. 737 */ 738 rxr->rx_agg_prod = prod; 739 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i); 740 return NULL; 741 } 742 743 dma_unmap_page(&pdev->dev, mapping, PAGE_SIZE, 744 PCI_DMA_FROMDEVICE); 745 746 skb->data_len += frag_len; 747 skb->len += frag_len; 748 skb->truesize += PAGE_SIZE; 749 750 prod = NEXT_RX_AGG(prod); 751 cp_cons = NEXT_CMP(cp_cons); 752 } 753 rxr->rx_agg_prod = prod; 754 return skb; 755 } 756 757 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 758 u8 agg_bufs, u32 *raw_cons) 759 { 760 u16 last; 761 struct rx_agg_cmp *agg; 762 763 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); 764 last = RING_CMP(*raw_cons); 765 agg = (struct rx_agg_cmp *) 766 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; 767 return RX_AGG_CMP_VALID(agg, *raw_cons); 768 } 769 770 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, 771 unsigned int len, 772 dma_addr_t mapping) 773 { 774 struct bnxt *bp = bnapi->bp; 775 struct pci_dev *pdev = bp->pdev; 776 struct sk_buff *skb; 777 778 skb = napi_alloc_skb(&bnapi->napi, len); 779 if (!skb) 780 return NULL; 781 782 dma_sync_single_for_cpu(&pdev->dev, mapping, 783 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE); 784 785 memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET); 786 787 dma_sync_single_for_device(&pdev->dev, mapping, 788 bp->rx_copy_thresh, 789 PCI_DMA_FROMDEVICE); 790 791 skb_put(skb, len); 792 return skb; 793 } 794 795 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 796 struct rx_tpa_start_cmp *tpa_start, 797 struct rx_tpa_start_cmp_ext *tpa_start1) 798 { 799 u8 agg_id = TPA_START_AGG_ID(tpa_start); 800 u16 cons, prod; 801 struct bnxt_tpa_info *tpa_info; 802 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 803 struct rx_bd *prod_bd; 804 dma_addr_t mapping; 805 806 cons = tpa_start->rx_tpa_start_cmp_opaque; 807 prod = rxr->rx_prod; 808 cons_rx_buf = &rxr->rx_buf_ring[cons]; 809 prod_rx_buf = &rxr->rx_buf_ring[prod]; 810 tpa_info = &rxr->rx_tpa[agg_id]; 811 812 prod_rx_buf->data = tpa_info->data; 813 814 mapping = tpa_info->mapping; 815 dma_unmap_addr_set(prod_rx_buf, mapping, mapping); 816 817 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 818 819 prod_bd->rx_bd_haddr = cpu_to_le64(mapping); 820 821 tpa_info->data = cons_rx_buf->data; 822 cons_rx_buf->data = NULL; 823 tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping); 824 825 tpa_info->len = 826 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> 827 RX_TPA_START_CMP_LEN_SHIFT; 828 if (likely(TPA_START_HASH_VALID(tpa_start))) { 829 u32 hash_type = TPA_START_HASH_TYPE(tpa_start); 830 831 tpa_info->hash_type = PKT_HASH_TYPE_L4; 832 tpa_info->gso_type = SKB_GSO_TCPV4; 833 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 834 if (hash_type == 3) 835 tpa_info->gso_type = SKB_GSO_TCPV6; 836 tpa_info->rss_hash = 837 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); 838 } else { 839 tpa_info->hash_type = PKT_HASH_TYPE_NONE; 840 tpa_info->gso_type = 0; 841 if (netif_msg_rx_err(bp)) 842 netdev_warn(bp->dev, "TPA packet without valid hash\n"); 843 } 844 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); 845 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); 846 847 rxr->rx_prod = NEXT_RX(prod); 848 cons = NEXT_RX(cons); 849 cons_rx_buf = &rxr->rx_buf_ring[cons]; 850 851 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); 852 rxr->rx_prod = NEXT_RX(rxr->rx_prod); 853 cons_rx_buf->data = NULL; 854 } 855 856 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi, 857 u16 cp_cons, u32 agg_bufs) 858 { 859 if (agg_bufs) 860 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs); 861 } 862 863 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) 864 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) 865 866 static inline struct sk_buff *bnxt_gro_skb(struct bnxt_tpa_info *tpa_info, 867 struct rx_tpa_end_cmp *tpa_end, 868 struct rx_tpa_end_cmp_ext *tpa_end1, 869 struct sk_buff *skb) 870 { 871 #ifdef CONFIG_INET 872 struct tcphdr *th; 873 int payload_off, tcp_opt_len = 0; 874 int len, nw_off; 875 u16 segs; 876 877 segs = TPA_END_TPA_SEGS(tpa_end); 878 if (segs == 1) 879 return skb; 880 881 NAPI_GRO_CB(skb)->count = segs; 882 skb_shinfo(skb)->gso_size = 883 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); 884 skb_shinfo(skb)->gso_type = tpa_info->gso_type; 885 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 886 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> 887 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT; 888 if (TPA_END_GRO_TS(tpa_end)) 889 tcp_opt_len = 12; 890 891 if (tpa_info->gso_type == SKB_GSO_TCPV4) { 892 struct iphdr *iph; 893 894 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - 895 ETH_HLEN; 896 skb_set_network_header(skb, nw_off); 897 iph = ip_hdr(skb); 898 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 899 len = skb->len - skb_transport_offset(skb); 900 th = tcp_hdr(skb); 901 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 902 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { 903 struct ipv6hdr *iph; 904 905 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - 906 ETH_HLEN; 907 skb_set_network_header(skb, nw_off); 908 iph = ipv6_hdr(skb); 909 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 910 len = skb->len - skb_transport_offset(skb); 911 th = tcp_hdr(skb); 912 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 913 } else { 914 dev_kfree_skb_any(skb); 915 return NULL; 916 } 917 tcp_gro_complete(skb); 918 919 if (nw_off) { /* tunnel */ 920 struct udphdr *uh = NULL; 921 922 if (skb->protocol == htons(ETH_P_IP)) { 923 struct iphdr *iph = (struct iphdr *)skb->data; 924 925 if (iph->protocol == IPPROTO_UDP) 926 uh = (struct udphdr *)(iph + 1); 927 } else { 928 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 929 930 if (iph->nexthdr == IPPROTO_UDP) 931 uh = (struct udphdr *)(iph + 1); 932 } 933 if (uh) { 934 if (uh->check) 935 skb_shinfo(skb)->gso_type |= 936 SKB_GSO_UDP_TUNNEL_CSUM; 937 else 938 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 939 } 940 } 941 #endif 942 return skb; 943 } 944 945 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, 946 struct bnxt_napi *bnapi, 947 u32 *raw_cons, 948 struct rx_tpa_end_cmp *tpa_end, 949 struct rx_tpa_end_cmp_ext *tpa_end1, 950 bool *agg_event) 951 { 952 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 953 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 954 u8 agg_id = TPA_END_AGG_ID(tpa_end); 955 u8 *data, agg_bufs; 956 u16 cp_cons = RING_CMP(*raw_cons); 957 unsigned int len; 958 struct bnxt_tpa_info *tpa_info; 959 dma_addr_t mapping; 960 struct sk_buff *skb; 961 962 tpa_info = &rxr->rx_tpa[agg_id]; 963 data = tpa_info->data; 964 prefetch(data); 965 len = tpa_info->len; 966 mapping = tpa_info->mapping; 967 968 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 969 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT; 970 971 if (agg_bufs) { 972 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) 973 return ERR_PTR(-EBUSY); 974 975 *agg_event = true; 976 cp_cons = NEXT_CMP(cp_cons); 977 } 978 979 if (unlikely(agg_bufs > MAX_SKB_FRAGS)) { 980 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 981 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", 982 agg_bufs, (int)MAX_SKB_FRAGS); 983 return NULL; 984 } 985 986 if (len <= bp->rx_copy_thresh) { 987 skb = bnxt_copy_skb(bnapi, data, len, mapping); 988 if (!skb) { 989 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 990 return NULL; 991 } 992 } else { 993 u8 *new_data; 994 dma_addr_t new_mapping; 995 996 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC); 997 if (!new_data) { 998 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 999 return NULL; 1000 } 1001 1002 tpa_info->data = new_data; 1003 tpa_info->mapping = new_mapping; 1004 1005 skb = build_skb(data, 0); 1006 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size, 1007 PCI_DMA_FROMDEVICE); 1008 1009 if (!skb) { 1010 kfree(data); 1011 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1012 return NULL; 1013 } 1014 skb_reserve(skb, BNXT_RX_OFFSET); 1015 skb_put(skb, len); 1016 } 1017 1018 if (agg_bufs) { 1019 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs); 1020 if (!skb) { 1021 /* Page reuse already handled by bnxt_rx_pages(). */ 1022 return NULL; 1023 } 1024 } 1025 skb->protocol = eth_type_trans(skb, bp->dev); 1026 1027 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) 1028 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); 1029 1030 if (tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) { 1031 netdev_features_t features = skb->dev->features; 1032 u16 vlan_proto = tpa_info->metadata >> 1033 RX_CMP_FLAGS2_METADATA_TPID_SFT; 1034 1035 if (((features & NETIF_F_HW_VLAN_CTAG_RX) && 1036 vlan_proto == ETH_P_8021Q) || 1037 ((features & NETIF_F_HW_VLAN_STAG_RX) && 1038 vlan_proto == ETH_P_8021AD)) { 1039 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), 1040 tpa_info->metadata & 1041 RX_CMP_FLAGS2_METADATA_VID_MASK); 1042 } 1043 } 1044 1045 skb_checksum_none_assert(skb); 1046 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { 1047 skb->ip_summed = CHECKSUM_UNNECESSARY; 1048 skb->csum_level = 1049 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; 1050 } 1051 1052 if (TPA_END_GRO(tpa_end)) 1053 skb = bnxt_gro_skb(tpa_info, tpa_end, tpa_end1, skb); 1054 1055 return skb; 1056 } 1057 1058 /* returns the following: 1059 * 1 - 1 packet successfully received 1060 * 0 - successful TPA_START, packet not completed yet 1061 * -EBUSY - completion ring does not have all the agg buffers yet 1062 * -ENOMEM - packet aborted due to out of memory 1063 * -EIO - packet aborted due to hw error indicated in BD 1064 */ 1065 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons, 1066 bool *agg_event) 1067 { 1068 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1069 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1070 struct net_device *dev = bp->dev; 1071 struct rx_cmp *rxcmp; 1072 struct rx_cmp_ext *rxcmp1; 1073 u32 tmp_raw_cons = *raw_cons; 1074 u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons); 1075 struct bnxt_sw_rx_bd *rx_buf; 1076 unsigned int len; 1077 u8 *data, agg_bufs, cmp_type; 1078 dma_addr_t dma_addr; 1079 struct sk_buff *skb; 1080 int rc = 0; 1081 1082 rxcmp = (struct rx_cmp *) 1083 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1084 1085 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1086 cp_cons = RING_CMP(tmp_raw_cons); 1087 rxcmp1 = (struct rx_cmp_ext *) 1088 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1089 1090 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1091 return -EBUSY; 1092 1093 cmp_type = RX_CMP_TYPE(rxcmp); 1094 1095 prod = rxr->rx_prod; 1096 1097 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { 1098 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, 1099 (struct rx_tpa_start_cmp_ext *)rxcmp1); 1100 1101 goto next_rx_no_prod; 1102 1103 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1104 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons, 1105 (struct rx_tpa_end_cmp *)rxcmp, 1106 (struct rx_tpa_end_cmp_ext *)rxcmp1, 1107 agg_event); 1108 1109 if (unlikely(IS_ERR(skb))) 1110 return -EBUSY; 1111 1112 rc = -ENOMEM; 1113 if (likely(skb)) { 1114 skb_record_rx_queue(skb, bnapi->index); 1115 skb_mark_napi_id(skb, &bnapi->napi); 1116 if (bnxt_busy_polling(bnapi)) 1117 netif_receive_skb(skb); 1118 else 1119 napi_gro_receive(&bnapi->napi, skb); 1120 rc = 1; 1121 } 1122 goto next_rx_no_prod; 1123 } 1124 1125 cons = rxcmp->rx_cmp_opaque; 1126 rx_buf = &rxr->rx_buf_ring[cons]; 1127 data = rx_buf->data; 1128 prefetch(data); 1129 1130 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >> 1131 RX_CMP_AGG_BUFS_SHIFT; 1132 1133 if (agg_bufs) { 1134 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1135 return -EBUSY; 1136 1137 cp_cons = NEXT_CMP(cp_cons); 1138 *agg_event = true; 1139 } 1140 1141 rx_buf->data = NULL; 1142 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { 1143 bnxt_reuse_rx_data(rxr, cons, data); 1144 if (agg_bufs) 1145 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs); 1146 1147 rc = -EIO; 1148 goto next_rx; 1149 } 1150 1151 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 1152 dma_addr = dma_unmap_addr(rx_buf, mapping); 1153 1154 if (len <= bp->rx_copy_thresh) { 1155 skb = bnxt_copy_skb(bnapi, data, len, dma_addr); 1156 bnxt_reuse_rx_data(rxr, cons, data); 1157 if (!skb) { 1158 rc = -ENOMEM; 1159 goto next_rx; 1160 } 1161 } else { 1162 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len); 1163 if (!skb) { 1164 rc = -ENOMEM; 1165 goto next_rx; 1166 } 1167 } 1168 1169 if (agg_bufs) { 1170 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs); 1171 if (!skb) { 1172 rc = -ENOMEM; 1173 goto next_rx; 1174 } 1175 } 1176 1177 if (RX_CMP_HASH_VALID(rxcmp)) { 1178 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); 1179 enum pkt_hash_types type = PKT_HASH_TYPE_L4; 1180 1181 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1182 if (hash_type != 1 && hash_type != 3) 1183 type = PKT_HASH_TYPE_L3; 1184 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); 1185 } 1186 1187 skb->protocol = eth_type_trans(skb, dev); 1188 1189 if (rxcmp1->rx_cmp_flags2 & 1190 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) { 1191 netdev_features_t features = skb->dev->features; 1192 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); 1193 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT; 1194 1195 if (((features & NETIF_F_HW_VLAN_CTAG_RX) && 1196 vlan_proto == ETH_P_8021Q) || 1197 ((features & NETIF_F_HW_VLAN_STAG_RX) && 1198 vlan_proto == ETH_P_8021AD)) 1199 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), 1200 meta_data & 1201 RX_CMP_FLAGS2_METADATA_VID_MASK); 1202 } 1203 1204 skb_checksum_none_assert(skb); 1205 if (RX_CMP_L4_CS_OK(rxcmp1)) { 1206 if (dev->features & NETIF_F_RXCSUM) { 1207 skb->ip_summed = CHECKSUM_UNNECESSARY; 1208 skb->csum_level = RX_CMP_ENCAP(rxcmp1); 1209 } 1210 } else { 1211 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { 1212 if (dev->features & NETIF_F_RXCSUM) 1213 cpr->rx_l4_csum_errors++; 1214 } 1215 } 1216 1217 skb_record_rx_queue(skb, bnapi->index); 1218 skb_mark_napi_id(skb, &bnapi->napi); 1219 if (bnxt_busy_polling(bnapi)) 1220 netif_receive_skb(skb); 1221 else 1222 napi_gro_receive(&bnapi->napi, skb); 1223 rc = 1; 1224 1225 next_rx: 1226 rxr->rx_prod = NEXT_RX(prod); 1227 1228 next_rx_no_prod: 1229 *raw_cons = tmp_raw_cons; 1230 1231 return rc; 1232 } 1233 1234 static int bnxt_async_event_process(struct bnxt *bp, 1235 struct hwrm_async_event_cmpl *cmpl) 1236 { 1237 u16 event_id = le16_to_cpu(cmpl->event_id); 1238 1239 /* TODO CHIMP_FW: Define event id's for link change, error etc */ 1240 switch (event_id) { 1241 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: 1242 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); 1243 schedule_work(&bp->sp_task); 1244 break; 1245 default: 1246 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n", 1247 event_id); 1248 break; 1249 } 1250 return 0; 1251 } 1252 1253 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) 1254 { 1255 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; 1256 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; 1257 struct hwrm_fwd_req_cmpl *fwd_req_cmpl = 1258 (struct hwrm_fwd_req_cmpl *)txcmp; 1259 1260 switch (cmpl_type) { 1261 case CMPL_BASE_TYPE_HWRM_DONE: 1262 seq_id = le16_to_cpu(h_cmpl->sequence_id); 1263 if (seq_id == bp->hwrm_intr_seq_id) 1264 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID; 1265 else 1266 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id); 1267 break; 1268 1269 case CMPL_BASE_TYPE_HWRM_FWD_REQ: 1270 vf_id = le16_to_cpu(fwd_req_cmpl->source_id); 1271 1272 if ((vf_id < bp->pf.first_vf_id) || 1273 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { 1274 netdev_err(bp->dev, "Msg contains invalid VF id %x\n", 1275 vf_id); 1276 return -EINVAL; 1277 } 1278 1279 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); 1280 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event); 1281 schedule_work(&bp->sp_task); 1282 break; 1283 1284 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: 1285 bnxt_async_event_process(bp, 1286 (struct hwrm_async_event_cmpl *)txcmp); 1287 1288 default: 1289 break; 1290 } 1291 1292 return 0; 1293 } 1294 1295 static irqreturn_t bnxt_msix(int irq, void *dev_instance) 1296 { 1297 struct bnxt_napi *bnapi = dev_instance; 1298 struct bnxt *bp = bnapi->bp; 1299 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1300 u32 cons = RING_CMP(cpr->cp_raw_cons); 1301 1302 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 1303 napi_schedule(&bnapi->napi); 1304 return IRQ_HANDLED; 1305 } 1306 1307 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) 1308 { 1309 u32 raw_cons = cpr->cp_raw_cons; 1310 u16 cons = RING_CMP(raw_cons); 1311 struct tx_cmp *txcmp; 1312 1313 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 1314 1315 return TX_CMP_VALID(txcmp, raw_cons); 1316 } 1317 1318 static irqreturn_t bnxt_inta(int irq, void *dev_instance) 1319 { 1320 struct bnxt_napi *bnapi = dev_instance; 1321 struct bnxt *bp = bnapi->bp; 1322 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1323 u32 cons = RING_CMP(cpr->cp_raw_cons); 1324 u32 int_status; 1325 1326 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 1327 1328 if (!bnxt_has_work(bp, cpr)) { 1329 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); 1330 /* return if erroneous interrupt */ 1331 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) 1332 return IRQ_NONE; 1333 } 1334 1335 /* disable ring IRQ */ 1336 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell); 1337 1338 /* Return here if interrupt is shared and is disabled. */ 1339 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 1340 return IRQ_HANDLED; 1341 1342 napi_schedule(&bnapi->napi); 1343 return IRQ_HANDLED; 1344 } 1345 1346 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) 1347 { 1348 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1349 u32 raw_cons = cpr->cp_raw_cons; 1350 u32 cons; 1351 int tx_pkts = 0; 1352 int rx_pkts = 0; 1353 bool rx_event = false; 1354 bool agg_event = false; 1355 struct tx_cmp *txcmp; 1356 1357 while (1) { 1358 int rc; 1359 1360 cons = RING_CMP(raw_cons); 1361 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 1362 1363 if (!TX_CMP_VALID(txcmp, raw_cons)) 1364 break; 1365 1366 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { 1367 tx_pkts++; 1368 /* return full budget so NAPI will complete. */ 1369 if (unlikely(tx_pkts > bp->tx_wake_thresh)) 1370 rx_pkts = budget; 1371 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 1372 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event); 1373 if (likely(rc >= 0)) 1374 rx_pkts += rc; 1375 else if (rc == -EBUSY) /* partial completion */ 1376 break; 1377 rx_event = true; 1378 } else if (unlikely((TX_CMP_TYPE(txcmp) == 1379 CMPL_BASE_TYPE_HWRM_DONE) || 1380 (TX_CMP_TYPE(txcmp) == 1381 CMPL_BASE_TYPE_HWRM_FWD_REQ) || 1382 (TX_CMP_TYPE(txcmp) == 1383 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { 1384 bnxt_hwrm_handler(bp, txcmp); 1385 } 1386 raw_cons = NEXT_RAW_CMP(raw_cons); 1387 1388 if (rx_pkts == budget) 1389 break; 1390 } 1391 1392 cpr->cp_raw_cons = raw_cons; 1393 /* ACK completion ring before freeing tx ring and producing new 1394 * buffers in rx/agg rings to prevent overflowing the completion 1395 * ring. 1396 */ 1397 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 1398 1399 if (tx_pkts) 1400 bnxt_tx_int(bp, bnapi, tx_pkts); 1401 1402 if (rx_event) { 1403 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1404 1405 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); 1406 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); 1407 if (agg_event) { 1408 writel(DB_KEY_RX | rxr->rx_agg_prod, 1409 rxr->rx_agg_doorbell); 1410 writel(DB_KEY_RX | rxr->rx_agg_prod, 1411 rxr->rx_agg_doorbell); 1412 } 1413 } 1414 return rx_pkts; 1415 } 1416 1417 static int bnxt_poll(struct napi_struct *napi, int budget) 1418 { 1419 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 1420 struct bnxt *bp = bnapi->bp; 1421 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1422 int work_done = 0; 1423 1424 if (!bnxt_lock_napi(bnapi)) 1425 return budget; 1426 1427 while (1) { 1428 work_done += bnxt_poll_work(bp, bnapi, budget - work_done); 1429 1430 if (work_done >= budget) 1431 break; 1432 1433 if (!bnxt_has_work(bp, cpr)) { 1434 napi_complete(napi); 1435 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons); 1436 break; 1437 } 1438 } 1439 mmiowb(); 1440 bnxt_unlock_napi(bnapi); 1441 return work_done; 1442 } 1443 1444 #ifdef CONFIG_NET_RX_BUSY_POLL 1445 static int bnxt_busy_poll(struct napi_struct *napi) 1446 { 1447 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 1448 struct bnxt *bp = bnapi->bp; 1449 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1450 int rx_work, budget = 4; 1451 1452 if (atomic_read(&bp->intr_sem) != 0) 1453 return LL_FLUSH_FAILED; 1454 1455 if (!bnxt_lock_poll(bnapi)) 1456 return LL_FLUSH_BUSY; 1457 1458 rx_work = bnxt_poll_work(bp, bnapi, budget); 1459 1460 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons); 1461 1462 bnxt_unlock_poll(bnapi); 1463 return rx_work; 1464 } 1465 #endif 1466 1467 static void bnxt_free_tx_skbs(struct bnxt *bp) 1468 { 1469 int i, max_idx; 1470 struct pci_dev *pdev = bp->pdev; 1471 1472 if (!bp->tx_ring) 1473 return; 1474 1475 max_idx = bp->tx_nr_pages * TX_DESC_CNT; 1476 for (i = 0; i < bp->tx_nr_rings; i++) { 1477 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 1478 int j; 1479 1480 for (j = 0; j < max_idx;) { 1481 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; 1482 struct sk_buff *skb = tx_buf->skb; 1483 int k, last; 1484 1485 if (!skb) { 1486 j++; 1487 continue; 1488 } 1489 1490 tx_buf->skb = NULL; 1491 1492 if (tx_buf->is_push) { 1493 dev_kfree_skb(skb); 1494 j += 2; 1495 continue; 1496 } 1497 1498 dma_unmap_single(&pdev->dev, 1499 dma_unmap_addr(tx_buf, mapping), 1500 skb_headlen(skb), 1501 PCI_DMA_TODEVICE); 1502 1503 last = tx_buf->nr_frags; 1504 j += 2; 1505 for (k = 0; k < last; k++, j++) { 1506 int ring_idx = j & bp->tx_ring_mask; 1507 skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; 1508 1509 tx_buf = &txr->tx_buf_ring[ring_idx]; 1510 dma_unmap_page( 1511 &pdev->dev, 1512 dma_unmap_addr(tx_buf, mapping), 1513 skb_frag_size(frag), PCI_DMA_TODEVICE); 1514 } 1515 dev_kfree_skb(skb); 1516 } 1517 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); 1518 } 1519 } 1520 1521 static void bnxt_free_rx_skbs(struct bnxt *bp) 1522 { 1523 int i, max_idx, max_agg_idx; 1524 struct pci_dev *pdev = bp->pdev; 1525 1526 if (!bp->rx_ring) 1527 return; 1528 1529 max_idx = bp->rx_nr_pages * RX_DESC_CNT; 1530 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; 1531 for (i = 0; i < bp->rx_nr_rings; i++) { 1532 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 1533 int j; 1534 1535 if (rxr->rx_tpa) { 1536 for (j = 0; j < MAX_TPA; j++) { 1537 struct bnxt_tpa_info *tpa_info = 1538 &rxr->rx_tpa[j]; 1539 u8 *data = tpa_info->data; 1540 1541 if (!data) 1542 continue; 1543 1544 dma_unmap_single( 1545 &pdev->dev, 1546 dma_unmap_addr(tpa_info, mapping), 1547 bp->rx_buf_use_size, 1548 PCI_DMA_FROMDEVICE); 1549 1550 tpa_info->data = NULL; 1551 1552 kfree(data); 1553 } 1554 } 1555 1556 for (j = 0; j < max_idx; j++) { 1557 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j]; 1558 u8 *data = rx_buf->data; 1559 1560 if (!data) 1561 continue; 1562 1563 dma_unmap_single(&pdev->dev, 1564 dma_unmap_addr(rx_buf, mapping), 1565 bp->rx_buf_use_size, 1566 PCI_DMA_FROMDEVICE); 1567 1568 rx_buf->data = NULL; 1569 1570 kfree(data); 1571 } 1572 1573 for (j = 0; j < max_agg_idx; j++) { 1574 struct bnxt_sw_rx_agg_bd *rx_agg_buf = 1575 &rxr->rx_agg_ring[j]; 1576 struct page *page = rx_agg_buf->page; 1577 1578 if (!page) 1579 continue; 1580 1581 dma_unmap_page(&pdev->dev, 1582 dma_unmap_addr(rx_agg_buf, mapping), 1583 PAGE_SIZE, PCI_DMA_FROMDEVICE); 1584 1585 rx_agg_buf->page = NULL; 1586 __clear_bit(j, rxr->rx_agg_bmap); 1587 1588 __free_page(page); 1589 } 1590 } 1591 } 1592 1593 static void bnxt_free_skbs(struct bnxt *bp) 1594 { 1595 bnxt_free_tx_skbs(bp); 1596 bnxt_free_rx_skbs(bp); 1597 } 1598 1599 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring) 1600 { 1601 struct pci_dev *pdev = bp->pdev; 1602 int i; 1603 1604 for (i = 0; i < ring->nr_pages; i++) { 1605 if (!ring->pg_arr[i]) 1606 continue; 1607 1608 dma_free_coherent(&pdev->dev, ring->page_size, 1609 ring->pg_arr[i], ring->dma_arr[i]); 1610 1611 ring->pg_arr[i] = NULL; 1612 } 1613 if (ring->pg_tbl) { 1614 dma_free_coherent(&pdev->dev, ring->nr_pages * 8, 1615 ring->pg_tbl, ring->pg_tbl_map); 1616 ring->pg_tbl = NULL; 1617 } 1618 if (ring->vmem_size && *ring->vmem) { 1619 vfree(*ring->vmem); 1620 *ring->vmem = NULL; 1621 } 1622 } 1623 1624 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring) 1625 { 1626 int i; 1627 struct pci_dev *pdev = bp->pdev; 1628 1629 if (ring->nr_pages > 1) { 1630 ring->pg_tbl = dma_alloc_coherent(&pdev->dev, 1631 ring->nr_pages * 8, 1632 &ring->pg_tbl_map, 1633 GFP_KERNEL); 1634 if (!ring->pg_tbl) 1635 return -ENOMEM; 1636 } 1637 1638 for (i = 0; i < ring->nr_pages; i++) { 1639 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev, 1640 ring->page_size, 1641 &ring->dma_arr[i], 1642 GFP_KERNEL); 1643 if (!ring->pg_arr[i]) 1644 return -ENOMEM; 1645 1646 if (ring->nr_pages > 1) 1647 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]); 1648 } 1649 1650 if (ring->vmem_size) { 1651 *ring->vmem = vzalloc(ring->vmem_size); 1652 if (!(*ring->vmem)) 1653 return -ENOMEM; 1654 } 1655 return 0; 1656 } 1657 1658 static void bnxt_free_rx_rings(struct bnxt *bp) 1659 { 1660 int i; 1661 1662 if (!bp->rx_ring) 1663 return; 1664 1665 for (i = 0; i < bp->rx_nr_rings; i++) { 1666 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 1667 struct bnxt_ring_struct *ring; 1668 1669 kfree(rxr->rx_tpa); 1670 rxr->rx_tpa = NULL; 1671 1672 kfree(rxr->rx_agg_bmap); 1673 rxr->rx_agg_bmap = NULL; 1674 1675 ring = &rxr->rx_ring_struct; 1676 bnxt_free_ring(bp, ring); 1677 1678 ring = &rxr->rx_agg_ring_struct; 1679 bnxt_free_ring(bp, ring); 1680 } 1681 } 1682 1683 static int bnxt_alloc_rx_rings(struct bnxt *bp) 1684 { 1685 int i, rc, agg_rings = 0, tpa_rings = 0; 1686 1687 if (!bp->rx_ring) 1688 return -ENOMEM; 1689 1690 if (bp->flags & BNXT_FLAG_AGG_RINGS) 1691 agg_rings = 1; 1692 1693 if (bp->flags & BNXT_FLAG_TPA) 1694 tpa_rings = 1; 1695 1696 for (i = 0; i < bp->rx_nr_rings; i++) { 1697 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 1698 struct bnxt_ring_struct *ring; 1699 1700 ring = &rxr->rx_ring_struct; 1701 1702 rc = bnxt_alloc_ring(bp, ring); 1703 if (rc) 1704 return rc; 1705 1706 if (agg_rings) { 1707 u16 mem_size; 1708 1709 ring = &rxr->rx_agg_ring_struct; 1710 rc = bnxt_alloc_ring(bp, ring); 1711 if (rc) 1712 return rc; 1713 1714 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; 1715 mem_size = rxr->rx_agg_bmap_size / 8; 1716 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); 1717 if (!rxr->rx_agg_bmap) 1718 return -ENOMEM; 1719 1720 if (tpa_rings) { 1721 rxr->rx_tpa = kcalloc(MAX_TPA, 1722 sizeof(struct bnxt_tpa_info), 1723 GFP_KERNEL); 1724 if (!rxr->rx_tpa) 1725 return -ENOMEM; 1726 } 1727 } 1728 } 1729 return 0; 1730 } 1731 1732 static void bnxt_free_tx_rings(struct bnxt *bp) 1733 { 1734 int i; 1735 struct pci_dev *pdev = bp->pdev; 1736 1737 if (!bp->tx_ring) 1738 return; 1739 1740 for (i = 0; i < bp->tx_nr_rings; i++) { 1741 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 1742 struct bnxt_ring_struct *ring; 1743 1744 if (txr->tx_push) { 1745 dma_free_coherent(&pdev->dev, bp->tx_push_size, 1746 txr->tx_push, txr->tx_push_mapping); 1747 txr->tx_push = NULL; 1748 } 1749 1750 ring = &txr->tx_ring_struct; 1751 1752 bnxt_free_ring(bp, ring); 1753 } 1754 } 1755 1756 static int bnxt_alloc_tx_rings(struct bnxt *bp) 1757 { 1758 int i, j, rc; 1759 struct pci_dev *pdev = bp->pdev; 1760 1761 bp->tx_push_size = 0; 1762 if (bp->tx_push_thresh) { 1763 int push_size; 1764 1765 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + 1766 bp->tx_push_thresh); 1767 1768 if (push_size > 256) { 1769 push_size = 0; 1770 bp->tx_push_thresh = 0; 1771 } 1772 1773 bp->tx_push_size = push_size; 1774 } 1775 1776 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { 1777 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 1778 struct bnxt_ring_struct *ring; 1779 1780 ring = &txr->tx_ring_struct; 1781 1782 rc = bnxt_alloc_ring(bp, ring); 1783 if (rc) 1784 return rc; 1785 1786 if (bp->tx_push_size) { 1787 dma_addr_t mapping; 1788 1789 /* One pre-allocated DMA buffer to backup 1790 * TX push operation 1791 */ 1792 txr->tx_push = dma_alloc_coherent(&pdev->dev, 1793 bp->tx_push_size, 1794 &txr->tx_push_mapping, 1795 GFP_KERNEL); 1796 1797 if (!txr->tx_push) 1798 return -ENOMEM; 1799 1800 mapping = txr->tx_push_mapping + 1801 sizeof(struct tx_push_bd); 1802 txr->data_mapping = cpu_to_le64(mapping); 1803 1804 memset(txr->tx_push, 0, sizeof(struct tx_push_bd)); 1805 } 1806 ring->queue_id = bp->q_info[j].queue_id; 1807 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) 1808 j++; 1809 } 1810 return 0; 1811 } 1812 1813 static void bnxt_free_cp_rings(struct bnxt *bp) 1814 { 1815 int i; 1816 1817 if (!bp->bnapi) 1818 return; 1819 1820 for (i = 0; i < bp->cp_nr_rings; i++) { 1821 struct bnxt_napi *bnapi = bp->bnapi[i]; 1822 struct bnxt_cp_ring_info *cpr; 1823 struct bnxt_ring_struct *ring; 1824 1825 if (!bnapi) 1826 continue; 1827 1828 cpr = &bnapi->cp_ring; 1829 ring = &cpr->cp_ring_struct; 1830 1831 bnxt_free_ring(bp, ring); 1832 } 1833 } 1834 1835 static int bnxt_alloc_cp_rings(struct bnxt *bp) 1836 { 1837 int i, rc; 1838 1839 for (i = 0; i < bp->cp_nr_rings; i++) { 1840 struct bnxt_napi *bnapi = bp->bnapi[i]; 1841 struct bnxt_cp_ring_info *cpr; 1842 struct bnxt_ring_struct *ring; 1843 1844 if (!bnapi) 1845 continue; 1846 1847 cpr = &bnapi->cp_ring; 1848 ring = &cpr->cp_ring_struct; 1849 1850 rc = bnxt_alloc_ring(bp, ring); 1851 if (rc) 1852 return rc; 1853 } 1854 return 0; 1855 } 1856 1857 static void bnxt_init_ring_struct(struct bnxt *bp) 1858 { 1859 int i; 1860 1861 for (i = 0; i < bp->cp_nr_rings; i++) { 1862 struct bnxt_napi *bnapi = bp->bnapi[i]; 1863 struct bnxt_cp_ring_info *cpr; 1864 struct bnxt_rx_ring_info *rxr; 1865 struct bnxt_tx_ring_info *txr; 1866 struct bnxt_ring_struct *ring; 1867 1868 if (!bnapi) 1869 continue; 1870 1871 cpr = &bnapi->cp_ring; 1872 ring = &cpr->cp_ring_struct; 1873 ring->nr_pages = bp->cp_nr_pages; 1874 ring->page_size = HW_CMPD_RING_SIZE; 1875 ring->pg_arr = (void **)cpr->cp_desc_ring; 1876 ring->dma_arr = cpr->cp_desc_mapping; 1877 ring->vmem_size = 0; 1878 1879 rxr = bnapi->rx_ring; 1880 if (!rxr) 1881 goto skip_rx; 1882 1883 ring = &rxr->rx_ring_struct; 1884 ring->nr_pages = bp->rx_nr_pages; 1885 ring->page_size = HW_RXBD_RING_SIZE; 1886 ring->pg_arr = (void **)rxr->rx_desc_ring; 1887 ring->dma_arr = rxr->rx_desc_mapping; 1888 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; 1889 ring->vmem = (void **)&rxr->rx_buf_ring; 1890 1891 ring = &rxr->rx_agg_ring_struct; 1892 ring->nr_pages = bp->rx_agg_nr_pages; 1893 ring->page_size = HW_RXBD_RING_SIZE; 1894 ring->pg_arr = (void **)rxr->rx_agg_desc_ring; 1895 ring->dma_arr = rxr->rx_agg_desc_mapping; 1896 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; 1897 ring->vmem = (void **)&rxr->rx_agg_ring; 1898 1899 skip_rx: 1900 txr = bnapi->tx_ring; 1901 if (!txr) 1902 continue; 1903 1904 ring = &txr->tx_ring_struct; 1905 ring->nr_pages = bp->tx_nr_pages; 1906 ring->page_size = HW_RXBD_RING_SIZE; 1907 ring->pg_arr = (void **)txr->tx_desc_ring; 1908 ring->dma_arr = txr->tx_desc_mapping; 1909 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; 1910 ring->vmem = (void **)&txr->tx_buf_ring; 1911 } 1912 } 1913 1914 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) 1915 { 1916 int i; 1917 u32 prod; 1918 struct rx_bd **rx_buf_ring; 1919 1920 rx_buf_ring = (struct rx_bd **)ring->pg_arr; 1921 for (i = 0, prod = 0; i < ring->nr_pages; i++) { 1922 int j; 1923 struct rx_bd *rxbd; 1924 1925 rxbd = rx_buf_ring[i]; 1926 if (!rxbd) 1927 continue; 1928 1929 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { 1930 rxbd->rx_bd_len_flags_type = cpu_to_le32(type); 1931 rxbd->rx_bd_opaque = prod; 1932 } 1933 } 1934 } 1935 1936 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) 1937 { 1938 struct net_device *dev = bp->dev; 1939 struct bnxt_rx_ring_info *rxr; 1940 struct bnxt_ring_struct *ring; 1941 u32 prod, type; 1942 int i; 1943 1944 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | 1945 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; 1946 1947 if (NET_IP_ALIGN == 2) 1948 type |= RX_BD_FLAGS_SOP; 1949 1950 rxr = &bp->rx_ring[ring_nr]; 1951 ring = &rxr->rx_ring_struct; 1952 bnxt_init_rxbd_pages(ring, type); 1953 1954 prod = rxr->rx_prod; 1955 for (i = 0; i < bp->rx_ring_size; i++) { 1956 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) { 1957 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", 1958 ring_nr, i, bp->rx_ring_size); 1959 break; 1960 } 1961 prod = NEXT_RX(prod); 1962 } 1963 rxr->rx_prod = prod; 1964 ring->fw_ring_id = INVALID_HW_RING_ID; 1965 1966 ring = &rxr->rx_agg_ring_struct; 1967 ring->fw_ring_id = INVALID_HW_RING_ID; 1968 1969 if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) 1970 return 0; 1971 1972 type = ((u32)PAGE_SIZE << RX_BD_LEN_SHIFT) | 1973 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; 1974 1975 bnxt_init_rxbd_pages(ring, type); 1976 1977 prod = rxr->rx_agg_prod; 1978 for (i = 0; i < bp->rx_agg_ring_size; i++) { 1979 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) { 1980 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", 1981 ring_nr, i, bp->rx_ring_size); 1982 break; 1983 } 1984 prod = NEXT_RX_AGG(prod); 1985 } 1986 rxr->rx_agg_prod = prod; 1987 1988 if (bp->flags & BNXT_FLAG_TPA) { 1989 if (rxr->rx_tpa) { 1990 u8 *data; 1991 dma_addr_t mapping; 1992 1993 for (i = 0; i < MAX_TPA; i++) { 1994 data = __bnxt_alloc_rx_data(bp, &mapping, 1995 GFP_KERNEL); 1996 if (!data) 1997 return -ENOMEM; 1998 1999 rxr->rx_tpa[i].data = data; 2000 rxr->rx_tpa[i].mapping = mapping; 2001 } 2002 } else { 2003 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n"); 2004 return -ENOMEM; 2005 } 2006 } 2007 2008 return 0; 2009 } 2010 2011 static int bnxt_init_rx_rings(struct bnxt *bp) 2012 { 2013 int i, rc = 0; 2014 2015 for (i = 0; i < bp->rx_nr_rings; i++) { 2016 rc = bnxt_init_one_rx_ring(bp, i); 2017 if (rc) 2018 break; 2019 } 2020 2021 return rc; 2022 } 2023 2024 static int bnxt_init_tx_rings(struct bnxt *bp) 2025 { 2026 u16 i; 2027 2028 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, 2029 MAX_SKB_FRAGS + 1); 2030 2031 for (i = 0; i < bp->tx_nr_rings; i++) { 2032 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2033 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 2034 2035 ring->fw_ring_id = INVALID_HW_RING_ID; 2036 } 2037 2038 return 0; 2039 } 2040 2041 static void bnxt_free_ring_grps(struct bnxt *bp) 2042 { 2043 kfree(bp->grp_info); 2044 bp->grp_info = NULL; 2045 } 2046 2047 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) 2048 { 2049 int i; 2050 2051 if (irq_re_init) { 2052 bp->grp_info = kcalloc(bp->cp_nr_rings, 2053 sizeof(struct bnxt_ring_grp_info), 2054 GFP_KERNEL); 2055 if (!bp->grp_info) 2056 return -ENOMEM; 2057 } 2058 for (i = 0; i < bp->cp_nr_rings; i++) { 2059 if (irq_re_init) 2060 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; 2061 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 2062 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; 2063 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; 2064 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 2065 } 2066 return 0; 2067 } 2068 2069 static void bnxt_free_vnics(struct bnxt *bp) 2070 { 2071 kfree(bp->vnic_info); 2072 bp->vnic_info = NULL; 2073 bp->nr_vnics = 0; 2074 } 2075 2076 static int bnxt_alloc_vnics(struct bnxt *bp) 2077 { 2078 int num_vnics = 1; 2079 2080 #ifdef CONFIG_RFS_ACCEL 2081 if (bp->flags & BNXT_FLAG_RFS) 2082 num_vnics += bp->rx_nr_rings; 2083 #endif 2084 2085 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), 2086 GFP_KERNEL); 2087 if (!bp->vnic_info) 2088 return -ENOMEM; 2089 2090 bp->nr_vnics = num_vnics; 2091 return 0; 2092 } 2093 2094 static void bnxt_init_vnics(struct bnxt *bp) 2095 { 2096 int i; 2097 2098 for (i = 0; i < bp->nr_vnics; i++) { 2099 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2100 2101 vnic->fw_vnic_id = INVALID_HW_RING_ID; 2102 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID; 2103 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; 2104 2105 if (bp->vnic_info[i].rss_hash_key) { 2106 if (i == 0) 2107 prandom_bytes(vnic->rss_hash_key, 2108 HW_HASH_KEY_SIZE); 2109 else 2110 memcpy(vnic->rss_hash_key, 2111 bp->vnic_info[0].rss_hash_key, 2112 HW_HASH_KEY_SIZE); 2113 } 2114 } 2115 } 2116 2117 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) 2118 { 2119 int pages; 2120 2121 pages = ring_size / desc_per_pg; 2122 2123 if (!pages) 2124 return 1; 2125 2126 pages++; 2127 2128 while (pages & (pages - 1)) 2129 pages++; 2130 2131 return pages; 2132 } 2133 2134 static void bnxt_set_tpa_flags(struct bnxt *bp) 2135 { 2136 bp->flags &= ~BNXT_FLAG_TPA; 2137 if (bp->dev->features & NETIF_F_LRO) 2138 bp->flags |= BNXT_FLAG_LRO; 2139 if ((bp->dev->features & NETIF_F_GRO) && (bp->pdev->revision > 0)) 2140 bp->flags |= BNXT_FLAG_GRO; 2141 } 2142 2143 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must 2144 * be set on entry. 2145 */ 2146 void bnxt_set_ring_params(struct bnxt *bp) 2147 { 2148 u32 ring_size, rx_size, rx_space; 2149 u32 agg_factor = 0, agg_ring_size = 0; 2150 2151 /* 8 for CRC and VLAN */ 2152 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); 2153 2154 rx_space = rx_size + NET_SKB_PAD + 2155 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2156 2157 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; 2158 ring_size = bp->rx_ring_size; 2159 bp->rx_agg_ring_size = 0; 2160 bp->rx_agg_nr_pages = 0; 2161 2162 if (bp->flags & BNXT_FLAG_TPA) 2163 agg_factor = 4; 2164 2165 bp->flags &= ~BNXT_FLAG_JUMBO; 2166 if (rx_space > PAGE_SIZE) { 2167 u32 jumbo_factor; 2168 2169 bp->flags |= BNXT_FLAG_JUMBO; 2170 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; 2171 if (jumbo_factor > agg_factor) 2172 agg_factor = jumbo_factor; 2173 } 2174 agg_ring_size = ring_size * agg_factor; 2175 2176 if (agg_ring_size) { 2177 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, 2178 RX_DESC_CNT); 2179 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { 2180 u32 tmp = agg_ring_size; 2181 2182 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; 2183 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; 2184 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", 2185 tmp, agg_ring_size); 2186 } 2187 bp->rx_agg_ring_size = agg_ring_size; 2188 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; 2189 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); 2190 rx_space = rx_size + NET_SKB_PAD + 2191 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2192 } 2193 2194 bp->rx_buf_use_size = rx_size; 2195 bp->rx_buf_size = rx_space; 2196 2197 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); 2198 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; 2199 2200 ring_size = bp->tx_ring_size; 2201 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); 2202 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; 2203 2204 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size; 2205 bp->cp_ring_size = ring_size; 2206 2207 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); 2208 if (bp->cp_nr_pages > MAX_CP_PAGES) { 2209 bp->cp_nr_pages = MAX_CP_PAGES; 2210 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; 2211 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", 2212 ring_size, bp->cp_ring_size); 2213 } 2214 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; 2215 bp->cp_ring_mask = bp->cp_bit - 1; 2216 } 2217 2218 static void bnxt_free_vnic_attributes(struct bnxt *bp) 2219 { 2220 int i; 2221 struct bnxt_vnic_info *vnic; 2222 struct pci_dev *pdev = bp->pdev; 2223 2224 if (!bp->vnic_info) 2225 return; 2226 2227 for (i = 0; i < bp->nr_vnics; i++) { 2228 vnic = &bp->vnic_info[i]; 2229 2230 kfree(vnic->fw_grp_ids); 2231 vnic->fw_grp_ids = NULL; 2232 2233 kfree(vnic->uc_list); 2234 vnic->uc_list = NULL; 2235 2236 if (vnic->mc_list) { 2237 dma_free_coherent(&pdev->dev, vnic->mc_list_size, 2238 vnic->mc_list, vnic->mc_list_mapping); 2239 vnic->mc_list = NULL; 2240 } 2241 2242 if (vnic->rss_table) { 2243 dma_free_coherent(&pdev->dev, PAGE_SIZE, 2244 vnic->rss_table, 2245 vnic->rss_table_dma_addr); 2246 vnic->rss_table = NULL; 2247 } 2248 2249 vnic->rss_hash_key = NULL; 2250 vnic->flags = 0; 2251 } 2252 } 2253 2254 static int bnxt_alloc_vnic_attributes(struct bnxt *bp) 2255 { 2256 int i, rc = 0, size; 2257 struct bnxt_vnic_info *vnic; 2258 struct pci_dev *pdev = bp->pdev; 2259 int max_rings; 2260 2261 for (i = 0; i < bp->nr_vnics; i++) { 2262 vnic = &bp->vnic_info[i]; 2263 2264 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { 2265 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; 2266 2267 if (mem_size > 0) { 2268 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); 2269 if (!vnic->uc_list) { 2270 rc = -ENOMEM; 2271 goto out; 2272 } 2273 } 2274 } 2275 2276 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { 2277 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; 2278 vnic->mc_list = 2279 dma_alloc_coherent(&pdev->dev, 2280 vnic->mc_list_size, 2281 &vnic->mc_list_mapping, 2282 GFP_KERNEL); 2283 if (!vnic->mc_list) { 2284 rc = -ENOMEM; 2285 goto out; 2286 } 2287 } 2288 2289 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 2290 max_rings = bp->rx_nr_rings; 2291 else 2292 max_rings = 1; 2293 2294 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); 2295 if (!vnic->fw_grp_ids) { 2296 rc = -ENOMEM; 2297 goto out; 2298 } 2299 2300 /* Allocate rss table and hash key */ 2301 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 2302 &vnic->rss_table_dma_addr, 2303 GFP_KERNEL); 2304 if (!vnic->rss_table) { 2305 rc = -ENOMEM; 2306 goto out; 2307 } 2308 2309 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); 2310 2311 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 2312 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 2313 } 2314 return 0; 2315 2316 out: 2317 return rc; 2318 } 2319 2320 static void bnxt_free_hwrm_resources(struct bnxt *bp) 2321 { 2322 struct pci_dev *pdev = bp->pdev; 2323 2324 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr, 2325 bp->hwrm_cmd_resp_dma_addr); 2326 2327 bp->hwrm_cmd_resp_addr = NULL; 2328 if (bp->hwrm_dbg_resp_addr) { 2329 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE, 2330 bp->hwrm_dbg_resp_addr, 2331 bp->hwrm_dbg_resp_dma_addr); 2332 2333 bp->hwrm_dbg_resp_addr = NULL; 2334 } 2335 } 2336 2337 static int bnxt_alloc_hwrm_resources(struct bnxt *bp) 2338 { 2339 struct pci_dev *pdev = bp->pdev; 2340 2341 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 2342 &bp->hwrm_cmd_resp_dma_addr, 2343 GFP_KERNEL); 2344 if (!bp->hwrm_cmd_resp_addr) 2345 return -ENOMEM; 2346 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev, 2347 HWRM_DBG_REG_BUF_SIZE, 2348 &bp->hwrm_dbg_resp_dma_addr, 2349 GFP_KERNEL); 2350 if (!bp->hwrm_dbg_resp_addr) 2351 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n"); 2352 2353 return 0; 2354 } 2355 2356 static void bnxt_free_stats(struct bnxt *bp) 2357 { 2358 u32 size, i; 2359 struct pci_dev *pdev = bp->pdev; 2360 2361 if (!bp->bnapi) 2362 return; 2363 2364 size = sizeof(struct ctx_hw_stats); 2365 2366 for (i = 0; i < bp->cp_nr_rings; i++) { 2367 struct bnxt_napi *bnapi = bp->bnapi[i]; 2368 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2369 2370 if (cpr->hw_stats) { 2371 dma_free_coherent(&pdev->dev, size, cpr->hw_stats, 2372 cpr->hw_stats_map); 2373 cpr->hw_stats = NULL; 2374 } 2375 } 2376 } 2377 2378 static int bnxt_alloc_stats(struct bnxt *bp) 2379 { 2380 u32 size, i; 2381 struct pci_dev *pdev = bp->pdev; 2382 2383 size = sizeof(struct ctx_hw_stats); 2384 2385 for (i = 0; i < bp->cp_nr_rings; i++) { 2386 struct bnxt_napi *bnapi = bp->bnapi[i]; 2387 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2388 2389 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size, 2390 &cpr->hw_stats_map, 2391 GFP_KERNEL); 2392 if (!cpr->hw_stats) 2393 return -ENOMEM; 2394 2395 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 2396 } 2397 return 0; 2398 } 2399 2400 static void bnxt_clear_ring_indices(struct bnxt *bp) 2401 { 2402 int i; 2403 2404 if (!bp->bnapi) 2405 return; 2406 2407 for (i = 0; i < bp->cp_nr_rings; i++) { 2408 struct bnxt_napi *bnapi = bp->bnapi[i]; 2409 struct bnxt_cp_ring_info *cpr; 2410 struct bnxt_rx_ring_info *rxr; 2411 struct bnxt_tx_ring_info *txr; 2412 2413 if (!bnapi) 2414 continue; 2415 2416 cpr = &bnapi->cp_ring; 2417 cpr->cp_raw_cons = 0; 2418 2419 txr = bnapi->tx_ring; 2420 if (txr) { 2421 txr->tx_prod = 0; 2422 txr->tx_cons = 0; 2423 } 2424 2425 rxr = bnapi->rx_ring; 2426 if (rxr) { 2427 rxr->rx_prod = 0; 2428 rxr->rx_agg_prod = 0; 2429 rxr->rx_sw_agg_prod = 0; 2430 } 2431 } 2432 } 2433 2434 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) 2435 { 2436 #ifdef CONFIG_RFS_ACCEL 2437 int i; 2438 2439 /* Under rtnl_lock and all our NAPIs have been disabled. It's 2440 * safe to delete the hash table. 2441 */ 2442 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 2443 struct hlist_head *head; 2444 struct hlist_node *tmp; 2445 struct bnxt_ntuple_filter *fltr; 2446 2447 head = &bp->ntp_fltr_hash_tbl[i]; 2448 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 2449 hlist_del(&fltr->hash); 2450 kfree(fltr); 2451 } 2452 } 2453 if (irq_reinit) { 2454 kfree(bp->ntp_fltr_bmap); 2455 bp->ntp_fltr_bmap = NULL; 2456 } 2457 bp->ntp_fltr_count = 0; 2458 #endif 2459 } 2460 2461 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) 2462 { 2463 #ifdef CONFIG_RFS_ACCEL 2464 int i, rc = 0; 2465 2466 if (!(bp->flags & BNXT_FLAG_RFS)) 2467 return 0; 2468 2469 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) 2470 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); 2471 2472 bp->ntp_fltr_count = 0; 2473 bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR), 2474 GFP_KERNEL); 2475 2476 if (!bp->ntp_fltr_bmap) 2477 rc = -ENOMEM; 2478 2479 return rc; 2480 #else 2481 return 0; 2482 #endif 2483 } 2484 2485 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) 2486 { 2487 bnxt_free_vnic_attributes(bp); 2488 bnxt_free_tx_rings(bp); 2489 bnxt_free_rx_rings(bp); 2490 bnxt_free_cp_rings(bp); 2491 bnxt_free_ntp_fltrs(bp, irq_re_init); 2492 if (irq_re_init) { 2493 bnxt_free_stats(bp); 2494 bnxt_free_ring_grps(bp); 2495 bnxt_free_vnics(bp); 2496 kfree(bp->tx_ring); 2497 bp->tx_ring = NULL; 2498 kfree(bp->rx_ring); 2499 bp->rx_ring = NULL; 2500 kfree(bp->bnapi); 2501 bp->bnapi = NULL; 2502 } else { 2503 bnxt_clear_ring_indices(bp); 2504 } 2505 } 2506 2507 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) 2508 { 2509 int i, j, rc, size, arr_size; 2510 void *bnapi; 2511 2512 if (irq_re_init) { 2513 /* Allocate bnapi mem pointer array and mem block for 2514 * all queues 2515 */ 2516 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * 2517 bp->cp_nr_rings); 2518 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); 2519 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); 2520 if (!bnapi) 2521 return -ENOMEM; 2522 2523 bp->bnapi = bnapi; 2524 bnapi += arr_size; 2525 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { 2526 bp->bnapi[i] = bnapi; 2527 bp->bnapi[i]->index = i; 2528 bp->bnapi[i]->bp = bp; 2529 } 2530 2531 bp->rx_ring = kcalloc(bp->rx_nr_rings, 2532 sizeof(struct bnxt_rx_ring_info), 2533 GFP_KERNEL); 2534 if (!bp->rx_ring) 2535 return -ENOMEM; 2536 2537 for (i = 0; i < bp->rx_nr_rings; i++) { 2538 bp->rx_ring[i].bnapi = bp->bnapi[i]; 2539 bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; 2540 } 2541 2542 bp->tx_ring = kcalloc(bp->tx_nr_rings, 2543 sizeof(struct bnxt_tx_ring_info), 2544 GFP_KERNEL); 2545 if (!bp->tx_ring) 2546 return -ENOMEM; 2547 2548 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 2549 j = 0; 2550 else 2551 j = bp->rx_nr_rings; 2552 2553 for (i = 0; i < bp->tx_nr_rings; i++, j++) { 2554 bp->tx_ring[i].bnapi = bp->bnapi[j]; 2555 bp->bnapi[j]->tx_ring = &bp->tx_ring[i]; 2556 } 2557 2558 rc = bnxt_alloc_stats(bp); 2559 if (rc) 2560 goto alloc_mem_err; 2561 2562 rc = bnxt_alloc_ntp_fltrs(bp); 2563 if (rc) 2564 goto alloc_mem_err; 2565 2566 rc = bnxt_alloc_vnics(bp); 2567 if (rc) 2568 goto alloc_mem_err; 2569 } 2570 2571 bnxt_init_ring_struct(bp); 2572 2573 rc = bnxt_alloc_rx_rings(bp); 2574 if (rc) 2575 goto alloc_mem_err; 2576 2577 rc = bnxt_alloc_tx_rings(bp); 2578 if (rc) 2579 goto alloc_mem_err; 2580 2581 rc = bnxt_alloc_cp_rings(bp); 2582 if (rc) 2583 goto alloc_mem_err; 2584 2585 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | 2586 BNXT_VNIC_UCAST_FLAG; 2587 rc = bnxt_alloc_vnic_attributes(bp); 2588 if (rc) 2589 goto alloc_mem_err; 2590 return 0; 2591 2592 alloc_mem_err: 2593 bnxt_free_mem(bp, true); 2594 return rc; 2595 } 2596 2597 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type, 2598 u16 cmpl_ring, u16 target_id) 2599 { 2600 struct hwrm_cmd_req_hdr *req = request; 2601 2602 req->cmpl_ring_req_type = 2603 cpu_to_le32(req_type | (cmpl_ring << HWRM_CMPL_RING_SFT)); 2604 req->target_id_seq_id = cpu_to_le32(target_id << HWRM_TARGET_FID_SFT); 2605 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr); 2606 } 2607 2608 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 2609 { 2610 int i, intr_process, rc; 2611 struct hwrm_cmd_req_hdr *req = msg; 2612 u32 *data = msg; 2613 __le32 *resp_len, *valid; 2614 u16 cp_ring_id, len = 0; 2615 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr; 2616 2617 req->target_id_seq_id |= cpu_to_le32(bp->hwrm_cmd_seq++); 2618 memset(resp, 0, PAGE_SIZE); 2619 cp_ring_id = (le32_to_cpu(req->cmpl_ring_req_type) & 2620 HWRM_CMPL_RING_MASK) >> 2621 HWRM_CMPL_RING_SFT; 2622 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1; 2623 2624 /* Write request msg to hwrm channel */ 2625 __iowrite32_copy(bp->bar0, data, msg_len / 4); 2626 2627 for (i = msg_len; i < HWRM_MAX_REQ_LEN; i += 4) 2628 writel(0, bp->bar0 + i); 2629 2630 /* currently supports only one outstanding message */ 2631 if (intr_process) 2632 bp->hwrm_intr_seq_id = le32_to_cpu(req->target_id_seq_id) & 2633 HWRM_SEQ_ID_MASK; 2634 2635 /* Ring channel doorbell */ 2636 writel(1, bp->bar0 + 0x100); 2637 2638 i = 0; 2639 if (intr_process) { 2640 /* Wait until hwrm response cmpl interrupt is processed */ 2641 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID && 2642 i++ < timeout) { 2643 usleep_range(600, 800); 2644 } 2645 2646 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) { 2647 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n", 2648 req->cmpl_ring_req_type); 2649 return -1; 2650 } 2651 } else { 2652 /* Check if response len is updated */ 2653 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET; 2654 for (i = 0; i < timeout; i++) { 2655 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> 2656 HWRM_RESP_LEN_SFT; 2657 if (len) 2658 break; 2659 usleep_range(600, 800); 2660 } 2661 2662 if (i >= timeout) { 2663 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n", 2664 timeout, req->cmpl_ring_req_type, 2665 req->target_id_seq_id, *resp_len); 2666 return -1; 2667 } 2668 2669 /* Last word of resp contains valid bit */ 2670 valid = bp->hwrm_cmd_resp_addr + len - 4; 2671 for (i = 0; i < timeout; i++) { 2672 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK) 2673 break; 2674 usleep_range(600, 800); 2675 } 2676 2677 if (i >= timeout) { 2678 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n", 2679 timeout, req->cmpl_ring_req_type, 2680 req->target_id_seq_id, len, *valid); 2681 return -1; 2682 } 2683 } 2684 2685 rc = le16_to_cpu(resp->error_code); 2686 if (rc) { 2687 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n", 2688 le16_to_cpu(resp->req_type), 2689 le16_to_cpu(resp->seq_id), rc); 2690 return rc; 2691 } 2692 return 0; 2693 } 2694 2695 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 2696 { 2697 int rc; 2698 2699 mutex_lock(&bp->hwrm_cmd_lock); 2700 rc = _hwrm_send_message(bp, msg, msg_len, timeout); 2701 mutex_unlock(&bp->hwrm_cmd_lock); 2702 return rc; 2703 } 2704 2705 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp) 2706 { 2707 struct hwrm_func_drv_rgtr_input req = {0}; 2708 int i; 2709 2710 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 2711 2712 req.enables = 2713 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | 2714 FUNC_DRV_RGTR_REQ_ENABLES_VER | 2715 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 2716 2717 /* TODO: current async event fwd bits are not defined and the firmware 2718 * only checks if it is non-zero to enable async event forwarding 2719 */ 2720 req.async_event_fwd[0] |= cpu_to_le32(1); 2721 req.os_type = cpu_to_le16(1); 2722 req.ver_maj = DRV_VER_MAJ; 2723 req.ver_min = DRV_VER_MIN; 2724 req.ver_upd = DRV_VER_UPD; 2725 2726 if (BNXT_PF(bp)) { 2727 DECLARE_BITMAP(vf_req_snif_bmap, 256); 2728 u32 *data = (u32 *)vf_req_snif_bmap; 2729 2730 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap)); 2731 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) 2732 __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap); 2733 2734 for (i = 0; i < 8; i++) 2735 req.vf_req_fwd[i] = cpu_to_le32(data[i]); 2736 2737 req.enables |= 2738 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); 2739 } 2740 2741 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2742 } 2743 2744 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) 2745 { 2746 struct hwrm_func_drv_unrgtr_input req = {0}; 2747 2748 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1); 2749 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2750 } 2751 2752 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) 2753 { 2754 u32 rc = 0; 2755 struct hwrm_tunnel_dst_port_free_input req = {0}; 2756 2757 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1); 2758 req.tunnel_type = tunnel_type; 2759 2760 switch (tunnel_type) { 2761 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: 2762 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id; 2763 break; 2764 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: 2765 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id; 2766 break; 2767 default: 2768 break; 2769 } 2770 2771 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2772 if (rc) 2773 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", 2774 rc); 2775 return rc; 2776 } 2777 2778 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, 2779 u8 tunnel_type) 2780 { 2781 u32 rc = 0; 2782 struct hwrm_tunnel_dst_port_alloc_input req = {0}; 2783 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr; 2784 2785 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1); 2786 2787 req.tunnel_type = tunnel_type; 2788 req.tunnel_dst_port_val = port; 2789 2790 mutex_lock(&bp->hwrm_cmd_lock); 2791 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2792 if (rc) { 2793 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", 2794 rc); 2795 goto err_out; 2796 } 2797 2798 if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN) 2799 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id; 2800 2801 else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE) 2802 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id; 2803 err_out: 2804 mutex_unlock(&bp->hwrm_cmd_lock); 2805 return rc; 2806 } 2807 2808 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) 2809 { 2810 struct hwrm_cfa_l2_set_rx_mask_input req = {0}; 2811 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 2812 2813 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1); 2814 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 2815 2816 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count); 2817 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); 2818 req.mask = cpu_to_le32(vnic->rx_mask); 2819 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2820 } 2821 2822 #ifdef CONFIG_RFS_ACCEL 2823 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, 2824 struct bnxt_ntuple_filter *fltr) 2825 { 2826 struct hwrm_cfa_ntuple_filter_free_input req = {0}; 2827 2828 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1); 2829 req.ntuple_filter_id = fltr->filter_id; 2830 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2831 } 2832 2833 #define BNXT_NTP_FLTR_FLAGS \ 2834 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ 2835 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ 2836 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ 2837 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ 2838 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ 2839 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ 2840 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ 2841 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ 2842 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ 2843 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ 2844 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ 2845 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ 2846 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ 2847 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) 2848 2849 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, 2850 struct bnxt_ntuple_filter *fltr) 2851 { 2852 int rc = 0; 2853 struct hwrm_cfa_ntuple_filter_alloc_input req = {0}; 2854 struct hwrm_cfa_ntuple_filter_alloc_output *resp = 2855 bp->hwrm_cmd_resp_addr; 2856 struct flow_keys *keys = &fltr->fkeys; 2857 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1]; 2858 2859 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1); 2860 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[0]; 2861 2862 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS); 2863 2864 req.ethertype = htons(ETH_P_IP); 2865 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN); 2866 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; 2867 req.ip_protocol = keys->basic.ip_proto; 2868 2869 req.src_ipaddr[0] = keys->addrs.v4addrs.src; 2870 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 2871 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst; 2872 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 2873 2874 req.src_port = keys->ports.src; 2875 req.src_port_mask = cpu_to_be16(0xffff); 2876 req.dst_port = keys->ports.dst; 2877 req.dst_port_mask = cpu_to_be16(0xffff); 2878 2879 req.dst_id = cpu_to_le16(vnic->fw_vnic_id); 2880 mutex_lock(&bp->hwrm_cmd_lock); 2881 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2882 if (!rc) 2883 fltr->filter_id = resp->ntuple_filter_id; 2884 mutex_unlock(&bp->hwrm_cmd_lock); 2885 return rc; 2886 } 2887 #endif 2888 2889 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, 2890 u8 *mac_addr) 2891 { 2892 u32 rc = 0; 2893 struct hwrm_cfa_l2_filter_alloc_input req = {0}; 2894 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 2895 2896 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1); 2897 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX | 2898 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); 2899 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); 2900 req.enables = 2901 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | 2902 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | 2903 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); 2904 memcpy(req.l2_addr, mac_addr, ETH_ALEN); 2905 req.l2_addr_mask[0] = 0xff; 2906 req.l2_addr_mask[1] = 0xff; 2907 req.l2_addr_mask[2] = 0xff; 2908 req.l2_addr_mask[3] = 0xff; 2909 req.l2_addr_mask[4] = 0xff; 2910 req.l2_addr_mask[5] = 0xff; 2911 2912 mutex_lock(&bp->hwrm_cmd_lock); 2913 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2914 if (!rc) 2915 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = 2916 resp->l2_filter_id; 2917 mutex_unlock(&bp->hwrm_cmd_lock); 2918 return rc; 2919 } 2920 2921 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) 2922 { 2923 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ 2924 int rc = 0; 2925 2926 /* Any associated ntuple filters will also be cleared by firmware. */ 2927 mutex_lock(&bp->hwrm_cmd_lock); 2928 for (i = 0; i < num_of_vnics; i++) { 2929 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2930 2931 for (j = 0; j < vnic->uc_filter_count; j++) { 2932 struct hwrm_cfa_l2_filter_free_input req = {0}; 2933 2934 bnxt_hwrm_cmd_hdr_init(bp, &req, 2935 HWRM_CFA_L2_FILTER_FREE, -1, -1); 2936 2937 req.l2_filter_id = vnic->fw_l2_filter_id[j]; 2938 2939 rc = _hwrm_send_message(bp, &req, sizeof(req), 2940 HWRM_CMD_TIMEOUT); 2941 } 2942 vnic->uc_filter_count = 0; 2943 } 2944 mutex_unlock(&bp->hwrm_cmd_lock); 2945 2946 return rc; 2947 } 2948 2949 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) 2950 { 2951 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 2952 struct hwrm_vnic_tpa_cfg_input req = {0}; 2953 2954 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1); 2955 2956 if (tpa_flags) { 2957 u16 mss = bp->dev->mtu - 40; 2958 u32 nsegs, n, segs = 0, flags; 2959 2960 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | 2961 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | 2962 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | 2963 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | 2964 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; 2965 if (tpa_flags & BNXT_FLAG_GRO) 2966 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; 2967 2968 req.flags = cpu_to_le32(flags); 2969 2970 req.enables = 2971 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | 2972 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | 2973 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); 2974 2975 /* Number of segs are log2 units, and first packet is not 2976 * included as part of this units. 2977 */ 2978 if (mss <= PAGE_SIZE) { 2979 n = PAGE_SIZE / mss; 2980 nsegs = (MAX_SKB_FRAGS - 1) * n; 2981 } else { 2982 n = mss / PAGE_SIZE; 2983 if (mss & (PAGE_SIZE - 1)) 2984 n++; 2985 nsegs = (MAX_SKB_FRAGS - n) / n; 2986 } 2987 2988 segs = ilog2(nsegs); 2989 req.max_agg_segs = cpu_to_le16(segs); 2990 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX); 2991 2992 req.min_agg_len = cpu_to_le32(512); 2993 } 2994 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 2995 2996 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2997 } 2998 2999 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) 3000 { 3001 u32 i, j, max_rings; 3002 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3003 struct hwrm_vnic_rss_cfg_input req = {0}; 3004 3005 if (vnic->fw_rss_cos_lb_ctx == INVALID_HW_RING_ID) 3006 return 0; 3007 3008 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 3009 if (set_rss) { 3010 vnic->hash_type = BNXT_RSS_HASH_TYPE_FLAG_IPV4 | 3011 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 | 3012 BNXT_RSS_HASH_TYPE_FLAG_IPV6 | 3013 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6; 3014 3015 req.hash_type = cpu_to_le32(vnic->hash_type); 3016 3017 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 3018 max_rings = bp->rx_nr_rings; 3019 else 3020 max_rings = 1; 3021 3022 /* Fill the RSS indirection table with ring group ids */ 3023 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) { 3024 if (j == max_rings) 3025 j = 0; 3026 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); 3027 } 3028 3029 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 3030 req.hash_key_tbl_addr = 3031 cpu_to_le64(vnic->rss_hash_key_dma_addr); 3032 } 3033 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx); 3034 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3035 } 3036 3037 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) 3038 { 3039 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3040 struct hwrm_vnic_plcmodes_cfg_input req = {0}; 3041 3042 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1); 3043 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT | 3044 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | 3045 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); 3046 req.enables = 3047 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID | 3048 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); 3049 /* thresholds not implemented in firmware yet */ 3050 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); 3051 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh); 3052 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 3053 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3054 } 3055 3056 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id) 3057 { 3058 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0}; 3059 3060 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1); 3061 req.rss_cos_lb_ctx_id = 3062 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx); 3063 3064 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3065 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID; 3066 } 3067 3068 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) 3069 { 3070 int i; 3071 3072 for (i = 0; i < bp->nr_vnics; i++) { 3073 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3074 3075 if (vnic->fw_rss_cos_lb_ctx != INVALID_HW_RING_ID) 3076 bnxt_hwrm_vnic_ctx_free_one(bp, i); 3077 } 3078 bp->rsscos_nr_ctxs = 0; 3079 } 3080 3081 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id) 3082 { 3083 int rc; 3084 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; 3085 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = 3086 bp->hwrm_cmd_resp_addr; 3087 3088 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1, 3089 -1); 3090 3091 mutex_lock(&bp->hwrm_cmd_lock); 3092 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3093 if (!rc) 3094 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = 3095 le16_to_cpu(resp->rss_cos_lb_ctx_id); 3096 mutex_unlock(&bp->hwrm_cmd_lock); 3097 3098 return rc; 3099 } 3100 3101 static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) 3102 { 3103 unsigned int ring = 0, grp_idx; 3104 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3105 struct hwrm_vnic_cfg_input req = {0}; 3106 3107 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1); 3108 /* Only RSS support for now TBD: COS & LB */ 3109 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP | 3110 VNIC_CFG_REQ_ENABLES_RSS_RULE); 3111 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx); 3112 req.cos_rule = cpu_to_le16(0xffff); 3113 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 3114 ring = 0; 3115 else if (vnic->flags & BNXT_VNIC_RFS_FLAG) 3116 ring = vnic_id - 1; 3117 3118 grp_idx = bp->rx_ring[ring].bnapi->index; 3119 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 3120 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); 3121 3122 req.lb_rule = cpu_to_le16(0xffff); 3123 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + 3124 VLAN_HLEN); 3125 3126 if (bp->flags & BNXT_FLAG_STRIP_VLAN) 3127 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); 3128 3129 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3130 } 3131 3132 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) 3133 { 3134 u32 rc = 0; 3135 3136 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { 3137 struct hwrm_vnic_free_input req = {0}; 3138 3139 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1); 3140 req.vnic_id = 3141 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); 3142 3143 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3144 if (rc) 3145 return rc; 3146 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; 3147 } 3148 return rc; 3149 } 3150 3151 static void bnxt_hwrm_vnic_free(struct bnxt *bp) 3152 { 3153 u16 i; 3154 3155 for (i = 0; i < bp->nr_vnics; i++) 3156 bnxt_hwrm_vnic_free_one(bp, i); 3157 } 3158 3159 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, 3160 unsigned int start_rx_ring_idx, 3161 unsigned int nr_rings) 3162 { 3163 int rc = 0; 3164 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; 3165 struct hwrm_vnic_alloc_input req = {0}; 3166 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr; 3167 3168 /* map ring groups to this vnic */ 3169 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { 3170 grp_idx = bp->rx_ring[i].bnapi->index; 3171 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { 3172 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", 3173 j, nr_rings); 3174 break; 3175 } 3176 bp->vnic_info[vnic_id].fw_grp_ids[j] = 3177 bp->grp_info[grp_idx].fw_grp_id; 3178 } 3179 3180 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID; 3181 if (vnic_id == 0) 3182 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); 3183 3184 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1); 3185 3186 mutex_lock(&bp->hwrm_cmd_lock); 3187 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3188 if (!rc) 3189 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id); 3190 mutex_unlock(&bp->hwrm_cmd_lock); 3191 return rc; 3192 } 3193 3194 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) 3195 { 3196 u16 i; 3197 u32 rc = 0; 3198 3199 mutex_lock(&bp->hwrm_cmd_lock); 3200 for (i = 0; i < bp->rx_nr_rings; i++) { 3201 struct hwrm_ring_grp_alloc_input req = {0}; 3202 struct hwrm_ring_grp_alloc_output *resp = 3203 bp->hwrm_cmd_resp_addr; 3204 unsigned int grp_idx = bp->rx_ring[i].bnapi->index; 3205 3206 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1); 3207 3208 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); 3209 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); 3210 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); 3211 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); 3212 3213 rc = _hwrm_send_message(bp, &req, sizeof(req), 3214 HWRM_CMD_TIMEOUT); 3215 if (rc) 3216 break; 3217 3218 bp->grp_info[grp_idx].fw_grp_id = 3219 le32_to_cpu(resp->ring_group_id); 3220 } 3221 mutex_unlock(&bp->hwrm_cmd_lock); 3222 return rc; 3223 } 3224 3225 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp) 3226 { 3227 u16 i; 3228 u32 rc = 0; 3229 struct hwrm_ring_grp_free_input req = {0}; 3230 3231 if (!bp->grp_info) 3232 return 0; 3233 3234 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1); 3235 3236 mutex_lock(&bp->hwrm_cmd_lock); 3237 for (i = 0; i < bp->cp_nr_rings; i++) { 3238 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) 3239 continue; 3240 req.ring_group_id = 3241 cpu_to_le32(bp->grp_info[i].fw_grp_id); 3242 3243 rc = _hwrm_send_message(bp, &req, sizeof(req), 3244 HWRM_CMD_TIMEOUT); 3245 if (rc) 3246 break; 3247 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 3248 } 3249 mutex_unlock(&bp->hwrm_cmd_lock); 3250 return rc; 3251 } 3252 3253 static int hwrm_ring_alloc_send_msg(struct bnxt *bp, 3254 struct bnxt_ring_struct *ring, 3255 u32 ring_type, u32 map_index, 3256 u32 stats_ctx_id) 3257 { 3258 int rc = 0, err = 0; 3259 struct hwrm_ring_alloc_input req = {0}; 3260 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; 3261 u16 ring_id; 3262 3263 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1); 3264 3265 req.enables = 0; 3266 if (ring->nr_pages > 1) { 3267 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map); 3268 /* Page size is in log2 units */ 3269 req.page_size = BNXT_PAGE_SHIFT; 3270 req.page_tbl_depth = 1; 3271 } else { 3272 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]); 3273 } 3274 req.fbo = 0; 3275 /* Association of ring index with doorbell index and MSIX number */ 3276 req.logical_id = cpu_to_le16(map_index); 3277 3278 switch (ring_type) { 3279 case HWRM_RING_ALLOC_TX: 3280 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX; 3281 /* Association of transmit ring with completion ring */ 3282 req.cmpl_ring_id = 3283 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id); 3284 req.length = cpu_to_le32(bp->tx_ring_mask + 1); 3285 req.stat_ctx_id = cpu_to_le32(stats_ctx_id); 3286 req.queue_id = cpu_to_le16(ring->queue_id); 3287 break; 3288 case HWRM_RING_ALLOC_RX: 3289 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 3290 req.length = cpu_to_le32(bp->rx_ring_mask + 1); 3291 break; 3292 case HWRM_RING_ALLOC_AGG: 3293 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 3294 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1); 3295 break; 3296 case HWRM_RING_ALLOC_CMPL: 3297 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL; 3298 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 3299 if (bp->flags & BNXT_FLAG_USING_MSIX) 3300 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 3301 break; 3302 default: 3303 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", 3304 ring_type); 3305 return -1; 3306 } 3307 3308 mutex_lock(&bp->hwrm_cmd_lock); 3309 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3310 err = le16_to_cpu(resp->error_code); 3311 ring_id = le16_to_cpu(resp->ring_id); 3312 mutex_unlock(&bp->hwrm_cmd_lock); 3313 3314 if (rc || err) { 3315 switch (ring_type) { 3316 case RING_FREE_REQ_RING_TYPE_CMPL: 3317 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n", 3318 rc, err); 3319 return -1; 3320 3321 case RING_FREE_REQ_RING_TYPE_RX: 3322 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n", 3323 rc, err); 3324 return -1; 3325 3326 case RING_FREE_REQ_RING_TYPE_TX: 3327 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n", 3328 rc, err); 3329 return -1; 3330 3331 default: 3332 netdev_err(bp->dev, "Invalid ring\n"); 3333 return -1; 3334 } 3335 } 3336 ring->fw_ring_id = ring_id; 3337 return rc; 3338 } 3339 3340 static int bnxt_hwrm_ring_alloc(struct bnxt *bp) 3341 { 3342 int i, rc = 0; 3343 3344 for (i = 0; i < bp->cp_nr_rings; i++) { 3345 struct bnxt_napi *bnapi = bp->bnapi[i]; 3346 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3347 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 3348 3349 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i, 3350 INVALID_STATS_CTX_ID); 3351 if (rc) 3352 goto err_out; 3353 cpr->cp_doorbell = bp->bar1 + i * 0x80; 3354 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 3355 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; 3356 } 3357 3358 for (i = 0; i < bp->tx_nr_rings; i++) { 3359 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 3360 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 3361 u32 map_idx = txr->bnapi->index; 3362 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx; 3363 3364 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX, 3365 map_idx, fw_stats_ctx); 3366 if (rc) 3367 goto err_out; 3368 txr->tx_doorbell = bp->bar1 + map_idx * 0x80; 3369 } 3370 3371 for (i = 0; i < bp->rx_nr_rings; i++) { 3372 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3373 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 3374 u32 map_idx = rxr->bnapi->index; 3375 3376 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX, 3377 map_idx, INVALID_STATS_CTX_ID); 3378 if (rc) 3379 goto err_out; 3380 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80; 3381 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); 3382 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; 3383 } 3384 3385 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 3386 for (i = 0; i < bp->rx_nr_rings; i++) { 3387 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3388 struct bnxt_ring_struct *ring = 3389 &rxr->rx_agg_ring_struct; 3390 u32 grp_idx = rxr->bnapi->index; 3391 u32 map_idx = grp_idx + bp->rx_nr_rings; 3392 3393 rc = hwrm_ring_alloc_send_msg(bp, ring, 3394 HWRM_RING_ALLOC_AGG, 3395 map_idx, 3396 INVALID_STATS_CTX_ID); 3397 if (rc) 3398 goto err_out; 3399 3400 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80; 3401 writel(DB_KEY_RX | rxr->rx_agg_prod, 3402 rxr->rx_agg_doorbell); 3403 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; 3404 } 3405 } 3406 err_out: 3407 return rc; 3408 } 3409 3410 static int hwrm_ring_free_send_msg(struct bnxt *bp, 3411 struct bnxt_ring_struct *ring, 3412 u32 ring_type, int cmpl_ring_id) 3413 { 3414 int rc; 3415 struct hwrm_ring_free_input req = {0}; 3416 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr; 3417 u16 error_code; 3418 3419 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1); 3420 req.ring_type = ring_type; 3421 req.ring_id = cpu_to_le16(ring->fw_ring_id); 3422 3423 mutex_lock(&bp->hwrm_cmd_lock); 3424 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3425 error_code = le16_to_cpu(resp->error_code); 3426 mutex_unlock(&bp->hwrm_cmd_lock); 3427 3428 if (rc || error_code) { 3429 switch (ring_type) { 3430 case RING_FREE_REQ_RING_TYPE_CMPL: 3431 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n", 3432 rc); 3433 return rc; 3434 case RING_FREE_REQ_RING_TYPE_RX: 3435 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n", 3436 rc); 3437 return rc; 3438 case RING_FREE_REQ_RING_TYPE_TX: 3439 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n", 3440 rc); 3441 return rc; 3442 default: 3443 netdev_err(bp->dev, "Invalid ring\n"); 3444 return -1; 3445 } 3446 } 3447 return 0; 3448 } 3449 3450 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) 3451 { 3452 int i; 3453 3454 if (!bp->bnapi) 3455 return; 3456 3457 for (i = 0; i < bp->tx_nr_rings; i++) { 3458 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 3459 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 3460 u32 grp_idx = txr->bnapi->index; 3461 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; 3462 3463 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 3464 hwrm_ring_free_send_msg(bp, ring, 3465 RING_FREE_REQ_RING_TYPE_TX, 3466 close_path ? cmpl_ring_id : 3467 INVALID_HW_RING_ID); 3468 ring->fw_ring_id = INVALID_HW_RING_ID; 3469 } 3470 } 3471 3472 for (i = 0; i < bp->rx_nr_rings; i++) { 3473 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3474 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 3475 u32 grp_idx = rxr->bnapi->index; 3476 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; 3477 3478 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 3479 hwrm_ring_free_send_msg(bp, ring, 3480 RING_FREE_REQ_RING_TYPE_RX, 3481 close_path ? cmpl_ring_id : 3482 INVALID_HW_RING_ID); 3483 ring->fw_ring_id = INVALID_HW_RING_ID; 3484 bp->grp_info[grp_idx].rx_fw_ring_id = 3485 INVALID_HW_RING_ID; 3486 } 3487 } 3488 3489 for (i = 0; i < bp->rx_nr_rings; i++) { 3490 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3491 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; 3492 u32 grp_idx = rxr->bnapi->index; 3493 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; 3494 3495 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 3496 hwrm_ring_free_send_msg(bp, ring, 3497 RING_FREE_REQ_RING_TYPE_RX, 3498 close_path ? cmpl_ring_id : 3499 INVALID_HW_RING_ID); 3500 ring->fw_ring_id = INVALID_HW_RING_ID; 3501 bp->grp_info[grp_idx].agg_fw_ring_id = 3502 INVALID_HW_RING_ID; 3503 } 3504 } 3505 3506 for (i = 0; i < bp->cp_nr_rings; i++) { 3507 struct bnxt_napi *bnapi = bp->bnapi[i]; 3508 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3509 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 3510 3511 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 3512 hwrm_ring_free_send_msg(bp, ring, 3513 RING_FREE_REQ_RING_TYPE_CMPL, 3514 INVALID_HW_RING_ID); 3515 ring->fw_ring_id = INVALID_HW_RING_ID; 3516 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 3517 } 3518 } 3519 } 3520 3521 int bnxt_hwrm_set_coal(struct bnxt *bp) 3522 { 3523 int i, rc = 0; 3524 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0}; 3525 u16 max_buf, max_buf_irq; 3526 u16 buf_tmr, buf_tmr_irq; 3527 u32 flags; 3528 3529 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, 3530 -1, -1); 3531 3532 /* Each rx completion (2 records) should be DMAed immediately */ 3533 max_buf = min_t(u16, bp->coal_bufs / 4, 2); 3534 /* max_buf must not be zero */ 3535 max_buf = clamp_t(u16, max_buf, 1, 63); 3536 max_buf_irq = clamp_t(u16, bp->coal_bufs_irq, 1, 63); 3537 buf_tmr = max_t(u16, bp->coal_ticks / 4, 1); 3538 buf_tmr_irq = max_t(u16, bp->coal_ticks_irq, 1); 3539 3540 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 3541 3542 /* RING_IDLE generates more IRQs for lower latency. Enable it only 3543 * if coal_ticks is less than 25 us. 3544 */ 3545 if (BNXT_COAL_TIMER_TO_USEC(bp->coal_ticks) < 25) 3546 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; 3547 3548 req.flags = cpu_to_le16(flags); 3549 req.num_cmpl_dma_aggr = cpu_to_le16(max_buf); 3550 req.num_cmpl_dma_aggr_during_int = cpu_to_le16(max_buf_irq); 3551 req.cmpl_aggr_dma_tmr = cpu_to_le16(buf_tmr); 3552 req.cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmr_irq); 3553 req.int_lat_tmr_min = cpu_to_le16(buf_tmr); 3554 req.int_lat_tmr_max = cpu_to_le16(bp->coal_ticks); 3555 req.num_cmpl_aggr_int = cpu_to_le16(bp->coal_bufs); 3556 3557 mutex_lock(&bp->hwrm_cmd_lock); 3558 for (i = 0; i < bp->cp_nr_rings; i++) { 3559 req.ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id); 3560 3561 rc = _hwrm_send_message(bp, &req, sizeof(req), 3562 HWRM_CMD_TIMEOUT); 3563 if (rc) 3564 break; 3565 } 3566 mutex_unlock(&bp->hwrm_cmd_lock); 3567 return rc; 3568 } 3569 3570 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp) 3571 { 3572 int rc = 0, i; 3573 struct hwrm_stat_ctx_free_input req = {0}; 3574 3575 if (!bp->bnapi) 3576 return 0; 3577 3578 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1); 3579 3580 mutex_lock(&bp->hwrm_cmd_lock); 3581 for (i = 0; i < bp->cp_nr_rings; i++) { 3582 struct bnxt_napi *bnapi = bp->bnapi[i]; 3583 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3584 3585 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { 3586 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); 3587 3588 rc = _hwrm_send_message(bp, &req, sizeof(req), 3589 HWRM_CMD_TIMEOUT); 3590 if (rc) 3591 break; 3592 3593 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 3594 } 3595 } 3596 mutex_unlock(&bp->hwrm_cmd_lock); 3597 return rc; 3598 } 3599 3600 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) 3601 { 3602 int rc = 0, i; 3603 struct hwrm_stat_ctx_alloc_input req = {0}; 3604 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; 3605 3606 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1); 3607 3608 req.update_period_ms = cpu_to_le32(1000); 3609 3610 mutex_lock(&bp->hwrm_cmd_lock); 3611 for (i = 0; i < bp->cp_nr_rings; i++) { 3612 struct bnxt_napi *bnapi = bp->bnapi[i]; 3613 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3614 3615 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map); 3616 3617 rc = _hwrm_send_message(bp, &req, sizeof(req), 3618 HWRM_CMD_TIMEOUT); 3619 if (rc) 3620 break; 3621 3622 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); 3623 3624 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; 3625 } 3626 mutex_unlock(&bp->hwrm_cmd_lock); 3627 return 0; 3628 } 3629 3630 int bnxt_hwrm_func_qcaps(struct bnxt *bp) 3631 { 3632 int rc = 0; 3633 struct hwrm_func_qcaps_input req = {0}; 3634 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 3635 3636 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1); 3637 req.fid = cpu_to_le16(0xffff); 3638 3639 mutex_lock(&bp->hwrm_cmd_lock); 3640 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3641 if (rc) 3642 goto hwrm_func_qcaps_exit; 3643 3644 if (BNXT_PF(bp)) { 3645 struct bnxt_pf_info *pf = &bp->pf; 3646 3647 pf->fw_fid = le16_to_cpu(resp->fid); 3648 pf->port_id = le16_to_cpu(resp->port_id); 3649 memcpy(pf->mac_addr, resp->perm_mac_address, ETH_ALEN); 3650 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN); 3651 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 3652 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 3653 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 3654 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 3655 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); 3656 if (!pf->max_hw_ring_grps) 3657 pf->max_hw_ring_grps = pf->max_tx_rings; 3658 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 3659 pf->max_vnics = le16_to_cpu(resp->max_vnics); 3660 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 3661 pf->first_vf_id = le16_to_cpu(resp->first_vf_id); 3662 pf->max_vfs = le16_to_cpu(resp->max_vfs); 3663 pf->max_encap_records = le32_to_cpu(resp->max_encap_records); 3664 pf->max_decap_records = le32_to_cpu(resp->max_decap_records); 3665 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); 3666 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); 3667 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); 3668 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); 3669 } else { 3670 #ifdef CONFIG_BNXT_SRIOV 3671 struct bnxt_vf_info *vf = &bp->vf; 3672 3673 vf->fw_fid = le16_to_cpu(resp->fid); 3674 memcpy(vf->mac_addr, resp->perm_mac_address, ETH_ALEN); 3675 if (is_valid_ether_addr(vf->mac_addr)) 3676 /* overwrite netdev dev_adr with admin VF MAC */ 3677 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN); 3678 else 3679 random_ether_addr(bp->dev->dev_addr); 3680 3681 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 3682 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 3683 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 3684 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 3685 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); 3686 if (!vf->max_hw_ring_grps) 3687 vf->max_hw_ring_grps = vf->max_tx_rings; 3688 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 3689 vf->max_vnics = le16_to_cpu(resp->max_vnics); 3690 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 3691 #endif 3692 } 3693 3694 bp->tx_push_thresh = 0; 3695 if (resp->flags & 3696 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)) 3697 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; 3698 3699 hwrm_func_qcaps_exit: 3700 mutex_unlock(&bp->hwrm_cmd_lock); 3701 return rc; 3702 } 3703 3704 static int bnxt_hwrm_func_reset(struct bnxt *bp) 3705 { 3706 struct hwrm_func_reset_input req = {0}; 3707 3708 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1); 3709 req.enables = 0; 3710 3711 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT); 3712 } 3713 3714 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) 3715 { 3716 int rc = 0; 3717 struct hwrm_queue_qportcfg_input req = {0}; 3718 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; 3719 u8 i, *qptr; 3720 3721 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1); 3722 3723 mutex_lock(&bp->hwrm_cmd_lock); 3724 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3725 if (rc) 3726 goto qportcfg_exit; 3727 3728 if (!resp->max_configurable_queues) { 3729 rc = -EINVAL; 3730 goto qportcfg_exit; 3731 } 3732 bp->max_tc = resp->max_configurable_queues; 3733 if (bp->max_tc > BNXT_MAX_QUEUE) 3734 bp->max_tc = BNXT_MAX_QUEUE; 3735 3736 qptr = &resp->queue_id0; 3737 for (i = 0; i < bp->max_tc; i++) { 3738 bp->q_info[i].queue_id = *qptr++; 3739 bp->q_info[i].queue_profile = *qptr++; 3740 } 3741 3742 qportcfg_exit: 3743 mutex_unlock(&bp->hwrm_cmd_lock); 3744 return rc; 3745 } 3746 3747 static int bnxt_hwrm_ver_get(struct bnxt *bp) 3748 { 3749 int rc; 3750 struct hwrm_ver_get_input req = {0}; 3751 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr; 3752 3753 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1); 3754 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 3755 req.hwrm_intf_min = HWRM_VERSION_MINOR; 3756 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 3757 mutex_lock(&bp->hwrm_cmd_lock); 3758 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3759 if (rc) 3760 goto hwrm_ver_get_exit; 3761 3762 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); 3763 3764 if (resp->hwrm_intf_maj < 1) { 3765 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", 3766 resp->hwrm_intf_maj, resp->hwrm_intf_min, 3767 resp->hwrm_intf_upd); 3768 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); 3769 } 3770 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "bc %d.%d.%d rm %d.%d.%d", 3771 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld, 3772 resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd); 3773 3774 hwrm_ver_get_exit: 3775 mutex_unlock(&bp->hwrm_cmd_lock); 3776 return rc; 3777 } 3778 3779 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) 3780 { 3781 if (bp->vxlan_port_cnt) { 3782 bnxt_hwrm_tunnel_dst_port_free( 3783 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 3784 } 3785 bp->vxlan_port_cnt = 0; 3786 if (bp->nge_port_cnt) { 3787 bnxt_hwrm_tunnel_dst_port_free( 3788 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 3789 } 3790 bp->nge_port_cnt = 0; 3791 } 3792 3793 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) 3794 { 3795 int rc, i; 3796 u32 tpa_flags = 0; 3797 3798 if (set_tpa) 3799 tpa_flags = bp->flags & BNXT_FLAG_TPA; 3800 for (i = 0; i < bp->nr_vnics; i++) { 3801 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); 3802 if (rc) { 3803 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", 3804 rc, i); 3805 return rc; 3806 } 3807 } 3808 return 0; 3809 } 3810 3811 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) 3812 { 3813 int i; 3814 3815 for (i = 0; i < bp->nr_vnics; i++) 3816 bnxt_hwrm_vnic_set_rss(bp, i, false); 3817 } 3818 3819 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, 3820 bool irq_re_init) 3821 { 3822 if (bp->vnic_info) { 3823 bnxt_hwrm_clear_vnic_filter(bp); 3824 /* clear all RSS setting before free vnic ctx */ 3825 bnxt_hwrm_clear_vnic_rss(bp); 3826 bnxt_hwrm_vnic_ctx_free(bp); 3827 /* before free the vnic, undo the vnic tpa settings */ 3828 if (bp->flags & BNXT_FLAG_TPA) 3829 bnxt_set_tpa(bp, false); 3830 bnxt_hwrm_vnic_free(bp); 3831 } 3832 bnxt_hwrm_ring_free(bp, close_path); 3833 bnxt_hwrm_ring_grp_free(bp); 3834 if (irq_re_init) { 3835 bnxt_hwrm_stat_ctx_free(bp); 3836 bnxt_hwrm_free_tunnel_ports(bp); 3837 } 3838 } 3839 3840 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 3841 { 3842 int rc; 3843 3844 /* allocate context for vnic */ 3845 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id); 3846 if (rc) { 3847 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 3848 vnic_id, rc); 3849 goto vnic_setup_err; 3850 } 3851 bp->rsscos_nr_ctxs++; 3852 3853 /* configure default vnic, ring grp */ 3854 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 3855 if (rc) { 3856 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 3857 vnic_id, rc); 3858 goto vnic_setup_err; 3859 } 3860 3861 /* Enable RSS hashing on vnic */ 3862 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); 3863 if (rc) { 3864 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", 3865 vnic_id, rc); 3866 goto vnic_setup_err; 3867 } 3868 3869 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 3870 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 3871 if (rc) { 3872 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 3873 vnic_id, rc); 3874 } 3875 } 3876 3877 vnic_setup_err: 3878 return rc; 3879 } 3880 3881 static int bnxt_alloc_rfs_vnics(struct bnxt *bp) 3882 { 3883 #ifdef CONFIG_RFS_ACCEL 3884 int i, rc = 0; 3885 3886 for (i = 0; i < bp->rx_nr_rings; i++) { 3887 u16 vnic_id = i + 1; 3888 u16 ring_id = i; 3889 3890 if (vnic_id >= bp->nr_vnics) 3891 break; 3892 3893 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG; 3894 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); 3895 if (rc) { 3896 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 3897 vnic_id, rc); 3898 break; 3899 } 3900 rc = bnxt_setup_vnic(bp, vnic_id); 3901 if (rc) 3902 break; 3903 } 3904 return rc; 3905 #else 3906 return 0; 3907 #endif 3908 } 3909 3910 static int bnxt_cfg_rx_mode(struct bnxt *); 3911 3912 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) 3913 { 3914 int rc = 0; 3915 3916 if (irq_re_init) { 3917 rc = bnxt_hwrm_stat_ctx_alloc(bp); 3918 if (rc) { 3919 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", 3920 rc); 3921 goto err_out; 3922 } 3923 } 3924 3925 rc = bnxt_hwrm_ring_alloc(bp); 3926 if (rc) { 3927 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); 3928 goto err_out; 3929 } 3930 3931 rc = bnxt_hwrm_ring_grp_alloc(bp); 3932 if (rc) { 3933 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); 3934 goto err_out; 3935 } 3936 3937 /* default vnic 0 */ 3938 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, bp->rx_nr_rings); 3939 if (rc) { 3940 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); 3941 goto err_out; 3942 } 3943 3944 rc = bnxt_setup_vnic(bp, 0); 3945 if (rc) 3946 goto err_out; 3947 3948 if (bp->flags & BNXT_FLAG_RFS) { 3949 rc = bnxt_alloc_rfs_vnics(bp); 3950 if (rc) 3951 goto err_out; 3952 } 3953 3954 if (bp->flags & BNXT_FLAG_TPA) { 3955 rc = bnxt_set_tpa(bp, true); 3956 if (rc) 3957 goto err_out; 3958 } 3959 3960 if (BNXT_VF(bp)) 3961 bnxt_update_vf_mac(bp); 3962 3963 /* Filter for default vnic 0 */ 3964 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); 3965 if (rc) { 3966 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); 3967 goto err_out; 3968 } 3969 bp->vnic_info[0].uc_filter_count = 1; 3970 3971 bp->vnic_info[0].rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 3972 3973 if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp)) 3974 bp->vnic_info[0].rx_mask |= 3975 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 3976 3977 rc = bnxt_cfg_rx_mode(bp); 3978 if (rc) 3979 goto err_out; 3980 3981 rc = bnxt_hwrm_set_coal(bp); 3982 if (rc) 3983 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", 3984 rc); 3985 3986 return 0; 3987 3988 err_out: 3989 bnxt_hwrm_resource_free(bp, 0, true); 3990 3991 return rc; 3992 } 3993 3994 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) 3995 { 3996 bnxt_hwrm_resource_free(bp, 1, irq_re_init); 3997 return 0; 3998 } 3999 4000 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) 4001 { 4002 bnxt_init_rx_rings(bp); 4003 bnxt_init_tx_rings(bp); 4004 bnxt_init_ring_grps(bp, irq_re_init); 4005 bnxt_init_vnics(bp); 4006 4007 return bnxt_init_chip(bp, irq_re_init); 4008 } 4009 4010 static void bnxt_disable_int(struct bnxt *bp) 4011 { 4012 int i; 4013 4014 if (!bp->bnapi) 4015 return; 4016 4017 for (i = 0; i < bp->cp_nr_rings; i++) { 4018 struct bnxt_napi *bnapi = bp->bnapi[i]; 4019 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4020 4021 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 4022 } 4023 } 4024 4025 static void bnxt_enable_int(struct bnxt *bp) 4026 { 4027 int i; 4028 4029 atomic_set(&bp->intr_sem, 0); 4030 for (i = 0; i < bp->cp_nr_rings; i++) { 4031 struct bnxt_napi *bnapi = bp->bnapi[i]; 4032 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4033 4034 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons); 4035 } 4036 } 4037 4038 static int bnxt_set_real_num_queues(struct bnxt *bp) 4039 { 4040 int rc; 4041 struct net_device *dev = bp->dev; 4042 4043 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings); 4044 if (rc) 4045 return rc; 4046 4047 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); 4048 if (rc) 4049 return rc; 4050 4051 #ifdef CONFIG_RFS_ACCEL 4052 if (bp->flags & BNXT_FLAG_RFS) 4053 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); 4054 #endif 4055 4056 return rc; 4057 } 4058 4059 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 4060 bool shared) 4061 { 4062 int _rx = *rx, _tx = *tx; 4063 4064 if (shared) { 4065 *rx = min_t(int, _rx, max); 4066 *tx = min_t(int, _tx, max); 4067 } else { 4068 if (max < 2) 4069 return -ENOMEM; 4070 4071 while (_rx + _tx > max) { 4072 if (_rx > _tx && _rx > 1) 4073 _rx--; 4074 else if (_tx > 1) 4075 _tx--; 4076 } 4077 *rx = _rx; 4078 *tx = _tx; 4079 } 4080 return 0; 4081 } 4082 4083 static int bnxt_setup_msix(struct bnxt *bp) 4084 { 4085 struct msix_entry *msix_ent; 4086 struct net_device *dev = bp->dev; 4087 int i, total_vecs, rc = 0, min = 1; 4088 const int len = sizeof(bp->irq_tbl[0].name); 4089 4090 bp->flags &= ~BNXT_FLAG_USING_MSIX; 4091 total_vecs = bp->cp_nr_rings; 4092 4093 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); 4094 if (!msix_ent) 4095 return -ENOMEM; 4096 4097 for (i = 0; i < total_vecs; i++) { 4098 msix_ent[i].entry = i; 4099 msix_ent[i].vector = 0; 4100 } 4101 4102 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 4103 min = 2; 4104 4105 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); 4106 if (total_vecs < 0) { 4107 rc = -ENODEV; 4108 goto msix_setup_exit; 4109 } 4110 4111 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); 4112 if (bp->irq_tbl) { 4113 int tcs; 4114 4115 /* Trim rings based upon num of vectors allocated */ 4116 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, 4117 total_vecs, min == 1); 4118 if (rc) 4119 goto msix_setup_exit; 4120 4121 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 4122 tcs = netdev_get_num_tc(dev); 4123 if (tcs > 1) { 4124 bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs; 4125 if (bp->tx_nr_rings_per_tc == 0) { 4126 netdev_reset_tc(dev); 4127 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 4128 } else { 4129 int i, off, count; 4130 4131 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs; 4132 for (i = 0; i < tcs; i++) { 4133 count = bp->tx_nr_rings_per_tc; 4134 off = i * count; 4135 netdev_set_tc_queue(dev, i, count, off); 4136 } 4137 } 4138 } 4139 bp->cp_nr_rings = total_vecs; 4140 4141 for (i = 0; i < bp->cp_nr_rings; i++) { 4142 char *attr; 4143 4144 bp->irq_tbl[i].vector = msix_ent[i].vector; 4145 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 4146 attr = "TxRx"; 4147 else if (i < bp->rx_nr_rings) 4148 attr = "rx"; 4149 else 4150 attr = "tx"; 4151 4152 snprintf(bp->irq_tbl[i].name, len, 4153 "%s-%s-%d", dev->name, attr, i); 4154 bp->irq_tbl[i].handler = bnxt_msix; 4155 } 4156 rc = bnxt_set_real_num_queues(bp); 4157 if (rc) 4158 goto msix_setup_exit; 4159 } else { 4160 rc = -ENOMEM; 4161 goto msix_setup_exit; 4162 } 4163 bp->flags |= BNXT_FLAG_USING_MSIX; 4164 kfree(msix_ent); 4165 return 0; 4166 4167 msix_setup_exit: 4168 netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc); 4169 pci_disable_msix(bp->pdev); 4170 kfree(msix_ent); 4171 return rc; 4172 } 4173 4174 static int bnxt_setup_inta(struct bnxt *bp) 4175 { 4176 int rc; 4177 const int len = sizeof(bp->irq_tbl[0].name); 4178 4179 if (netdev_get_num_tc(bp->dev)) 4180 netdev_reset_tc(bp->dev); 4181 4182 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL); 4183 if (!bp->irq_tbl) { 4184 rc = -ENOMEM; 4185 return rc; 4186 } 4187 bp->rx_nr_rings = 1; 4188 bp->tx_nr_rings = 1; 4189 bp->cp_nr_rings = 1; 4190 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 4191 bp->flags |= BNXT_FLAG_SHARED_RINGS; 4192 bp->irq_tbl[0].vector = bp->pdev->irq; 4193 snprintf(bp->irq_tbl[0].name, len, 4194 "%s-%s-%d", bp->dev->name, "TxRx", 0); 4195 bp->irq_tbl[0].handler = bnxt_inta; 4196 rc = bnxt_set_real_num_queues(bp); 4197 return rc; 4198 } 4199 4200 static int bnxt_setup_int_mode(struct bnxt *bp) 4201 { 4202 int rc = 0; 4203 4204 if (bp->flags & BNXT_FLAG_MSIX_CAP) 4205 rc = bnxt_setup_msix(bp); 4206 4207 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) { 4208 /* fallback to INTA */ 4209 rc = bnxt_setup_inta(bp); 4210 } 4211 return rc; 4212 } 4213 4214 static void bnxt_free_irq(struct bnxt *bp) 4215 { 4216 struct bnxt_irq *irq; 4217 int i; 4218 4219 #ifdef CONFIG_RFS_ACCEL 4220 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); 4221 bp->dev->rx_cpu_rmap = NULL; 4222 #endif 4223 if (!bp->irq_tbl) 4224 return; 4225 4226 for (i = 0; i < bp->cp_nr_rings; i++) { 4227 irq = &bp->irq_tbl[i]; 4228 if (irq->requested) 4229 free_irq(irq->vector, bp->bnapi[i]); 4230 irq->requested = 0; 4231 } 4232 if (bp->flags & BNXT_FLAG_USING_MSIX) 4233 pci_disable_msix(bp->pdev); 4234 kfree(bp->irq_tbl); 4235 bp->irq_tbl = NULL; 4236 } 4237 4238 static int bnxt_request_irq(struct bnxt *bp) 4239 { 4240 int i, j, rc = 0; 4241 unsigned long flags = 0; 4242 #ifdef CONFIG_RFS_ACCEL 4243 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap; 4244 #endif 4245 4246 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) 4247 flags = IRQF_SHARED; 4248 4249 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { 4250 struct bnxt_irq *irq = &bp->irq_tbl[i]; 4251 #ifdef CONFIG_RFS_ACCEL 4252 if (rmap && bp->bnapi[i]->rx_ring) { 4253 rc = irq_cpu_rmap_add(rmap, irq->vector); 4254 if (rc) 4255 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", 4256 j); 4257 j++; 4258 } 4259 #endif 4260 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 4261 bp->bnapi[i]); 4262 if (rc) 4263 break; 4264 4265 irq->requested = 1; 4266 } 4267 return rc; 4268 } 4269 4270 static void bnxt_del_napi(struct bnxt *bp) 4271 { 4272 int i; 4273 4274 if (!bp->bnapi) 4275 return; 4276 4277 for (i = 0; i < bp->cp_nr_rings; i++) { 4278 struct bnxt_napi *bnapi = bp->bnapi[i]; 4279 4280 napi_hash_del(&bnapi->napi); 4281 netif_napi_del(&bnapi->napi); 4282 } 4283 } 4284 4285 static void bnxt_init_napi(struct bnxt *bp) 4286 { 4287 int i; 4288 struct bnxt_napi *bnapi; 4289 4290 if (bp->flags & BNXT_FLAG_USING_MSIX) { 4291 for (i = 0; i < bp->cp_nr_rings; i++) { 4292 bnapi = bp->bnapi[i]; 4293 netif_napi_add(bp->dev, &bnapi->napi, 4294 bnxt_poll, 64); 4295 } 4296 } else { 4297 bnapi = bp->bnapi[0]; 4298 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64); 4299 } 4300 } 4301 4302 static void bnxt_disable_napi(struct bnxt *bp) 4303 { 4304 int i; 4305 4306 if (!bp->bnapi) 4307 return; 4308 4309 for (i = 0; i < bp->cp_nr_rings; i++) { 4310 napi_disable(&bp->bnapi[i]->napi); 4311 bnxt_disable_poll(bp->bnapi[i]); 4312 } 4313 } 4314 4315 static void bnxt_enable_napi(struct bnxt *bp) 4316 { 4317 int i; 4318 4319 for (i = 0; i < bp->cp_nr_rings; i++) { 4320 bnxt_enable_poll(bp->bnapi[i]); 4321 napi_enable(&bp->bnapi[i]->napi); 4322 } 4323 } 4324 4325 static void bnxt_tx_disable(struct bnxt *bp) 4326 { 4327 int i; 4328 struct bnxt_tx_ring_info *txr; 4329 struct netdev_queue *txq; 4330 4331 if (bp->tx_ring) { 4332 for (i = 0; i < bp->tx_nr_rings; i++) { 4333 txr = &bp->tx_ring[i]; 4334 txq = netdev_get_tx_queue(bp->dev, i); 4335 __netif_tx_lock(txq, smp_processor_id()); 4336 txr->dev_state = BNXT_DEV_STATE_CLOSING; 4337 __netif_tx_unlock(txq); 4338 } 4339 } 4340 /* Stop all TX queues */ 4341 netif_tx_disable(bp->dev); 4342 netif_carrier_off(bp->dev); 4343 } 4344 4345 static void bnxt_tx_enable(struct bnxt *bp) 4346 { 4347 int i; 4348 struct bnxt_tx_ring_info *txr; 4349 struct netdev_queue *txq; 4350 4351 for (i = 0; i < bp->tx_nr_rings; i++) { 4352 txr = &bp->tx_ring[i]; 4353 txq = netdev_get_tx_queue(bp->dev, i); 4354 txr->dev_state = 0; 4355 } 4356 netif_tx_wake_all_queues(bp->dev); 4357 if (bp->link_info.link_up) 4358 netif_carrier_on(bp->dev); 4359 } 4360 4361 static void bnxt_report_link(struct bnxt *bp) 4362 { 4363 if (bp->link_info.link_up) { 4364 const char *duplex; 4365 const char *flow_ctrl; 4366 u16 speed; 4367 4368 netif_carrier_on(bp->dev); 4369 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) 4370 duplex = "full"; 4371 else 4372 duplex = "half"; 4373 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) 4374 flow_ctrl = "ON - receive & transmit"; 4375 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) 4376 flow_ctrl = "ON - transmit"; 4377 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) 4378 flow_ctrl = "ON - receive"; 4379 else 4380 flow_ctrl = "none"; 4381 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); 4382 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n", 4383 speed, duplex, flow_ctrl); 4384 } else { 4385 netif_carrier_off(bp->dev); 4386 netdev_err(bp->dev, "NIC Link is Down\n"); 4387 } 4388 } 4389 4390 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) 4391 { 4392 int rc = 0; 4393 struct bnxt_link_info *link_info = &bp->link_info; 4394 struct hwrm_port_phy_qcfg_input req = {0}; 4395 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 4396 u8 link_up = link_info->link_up; 4397 4398 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1); 4399 4400 mutex_lock(&bp->hwrm_cmd_lock); 4401 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4402 if (rc) { 4403 mutex_unlock(&bp->hwrm_cmd_lock); 4404 return rc; 4405 } 4406 4407 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); 4408 link_info->phy_link_status = resp->link; 4409 link_info->duplex = resp->duplex; 4410 link_info->pause = resp->pause; 4411 link_info->auto_mode = resp->auto_mode; 4412 link_info->auto_pause_setting = resp->auto_pause; 4413 link_info->force_pause_setting = resp->force_pause; 4414 link_info->duplex_setting = resp->duplex; 4415 if (link_info->phy_link_status == BNXT_LINK_LINK) 4416 link_info->link_speed = le16_to_cpu(resp->link_speed); 4417 else 4418 link_info->link_speed = 0; 4419 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); 4420 link_info->auto_link_speed = le16_to_cpu(resp->auto_link_speed); 4421 link_info->support_speeds = le16_to_cpu(resp->support_speeds); 4422 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); 4423 link_info->preemphasis = le32_to_cpu(resp->preemphasis); 4424 link_info->phy_ver[0] = resp->phy_maj; 4425 link_info->phy_ver[1] = resp->phy_min; 4426 link_info->phy_ver[2] = resp->phy_bld; 4427 link_info->media_type = resp->media_type; 4428 link_info->transceiver = resp->transceiver_type; 4429 link_info->phy_addr = resp->phy_addr; 4430 4431 /* TODO: need to add more logic to report VF link */ 4432 if (chng_link_state) { 4433 if (link_info->phy_link_status == BNXT_LINK_LINK) 4434 link_info->link_up = 1; 4435 else 4436 link_info->link_up = 0; 4437 if (link_up != link_info->link_up) 4438 bnxt_report_link(bp); 4439 } else { 4440 /* alwasy link down if not require to update link state */ 4441 link_info->link_up = 0; 4442 } 4443 mutex_unlock(&bp->hwrm_cmd_lock); 4444 return 0; 4445 } 4446 4447 static void 4448 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) 4449 { 4450 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { 4451 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 4452 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; 4453 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 4454 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; 4455 req->enables |= 4456 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 4457 } else { 4458 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 4459 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; 4460 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 4461 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; 4462 req->enables |= 4463 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); 4464 } 4465 } 4466 4467 static void bnxt_hwrm_set_link_common(struct bnxt *bp, 4468 struct hwrm_port_phy_cfg_input *req) 4469 { 4470 u8 autoneg = bp->link_info.autoneg; 4471 u16 fw_link_speed = bp->link_info.req_link_speed; 4472 u32 advertising = bp->link_info.advertising; 4473 4474 if (autoneg & BNXT_AUTONEG_SPEED) { 4475 req->auto_mode |= 4476 PORT_PHY_CFG_REQ_AUTO_MODE_MASK; 4477 4478 req->enables |= cpu_to_le32( 4479 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); 4480 req->auto_link_speed_mask = cpu_to_le16(advertising); 4481 4482 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); 4483 req->flags |= 4484 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); 4485 } else { 4486 req->force_link_speed = cpu_to_le16(fw_link_speed); 4487 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); 4488 } 4489 4490 /* currently don't support half duplex */ 4491 req->auto_duplex = PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL; 4492 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX); 4493 /* tell chimp that the setting takes effect immediately */ 4494 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 4495 } 4496 4497 int bnxt_hwrm_set_pause(struct bnxt *bp) 4498 { 4499 struct hwrm_port_phy_cfg_input req = {0}; 4500 int rc; 4501 4502 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 4503 bnxt_hwrm_set_pause_common(bp, &req); 4504 4505 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || 4506 bp->link_info.force_link_chng) 4507 bnxt_hwrm_set_link_common(bp, &req); 4508 4509 mutex_lock(&bp->hwrm_cmd_lock); 4510 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4511 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { 4512 /* since changing of pause setting doesn't trigger any link 4513 * change event, the driver needs to update the current pause 4514 * result upon successfully return of the phy_cfg command 4515 */ 4516 bp->link_info.pause = 4517 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; 4518 bp->link_info.auto_pause_setting = 0; 4519 if (!bp->link_info.force_link_chng) 4520 bnxt_report_link(bp); 4521 } 4522 bp->link_info.force_link_chng = false; 4523 mutex_unlock(&bp->hwrm_cmd_lock); 4524 return rc; 4525 } 4526 4527 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause) 4528 { 4529 struct hwrm_port_phy_cfg_input req = {0}; 4530 4531 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 4532 if (set_pause) 4533 bnxt_hwrm_set_pause_common(bp, &req); 4534 4535 bnxt_hwrm_set_link_common(bp, &req); 4536 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4537 } 4538 4539 static int bnxt_update_phy_setting(struct bnxt *bp) 4540 { 4541 int rc; 4542 bool update_link = false; 4543 bool update_pause = false; 4544 struct bnxt_link_info *link_info = &bp->link_info; 4545 4546 rc = bnxt_update_link(bp, true); 4547 if (rc) { 4548 netdev_err(bp->dev, "failed to update link (rc: %x)\n", 4549 rc); 4550 return rc; 4551 } 4552 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 4553 link_info->auto_pause_setting != link_info->req_flow_ctrl) 4554 update_pause = true; 4555 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 4556 link_info->force_pause_setting != link_info->req_flow_ctrl) 4557 update_pause = true; 4558 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 4559 if (BNXT_AUTO_MODE(link_info->auto_mode)) 4560 update_link = true; 4561 if (link_info->req_link_speed != link_info->force_link_speed) 4562 update_link = true; 4563 if (link_info->req_duplex != link_info->duplex_setting) 4564 update_link = true; 4565 } else { 4566 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) 4567 update_link = true; 4568 if (link_info->advertising != link_info->auto_link_speeds) 4569 update_link = true; 4570 } 4571 4572 if (update_link) 4573 rc = bnxt_hwrm_set_link_setting(bp, update_pause); 4574 else if (update_pause) 4575 rc = bnxt_hwrm_set_pause(bp); 4576 if (rc) { 4577 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", 4578 rc); 4579 return rc; 4580 } 4581 4582 return rc; 4583 } 4584 4585 /* Common routine to pre-map certain register block to different GRC window. 4586 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows 4587 * in PF and 3 windows in VF that can be customized to map in different 4588 * register blocks. 4589 */ 4590 static void bnxt_preset_reg_win(struct bnxt *bp) 4591 { 4592 if (BNXT_PF(bp)) { 4593 /* CAG registers map to GRC window #4 */ 4594 writel(BNXT_CAG_REG_BASE, 4595 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); 4596 } 4597 } 4598 4599 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 4600 { 4601 int rc = 0; 4602 4603 bnxt_preset_reg_win(bp); 4604 netif_carrier_off(bp->dev); 4605 if (irq_re_init) { 4606 rc = bnxt_setup_int_mode(bp); 4607 if (rc) { 4608 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", 4609 rc); 4610 return rc; 4611 } 4612 } 4613 if ((bp->flags & BNXT_FLAG_RFS) && 4614 !(bp->flags & BNXT_FLAG_USING_MSIX)) { 4615 /* disable RFS if falling back to INTA */ 4616 bp->dev->hw_features &= ~NETIF_F_NTUPLE; 4617 bp->flags &= ~BNXT_FLAG_RFS; 4618 } 4619 4620 rc = bnxt_alloc_mem(bp, irq_re_init); 4621 if (rc) { 4622 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 4623 goto open_err_free_mem; 4624 } 4625 4626 if (irq_re_init) { 4627 bnxt_init_napi(bp); 4628 rc = bnxt_request_irq(bp); 4629 if (rc) { 4630 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); 4631 goto open_err; 4632 } 4633 } 4634 4635 bnxt_enable_napi(bp); 4636 4637 rc = bnxt_init_nic(bp, irq_re_init); 4638 if (rc) { 4639 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 4640 goto open_err; 4641 } 4642 4643 if (link_re_init) { 4644 rc = bnxt_update_phy_setting(bp); 4645 if (rc) 4646 netdev_warn(bp->dev, "failed to update phy settings\n"); 4647 } 4648 4649 if (irq_re_init) { 4650 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE) 4651 vxlan_get_rx_port(bp->dev); 4652 #endif 4653 if (!bnxt_hwrm_tunnel_dst_port_alloc( 4654 bp, htons(0x17c1), 4655 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE)) 4656 bp->nge_port_cnt = 1; 4657 } 4658 4659 set_bit(BNXT_STATE_OPEN, &bp->state); 4660 bnxt_enable_int(bp); 4661 /* Enable TX queues */ 4662 bnxt_tx_enable(bp); 4663 mod_timer(&bp->timer, jiffies + bp->current_interval); 4664 bnxt_update_link(bp, true); 4665 4666 return 0; 4667 4668 open_err: 4669 bnxt_disable_napi(bp); 4670 bnxt_del_napi(bp); 4671 4672 open_err_free_mem: 4673 bnxt_free_skbs(bp); 4674 bnxt_free_irq(bp); 4675 bnxt_free_mem(bp, true); 4676 return rc; 4677 } 4678 4679 /* rtnl_lock held */ 4680 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 4681 { 4682 int rc = 0; 4683 4684 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); 4685 if (rc) { 4686 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); 4687 dev_close(bp->dev); 4688 } 4689 return rc; 4690 } 4691 4692 static int bnxt_open(struct net_device *dev) 4693 { 4694 struct bnxt *bp = netdev_priv(dev); 4695 int rc = 0; 4696 4697 rc = bnxt_hwrm_func_reset(bp); 4698 if (rc) { 4699 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n", 4700 rc); 4701 rc = -1; 4702 return rc; 4703 } 4704 return __bnxt_open_nic(bp, true, true); 4705 } 4706 4707 static void bnxt_disable_int_sync(struct bnxt *bp) 4708 { 4709 int i; 4710 4711 atomic_inc(&bp->intr_sem); 4712 if (!netif_running(bp->dev)) 4713 return; 4714 4715 bnxt_disable_int(bp); 4716 for (i = 0; i < bp->cp_nr_rings; i++) 4717 synchronize_irq(bp->irq_tbl[i].vector); 4718 } 4719 4720 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 4721 { 4722 int rc = 0; 4723 4724 #ifdef CONFIG_BNXT_SRIOV 4725 if (bp->sriov_cfg) { 4726 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, 4727 !bp->sriov_cfg, 4728 BNXT_SRIOV_CFG_WAIT_TMO); 4729 if (rc) 4730 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); 4731 } 4732 #endif 4733 /* Change device state to avoid TX queue wake up's */ 4734 bnxt_tx_disable(bp); 4735 4736 clear_bit(BNXT_STATE_OPEN, &bp->state); 4737 smp_mb__after_atomic(); 4738 while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state)) 4739 msleep(20); 4740 4741 /* Flush rings before disabling interrupts */ 4742 bnxt_shutdown_nic(bp, irq_re_init); 4743 4744 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ 4745 4746 bnxt_disable_napi(bp); 4747 bnxt_disable_int_sync(bp); 4748 del_timer_sync(&bp->timer); 4749 bnxt_free_skbs(bp); 4750 4751 if (irq_re_init) { 4752 bnxt_free_irq(bp); 4753 bnxt_del_napi(bp); 4754 } 4755 bnxt_free_mem(bp, irq_re_init); 4756 return rc; 4757 } 4758 4759 static int bnxt_close(struct net_device *dev) 4760 { 4761 struct bnxt *bp = netdev_priv(dev); 4762 4763 bnxt_close_nic(bp, true, true); 4764 return 0; 4765 } 4766 4767 /* rtnl_lock held */ 4768 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4769 { 4770 switch (cmd) { 4771 case SIOCGMIIPHY: 4772 /* fallthru */ 4773 case SIOCGMIIREG: { 4774 if (!netif_running(dev)) 4775 return -EAGAIN; 4776 4777 return 0; 4778 } 4779 4780 case SIOCSMIIREG: 4781 if (!netif_running(dev)) 4782 return -EAGAIN; 4783 4784 return 0; 4785 4786 default: 4787 /* do nothing */ 4788 break; 4789 } 4790 return -EOPNOTSUPP; 4791 } 4792 4793 static struct rtnl_link_stats64 * 4794 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4795 { 4796 u32 i; 4797 struct bnxt *bp = netdev_priv(dev); 4798 4799 memset(stats, 0, sizeof(struct rtnl_link_stats64)); 4800 4801 if (!bp->bnapi) 4802 return stats; 4803 4804 /* TODO check if we need to synchronize with bnxt_close path */ 4805 for (i = 0; i < bp->cp_nr_rings; i++) { 4806 struct bnxt_napi *bnapi = bp->bnapi[i]; 4807 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4808 struct ctx_hw_stats *hw_stats = cpr->hw_stats; 4809 4810 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts); 4811 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts); 4812 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts); 4813 4814 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts); 4815 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts); 4816 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts); 4817 4818 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes); 4819 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes); 4820 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes); 4821 4822 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes); 4823 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes); 4824 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes); 4825 4826 stats->rx_missed_errors += 4827 le64_to_cpu(hw_stats->rx_discard_pkts); 4828 4829 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts); 4830 4831 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts); 4832 } 4833 4834 return stats; 4835 } 4836 4837 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) 4838 { 4839 struct net_device *dev = bp->dev; 4840 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 4841 struct netdev_hw_addr *ha; 4842 u8 *haddr; 4843 int mc_count = 0; 4844 bool update = false; 4845 int off = 0; 4846 4847 netdev_for_each_mc_addr(ha, dev) { 4848 if (mc_count >= BNXT_MAX_MC_ADDRS) { 4849 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 4850 vnic->mc_list_count = 0; 4851 return false; 4852 } 4853 haddr = ha->addr; 4854 if (!ether_addr_equal(haddr, vnic->mc_list + off)) { 4855 memcpy(vnic->mc_list + off, haddr, ETH_ALEN); 4856 update = true; 4857 } 4858 off += ETH_ALEN; 4859 mc_count++; 4860 } 4861 if (mc_count) 4862 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; 4863 4864 if (mc_count != vnic->mc_list_count) { 4865 vnic->mc_list_count = mc_count; 4866 update = true; 4867 } 4868 return update; 4869 } 4870 4871 static bool bnxt_uc_list_updated(struct bnxt *bp) 4872 { 4873 struct net_device *dev = bp->dev; 4874 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 4875 struct netdev_hw_addr *ha; 4876 int off = 0; 4877 4878 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) 4879 return true; 4880 4881 netdev_for_each_uc_addr(ha, dev) { 4882 if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) 4883 return true; 4884 4885 off += ETH_ALEN; 4886 } 4887 return false; 4888 } 4889 4890 static void bnxt_set_rx_mode(struct net_device *dev) 4891 { 4892 struct bnxt *bp = netdev_priv(dev); 4893 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 4894 u32 mask = vnic->rx_mask; 4895 bool mc_update = false; 4896 bool uc_update; 4897 4898 if (!netif_running(dev)) 4899 return; 4900 4901 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | 4902 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | 4903 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST); 4904 4905 /* Only allow PF to be in promiscuous mode */ 4906 if ((dev->flags & IFF_PROMISC) && BNXT_PF(bp)) 4907 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 4908 4909 uc_update = bnxt_uc_list_updated(bp); 4910 4911 if (dev->flags & IFF_ALLMULTI) { 4912 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 4913 vnic->mc_list_count = 0; 4914 } else { 4915 mc_update = bnxt_mc_list_updated(bp, &mask); 4916 } 4917 4918 if (mask != vnic->rx_mask || uc_update || mc_update) { 4919 vnic->rx_mask = mask; 4920 4921 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); 4922 schedule_work(&bp->sp_task); 4923 } 4924 } 4925 4926 static int bnxt_cfg_rx_mode(struct bnxt *bp) 4927 { 4928 struct net_device *dev = bp->dev; 4929 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 4930 struct netdev_hw_addr *ha; 4931 int i, off = 0, rc; 4932 bool uc_update; 4933 4934 netif_addr_lock_bh(dev); 4935 uc_update = bnxt_uc_list_updated(bp); 4936 netif_addr_unlock_bh(dev); 4937 4938 if (!uc_update) 4939 goto skip_uc; 4940 4941 mutex_lock(&bp->hwrm_cmd_lock); 4942 for (i = 1; i < vnic->uc_filter_count; i++) { 4943 struct hwrm_cfa_l2_filter_free_input req = {0}; 4944 4945 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1, 4946 -1); 4947 4948 req.l2_filter_id = vnic->fw_l2_filter_id[i]; 4949 4950 rc = _hwrm_send_message(bp, &req, sizeof(req), 4951 HWRM_CMD_TIMEOUT); 4952 } 4953 mutex_unlock(&bp->hwrm_cmd_lock); 4954 4955 vnic->uc_filter_count = 1; 4956 4957 netif_addr_lock_bh(dev); 4958 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { 4959 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 4960 } else { 4961 netdev_for_each_uc_addr(ha, dev) { 4962 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); 4963 off += ETH_ALEN; 4964 vnic->uc_filter_count++; 4965 } 4966 } 4967 netif_addr_unlock_bh(dev); 4968 4969 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { 4970 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); 4971 if (rc) { 4972 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", 4973 rc); 4974 vnic->uc_filter_count = i; 4975 return rc; 4976 } 4977 } 4978 4979 skip_uc: 4980 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 4981 if (rc) 4982 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n", 4983 rc); 4984 4985 return rc; 4986 } 4987 4988 static bool bnxt_rfs_capable(struct bnxt *bp) 4989 { 4990 #ifdef CONFIG_RFS_ACCEL 4991 struct bnxt_pf_info *pf = &bp->pf; 4992 int vnics; 4993 4994 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP)) 4995 return false; 4996 4997 vnics = 1 + bp->rx_nr_rings; 4998 if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics) 4999 return false; 5000 5001 return true; 5002 #else 5003 return false; 5004 #endif 5005 } 5006 5007 static netdev_features_t bnxt_fix_features(struct net_device *dev, 5008 netdev_features_t features) 5009 { 5010 struct bnxt *bp = netdev_priv(dev); 5011 5012 if (!bnxt_rfs_capable(bp)) 5013 features &= ~NETIF_F_NTUPLE; 5014 return features; 5015 } 5016 5017 static int bnxt_set_features(struct net_device *dev, netdev_features_t features) 5018 { 5019 struct bnxt *bp = netdev_priv(dev); 5020 u32 flags = bp->flags; 5021 u32 changes; 5022 int rc = 0; 5023 bool re_init = false; 5024 bool update_tpa = false; 5025 5026 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; 5027 if ((features & NETIF_F_GRO) && (bp->pdev->revision > 0)) 5028 flags |= BNXT_FLAG_GRO; 5029 if (features & NETIF_F_LRO) 5030 flags |= BNXT_FLAG_LRO; 5031 5032 if (features & NETIF_F_HW_VLAN_CTAG_RX) 5033 flags |= BNXT_FLAG_STRIP_VLAN; 5034 5035 if (features & NETIF_F_NTUPLE) 5036 flags |= BNXT_FLAG_RFS; 5037 5038 changes = flags ^ bp->flags; 5039 if (changes & BNXT_FLAG_TPA) { 5040 update_tpa = true; 5041 if ((bp->flags & BNXT_FLAG_TPA) == 0 || 5042 (flags & BNXT_FLAG_TPA) == 0) 5043 re_init = true; 5044 } 5045 5046 if (changes & ~BNXT_FLAG_TPA) 5047 re_init = true; 5048 5049 if (flags != bp->flags) { 5050 u32 old_flags = bp->flags; 5051 5052 bp->flags = flags; 5053 5054 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 5055 if (update_tpa) 5056 bnxt_set_ring_params(bp); 5057 return rc; 5058 } 5059 5060 if (re_init) { 5061 bnxt_close_nic(bp, false, false); 5062 if (update_tpa) 5063 bnxt_set_ring_params(bp); 5064 5065 return bnxt_open_nic(bp, false, false); 5066 } 5067 if (update_tpa) { 5068 rc = bnxt_set_tpa(bp, 5069 (flags & BNXT_FLAG_TPA) ? 5070 true : false); 5071 if (rc) 5072 bp->flags = old_flags; 5073 } 5074 } 5075 return rc; 5076 } 5077 5078 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) 5079 { 5080 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 5081 int i = bnapi->index; 5082 5083 if (!txr) 5084 return; 5085 5086 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", 5087 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, 5088 txr->tx_cons); 5089 } 5090 5091 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) 5092 { 5093 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 5094 int i = bnapi->index; 5095 5096 if (!rxr) 5097 return; 5098 5099 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", 5100 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, 5101 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, 5102 rxr->rx_sw_agg_prod); 5103 } 5104 5105 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) 5106 { 5107 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5108 int i = bnapi->index; 5109 5110 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", 5111 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); 5112 } 5113 5114 static void bnxt_dbg_dump_states(struct bnxt *bp) 5115 { 5116 int i; 5117 struct bnxt_napi *bnapi; 5118 5119 for (i = 0; i < bp->cp_nr_rings; i++) { 5120 bnapi = bp->bnapi[i]; 5121 if (netif_msg_drv(bp)) { 5122 bnxt_dump_tx_sw_state(bnapi); 5123 bnxt_dump_rx_sw_state(bnapi); 5124 bnxt_dump_cp_sw_state(bnapi); 5125 } 5126 } 5127 } 5128 5129 static void bnxt_reset_task(struct bnxt *bp) 5130 { 5131 bnxt_dbg_dump_states(bp); 5132 if (netif_running(bp->dev)) { 5133 bnxt_close_nic(bp, false, false); 5134 bnxt_open_nic(bp, false, false); 5135 } 5136 } 5137 5138 static void bnxt_tx_timeout(struct net_device *dev) 5139 { 5140 struct bnxt *bp = netdev_priv(dev); 5141 5142 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); 5143 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 5144 schedule_work(&bp->sp_task); 5145 } 5146 5147 #ifdef CONFIG_NET_POLL_CONTROLLER 5148 static void bnxt_poll_controller(struct net_device *dev) 5149 { 5150 struct bnxt *bp = netdev_priv(dev); 5151 int i; 5152 5153 for (i = 0; i < bp->cp_nr_rings; i++) { 5154 struct bnxt_irq *irq = &bp->irq_tbl[i]; 5155 5156 disable_irq(irq->vector); 5157 irq->handler(irq->vector, bp->bnapi[i]); 5158 enable_irq(irq->vector); 5159 } 5160 } 5161 #endif 5162 5163 static void bnxt_timer(unsigned long data) 5164 { 5165 struct bnxt *bp = (struct bnxt *)data; 5166 struct net_device *dev = bp->dev; 5167 5168 if (!netif_running(dev)) 5169 return; 5170 5171 if (atomic_read(&bp->intr_sem) != 0) 5172 goto bnxt_restart_timer; 5173 5174 bnxt_restart_timer: 5175 mod_timer(&bp->timer, jiffies + bp->current_interval); 5176 } 5177 5178 static void bnxt_cfg_ntp_filters(struct bnxt *); 5179 5180 static void bnxt_sp_task(struct work_struct *work) 5181 { 5182 struct bnxt *bp = container_of(work, struct bnxt, sp_task); 5183 int rc; 5184 5185 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 5186 smp_mb__after_atomic(); 5187 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 5188 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 5189 return; 5190 } 5191 5192 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) 5193 bnxt_cfg_rx_mode(bp); 5194 5195 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) 5196 bnxt_cfg_ntp_filters(bp); 5197 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { 5198 rc = bnxt_update_link(bp, true); 5199 if (rc) 5200 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", 5201 rc); 5202 } 5203 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) 5204 bnxt_hwrm_exec_fwd_req(bp); 5205 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) { 5206 bnxt_hwrm_tunnel_dst_port_alloc( 5207 bp, bp->vxlan_port, 5208 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 5209 } 5210 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) { 5211 bnxt_hwrm_tunnel_dst_port_free( 5212 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 5213 } 5214 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) { 5215 /* bnxt_reset_task() calls bnxt_close_nic() which waits 5216 * for BNXT_STATE_IN_SP_TASK to clear. 5217 */ 5218 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 5219 rtnl_lock(); 5220 bnxt_reset_task(bp); 5221 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 5222 rtnl_unlock(); 5223 } 5224 5225 smp_mb__before_atomic(); 5226 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 5227 } 5228 5229 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) 5230 { 5231 int rc; 5232 struct bnxt *bp = netdev_priv(dev); 5233 5234 SET_NETDEV_DEV(dev, &pdev->dev); 5235 5236 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 5237 rc = pci_enable_device(pdev); 5238 if (rc) { 5239 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 5240 goto init_err; 5241 } 5242 5243 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 5244 dev_err(&pdev->dev, 5245 "Cannot find PCI device base address, aborting\n"); 5246 rc = -ENODEV; 5247 goto init_err_disable; 5248 } 5249 5250 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 5251 if (rc) { 5252 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 5253 goto init_err_disable; 5254 } 5255 5256 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && 5257 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { 5258 dev_err(&pdev->dev, "System does not support DMA, aborting\n"); 5259 goto init_err_disable; 5260 } 5261 5262 pci_set_master(pdev); 5263 5264 bp->dev = dev; 5265 bp->pdev = pdev; 5266 5267 bp->bar0 = pci_ioremap_bar(pdev, 0); 5268 if (!bp->bar0) { 5269 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 5270 rc = -ENOMEM; 5271 goto init_err_release; 5272 } 5273 5274 bp->bar1 = pci_ioremap_bar(pdev, 2); 5275 if (!bp->bar1) { 5276 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n"); 5277 rc = -ENOMEM; 5278 goto init_err_release; 5279 } 5280 5281 bp->bar2 = pci_ioremap_bar(pdev, 4); 5282 if (!bp->bar2) { 5283 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); 5284 rc = -ENOMEM; 5285 goto init_err_release; 5286 } 5287 5288 INIT_WORK(&bp->sp_task, bnxt_sp_task); 5289 5290 spin_lock_init(&bp->ntp_fltr_lock); 5291 5292 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; 5293 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; 5294 5295 bp->coal_ticks = BNXT_USEC_TO_COAL_TIMER(4); 5296 bp->coal_bufs = 20; 5297 bp->coal_ticks_irq = BNXT_USEC_TO_COAL_TIMER(1); 5298 bp->coal_bufs_irq = 2; 5299 5300 init_timer(&bp->timer); 5301 bp->timer.data = (unsigned long)bp; 5302 bp->timer.function = bnxt_timer; 5303 bp->current_interval = BNXT_TIMER_INTERVAL; 5304 5305 clear_bit(BNXT_STATE_OPEN, &bp->state); 5306 5307 return 0; 5308 5309 init_err_release: 5310 if (bp->bar2) { 5311 pci_iounmap(pdev, bp->bar2); 5312 bp->bar2 = NULL; 5313 } 5314 5315 if (bp->bar1) { 5316 pci_iounmap(pdev, bp->bar1); 5317 bp->bar1 = NULL; 5318 } 5319 5320 if (bp->bar0) { 5321 pci_iounmap(pdev, bp->bar0); 5322 bp->bar0 = NULL; 5323 } 5324 5325 pci_release_regions(pdev); 5326 5327 init_err_disable: 5328 pci_disable_device(pdev); 5329 5330 init_err: 5331 return rc; 5332 } 5333 5334 /* rtnl_lock held */ 5335 static int bnxt_change_mac_addr(struct net_device *dev, void *p) 5336 { 5337 struct sockaddr *addr = p; 5338 struct bnxt *bp = netdev_priv(dev); 5339 int rc = 0; 5340 5341 if (!is_valid_ether_addr(addr->sa_data)) 5342 return -EADDRNOTAVAIL; 5343 5344 #ifdef CONFIG_BNXT_SRIOV 5345 if (BNXT_VF(bp) && is_valid_ether_addr(bp->vf.mac_addr)) 5346 return -EADDRNOTAVAIL; 5347 #endif 5348 5349 if (ether_addr_equal(addr->sa_data, dev->dev_addr)) 5350 return 0; 5351 5352 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 5353 if (netif_running(dev)) { 5354 bnxt_close_nic(bp, false, false); 5355 rc = bnxt_open_nic(bp, false, false); 5356 } 5357 5358 return rc; 5359 } 5360 5361 /* rtnl_lock held */ 5362 static int bnxt_change_mtu(struct net_device *dev, int new_mtu) 5363 { 5364 struct bnxt *bp = netdev_priv(dev); 5365 5366 if (new_mtu < 60 || new_mtu > 9000) 5367 return -EINVAL; 5368 5369 if (netif_running(dev)) 5370 bnxt_close_nic(bp, false, false); 5371 5372 dev->mtu = new_mtu; 5373 bnxt_set_ring_params(bp); 5374 5375 if (netif_running(dev)) 5376 return bnxt_open_nic(bp, false, false); 5377 5378 return 0; 5379 } 5380 5381 static int bnxt_setup_tc(struct net_device *dev, u8 tc) 5382 { 5383 struct bnxt *bp = netdev_priv(dev); 5384 5385 if (tc > bp->max_tc) { 5386 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n", 5387 tc, bp->max_tc); 5388 return -EINVAL; 5389 } 5390 5391 if (netdev_get_num_tc(dev) == tc) 5392 return 0; 5393 5394 if (tc) { 5395 int max_rx_rings, max_tx_rings, rc; 5396 bool sh = false; 5397 5398 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 5399 sh = true; 5400 5401 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh); 5402 if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings) 5403 return -ENOMEM; 5404 } 5405 5406 /* Needs to close the device and do hw resource re-allocations */ 5407 if (netif_running(bp->dev)) 5408 bnxt_close_nic(bp, true, false); 5409 5410 if (tc) { 5411 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; 5412 netdev_set_num_tc(dev, tc); 5413 } else { 5414 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 5415 netdev_reset_tc(dev); 5416 } 5417 bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings); 5418 bp->num_stat_ctxs = bp->cp_nr_rings; 5419 5420 if (netif_running(bp->dev)) 5421 return bnxt_open_nic(bp, true, false); 5422 5423 return 0; 5424 } 5425 5426 #ifdef CONFIG_RFS_ACCEL 5427 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, 5428 struct bnxt_ntuple_filter *f2) 5429 { 5430 struct flow_keys *keys1 = &f1->fkeys; 5431 struct flow_keys *keys2 = &f2->fkeys; 5432 5433 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src && 5434 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst && 5435 keys1->ports.ports == keys2->ports.ports && 5436 keys1->basic.ip_proto == keys2->basic.ip_proto && 5437 keys1->basic.n_proto == keys2->basic.n_proto && 5438 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr)) 5439 return true; 5440 5441 return false; 5442 } 5443 5444 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 5445 u16 rxq_index, u32 flow_id) 5446 { 5447 struct bnxt *bp = netdev_priv(dev); 5448 struct bnxt_ntuple_filter *fltr, *new_fltr; 5449 struct flow_keys *fkeys; 5450 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); 5451 int rc = 0, idx, bit_id; 5452 struct hlist_head *head; 5453 5454 if (skb->encapsulation) 5455 return -EPROTONOSUPPORT; 5456 5457 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); 5458 if (!new_fltr) 5459 return -ENOMEM; 5460 5461 fkeys = &new_fltr->fkeys; 5462 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { 5463 rc = -EPROTONOSUPPORT; 5464 goto err_free; 5465 } 5466 5467 if ((fkeys->basic.n_proto != htons(ETH_P_IP)) || 5468 ((fkeys->basic.ip_proto != IPPROTO_TCP) && 5469 (fkeys->basic.ip_proto != IPPROTO_UDP))) { 5470 rc = -EPROTONOSUPPORT; 5471 goto err_free; 5472 } 5473 5474 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); 5475 5476 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; 5477 head = &bp->ntp_fltr_hash_tbl[idx]; 5478 rcu_read_lock(); 5479 hlist_for_each_entry_rcu(fltr, head, hash) { 5480 if (bnxt_fltr_match(fltr, new_fltr)) { 5481 rcu_read_unlock(); 5482 rc = 0; 5483 goto err_free; 5484 } 5485 } 5486 rcu_read_unlock(); 5487 5488 spin_lock_bh(&bp->ntp_fltr_lock); 5489 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, 5490 BNXT_NTP_FLTR_MAX_FLTR, 0); 5491 if (bit_id < 0) { 5492 spin_unlock_bh(&bp->ntp_fltr_lock); 5493 rc = -ENOMEM; 5494 goto err_free; 5495 } 5496 5497 new_fltr->sw_id = (u16)bit_id; 5498 new_fltr->flow_id = flow_id; 5499 new_fltr->rxq = rxq_index; 5500 hlist_add_head_rcu(&new_fltr->hash, head); 5501 bp->ntp_fltr_count++; 5502 spin_unlock_bh(&bp->ntp_fltr_lock); 5503 5504 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 5505 schedule_work(&bp->sp_task); 5506 5507 return new_fltr->sw_id; 5508 5509 err_free: 5510 kfree(new_fltr); 5511 return rc; 5512 } 5513 5514 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 5515 { 5516 int i; 5517 5518 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 5519 struct hlist_head *head; 5520 struct hlist_node *tmp; 5521 struct bnxt_ntuple_filter *fltr; 5522 int rc; 5523 5524 head = &bp->ntp_fltr_hash_tbl[i]; 5525 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 5526 bool del = false; 5527 5528 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { 5529 if (rps_may_expire_flow(bp->dev, fltr->rxq, 5530 fltr->flow_id, 5531 fltr->sw_id)) { 5532 bnxt_hwrm_cfa_ntuple_filter_free(bp, 5533 fltr); 5534 del = true; 5535 } 5536 } else { 5537 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, 5538 fltr); 5539 if (rc) 5540 del = true; 5541 else 5542 set_bit(BNXT_FLTR_VALID, &fltr->state); 5543 } 5544 5545 if (del) { 5546 spin_lock_bh(&bp->ntp_fltr_lock); 5547 hlist_del_rcu(&fltr->hash); 5548 bp->ntp_fltr_count--; 5549 spin_unlock_bh(&bp->ntp_fltr_lock); 5550 synchronize_rcu(); 5551 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); 5552 kfree(fltr); 5553 } 5554 } 5555 } 5556 } 5557 5558 #else 5559 5560 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 5561 { 5562 } 5563 5564 #endif /* CONFIG_RFS_ACCEL */ 5565 5566 static void bnxt_add_vxlan_port(struct net_device *dev, sa_family_t sa_family, 5567 __be16 port) 5568 { 5569 struct bnxt *bp = netdev_priv(dev); 5570 5571 if (!netif_running(dev)) 5572 return; 5573 5574 if (sa_family != AF_INET6 && sa_family != AF_INET) 5575 return; 5576 5577 if (bp->vxlan_port_cnt && bp->vxlan_port != port) 5578 return; 5579 5580 bp->vxlan_port_cnt++; 5581 if (bp->vxlan_port_cnt == 1) { 5582 bp->vxlan_port = port; 5583 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event); 5584 schedule_work(&bp->sp_task); 5585 } 5586 } 5587 5588 static void bnxt_del_vxlan_port(struct net_device *dev, sa_family_t sa_family, 5589 __be16 port) 5590 { 5591 struct bnxt *bp = netdev_priv(dev); 5592 5593 if (!netif_running(dev)) 5594 return; 5595 5596 if (sa_family != AF_INET6 && sa_family != AF_INET) 5597 return; 5598 5599 if (bp->vxlan_port_cnt && bp->vxlan_port == port) { 5600 bp->vxlan_port_cnt--; 5601 5602 if (bp->vxlan_port_cnt == 0) { 5603 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event); 5604 schedule_work(&bp->sp_task); 5605 } 5606 } 5607 } 5608 5609 static const struct net_device_ops bnxt_netdev_ops = { 5610 .ndo_open = bnxt_open, 5611 .ndo_start_xmit = bnxt_start_xmit, 5612 .ndo_stop = bnxt_close, 5613 .ndo_get_stats64 = bnxt_get_stats64, 5614 .ndo_set_rx_mode = bnxt_set_rx_mode, 5615 .ndo_do_ioctl = bnxt_ioctl, 5616 .ndo_validate_addr = eth_validate_addr, 5617 .ndo_set_mac_address = bnxt_change_mac_addr, 5618 .ndo_change_mtu = bnxt_change_mtu, 5619 .ndo_fix_features = bnxt_fix_features, 5620 .ndo_set_features = bnxt_set_features, 5621 .ndo_tx_timeout = bnxt_tx_timeout, 5622 #ifdef CONFIG_BNXT_SRIOV 5623 .ndo_get_vf_config = bnxt_get_vf_config, 5624 .ndo_set_vf_mac = bnxt_set_vf_mac, 5625 .ndo_set_vf_vlan = bnxt_set_vf_vlan, 5626 .ndo_set_vf_rate = bnxt_set_vf_bw, 5627 .ndo_set_vf_link_state = bnxt_set_vf_link_state, 5628 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, 5629 #endif 5630 #ifdef CONFIG_NET_POLL_CONTROLLER 5631 .ndo_poll_controller = bnxt_poll_controller, 5632 #endif 5633 .ndo_setup_tc = bnxt_setup_tc, 5634 #ifdef CONFIG_RFS_ACCEL 5635 .ndo_rx_flow_steer = bnxt_rx_flow_steer, 5636 #endif 5637 .ndo_add_vxlan_port = bnxt_add_vxlan_port, 5638 .ndo_del_vxlan_port = bnxt_del_vxlan_port, 5639 #ifdef CONFIG_NET_RX_BUSY_POLL 5640 .ndo_busy_poll = bnxt_busy_poll, 5641 #endif 5642 }; 5643 5644 static void bnxt_remove_one(struct pci_dev *pdev) 5645 { 5646 struct net_device *dev = pci_get_drvdata(pdev); 5647 struct bnxt *bp = netdev_priv(dev); 5648 5649 if (BNXT_PF(bp)) 5650 bnxt_sriov_disable(bp); 5651 5652 unregister_netdev(dev); 5653 cancel_work_sync(&bp->sp_task); 5654 bp->sp_event = 0; 5655 5656 bnxt_hwrm_func_drv_unrgtr(bp); 5657 bnxt_free_hwrm_resources(bp); 5658 pci_iounmap(pdev, bp->bar2); 5659 pci_iounmap(pdev, bp->bar1); 5660 pci_iounmap(pdev, bp->bar0); 5661 free_netdev(dev); 5662 5663 pci_release_regions(pdev); 5664 pci_disable_device(pdev); 5665 } 5666 5667 static int bnxt_probe_phy(struct bnxt *bp) 5668 { 5669 int rc = 0; 5670 struct bnxt_link_info *link_info = &bp->link_info; 5671 char phy_ver[PHY_VER_STR_LEN]; 5672 5673 rc = bnxt_update_link(bp, false); 5674 if (rc) { 5675 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", 5676 rc); 5677 return rc; 5678 } 5679 5680 /*initialize the ethool setting copy with NVM settings */ 5681 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 5682 link_info->autoneg = BNXT_AUTONEG_SPEED | 5683 BNXT_AUTONEG_FLOW_CTRL; 5684 link_info->advertising = link_info->auto_link_speeds; 5685 link_info->req_flow_ctrl = link_info->auto_pause_setting; 5686 } else { 5687 link_info->req_link_speed = link_info->force_link_speed; 5688 link_info->req_duplex = link_info->duplex_setting; 5689 link_info->req_flow_ctrl = link_info->force_pause_setting; 5690 } 5691 snprintf(phy_ver, PHY_VER_STR_LEN, " ph %d.%d.%d", 5692 link_info->phy_ver[0], 5693 link_info->phy_ver[1], 5694 link_info->phy_ver[2]); 5695 strcat(bp->fw_ver_str, phy_ver); 5696 return rc; 5697 } 5698 5699 static int bnxt_get_max_irq(struct pci_dev *pdev) 5700 { 5701 u16 ctrl; 5702 5703 if (!pdev->msix_cap) 5704 return 1; 5705 5706 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 5707 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 5708 } 5709 5710 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, 5711 int *max_cp) 5712 { 5713 int max_ring_grps = 0; 5714 5715 #ifdef CONFIG_BNXT_SRIOV 5716 if (!BNXT_PF(bp)) { 5717 *max_tx = bp->vf.max_tx_rings; 5718 *max_rx = bp->vf.max_rx_rings; 5719 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings); 5720 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs); 5721 max_ring_grps = bp->vf.max_hw_ring_grps; 5722 } else 5723 #endif 5724 { 5725 *max_tx = bp->pf.max_tx_rings; 5726 *max_rx = bp->pf.max_rx_rings; 5727 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings); 5728 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs); 5729 max_ring_grps = bp->pf.max_hw_ring_grps; 5730 } 5731 5732 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5733 *max_rx >>= 1; 5734 *max_rx = min_t(int, *max_rx, max_ring_grps); 5735 } 5736 5737 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) 5738 { 5739 int rx, tx, cp; 5740 5741 _bnxt_get_max_rings(bp, &rx, &tx, &cp); 5742 if (!rx || !tx || !cp) 5743 return -ENOMEM; 5744 5745 *max_rx = rx; 5746 *max_tx = tx; 5747 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); 5748 } 5749 5750 static int bnxt_set_dflt_rings(struct bnxt *bp) 5751 { 5752 int dflt_rings, max_rx_rings, max_tx_rings, rc; 5753 bool sh = true; 5754 5755 if (sh) 5756 bp->flags |= BNXT_FLAG_SHARED_RINGS; 5757 dflt_rings = netif_get_num_default_rss_queues(); 5758 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh); 5759 if (rc) 5760 return rc; 5761 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); 5762 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); 5763 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 5764 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 5765 bp->tx_nr_rings + bp->rx_nr_rings; 5766 bp->num_stat_ctxs = bp->cp_nr_rings; 5767 return rc; 5768 } 5769 5770 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5771 { 5772 static int version_printed; 5773 struct net_device *dev; 5774 struct bnxt *bp; 5775 int rc, max_irqs; 5776 5777 if (version_printed++ == 0) 5778 pr_info("%s", version); 5779 5780 max_irqs = bnxt_get_max_irq(pdev); 5781 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); 5782 if (!dev) 5783 return -ENOMEM; 5784 5785 bp = netdev_priv(dev); 5786 5787 if (bnxt_vf_pciid(ent->driver_data)) 5788 bp->flags |= BNXT_FLAG_VF; 5789 5790 if (pdev->msix_cap) 5791 bp->flags |= BNXT_FLAG_MSIX_CAP; 5792 5793 rc = bnxt_init_board(pdev, dev); 5794 if (rc < 0) 5795 goto init_err_free; 5796 5797 dev->netdev_ops = &bnxt_netdev_ops; 5798 dev->watchdog_timeo = BNXT_TX_TIMEOUT; 5799 dev->ethtool_ops = &bnxt_ethtool_ops; 5800 5801 pci_set_drvdata(pdev, dev); 5802 5803 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 5804 NETIF_F_TSO | NETIF_F_TSO6 | 5805 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 5806 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT | 5807 NETIF_F_RXHASH | 5808 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO; 5809 5810 dev->hw_enc_features = 5811 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 5812 NETIF_F_TSO | NETIF_F_TSO6 | 5813 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 5814 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT; 5815 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; 5816 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 5817 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX; 5818 dev->features |= dev->hw_features | NETIF_F_HIGHDMA; 5819 dev->priv_flags |= IFF_UNICAST_FLT; 5820 5821 #ifdef CONFIG_BNXT_SRIOV 5822 init_waitqueue_head(&bp->sriov_cfg_wait); 5823 #endif 5824 rc = bnxt_alloc_hwrm_resources(bp); 5825 if (rc) 5826 goto init_err; 5827 5828 mutex_init(&bp->hwrm_cmd_lock); 5829 bnxt_hwrm_ver_get(bp); 5830 5831 rc = bnxt_hwrm_func_drv_rgtr(bp); 5832 if (rc) 5833 goto init_err; 5834 5835 /* Get the MAX capabilities for this function */ 5836 rc = bnxt_hwrm_func_qcaps(bp); 5837 if (rc) { 5838 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", 5839 rc); 5840 rc = -1; 5841 goto init_err; 5842 } 5843 5844 rc = bnxt_hwrm_queue_qportcfg(bp); 5845 if (rc) { 5846 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n", 5847 rc); 5848 rc = -1; 5849 goto init_err; 5850 } 5851 5852 bnxt_set_tpa_flags(bp); 5853 bnxt_set_ring_params(bp); 5854 if (BNXT_PF(bp)) 5855 bp->pf.max_irqs = max_irqs; 5856 #if defined(CONFIG_BNXT_SRIOV) 5857 else 5858 bp->vf.max_irqs = max_irqs; 5859 #endif 5860 bnxt_set_dflt_rings(bp); 5861 5862 if (BNXT_PF(bp)) { 5863 dev->hw_features |= NETIF_F_NTUPLE; 5864 if (bnxt_rfs_capable(bp)) { 5865 bp->flags |= BNXT_FLAG_RFS; 5866 dev->features |= NETIF_F_NTUPLE; 5867 } 5868 } 5869 5870 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX) 5871 bp->flags |= BNXT_FLAG_STRIP_VLAN; 5872 5873 rc = bnxt_probe_phy(bp); 5874 if (rc) 5875 goto init_err; 5876 5877 rc = register_netdev(dev); 5878 if (rc) 5879 goto init_err; 5880 5881 netdev_info(dev, "%s found at mem %lx, node addr %pM\n", 5882 board_info[ent->driver_data].name, 5883 (long)pci_resource_start(pdev, 0), dev->dev_addr); 5884 5885 return 0; 5886 5887 init_err: 5888 pci_iounmap(pdev, bp->bar0); 5889 pci_release_regions(pdev); 5890 pci_disable_device(pdev); 5891 5892 init_err_free: 5893 free_netdev(dev); 5894 return rc; 5895 } 5896 5897 static struct pci_driver bnxt_pci_driver = { 5898 .name = DRV_MODULE_NAME, 5899 .id_table = bnxt_pci_tbl, 5900 .probe = bnxt_init_one, 5901 .remove = bnxt_remove_one, 5902 #if defined(CONFIG_BNXT_SRIOV) 5903 .sriov_configure = bnxt_sriov_configure, 5904 #endif 5905 }; 5906 5907 module_pci_driver(bnxt_pci_driver); 5908