1 /* bnx2x_init_ops.h: Broadcom Everest network driver. 2 * Static functions needed during the initialization. 3 * This file is "included" in bnx2x_main.c. 4 * 5 * Copyright (c) 2007-2011 Broadcom Corporation 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 12 * Written by: Vladislav Zolotarov <vladz@broadcom.com> 13 */ 14 15 #ifndef BNX2X_INIT_OPS_H 16 #define BNX2X_INIT_OPS_H 17 18 19 #ifndef BP_ILT 20 #define BP_ILT(bp) NULL 21 #endif 22 23 #ifndef BP_FUNC 24 #define BP_FUNC(bp) 0 25 #endif 26 27 #ifndef BP_PORT 28 #define BP_PORT(bp) 0 29 #endif 30 31 #ifndef BNX2X_ILT_FREE 32 #define BNX2X_ILT_FREE(x, y, sz) 33 #endif 34 35 #ifndef BNX2X_ILT_ZALLOC 36 #define BNX2X_ILT_ZALLOC(x, y, sz) 37 #endif 38 39 #ifndef ILOG2 40 #define ILOG2(x) x 41 #endif 42 43 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len); 44 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val); 45 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, 46 dma_addr_t phys_addr, u32 addr, 47 u32 len); 48 49 static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, 50 const u32 *data, u32 len) 51 { 52 u32 i; 53 54 for (i = 0; i < len; i++) 55 REG_WR(bp, addr + i*4, data[i]); 56 } 57 58 static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, 59 const u32 *data, u32 len) 60 { 61 u32 i; 62 63 for (i = 0; i < len; i++) 64 bnx2x_reg_wr_ind(bp, addr + i*4, data[i]); 65 } 66 67 static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len, 68 u8 wb) 69 { 70 if (bp->dmae_ready) 71 bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len); 72 else if (wb) 73 /* 74 * Wide bus registers with no dmae need to be written 75 * using indirect write. 76 */ 77 bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len); 78 else 79 bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len); 80 } 81 82 static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, 83 u32 len, u8 wb) 84 { 85 u32 buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4)); 86 u32 buf_len32 = buf_len/4; 87 u32 i; 88 89 memset(GUNZIP_BUF(bp), (u8)fill, buf_len); 90 91 for (i = 0; i < len; i += buf_len32) { 92 u32 cur_len = min(buf_len32, len - i); 93 94 bnx2x_write_big_buf(bp, addr + i*4, cur_len, wb); 95 } 96 } 97 98 static void bnx2x_write_big_buf_wb(struct bnx2x *bp, u32 addr, u32 len) 99 { 100 if (bp->dmae_ready) 101 bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len); 102 else 103 bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len); 104 } 105 106 static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, 107 const u32 *data, u32 len64) 108 { 109 u32 buf_len32 = FW_BUF_SIZE/4; 110 u32 len = len64*2; 111 u64 data64 = 0; 112 u32 i; 113 114 /* 64 bit value is in a blob: first low DWORD, then high DWORD */ 115 data64 = HILO_U64((*(data + 1)), (*data)); 116 117 len64 = min((u32)(FW_BUF_SIZE/8), len64); 118 for (i = 0; i < len64; i++) { 119 u64 *pdata = ((u64 *)(GUNZIP_BUF(bp))) + i; 120 121 *pdata = data64; 122 } 123 124 for (i = 0; i < len; i += buf_len32) { 125 u32 cur_len = min(buf_len32, len - i); 126 127 bnx2x_write_big_buf_wb(bp, addr + i*4, cur_len); 128 } 129 } 130 131 /********************************************************* 132 There are different blobs for each PRAM section. 133 In addition, each blob write operation is divided into a few operations 134 in order to decrease the amount of phys. contiguous buffer needed. 135 Thus, when we select a blob the address may be with some offset 136 from the beginning of PRAM section. 137 The same holds for the INT_TABLE sections. 138 **********************************************************/ 139 #define IF_IS_INT_TABLE_ADDR(base, addr) \ 140 if (((base) <= (addr)) && ((base) + 0x400 >= (addr))) 141 142 #define IF_IS_PRAM_ADDR(base, addr) \ 143 if (((base) <= (addr)) && ((base) + 0x40000 >= (addr))) 144 145 static const u8 *bnx2x_sel_blob(struct bnx2x *bp, u32 addr, 146 const u8 *data) 147 { 148 IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr) 149 data = INIT_TSEM_INT_TABLE_DATA(bp); 150 else 151 IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr) 152 data = INIT_CSEM_INT_TABLE_DATA(bp); 153 else 154 IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr) 155 data = INIT_USEM_INT_TABLE_DATA(bp); 156 else 157 IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr) 158 data = INIT_XSEM_INT_TABLE_DATA(bp); 159 else 160 IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr) 161 data = INIT_TSEM_PRAM_DATA(bp); 162 else 163 IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr) 164 data = INIT_CSEM_PRAM_DATA(bp); 165 else 166 IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr) 167 data = INIT_USEM_PRAM_DATA(bp); 168 else 169 IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr) 170 data = INIT_XSEM_PRAM_DATA(bp); 171 172 return data; 173 } 174 175 static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, 176 const u32 *data, u32 len) 177 { 178 if (bp->dmae_ready) 179 VIRT_WR_DMAE_LEN(bp, data, addr, len, 0); 180 else 181 bnx2x_init_ind_wr(bp, addr, data, len); 182 } 183 184 static void bnx2x_wr_64(struct bnx2x *bp, u32 reg, u32 val_lo, 185 u32 val_hi) 186 { 187 u32 wb_write[2]; 188 189 wb_write[0] = val_lo; 190 wb_write[1] = val_hi; 191 REG_WR_DMAE_LEN(bp, reg, wb_write, 2); 192 } 193 static void bnx2x_init_wr_zp(struct bnx2x *bp, u32 addr, u32 len, 194 u32 blob_off) 195 { 196 const u8 *data = NULL; 197 int rc; 198 u32 i; 199 200 data = bnx2x_sel_blob(bp, addr, data) + blob_off*4; 201 202 rc = bnx2x_gunzip(bp, data, len); 203 if (rc) 204 return; 205 206 /* gunzip_outlen is in dwords */ 207 len = GUNZIP_OUTLEN(bp); 208 for (i = 0; i < len; i++) 209 ((u32 *)GUNZIP_BUF(bp))[i] = 210 cpu_to_le32(((u32 *)GUNZIP_BUF(bp))[i]); 211 212 bnx2x_write_big_buf_wb(bp, addr, len); 213 } 214 215 static void bnx2x_init_block(struct bnx2x *bp, u32 block, u32 stage) 216 { 217 u16 op_start = 218 INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage, 219 STAGE_START)]; 220 u16 op_end = 221 INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage, 222 STAGE_END)]; 223 union init_op *op; 224 u32 op_idx, op_type, addr, len; 225 const u32 *data, *data_base; 226 227 /* If empty block */ 228 if (op_start == op_end) 229 return; 230 231 data_base = INIT_DATA(bp); 232 233 for (op_idx = op_start; op_idx < op_end; op_idx++) { 234 235 op = (union init_op *)&(INIT_OPS(bp)[op_idx]); 236 /* Get generic data */ 237 op_type = op->raw.op; 238 addr = op->raw.offset; 239 /* Get data that's used for OP_SW, OP_WB, OP_FW, OP_ZP and 240 * OP_WR64 (we assume that op_arr_write and op_write have the 241 * same structure). 242 */ 243 len = op->arr_wr.data_len; 244 data = data_base + op->arr_wr.data_off; 245 246 switch (op_type) { 247 case OP_RD: 248 REG_RD(bp, addr); 249 break; 250 case OP_WR: 251 REG_WR(bp, addr, op->write.val); 252 break; 253 case OP_SW: 254 bnx2x_init_str_wr(bp, addr, data, len); 255 break; 256 case OP_WB: 257 bnx2x_init_wr_wb(bp, addr, data, len); 258 break; 259 case OP_ZR: 260 bnx2x_init_fill(bp, addr, 0, op->zero.len, 0); 261 break; 262 case OP_WB_ZR: 263 bnx2x_init_fill(bp, addr, 0, op->zero.len, 1); 264 break; 265 case OP_ZP: 266 bnx2x_init_wr_zp(bp, addr, len, 267 op->arr_wr.data_off); 268 break; 269 case OP_WR_64: 270 bnx2x_init_wr_64(bp, addr, data, len); 271 break; 272 case OP_IF_MODE_AND: 273 /* if any of the flags doesn't match, skip the 274 * conditional block. 275 */ 276 if ((INIT_MODE_FLAGS(bp) & 277 op->if_mode.mode_bit_map) != 278 op->if_mode.mode_bit_map) 279 op_idx += op->if_mode.cmd_offset; 280 break; 281 case OP_IF_MODE_OR: 282 /* if all the flags don't match, skip the conditional 283 * block. 284 */ 285 if ((INIT_MODE_FLAGS(bp) & 286 op->if_mode.mode_bit_map) == 0) 287 op_idx += op->if_mode.cmd_offset; 288 break; 289 default: 290 /* Should never get here! */ 291 292 break; 293 } 294 } 295 } 296 297 298 /**************************************************************************** 299 * PXP Arbiter 300 ****************************************************************************/ 301 /* 302 * This code configures the PCI read/write arbiter 303 * which implements a weighted round robin 304 * between the virtual queues in the chip. 305 * 306 * The values were derived for each PCI max payload and max request size. 307 * since max payload and max request size are only known at run time, 308 * this is done as a separate init stage. 309 */ 310 311 #define NUM_WR_Q 13 312 #define NUM_RD_Q 29 313 #define MAX_RD_ORD 3 314 #define MAX_WR_ORD 2 315 316 /* configuration for one arbiter queue */ 317 struct arb_line { 318 int l; 319 int add; 320 int ubound; 321 }; 322 323 /* derived configuration for each read queue for each max request size */ 324 static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = { 325 /* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} }, 326 { {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} }, 327 { {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} }, 328 { {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} }, 329 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} }, 330 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, 331 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, 332 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, 333 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, 334 /* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 335 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 336 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 337 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 338 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 339 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 340 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 341 { {8, 64, 6}, {16, 64, 11}, {32, 64, 21}, {32, 64, 21} }, 342 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 343 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 344 /* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 345 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 346 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 347 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 348 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 349 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 350 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 351 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 352 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 353 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} } 354 }; 355 356 /* derived configuration for each write queue for each max request size */ 357 static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = { 358 /* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} }, 359 { {4, 2, 3}, {4, 2, 3}, {4, 2, 3} }, 360 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} }, 361 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} }, 362 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} }, 363 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} }, 364 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} }, 365 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} }, 366 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} }, 367 /* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} }, 368 { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} }, 369 { {8, 9, 6}, {16, 9, 11}, {16, 9, 11} }, 370 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} } 371 }; 372 373 /* register addresses for read queues */ 374 static const struct arb_line read_arb_addr[NUM_RD_Q-1] = { 375 /* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0, 376 PXP2_REG_RQ_BW_RD_UBOUND0}, 377 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, 378 PXP2_REG_PSWRQ_BW_UB1}, 379 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2, 380 PXP2_REG_PSWRQ_BW_UB2}, 381 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3, 382 PXP2_REG_PSWRQ_BW_UB3}, 383 {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4, 384 PXP2_REG_RQ_BW_RD_UBOUND4}, 385 {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5, 386 PXP2_REG_RQ_BW_RD_UBOUND5}, 387 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6, 388 PXP2_REG_PSWRQ_BW_UB6}, 389 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7, 390 PXP2_REG_PSWRQ_BW_UB7}, 391 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8, 392 PXP2_REG_PSWRQ_BW_UB8}, 393 /* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9, 394 PXP2_REG_PSWRQ_BW_UB9}, 395 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10, 396 PXP2_REG_PSWRQ_BW_UB10}, 397 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11, 398 PXP2_REG_PSWRQ_BW_UB11}, 399 {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12, 400 PXP2_REG_RQ_BW_RD_UBOUND12}, 401 {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13, 402 PXP2_REG_RQ_BW_RD_UBOUND13}, 403 {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14, 404 PXP2_REG_RQ_BW_RD_UBOUND14}, 405 {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15, 406 PXP2_REG_RQ_BW_RD_UBOUND15}, 407 {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16, 408 PXP2_REG_RQ_BW_RD_UBOUND16}, 409 {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17, 410 PXP2_REG_RQ_BW_RD_UBOUND17}, 411 {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18, 412 PXP2_REG_RQ_BW_RD_UBOUND18}, 413 /* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19, 414 PXP2_REG_RQ_BW_RD_UBOUND19}, 415 {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20, 416 PXP2_REG_RQ_BW_RD_UBOUND20}, 417 {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22, 418 PXP2_REG_RQ_BW_RD_UBOUND22}, 419 {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23, 420 PXP2_REG_RQ_BW_RD_UBOUND23}, 421 {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24, 422 PXP2_REG_RQ_BW_RD_UBOUND24}, 423 {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25, 424 PXP2_REG_RQ_BW_RD_UBOUND25}, 425 {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26, 426 PXP2_REG_RQ_BW_RD_UBOUND26}, 427 {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27, 428 PXP2_REG_RQ_BW_RD_UBOUND27}, 429 {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28, 430 PXP2_REG_PSWRQ_BW_UB28} 431 }; 432 433 /* register addresses for write queues */ 434 static const struct arb_line write_arb_addr[NUM_WR_Q-1] = { 435 /* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, 436 PXP2_REG_PSWRQ_BW_UB1}, 437 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2, 438 PXP2_REG_PSWRQ_BW_UB2}, 439 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3, 440 PXP2_REG_PSWRQ_BW_UB3}, 441 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6, 442 PXP2_REG_PSWRQ_BW_UB6}, 443 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7, 444 PXP2_REG_PSWRQ_BW_UB7}, 445 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8, 446 PXP2_REG_PSWRQ_BW_UB8}, 447 {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9, 448 PXP2_REG_PSWRQ_BW_UB9}, 449 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10, 450 PXP2_REG_PSWRQ_BW_UB10}, 451 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11, 452 PXP2_REG_PSWRQ_BW_UB11}, 453 /* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28, 454 PXP2_REG_PSWRQ_BW_UB28}, 455 {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29, 456 PXP2_REG_RQ_BW_WR_UBOUND29}, 457 {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30, 458 PXP2_REG_RQ_BW_WR_UBOUND30} 459 }; 460 461 static void bnx2x_init_pxp_arb(struct bnx2x *bp, int r_order, 462 int w_order) 463 { 464 u32 val, i; 465 466 if (r_order > MAX_RD_ORD) { 467 DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n", 468 r_order, MAX_RD_ORD); 469 r_order = MAX_RD_ORD; 470 } 471 if (w_order > MAX_WR_ORD) { 472 DP(NETIF_MSG_HW, "write order of %d order adjusted to %d\n", 473 w_order, MAX_WR_ORD); 474 w_order = MAX_WR_ORD; 475 } 476 if (CHIP_REV_IS_FPGA(bp)) { 477 DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n"); 478 w_order = 0; 479 } 480 DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order); 481 482 for (i = 0; i < NUM_RD_Q-1; i++) { 483 REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l); 484 REG_WR(bp, read_arb_addr[i].add, 485 read_arb_data[i][r_order].add); 486 REG_WR(bp, read_arb_addr[i].ubound, 487 read_arb_data[i][r_order].ubound); 488 } 489 490 for (i = 0; i < NUM_WR_Q-1; i++) { 491 if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) || 492 (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) { 493 494 REG_WR(bp, write_arb_addr[i].l, 495 write_arb_data[i][w_order].l); 496 497 REG_WR(bp, write_arb_addr[i].add, 498 write_arb_data[i][w_order].add); 499 500 REG_WR(bp, write_arb_addr[i].ubound, 501 write_arb_data[i][w_order].ubound); 502 } else { 503 504 val = REG_RD(bp, write_arb_addr[i].l); 505 REG_WR(bp, write_arb_addr[i].l, 506 val | (write_arb_data[i][w_order].l << 10)); 507 508 val = REG_RD(bp, write_arb_addr[i].add); 509 REG_WR(bp, write_arb_addr[i].add, 510 val | (write_arb_data[i][w_order].add << 10)); 511 512 val = REG_RD(bp, write_arb_addr[i].ubound); 513 REG_WR(bp, write_arb_addr[i].ubound, 514 val | (write_arb_data[i][w_order].ubound << 7)); 515 } 516 } 517 518 val = write_arb_data[NUM_WR_Q-1][w_order].add; 519 val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10; 520 val += write_arb_data[NUM_WR_Q-1][w_order].l << 17; 521 REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val); 522 523 val = read_arb_data[NUM_RD_Q-1][r_order].add; 524 val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10; 525 val += read_arb_data[NUM_RD_Q-1][r_order].l << 17; 526 REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val); 527 528 REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order); 529 REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order); 530 REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order); 531 REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order); 532 533 if ((CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) && (r_order == MAX_RD_ORD)) 534 REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00); 535 536 if (CHIP_IS_E3(bp)) 537 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order)); 538 else if (CHIP_IS_E2(bp)) 539 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order)); 540 else 541 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order)); 542 543 if (!CHIP_IS_E1(bp)) { 544 /* MPS w_order optimal TH presently TH 545 * 128 0 0 2 546 * 256 1 1 3 547 * >=512 2 2 3 548 */ 549 /* DMAE is special */ 550 if (!CHIP_IS_E1H(bp)) { 551 /* E2 can use optimal TH */ 552 val = w_order; 553 REG_WR(bp, PXP2_REG_WR_DMAE_MPS, val); 554 } else { 555 val = ((w_order == 0) ? 2 : 3); 556 REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); 557 } 558 559 REG_WR(bp, PXP2_REG_WR_HC_MPS, val); 560 REG_WR(bp, PXP2_REG_WR_USDM_MPS, val); 561 REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val); 562 REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val); 563 REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val); 564 REG_WR(bp, PXP2_REG_WR_QM_MPS, val); 565 REG_WR(bp, PXP2_REG_WR_TM_MPS, val); 566 REG_WR(bp, PXP2_REG_WR_SRC_MPS, val); 567 REG_WR(bp, PXP2_REG_WR_DBG_MPS, val); 568 REG_WR(bp, PXP2_REG_WR_CDU_MPS, val); 569 } 570 571 /* Validate number of tags suppoted by device */ 572 #define PCIE_REG_PCIER_TL_HDR_FC_ST 0x2980 573 val = REG_RD(bp, PCIE_REG_PCIER_TL_HDR_FC_ST); 574 val &= 0xFF; 575 if (val <= 0x20) 576 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x20); 577 } 578 579 /**************************************************************************** 580 * ILT management 581 ****************************************************************************/ 582 /* 583 * This codes hides the low level HW interaction for ILT management and 584 * configuration. The API consists of a shadow ILT table which is set by the 585 * driver and a set of routines to use it to configure the HW. 586 * 587 */ 588 589 /* ILT HW init operations */ 590 591 /* ILT memory management operations */ 592 #define ILT_MEMOP_ALLOC 0 593 #define ILT_MEMOP_FREE 1 594 595 /* the phys address is shifted right 12 bits and has an added 596 * 1=valid bit added to the 53rd bit 597 * then since this is a wide register(TM) 598 * we split it into two 32 bit writes 599 */ 600 #define ILT_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 601 #define ILT_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 602 #define ILT_RANGE(f, l) (((l) << 10) | f) 603 604 static int bnx2x_ilt_line_mem_op(struct bnx2x *bp, 605 struct ilt_line *line, u32 size, u8 memop) 606 { 607 if (memop == ILT_MEMOP_FREE) { 608 BNX2X_ILT_FREE(line->page, line->page_mapping, line->size); 609 return 0; 610 } 611 BNX2X_ILT_ZALLOC(line->page, &line->page_mapping, size); 612 if (!line->page) 613 return -1; 614 line->size = size; 615 return 0; 616 } 617 618 619 static int bnx2x_ilt_client_mem_op(struct bnx2x *bp, int cli_num, 620 u8 memop) 621 { 622 int i, rc; 623 struct bnx2x_ilt *ilt = BP_ILT(bp); 624 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num]; 625 626 if (!ilt || !ilt->lines) 627 return -1; 628 629 if (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM)) 630 return 0; 631 632 for (rc = 0, i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) { 633 rc = bnx2x_ilt_line_mem_op(bp, &ilt->lines[i], 634 ilt_cli->page_size, memop); 635 } 636 return rc; 637 } 638 639 static int bnx2x_ilt_mem_op(struct bnx2x *bp, u8 memop) 640 { 641 int rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_CDU, memop); 642 if (!rc) 643 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_QM, memop); 644 if (!rc) 645 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_SRC, memop); 646 if (!rc) 647 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_TM, memop); 648 649 return rc; 650 } 651 652 static void bnx2x_ilt_line_wr(struct bnx2x *bp, int abs_idx, 653 dma_addr_t page_mapping) 654 { 655 u32 reg; 656 657 if (CHIP_IS_E1(bp)) 658 reg = PXP2_REG_RQ_ONCHIP_AT + abs_idx*8; 659 else 660 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8; 661 662 bnx2x_wr_64(bp, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping)); 663 } 664 665 static void bnx2x_ilt_line_init_op(struct bnx2x *bp, 666 struct bnx2x_ilt *ilt, int idx, u8 initop) 667 { 668 dma_addr_t null_mapping; 669 int abs_idx = ilt->start_line + idx; 670 671 672 switch (initop) { 673 case INITOP_INIT: 674 /* set in the init-value array */ 675 case INITOP_SET: 676 bnx2x_ilt_line_wr(bp, abs_idx, ilt->lines[idx].page_mapping); 677 break; 678 case INITOP_CLEAR: 679 null_mapping = 0; 680 bnx2x_ilt_line_wr(bp, abs_idx, null_mapping); 681 break; 682 } 683 } 684 685 static void bnx2x_ilt_boundry_init_op(struct bnx2x *bp, 686 struct ilt_client_info *ilt_cli, 687 u32 ilt_start, u8 initop) 688 { 689 u32 start_reg = 0; 690 u32 end_reg = 0; 691 692 /* The boundary is either SET or INIT, 693 CLEAR => SET and for now SET ~~ INIT */ 694 695 /* find the appropriate regs */ 696 if (CHIP_IS_E1(bp)) { 697 switch (ilt_cli->client_num) { 698 case ILT_CLIENT_CDU: 699 start_reg = PXP2_REG_PSWRQ_CDU0_L2P; 700 break; 701 case ILT_CLIENT_QM: 702 start_reg = PXP2_REG_PSWRQ_QM0_L2P; 703 break; 704 case ILT_CLIENT_SRC: 705 start_reg = PXP2_REG_PSWRQ_SRC0_L2P; 706 break; 707 case ILT_CLIENT_TM: 708 start_reg = PXP2_REG_PSWRQ_TM0_L2P; 709 break; 710 } 711 REG_WR(bp, start_reg + BP_FUNC(bp)*4, 712 ILT_RANGE((ilt_start + ilt_cli->start), 713 (ilt_start + ilt_cli->end))); 714 } else { 715 switch (ilt_cli->client_num) { 716 case ILT_CLIENT_CDU: 717 start_reg = PXP2_REG_RQ_CDU_FIRST_ILT; 718 end_reg = PXP2_REG_RQ_CDU_LAST_ILT; 719 break; 720 case ILT_CLIENT_QM: 721 start_reg = PXP2_REG_RQ_QM_FIRST_ILT; 722 end_reg = PXP2_REG_RQ_QM_LAST_ILT; 723 break; 724 case ILT_CLIENT_SRC: 725 start_reg = PXP2_REG_RQ_SRC_FIRST_ILT; 726 end_reg = PXP2_REG_RQ_SRC_LAST_ILT; 727 break; 728 case ILT_CLIENT_TM: 729 start_reg = PXP2_REG_RQ_TM_FIRST_ILT; 730 end_reg = PXP2_REG_RQ_TM_LAST_ILT; 731 break; 732 } 733 REG_WR(bp, start_reg, (ilt_start + ilt_cli->start)); 734 REG_WR(bp, end_reg, (ilt_start + ilt_cli->end)); 735 } 736 } 737 738 static void bnx2x_ilt_client_init_op_ilt(struct bnx2x *bp, 739 struct bnx2x_ilt *ilt, 740 struct ilt_client_info *ilt_cli, 741 u8 initop) 742 { 743 int i; 744 745 if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT) 746 return; 747 748 for (i = ilt_cli->start; i <= ilt_cli->end; i++) 749 bnx2x_ilt_line_init_op(bp, ilt, i, initop); 750 751 /* init/clear the ILT boundries */ 752 bnx2x_ilt_boundry_init_op(bp, ilt_cli, ilt->start_line, initop); 753 } 754 755 static void bnx2x_ilt_client_init_op(struct bnx2x *bp, 756 struct ilt_client_info *ilt_cli, u8 initop) 757 { 758 struct bnx2x_ilt *ilt = BP_ILT(bp); 759 760 bnx2x_ilt_client_init_op_ilt(bp, ilt, ilt_cli, initop); 761 } 762 763 static void bnx2x_ilt_client_id_init_op(struct bnx2x *bp, 764 int cli_num, u8 initop) 765 { 766 struct bnx2x_ilt *ilt = BP_ILT(bp); 767 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num]; 768 769 bnx2x_ilt_client_init_op(bp, ilt_cli, initop); 770 } 771 772 static void bnx2x_ilt_init_op(struct bnx2x *bp, u8 initop) 773 { 774 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_CDU, initop); 775 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_QM, initop); 776 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_SRC, initop); 777 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_TM, initop); 778 } 779 780 static void bnx2x_ilt_init_client_psz(struct bnx2x *bp, int cli_num, 781 u32 psz_reg, u8 initop) 782 { 783 struct bnx2x_ilt *ilt = BP_ILT(bp); 784 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num]; 785 786 if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT) 787 return; 788 789 switch (initop) { 790 case INITOP_INIT: 791 /* set in the init-value array */ 792 case INITOP_SET: 793 REG_WR(bp, psz_reg, ILOG2(ilt_cli->page_size >> 12)); 794 break; 795 case INITOP_CLEAR: 796 break; 797 } 798 } 799 800 /* 801 * called during init common stage, ilt clients should be initialized 802 * prioir to calling this function 803 */ 804 static void bnx2x_ilt_init_page_size(struct bnx2x *bp, u8 initop) 805 { 806 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_CDU, 807 PXP2_REG_RQ_CDU_P_SIZE, initop); 808 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_QM, 809 PXP2_REG_RQ_QM_P_SIZE, initop); 810 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_SRC, 811 PXP2_REG_RQ_SRC_P_SIZE, initop); 812 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_TM, 813 PXP2_REG_RQ_TM_P_SIZE, initop); 814 } 815 816 /**************************************************************************** 817 * QM initializations 818 ****************************************************************************/ 819 #define QM_QUEUES_PER_FUNC 16 /* E1 has 32, but only 16 are used */ 820 #define QM_INIT_MIN_CID_COUNT 31 821 #define QM_INIT(cid_cnt) (cid_cnt > QM_INIT_MIN_CID_COUNT) 822 823 /* called during init port stage */ 824 static void bnx2x_qm_init_cid_count(struct bnx2x *bp, int qm_cid_count, 825 u8 initop) 826 { 827 int port = BP_PORT(bp); 828 829 if (QM_INIT(qm_cid_count)) { 830 switch (initop) { 831 case INITOP_INIT: 832 /* set in the init-value array */ 833 case INITOP_SET: 834 REG_WR(bp, QM_REG_CONNNUM_0 + port*4, 835 qm_cid_count/16 - 1); 836 break; 837 case INITOP_CLEAR: 838 break; 839 } 840 } 841 } 842 843 static void bnx2x_qm_set_ptr_table(struct bnx2x *bp, int qm_cid_count) 844 { 845 int i; 846 u32 wb_data[2]; 847 848 wb_data[0] = wb_data[1] = 0; 849 850 for (i = 0; i < 4 * QM_QUEUES_PER_FUNC; i++) { 851 REG_WR(bp, QM_REG_BASEADDR + i*4, 852 qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC)); 853 bnx2x_init_ind_wr(bp, QM_REG_PTRTBL + i*8, 854 wb_data, 2); 855 856 if (CHIP_IS_E1H(bp)) { 857 REG_WR(bp, QM_REG_BASEADDR_EXT_A + i*4, 858 qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC)); 859 bnx2x_init_ind_wr(bp, QM_REG_PTRTBL_EXT_A + i*8, 860 wb_data, 2); 861 } 862 } 863 } 864 865 /* called during init common stage */ 866 static void bnx2x_qm_init_ptr_table(struct bnx2x *bp, int qm_cid_count, 867 u8 initop) 868 { 869 if (!QM_INIT(qm_cid_count)) 870 return; 871 872 switch (initop) { 873 case INITOP_INIT: 874 /* set in the init-value array */ 875 case INITOP_SET: 876 bnx2x_qm_set_ptr_table(bp, qm_cid_count); 877 break; 878 case INITOP_CLEAR: 879 break; 880 } 881 } 882 883 /**************************************************************************** 884 * SRC initializations 885 ****************************************************************************/ 886 #ifdef BCM_CNIC 887 /* called during init func stage */ 888 static void bnx2x_src_init_t2(struct bnx2x *bp, struct src_ent *t2, 889 dma_addr_t t2_mapping, int src_cid_count) 890 { 891 int i; 892 int port = BP_PORT(bp); 893 894 /* Initialize T2 */ 895 for (i = 0; i < src_cid_count-1; i++) 896 t2[i].next = (u64)(t2_mapping + 897 (i+1)*sizeof(struct src_ent)); 898 899 /* tell the searcher where the T2 table is */ 900 REG_WR(bp, SRC_REG_COUNTFREE0 + port*4, src_cid_count); 901 902 bnx2x_wr_64(bp, SRC_REG_FIRSTFREE0 + port*16, 903 U64_LO(t2_mapping), U64_HI(t2_mapping)); 904 905 bnx2x_wr_64(bp, SRC_REG_LASTFREE0 + port*16, 906 U64_LO((u64)t2_mapping + 907 (src_cid_count-1) * sizeof(struct src_ent)), 908 U64_HI((u64)t2_mapping + 909 (src_cid_count-1) * sizeof(struct src_ent))); 910 } 911 #endif 912 #endif /* BNX2X_INIT_OPS_H */ 913