1 /* bnx2x_cmn.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 #ifndef BNX2X_CMN_H 18 #define BNX2X_CMN_H 19 20 #include <linux/types.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 25 26 #include "bnx2x.h" 27 28 /* This is used as a replacement for an MCP if it's not present */ 29 extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ 30 31 extern int num_queues; 32 extern int int_mode; 33 34 /************************ Macros ********************************/ 35 #define BNX2X_PCI_FREE(x, y, size) \ 36 do { \ 37 if (x) { \ 38 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ 39 x = NULL; \ 40 y = 0; \ 41 } \ 42 } while (0) 43 44 #define BNX2X_FREE(x) \ 45 do { \ 46 if (x) { \ 47 kfree((void *)x); \ 48 x = NULL; \ 49 } \ 50 } while (0) 51 52 #define BNX2X_PCI_ALLOC(x, y, size) \ 53 do { \ 54 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 55 if (x == NULL) \ 56 goto alloc_mem_err; \ 57 memset((void *)x, 0, size); \ 58 } while (0) 59 60 #define BNX2X_ALLOC(x, size) \ 61 do { \ 62 x = kzalloc(size, GFP_KERNEL); \ 63 if (x == NULL) \ 64 goto alloc_mem_err; \ 65 } while (0) 66 67 /*********************** Interfaces **************************** 68 * Functions that need to be implemented by each driver version 69 */ 70 /* Init */ 71 72 /** 73 * bnx2x_send_unload_req - request unload mode from the MCP. 74 * 75 * @bp: driver handle 76 * @unload_mode: requested function's unload mode 77 * 78 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 79 */ 80 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); 81 82 /** 83 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 84 * 85 * @bp: driver handle 86 */ 87 void bnx2x_send_unload_done(struct bnx2x *bp); 88 89 /** 90 * bnx2x_config_rss_pf - configure RSS parameters in a PF. 91 * 92 * @bp: driver handle 93 * @rss_obj: RSS object to use 94 * @ind_table: indirection table to configure 95 * @config_hash: re-configure RSS hash keys configuration 96 */ 97 int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj, 98 bool config_hash); 99 100 /** 101 * bnx2x__init_func_obj - init function object 102 * 103 * @bp: driver handle 104 * 105 * Initializes the Function Object with the appropriate 106 * parameters which include a function slow path driver 107 * interface. 108 */ 109 void bnx2x__init_func_obj(struct bnx2x *bp); 110 111 /** 112 * bnx2x_setup_queue - setup eth queue. 113 * 114 * @bp: driver handle 115 * @fp: pointer to the fastpath structure 116 * @leading: boolean 117 * 118 */ 119 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 120 bool leading); 121 122 /** 123 * bnx2x_setup_leading - bring up a leading eth queue. 124 * 125 * @bp: driver handle 126 */ 127 int bnx2x_setup_leading(struct bnx2x *bp); 128 129 /** 130 * bnx2x_fw_command - send the MCP a request 131 * 132 * @bp: driver handle 133 * @command: request 134 * @param: request's parameter 135 * 136 * block until there is a reply 137 */ 138 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); 139 140 /** 141 * bnx2x_initial_phy_init - initialize link parameters structure variables. 142 * 143 * @bp: driver handle 144 * @load_mode: current mode 145 */ 146 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); 147 148 /** 149 * bnx2x_link_set - configure hw according to link parameters structure. 150 * 151 * @bp: driver handle 152 */ 153 void bnx2x_link_set(struct bnx2x *bp); 154 155 /** 156 * bnx2x_link_test - query link status. 157 * 158 * @bp: driver handle 159 * @is_serdes: bool 160 * 161 * Returns 0 if link is UP. 162 */ 163 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); 164 165 /** 166 * bnx2x_drv_pulse - write driver pulse to shmem 167 * 168 * @bp: driver handle 169 * 170 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox 171 * in the shmem. 172 */ 173 void bnx2x_drv_pulse(struct bnx2x *bp); 174 175 /** 176 * bnx2x_igu_ack_sb - update IGU with current SB value 177 * 178 * @bp: driver handle 179 * @igu_sb_id: SB id 180 * @segment: SB segment 181 * @index: SB index 182 * @op: SB operation 183 * @update: is HW update required 184 */ 185 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 186 u16 index, u8 op, u8 update); 187 188 /* Disable transactions from chip to host */ 189 void bnx2x_pf_disable(struct bnx2x *bp); 190 191 /** 192 * bnx2x__link_status_update - handles link status change. 193 * 194 * @bp: driver handle 195 */ 196 void bnx2x__link_status_update(struct bnx2x *bp); 197 198 /** 199 * bnx2x_link_report - report link status to upper layer. 200 * 201 * @bp: driver handle 202 */ 203 void bnx2x_link_report(struct bnx2x *bp); 204 205 /* None-atomic version of bnx2x_link_report() */ 206 void __bnx2x_link_report(struct bnx2x *bp); 207 208 /** 209 * bnx2x_get_mf_speed - calculate MF speed. 210 * 211 * @bp: driver handle 212 * 213 * Takes into account current linespeed and MF configuration. 214 */ 215 u16 bnx2x_get_mf_speed(struct bnx2x *bp); 216 217 /** 218 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler 219 * 220 * @irq: irq number 221 * @dev_instance: private instance 222 */ 223 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); 224 225 /** 226 * bnx2x_interrupt - non MSI-X interrupt handler 227 * 228 * @irq: irq number 229 * @dev_instance: private instance 230 */ 231 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); 232 #ifdef BCM_CNIC 233 234 /** 235 * bnx2x_cnic_notify - send command to cnic driver 236 * 237 * @bp: driver handle 238 * @cmd: command 239 */ 240 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); 241 242 /** 243 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information 244 * 245 * @bp: driver handle 246 */ 247 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); 248 249 /** 250 * bnx2x_setup_cnic_info - provides cnic with updated info 251 * 252 * @bp: driver handle 253 */ 254 void bnx2x_setup_cnic_info(struct bnx2x *bp); 255 256 #endif 257 258 /** 259 * bnx2x_int_enable - enable HW interrupts. 260 * 261 * @bp: driver handle 262 */ 263 void bnx2x_int_enable(struct bnx2x *bp); 264 265 /** 266 * bnx2x_int_disable_sync - disable interrupts. 267 * 268 * @bp: driver handle 269 * @disable_hw: true, disable HW interrupts. 270 * 271 * This function ensures that there are no 272 * ISRs or SP DPCs (sp_task) are running after it returns. 273 */ 274 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); 275 276 /** 277 * bnx2x_nic_init - init driver internals. 278 * 279 * @bp: driver handle 280 * @load_code: COMMON, PORT or FUNCTION 281 * 282 * Initializes: 283 * - rings 284 * - status blocks 285 * - etc. 286 */ 287 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code); 288 289 /** 290 * bnx2x_alloc_mem - allocate driver's memory. 291 * 292 * @bp: driver handle 293 */ 294 int bnx2x_alloc_mem(struct bnx2x *bp); 295 296 /** 297 * bnx2x_free_mem - release driver's memory. 298 * 299 * @bp: driver handle 300 */ 301 void bnx2x_free_mem(struct bnx2x *bp); 302 303 /** 304 * bnx2x_set_num_queues - set number of queues according to mode. 305 * 306 * @bp: driver handle 307 */ 308 void bnx2x_set_num_queues(struct bnx2x *bp); 309 310 /** 311 * bnx2x_chip_cleanup - cleanup chip internals. 312 * 313 * @bp: driver handle 314 * @unload_mode: COMMON, PORT, FUNCTION 315 * 316 * - Cleanup MAC configuration. 317 * - Closes clients. 318 * - etc. 319 */ 320 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode); 321 322 /** 323 * bnx2x_acquire_hw_lock - acquire HW lock. 324 * 325 * @bp: driver handle 326 * @resource: resource bit which was locked 327 */ 328 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); 329 330 /** 331 * bnx2x_release_hw_lock - release HW lock. 332 * 333 * @bp: driver handle 334 * @resource: resource bit which was locked 335 */ 336 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); 337 338 /** 339 * bnx2x_release_leader_lock - release recovery leader lock 340 * 341 * @bp: driver handle 342 */ 343 int bnx2x_release_leader_lock(struct bnx2x *bp); 344 345 /** 346 * bnx2x_set_eth_mac - configure eth MAC address in the HW 347 * 348 * @bp: driver handle 349 * @set: set or clear 350 * 351 * Configures according to the value in netdev->dev_addr. 352 */ 353 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); 354 355 /** 356 * bnx2x_set_rx_mode - set MAC filtering configurations. 357 * 358 * @dev: netdevice 359 * 360 * called with netif_tx_lock from dev_mcast.c 361 * If bp->state is OPEN, should be called with 362 * netif_addr_lock_bh() 363 */ 364 void bnx2x_set_rx_mode(struct net_device *dev); 365 366 /** 367 * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW. 368 * 369 * @bp: driver handle 370 * 371 * If bp->state is OPEN, should be called with 372 * netif_addr_lock_bh(). 373 */ 374 void bnx2x_set_storm_rx_mode(struct bnx2x *bp); 375 376 /** 377 * bnx2x_set_q_rx_mode - configures rx_mode for a single queue. 378 * 379 * @bp: driver handle 380 * @cl_id: client id 381 * @rx_mode_flags: rx mode configuration 382 * @rx_accept_flags: rx accept configuration 383 * @tx_accept_flags: tx accept configuration (tx switch) 384 * @ramrod_flags: ramrod configuration 385 */ 386 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 387 unsigned long rx_mode_flags, 388 unsigned long rx_accept_flags, 389 unsigned long tx_accept_flags, 390 unsigned long ramrod_flags); 391 392 /* Parity errors related */ 393 void bnx2x_set_pf_load(struct bnx2x *bp); 394 bool bnx2x_clear_pf_load(struct bnx2x *bp); 395 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print); 396 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine); 397 void bnx2x_set_reset_in_progress(struct bnx2x *bp); 398 void bnx2x_set_reset_global(struct bnx2x *bp); 399 void bnx2x_disable_close_the_gate(struct bnx2x *bp); 400 401 /** 402 * bnx2x_sp_event - handle ramrods completion. 403 * 404 * @fp: fastpath handle for the event 405 * @rr_cqe: eth_rx_cqe 406 */ 407 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); 408 409 /** 410 * bnx2x_ilt_set_info - prepare ILT configurations. 411 * 412 * @bp: driver handle 413 */ 414 void bnx2x_ilt_set_info(struct bnx2x *bp); 415 416 /** 417 * bnx2x_dcbx_init - initialize dcbx protocol. 418 * 419 * @bp: driver handle 420 */ 421 void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem); 422 423 /** 424 * bnx2x_set_power_state - set power state to the requested value. 425 * 426 * @bp: driver handle 427 * @state: required state D0 or D3hot 428 * 429 * Currently only D0 and D3hot are supported. 430 */ 431 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); 432 433 /** 434 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. 435 * 436 * @bp: driver handle 437 * @value: new value 438 */ 439 void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); 440 /* Error handling */ 441 void bnx2x_panic_dump(struct bnx2x *bp); 442 443 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); 444 445 /* validate currect fw is loaded */ 446 bool bnx2x_test_firmware_version(struct bnx2x *bp, bool is_err); 447 448 /* dev_close main block */ 449 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode); 450 451 /* dev_open main block */ 452 int bnx2x_nic_load(struct bnx2x *bp, int load_mode); 453 454 /* hard_xmit callback */ 455 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); 456 457 /* setup_tc callback */ 458 int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); 459 460 /* select_queue callback */ 461 u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); 462 463 /* reload helper */ 464 int bnx2x_reload_if_running(struct net_device *dev); 465 466 int bnx2x_change_mac_addr(struct net_device *dev, void *p); 467 468 /* NAPI poll Rx part */ 469 int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget); 470 471 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, 472 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod); 473 474 /* NAPI poll Tx part */ 475 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata); 476 477 /* suspend/resume callbacks */ 478 int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); 479 int bnx2x_resume(struct pci_dev *pdev); 480 481 /* Release IRQ vectors */ 482 void bnx2x_free_irq(struct bnx2x *bp); 483 484 void bnx2x_free_fp_mem(struct bnx2x *bp); 485 int bnx2x_alloc_fp_mem(struct bnx2x *bp); 486 void bnx2x_init_rx_rings(struct bnx2x *bp); 487 void bnx2x_free_skbs(struct bnx2x *bp); 488 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); 489 void bnx2x_netif_start(struct bnx2x *bp); 490 491 /** 492 * bnx2x_enable_msix - set msix configuration. 493 * 494 * @bp: driver handle 495 * 496 * fills msix_table, requests vectors, updates num_queues 497 * according to number of available vectors. 498 */ 499 int bnx2x_enable_msix(struct bnx2x *bp); 500 501 /** 502 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly 503 * 504 * @bp: driver handle 505 */ 506 int bnx2x_enable_msi(struct bnx2x *bp); 507 508 /** 509 * bnx2x_poll - NAPI callback 510 * 511 * @napi: napi structure 512 * @budget: 513 * 514 */ 515 int bnx2x_poll(struct napi_struct *napi, int budget); 516 517 /** 518 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure 519 * 520 * @bp: driver handle 521 */ 522 int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp); 523 524 /** 525 * bnx2x_free_mem_bp - release memories outsize main driver structure 526 * 527 * @bp: driver handle 528 */ 529 void bnx2x_free_mem_bp(struct bnx2x *bp); 530 531 /** 532 * bnx2x_change_mtu - change mtu netdev callback 533 * 534 * @dev: net device 535 * @new_mtu: requested mtu 536 * 537 */ 538 int bnx2x_change_mtu(struct net_device *dev, int new_mtu); 539 540 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) 541 /** 542 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port 543 * 544 * @dev: net_device 545 * @wwn: output buffer 546 * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port) 547 * 548 */ 549 int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type); 550 #endif 551 552 netdev_features_t bnx2x_fix_features(struct net_device *dev, 553 netdev_features_t features); 554 int bnx2x_set_features(struct net_device *dev, netdev_features_t features); 555 556 /** 557 * bnx2x_tx_timeout - tx timeout netdev callback 558 * 559 * @dev: net device 560 */ 561 void bnx2x_tx_timeout(struct net_device *dev); 562 563 /*********************** Inlines **********************************/ 564 /*********************** Fast path ********************************/ 565 static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) 566 { 567 barrier(); /* status block is written to by the chip */ 568 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 569 } 570 571 static inline void bnx2x_update_rx_prod_gen(struct bnx2x *bp, 572 struct bnx2x_fastpath *fp, u16 bd_prod, 573 u16 rx_comp_prod, u16 rx_sge_prod, u32 start) 574 { 575 struct ustorm_eth_rx_producers rx_prods = {0}; 576 u32 i; 577 578 /* Update producers */ 579 rx_prods.bd_prod = bd_prod; 580 rx_prods.cqe_prod = rx_comp_prod; 581 rx_prods.sge_prod = rx_sge_prod; 582 583 /* 584 * Make sure that the BD and SGE data is updated before updating the 585 * producers since FW might read the BD/SGE right after the producer 586 * is updated. 587 * This is only applicable for weak-ordered memory model archs such 588 * as IA-64. The following barrier is also mandatory since FW will 589 * assumes BDs must have buffers. 590 */ 591 wmb(); 592 593 for (i = 0; i < sizeof(rx_prods)/4; i++) 594 REG_WR(bp, start + i*4, ((u32 *)&rx_prods)[i]); 595 596 mmiowb(); /* keep prod updates ordered */ 597 598 DP(NETIF_MSG_RX_STATUS, 599 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", 600 fp->index, bd_prod, rx_comp_prod, rx_sge_prod); 601 } 602 603 static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, 604 u8 segment, u16 index, u8 op, 605 u8 update, u32 igu_addr) 606 { 607 struct igu_regular cmd_data = {0}; 608 609 cmd_data.sb_id_and_flags = 610 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 611 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 612 (update << IGU_REGULAR_BUPDATE_SHIFT) | 613 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 614 615 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", 616 cmd_data.sb_id_and_flags, igu_addr); 617 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); 618 619 /* Make sure that ACK is written */ 620 mmiowb(); 621 barrier(); 622 } 623 624 static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, 625 u8 storm, u16 index, u8 op, u8 update) 626 { 627 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 628 COMMAND_REG_INT_ACK); 629 struct igu_ack_register igu_ack; 630 631 igu_ack.status_block_index = index; 632 igu_ack.sb_id_and_flags = 633 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 634 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 635 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 636 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 637 638 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); 639 640 /* Make sure that ACK is written */ 641 mmiowb(); 642 barrier(); 643 } 644 645 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, 646 u16 index, u8 op, u8 update) 647 { 648 if (bp->common.int_block == INT_BLOCK_HC) 649 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); 650 else { 651 u8 segment; 652 653 if (CHIP_INT_MODE_IS_BC(bp)) 654 segment = storm; 655 else if (igu_sb_id != bp->igu_dsb_id) 656 segment = IGU_SEG_ACCESS_DEF; 657 else if (storm == ATTENTION_ID) 658 segment = IGU_SEG_ACCESS_ATTN; 659 else 660 segment = IGU_SEG_ACCESS_DEF; 661 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); 662 } 663 } 664 665 static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) 666 { 667 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 668 COMMAND_REG_SIMD_MASK); 669 u32 result = REG_RD(bp, hc_addr); 670 671 barrier(); 672 return result; 673 } 674 675 static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) 676 { 677 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 678 u32 result = REG_RD(bp, igu_addr); 679 680 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", 681 result, igu_addr); 682 683 barrier(); 684 return result; 685 } 686 687 static inline u16 bnx2x_ack_int(struct bnx2x *bp) 688 { 689 barrier(); 690 if (bp->common.int_block == INT_BLOCK_HC) 691 return bnx2x_hc_ack_int(bp); 692 else 693 return bnx2x_igu_ack_int(bp); 694 } 695 696 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata) 697 { 698 /* Tell compiler that consumer and producer can change */ 699 barrier(); 700 return txdata->tx_pkt_prod != txdata->tx_pkt_cons; 701 } 702 703 static inline u16 bnx2x_tx_avail(struct bnx2x *bp, 704 struct bnx2x_fp_txdata *txdata) 705 { 706 s16 used; 707 u16 prod; 708 u16 cons; 709 710 prod = txdata->tx_bd_prod; 711 cons = txdata->tx_bd_cons; 712 713 used = SUB_S16(prod, cons); 714 715 #ifdef BNX2X_STOP_ON_ERROR 716 WARN_ON(used < 0); 717 WARN_ON(used > txdata->tx_ring_size); 718 WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL); 719 #endif 720 721 return (s16)(txdata->tx_ring_size) - used; 722 } 723 724 static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata) 725 { 726 u16 hw_cons; 727 728 /* Tell compiler that status block fields can change */ 729 barrier(); 730 hw_cons = le16_to_cpu(*txdata->tx_cons_sb); 731 return hw_cons != txdata->tx_pkt_cons; 732 } 733 734 static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp) 735 { 736 u8 cos; 737 for_each_cos_in_tx_queue(fp, cos) 738 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) 739 return true; 740 return false; 741 } 742 743 static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) 744 { 745 u16 rx_cons_sb; 746 747 /* Tell compiler that status block fields can change */ 748 barrier(); 749 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); 750 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) 751 rx_cons_sb++; 752 return (fp->rx_comp_cons != rx_cons_sb); 753 } 754 755 /** 756 * bnx2x_tx_disable - disables tx from stack point of view 757 * 758 * @bp: driver handle 759 */ 760 static inline void bnx2x_tx_disable(struct bnx2x *bp) 761 { 762 netif_tx_disable(bp->dev); 763 netif_carrier_off(bp->dev); 764 } 765 766 static inline void bnx2x_free_rx_sge(struct bnx2x *bp, 767 struct bnx2x_fastpath *fp, u16 index) 768 { 769 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; 770 struct page *page = sw_buf->page; 771 struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; 772 773 /* Skip "next page" elements */ 774 if (!page) 775 return; 776 777 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), 778 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE); 779 __free_pages(page, PAGES_PER_SGE_SHIFT); 780 781 sw_buf->page = NULL; 782 sge->addr_hi = 0; 783 sge->addr_lo = 0; 784 } 785 786 static inline void bnx2x_add_all_napi(struct bnx2x *bp) 787 { 788 int i; 789 790 bp->num_napi_queues = bp->num_queues; 791 792 /* Add NAPI objects */ 793 for_each_rx_queue(bp, i) 794 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), 795 bnx2x_poll, BNX2X_NAPI_WEIGHT); 796 } 797 798 static inline void bnx2x_del_all_napi(struct bnx2x *bp) 799 { 800 int i; 801 802 for_each_rx_queue(bp, i) 803 netif_napi_del(&bnx2x_fp(bp, i, napi)); 804 } 805 806 void bnx2x_set_int_mode(struct bnx2x *bp); 807 808 static inline void bnx2x_disable_msi(struct bnx2x *bp) 809 { 810 if (bp->flags & USING_MSIX_FLAG) { 811 pci_disable_msix(bp->pdev); 812 bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG); 813 } else if (bp->flags & USING_MSI_FLAG) { 814 pci_disable_msi(bp->pdev); 815 bp->flags &= ~USING_MSI_FLAG; 816 } 817 } 818 819 static inline int bnx2x_calc_num_queues(struct bnx2x *bp) 820 { 821 return num_queues ? 822 min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) : 823 min_t(int, netif_get_num_default_rss_queues(), 824 BNX2X_MAX_QUEUES(bp)); 825 } 826 827 static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) 828 { 829 int i, j; 830 831 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { 832 int idx = RX_SGE_CNT * i - 1; 833 834 for (j = 0; j < 2; j++) { 835 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); 836 idx--; 837 } 838 } 839 } 840 841 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) 842 { 843 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ 844 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); 845 846 /* Clear the two last indices in the page to 1: 847 these are the indices that correspond to the "next" element, 848 hence will never be indicated and should be removed from 849 the calculations. */ 850 bnx2x_clear_sge_mask_next_elems(fp); 851 } 852 853 /* note that we are not allocating a new buffer, 854 * we are just moving one from cons to prod 855 * we are not creating a new mapping, 856 * so there is no need to check for dma_mapping_error(). 857 */ 858 static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp, 859 u16 cons, u16 prod) 860 { 861 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; 862 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; 863 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; 864 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; 865 866 dma_unmap_addr_set(prod_rx_buf, mapping, 867 dma_unmap_addr(cons_rx_buf, mapping)); 868 prod_rx_buf->data = cons_rx_buf->data; 869 *prod_bd = *cons_bd; 870 } 871 872 /************************* Init ******************************************/ 873 874 /* returns func by VN for current port */ 875 static inline int func_by_vn(struct bnx2x *bp, int vn) 876 { 877 return 2 * vn + BP_PORT(bp); 878 } 879 880 static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash) 881 { 882 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, config_hash); 883 } 884 885 /** 886 * bnx2x_func_start - init function 887 * 888 * @bp: driver handle 889 * 890 * Must be called before sending CLIENT_SETUP for the first client. 891 */ 892 static inline int bnx2x_func_start(struct bnx2x *bp) 893 { 894 struct bnx2x_func_state_params func_params = {NULL}; 895 struct bnx2x_func_start_params *start_params = 896 &func_params.params.start; 897 898 /* Prepare parameters for function state transitions */ 899 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 900 901 func_params.f_obj = &bp->func_obj; 902 func_params.cmd = BNX2X_F_CMD_START; 903 904 /* Function parameters */ 905 start_params->mf_mode = bp->mf_mode; 906 start_params->sd_vlan_tag = bp->mf_ov; 907 908 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) 909 start_params->network_cos_mode = STATIC_COS; 910 else /* CHIP_IS_E1X */ 911 start_params->network_cos_mode = FW_WRR; 912 913 return bnx2x_func_state_change(bp, &func_params); 914 } 915 916 917 /** 918 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format 919 * 920 * @fw_hi: pointer to upper part 921 * @fw_mid: pointer to middle part 922 * @fw_lo: pointer to lower part 923 * @mac: pointer to MAC address 924 */ 925 static inline void bnx2x_set_fw_mac_addr(u16 *fw_hi, u16 *fw_mid, u16 *fw_lo, 926 u8 *mac) 927 { 928 ((u8 *)fw_hi)[0] = mac[1]; 929 ((u8 *)fw_hi)[1] = mac[0]; 930 ((u8 *)fw_mid)[0] = mac[3]; 931 ((u8 *)fw_mid)[1] = mac[2]; 932 ((u8 *)fw_lo)[0] = mac[5]; 933 ((u8 *)fw_lo)[1] = mac[4]; 934 } 935 936 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, 937 struct bnx2x_fastpath *fp, int last) 938 { 939 int i; 940 941 if (fp->disable_tpa) 942 return; 943 944 for (i = 0; i < last; i++) 945 bnx2x_free_rx_sge(bp, fp, i); 946 } 947 948 static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) 949 { 950 int i; 951 952 for (i = 1; i <= NUM_RX_RINGS; i++) { 953 struct eth_rx_bd *rx_bd; 954 955 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; 956 rx_bd->addr_hi = 957 cpu_to_le32(U64_HI(fp->rx_desc_mapping + 958 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 959 rx_bd->addr_lo = 960 cpu_to_le32(U64_LO(fp->rx_desc_mapping + 961 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 962 } 963 } 964 965 /* Statistics ID are global per chip/path, while Client IDs for E1x are per 966 * port. 967 */ 968 static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) 969 { 970 struct bnx2x *bp = fp->bp; 971 if (!CHIP_IS_E1x(bp)) { 972 #ifdef BCM_CNIC 973 /* there are special statistics counters for FCoE 136..140 */ 974 if (IS_FCOE_FP(fp)) 975 return bp->cnic_base_cl_id + (bp->pf_num >> 1); 976 #endif 977 return fp->cl_id; 978 } 979 return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x; 980 } 981 982 static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, 983 bnx2x_obj_type obj_type) 984 { 985 struct bnx2x *bp = fp->bp; 986 987 /* Configure classification DBs */ 988 bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id, 989 fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), 990 bnx2x_sp_mapping(bp, mac_rdata), 991 BNX2X_FILTER_MAC_PENDING, 992 &bp->sp_state, obj_type, 993 &bp->macs_pool); 994 } 995 996 /** 997 * bnx2x_get_path_func_num - get number of active functions 998 * 999 * @bp: driver handle 1000 * 1001 * Calculates the number of active (not hidden) functions on the 1002 * current path. 1003 */ 1004 static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) 1005 { 1006 u8 func_num = 0, i; 1007 1008 /* 57710 has only one function per-port */ 1009 if (CHIP_IS_E1(bp)) 1010 return 1; 1011 1012 /* Calculate a number of functions enabled on the current 1013 * PATH/PORT. 1014 */ 1015 if (CHIP_REV_IS_SLOW(bp)) { 1016 if (IS_MF(bp)) 1017 func_num = 4; 1018 else 1019 func_num = 2; 1020 } else { 1021 for (i = 0; i < E1H_FUNC_MAX / 2; i++) { 1022 u32 func_config = 1023 MF_CFG_RD(bp, 1024 func_mf_config[BP_PORT(bp) + 2 * i]. 1025 config); 1026 func_num += 1027 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); 1028 } 1029 } 1030 1031 WARN_ON(!func_num); 1032 1033 return func_num; 1034 } 1035 1036 static inline void bnx2x_init_bp_objs(struct bnx2x *bp) 1037 { 1038 /* RX_MODE controlling object */ 1039 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); 1040 1041 /* multicast configuration controlling object */ 1042 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, 1043 BP_FUNC(bp), BP_FUNC(bp), 1044 bnx2x_sp(bp, mcast_rdata), 1045 bnx2x_sp_mapping(bp, mcast_rdata), 1046 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, 1047 BNX2X_OBJ_TYPE_RX); 1048 1049 /* Setup CAM credit pools */ 1050 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), 1051 bnx2x_get_path_func_num(bp)); 1052 1053 /* RSS configuration object */ 1054 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, 1055 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), 1056 bnx2x_sp(bp, rss_rdata), 1057 bnx2x_sp_mapping(bp, rss_rdata), 1058 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, 1059 BNX2X_OBJ_TYPE_RX); 1060 } 1061 1062 static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) 1063 { 1064 if (CHIP_IS_E1x(fp->bp)) 1065 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; 1066 else 1067 return fp->cl_id; 1068 } 1069 1070 static inline u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) 1071 { 1072 struct bnx2x *bp = fp->bp; 1073 1074 if (!CHIP_IS_E1x(bp)) 1075 return USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); 1076 else 1077 return USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); 1078 } 1079 1080 static inline void bnx2x_init_txdata(struct bnx2x *bp, 1081 struct bnx2x_fp_txdata *txdata, u32 cid, 1082 int txq_index, __le16 *tx_cons_sb, 1083 struct bnx2x_fastpath *fp) 1084 { 1085 txdata->cid = cid; 1086 txdata->txq_index = txq_index; 1087 txdata->tx_cons_sb = tx_cons_sb; 1088 txdata->parent_fp = fp; 1089 txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size; 1090 1091 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n", 1092 txdata->cid, txdata->txq_index); 1093 } 1094 1095 #ifdef BCM_CNIC 1096 static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) 1097 { 1098 return bp->cnic_base_cl_id + cl_idx + 1099 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; 1100 } 1101 1102 static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) 1103 { 1104 1105 /* the 'first' id is allocated for the cnic */ 1106 return bp->base_fw_ndsb; 1107 } 1108 1109 static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) 1110 { 1111 return bp->igu_base_sb; 1112 } 1113 1114 1115 static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp) 1116 { 1117 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 1118 unsigned long q_type = 0; 1119 1120 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); 1121 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, 1122 BNX2X_FCOE_ETH_CL_ID_IDX); 1123 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); 1124 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; 1125 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; 1126 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; 1127 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), 1128 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, 1129 fp); 1130 1131 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); 1132 1133 /* qZone id equals to FW (per path) client id */ 1134 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); 1135 /* init shortcut */ 1136 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = 1137 bnx2x_rx_ustorm_prods_offset(fp); 1138 1139 /* Configure Queue State object */ 1140 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 1141 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 1142 1143 /* No multi-CoS for FCoE L2 client */ 1144 BUG_ON(fp->max_cos != 1); 1145 1146 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, 1147 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 1148 bnx2x_sp_mapping(bp, q_rdata), q_type); 1149 1150 DP(NETIF_MSG_IFUP, 1151 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", 1152 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 1153 fp->igu_sb_id); 1154 } 1155 #endif 1156 1157 static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, 1158 struct bnx2x_fp_txdata *txdata) 1159 { 1160 int cnt = 1000; 1161 1162 while (bnx2x_has_tx_work_unload(txdata)) { 1163 if (!cnt) { 1164 BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", 1165 txdata->txq_index, txdata->tx_pkt_prod, 1166 txdata->tx_pkt_cons); 1167 #ifdef BNX2X_STOP_ON_ERROR 1168 bnx2x_panic(); 1169 return -EBUSY; 1170 #else 1171 break; 1172 #endif 1173 } 1174 cnt--; 1175 usleep_range(1000, 1000); 1176 } 1177 1178 return 0; 1179 } 1180 1181 int bnx2x_get_link_cfg_idx(struct bnx2x *bp); 1182 1183 static inline void __storm_memset_struct(struct bnx2x *bp, 1184 u32 addr, size_t size, u32 *data) 1185 { 1186 int i; 1187 for (i = 0; i < size/4; i++) 1188 REG_WR(bp, addr + (i * 4), data[i]); 1189 } 1190 1191 /** 1192 * bnx2x_wait_sp_comp - wait for the outstanding SP commands. 1193 * 1194 * @bp: driver handle 1195 * @mask: bits that need to be cleared 1196 */ 1197 static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) 1198 { 1199 int tout = 5000; /* Wait for 5 secs tops */ 1200 1201 while (tout--) { 1202 smp_mb(); 1203 netif_addr_lock_bh(bp->dev); 1204 if (!(bp->sp_state & mask)) { 1205 netif_addr_unlock_bh(bp->dev); 1206 return true; 1207 } 1208 netif_addr_unlock_bh(bp->dev); 1209 1210 usleep_range(1000, 1000); 1211 } 1212 1213 smp_mb(); 1214 1215 netif_addr_lock_bh(bp->dev); 1216 if (bp->sp_state & mask) { 1217 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n", 1218 bp->sp_state, mask); 1219 netif_addr_unlock_bh(bp->dev); 1220 return false; 1221 } 1222 netif_addr_unlock_bh(bp->dev); 1223 1224 return true; 1225 } 1226 1227 /** 1228 * bnx2x_set_ctx_validation - set CDU context validation values 1229 * 1230 * @bp: driver handle 1231 * @cxt: context of the connection on the host memory 1232 * @cid: SW CID of the connection to be configured 1233 */ 1234 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, 1235 u32 cid); 1236 1237 void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, 1238 u8 sb_index, u8 disable, u16 usec); 1239 void bnx2x_acquire_phy_lock(struct bnx2x *bp); 1240 void bnx2x_release_phy_lock(struct bnx2x *bp); 1241 1242 /** 1243 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. 1244 * 1245 * @bp: driver handle 1246 * @mf_cfg: MF configuration 1247 * 1248 */ 1249 static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) 1250 { 1251 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> 1252 FUNC_MF_CFG_MAX_BW_SHIFT; 1253 if (!max_cfg) { 1254 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL, 1255 "Max BW configured to 0 - using 100 instead\n"); 1256 max_cfg = 100; 1257 } 1258 return max_cfg; 1259 } 1260 1261 /* checks if HW supports GRO for given MTU */ 1262 static inline bool bnx2x_mtu_allows_gro(int mtu) 1263 { 1264 /* gro frags per page */ 1265 int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE); 1266 1267 /* 1268 * 1. number of frags should not grow above MAX_SKB_FRAGS 1269 * 2. frag must fit the page 1270 */ 1271 return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS; 1272 } 1273 #ifdef BCM_CNIC 1274 /** 1275 * bnx2x_get_iscsi_info - update iSCSI params according to licensing info. 1276 * 1277 * @bp: driver handle 1278 * 1279 */ 1280 void bnx2x_get_iscsi_info(struct bnx2x *bp); 1281 #endif 1282 1283 /** 1284 * bnx2x_link_sync_notify - send notification to other functions. 1285 * 1286 * @bp: driver handle 1287 * 1288 */ 1289 static inline void bnx2x_link_sync_notify(struct bnx2x *bp) 1290 { 1291 int func; 1292 int vn; 1293 1294 /* Set the attention towards other drivers on the same port */ 1295 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 1296 if (vn == BP_VN(bp)) 1297 continue; 1298 1299 func = func_by_vn(bp, vn); 1300 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + 1301 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); 1302 } 1303 } 1304 1305 /** 1306 * bnx2x_update_drv_flags - update flags in shmem 1307 * 1308 * @bp: driver handle 1309 * @flags: flags to update 1310 * @set: set or clear 1311 * 1312 */ 1313 static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set) 1314 { 1315 if (SHMEM2_HAS(bp, drv_flags)) { 1316 u32 drv_flags; 1317 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); 1318 drv_flags = SHMEM2_RD(bp, drv_flags); 1319 1320 if (set) 1321 SET_FLAGS(drv_flags, flags); 1322 else 1323 RESET_FLAGS(drv_flags, flags); 1324 1325 SHMEM2_WR(bp, drv_flags, drv_flags); 1326 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags); 1327 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); 1328 } 1329 } 1330 1331 static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr) 1332 { 1333 if (is_valid_ether_addr(addr)) 1334 return true; 1335 #ifdef BCM_CNIC 1336 if (is_zero_ether_addr(addr) && 1337 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) 1338 return true; 1339 #endif 1340 return false; 1341 } 1342 1343 #endif /* BNX2X_CMN_H */ 1344