1 /* bnx2x.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 */ 13 14 #ifndef BNX2X_H 15 #define BNX2X_H 16 17 #include <linux/pci.h> 18 #include <linux/netdevice.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/types.h> 21 #include <linux/pci_regs.h> 22 23 #include <linux/ptp_clock_kernel.h> 24 #include <linux/net_tstamp.h> 25 #include <linux/timecounter.h> 26 27 /* compilation time flags */ 28 29 /* define this to make the driver freeze on error to allow getting debug info 30 * (you will need to reboot afterwards) */ 31 /* #define BNX2X_STOP_ON_ERROR */ 32 33 #define DRV_MODULE_VERSION "1.710.51-0" 34 #define DRV_MODULE_RELDATE "2014/02/10" 35 #define BNX2X_BC_VER 0x040200 36 37 #if defined(CONFIG_DCB) 38 #define BCM_DCBNL 39 #endif 40 41 #include "bnx2x_hsi.h" 42 43 #include "../cnic_if.h" 44 45 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt) 46 47 #include <linux/mdio.h> 48 49 #include "bnx2x_reg.h" 50 #include "bnx2x_fw_defs.h" 51 #include "bnx2x_mfw_req.h" 52 #include "bnx2x_link.h" 53 #include "bnx2x_sp.h" 54 #include "bnx2x_dcb.h" 55 #include "bnx2x_stats.h" 56 #include "bnx2x_vfpf.h" 57 58 enum bnx2x_int_mode { 59 BNX2X_INT_MODE_MSIX, 60 BNX2X_INT_MODE_INTX, 61 BNX2X_INT_MODE_MSI 62 }; 63 64 /* error/debug prints */ 65 66 #define DRV_MODULE_NAME "bnx2x" 67 68 /* for messages that are currently off */ 69 #define BNX2X_MSG_OFF 0x0 70 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ 71 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ 72 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ 73 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ 74 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ 75 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ 76 #define BNX2X_MSG_IOV 0x0800000 77 #define BNX2X_MSG_PTP 0x1000000 78 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ 79 #define BNX2X_MSG_ETHTOOL 0x4000000 80 #define BNX2X_MSG_DCB 0x8000000 81 82 /* regular debug print */ 83 #define DP_INNER(fmt, ...) \ 84 pr_notice("[%s:%d(%s)]" fmt, \ 85 __func__, __LINE__, \ 86 bp->dev ? (bp->dev->name) : "?", \ 87 ##__VA_ARGS__); 88 89 #define DP(__mask, fmt, ...) \ 90 do { \ 91 if (unlikely(bp->msg_enable & (__mask))) \ 92 DP_INNER(fmt, ##__VA_ARGS__); \ 93 } while (0) 94 95 #define DP_AND(__mask, fmt, ...) \ 96 do { \ 97 if (unlikely((bp->msg_enable & (__mask)) == __mask)) \ 98 DP_INNER(fmt, ##__VA_ARGS__); \ 99 } while (0) 100 101 #define DP_CONT(__mask, fmt, ...) \ 102 do { \ 103 if (unlikely(bp->msg_enable & (__mask))) \ 104 pr_cont(fmt, ##__VA_ARGS__); \ 105 } while (0) 106 107 /* errors debug print */ 108 #define BNX2X_DBG_ERR(fmt, ...) \ 109 do { \ 110 if (unlikely(netif_msg_probe(bp))) \ 111 pr_err("[%s:%d(%s)]" fmt, \ 112 __func__, __LINE__, \ 113 bp->dev ? (bp->dev->name) : "?", \ 114 ##__VA_ARGS__); \ 115 } while (0) 116 117 /* for errors (never masked) */ 118 #define BNX2X_ERR(fmt, ...) \ 119 do { \ 120 pr_err("[%s:%d(%s)]" fmt, \ 121 __func__, __LINE__, \ 122 bp->dev ? (bp->dev->name) : "?", \ 123 ##__VA_ARGS__); \ 124 } while (0) 125 126 #define BNX2X_ERROR(fmt, ...) \ 127 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 128 129 /* before we have a dev->name use dev_info() */ 130 #define BNX2X_DEV_INFO(fmt, ...) \ 131 do { \ 132 if (unlikely(netif_msg_probe(bp))) \ 133 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 134 } while (0) 135 136 /* Error handling */ 137 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int); 138 #ifdef BNX2X_STOP_ON_ERROR 139 #define bnx2x_panic() \ 140 do { \ 141 bp->panic = 1; \ 142 BNX2X_ERR("driver assert\n"); \ 143 bnx2x_panic_dump(bp, true); \ 144 } while (0) 145 #else 146 #define bnx2x_panic() \ 147 do { \ 148 bp->panic = 1; \ 149 BNX2X_ERR("driver assert\n"); \ 150 bnx2x_panic_dump(bp, false); \ 151 } while (0) 152 #endif 153 154 #define bnx2x_mc_addr(ha) ((ha)->addr) 155 #define bnx2x_uc_addr(ha) ((ha)->addr) 156 157 #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff)) 158 #define U64_HI(x) ((u32)(((u64)(x)) >> 32)) 159 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 160 161 #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 162 163 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 164 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 165 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 166 167 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 168 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 169 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 170 171 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 172 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 173 174 #define REG_RD_DMAE(bp, offset, valp, len32) \ 175 do { \ 176 bnx2x_read_dmae(bp, offset, len32);\ 177 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 178 } while (0) 179 180 #define REG_WR_DMAE(bp, offset, valp, len32) \ 181 do { \ 182 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 183 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 184 offset, len32); \ 185 } while (0) 186 187 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 188 REG_WR_DMAE(bp, offset, valp, len32) 189 190 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 191 do { \ 192 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 193 bnx2x_write_big_buf_wb(bp, addr, len32); \ 194 } while (0) 195 196 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 197 offsetof(struct shmem_region, field)) 198 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 199 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 200 201 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 202 offsetof(struct shmem2_region, field)) 203 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 204 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 205 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 206 offsetof(struct mf_cfg, field)) 207 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 208 offsetof(struct mf2_cfg, field)) 209 210 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 211 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 212 MF_CFG_ADDR(bp, field), (val)) 213 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 214 215 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 216 (SHMEM2_RD((bp), size) > \ 217 offsetof(struct shmem2_region, field))) 218 219 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 220 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 221 222 /* SP SB indices */ 223 224 /* General SP events - stats query, cfc delete, etc */ 225 #define HC_SP_INDEX_ETH_DEF_CONS 3 226 227 /* EQ completions */ 228 #define HC_SP_INDEX_EQ_CONS 7 229 230 /* FCoE L2 connection completions */ 231 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 232 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 233 /* iSCSI L2 */ 234 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 235 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 236 237 /* Special clients parameters */ 238 239 /* SB indices */ 240 /* FCoE L2 */ 241 #define BNX2X_FCOE_L2_RX_INDEX \ 242 (&bp->def_status_blk->sp_sb.\ 243 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 244 245 #define BNX2X_FCOE_L2_TX_INDEX \ 246 (&bp->def_status_blk->sp_sb.\ 247 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 248 249 /** 250 * CIDs and CLIDs: 251 * CLIDs below is a CLID for func 0, then the CLID for other 252 * functions will be calculated by the formula: 253 * 254 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 255 * 256 */ 257 enum { 258 BNX2X_ISCSI_ETH_CL_ID_IDX, 259 BNX2X_FCOE_ETH_CL_ID_IDX, 260 BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 261 }; 262 263 /* use a value high enough to be above all the PFs, which has least significant 264 * nibble as 8, so when cnic needs to come up with a CID for UIO to use to 265 * calculate doorbell address according to old doorbell configuration scheme 266 * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number 267 * We must avoid coming up with cid 8 for iscsi since according to this method 268 * the designated UIO cid will come out 0 and it has a special handling for that 269 * case which doesn't suit us. Therefore will will cieling to closes cid which 270 * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18. 271 */ 272 273 #define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \ 274 (bp)->max_cos) 275 /* amount of cids traversed by UIO's DPM addition to doorbell */ 276 #define UIO_DPM 8 277 /* roundup to DPM offset */ 278 #define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \ 279 UIO_DPM)) 280 /* offset to nearest value which has lsb nibble matching DPM */ 281 #define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \ 282 (UIO_DPM * 2)) 283 /* add offset to rounded-up cid to get a value which could be used with UIO */ 284 #define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp)) 285 /* but wait - avoid UIO special case for cid 0 */ 286 #define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \ 287 (UIO_DPM_ALIGN(bp) == UIO_DPM)) 288 /* Properly DPM aligned CID dajusted to cid 0 secal case */ 289 #define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \ 290 (UIO_DPM_CID0_OFFSET(bp))) 291 /* how many cids were wasted - need this value for cid allocation */ 292 #define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \ 293 BNX2X_1st_NON_L2_ETH_CID(bp)) 294 /* iSCSI L2 */ 295 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) 296 /* FCoE L2 */ 297 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) 298 299 #define CNIC_SUPPORT(bp) ((bp)->cnic_support) 300 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled) 301 #define CNIC_LOADED(bp) ((bp)->cnic_loaded) 302 #define FCOE_INIT(bp) ((bp)->fcoe_init) 303 304 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 305 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 306 307 #define SM_RX_ID 0 308 #define SM_TX_ID 1 309 310 /* defines for multiple tx priority indices */ 311 #define FIRST_TX_ONLY_COS_INDEX 1 312 #define FIRST_TX_COS_INDEX 0 313 314 /* rules for calculating the cids of tx-only connections */ 315 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) 316 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ 317 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 318 319 /* fp index inside class of service range */ 320 #define FP_COS_TO_TXQ(fp, cos, bp) \ 321 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 322 323 /* Indexes for transmission queues array: 324 * txdata for RSS i CoS j is at location i + (j * num of RSS) 325 * txdata for FCoE (if exist) is at location max cos * num of RSS 326 * txdata for FWD (if exist) is one location after FCoE 327 * txdata for OOO (if exist) is one location after FWD 328 */ 329 enum { 330 FCOE_TXQ_IDX_OFFSET, 331 FWD_TXQ_IDX_OFFSET, 332 OOO_TXQ_IDX_OFFSET, 333 }; 334 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) 335 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) 336 337 /* fast path */ 338 /* 339 * This driver uses new build_skb() API : 340 * RX ring buffer contains pointer to kmalloc() data only, 341 * skb are built only after Hardware filled the frame. 342 */ 343 struct sw_rx_bd { 344 u8 *data; 345 DEFINE_DMA_UNMAP_ADDR(mapping); 346 }; 347 348 struct sw_tx_bd { 349 struct sk_buff *skb; 350 u16 first_bd; 351 u8 flags; 352 /* Set on the first BD descriptor when there is a split BD */ 353 #define BNX2X_TSO_SPLIT_BD (1<<0) 354 #define BNX2X_HAS_SECOND_PBD (1<<1) 355 }; 356 357 struct sw_rx_page { 358 struct page *page; 359 DEFINE_DMA_UNMAP_ADDR(mapping); 360 unsigned int offset; 361 }; 362 363 union db_prod { 364 struct doorbell_set_prod data; 365 u32 raw; 366 }; 367 368 /* dropless fc FW/HW related params */ 369 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 370 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 371 ETH_MAX_AGGREGATION_QUEUES_E1 :\ 372 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 373 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 374 #define FW_PREFETCH_CNT 16 375 #define DROPLESS_FC_HEADROOM 100 376 377 /* MC hsi */ 378 #define BCM_PAGE_SHIFT 12 379 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 380 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 381 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 382 383 #define PAGES_PER_SGE_SHIFT 0 384 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 385 #define SGE_PAGE_SHIFT 12 386 #define SGE_PAGE_SIZE (1 << SGE_PAGE_SHIFT) 387 #define SGE_PAGE_MASK (~(SGE_PAGE_SIZE - 1)) 388 #define SGE_PAGE_ALIGN(addr) (((addr) + SGE_PAGE_SIZE - 1) & SGE_PAGE_MASK) 389 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 390 #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \ 391 SGE_PAGES), 0xffff) 392 393 /* SGE ring related macros */ 394 #define NUM_RX_SGE_PAGES 2 395 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 396 #define NEXT_PAGE_SGE_DESC_CNT 2 397 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 398 /* RX_SGE_CNT is promised to be a power of 2 */ 399 #define RX_SGE_MASK (RX_SGE_CNT - 1) 400 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 401 #define MAX_RX_SGE (NUM_RX_SGE - 1) 402 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 403 (MAX_RX_SGE_CNT - 1)) ? \ 404 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 405 (x) + 1) 406 #define RX_SGE(x) ((x) & MAX_RX_SGE) 407 408 /* 409 * Number of required SGEs is the sum of two: 410 * 1. Number of possible opened aggregations (next packet for 411 * these aggregations will probably consume SGE immediately) 412 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 413 * after placement on BD for new TPA aggregation) 414 * 415 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 416 */ 417 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 418 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 419 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 420 MAX_RX_SGE_CNT) 421 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 422 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 423 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 424 425 /* Manipulate a bit vector defined as an array of u64 */ 426 427 /* Number of bits in one sge_mask array element */ 428 #define BIT_VEC64_ELEM_SZ 64 429 #define BIT_VEC64_ELEM_SHIFT 6 430 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 431 432 #define __BIT_VEC64_SET_BIT(el, bit) \ 433 do { \ 434 el = ((el) | ((u64)0x1 << (bit))); \ 435 } while (0) 436 437 #define __BIT_VEC64_CLEAR_BIT(el, bit) \ 438 do { \ 439 el = ((el) & (~((u64)0x1 << (bit)))); \ 440 } while (0) 441 442 #define BIT_VEC64_SET_BIT(vec64, idx) \ 443 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 444 (idx) & BIT_VEC64_ELEM_MASK) 445 446 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 447 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 448 (idx) & BIT_VEC64_ELEM_MASK) 449 450 #define BIT_VEC64_TEST_BIT(vec64, idx) \ 451 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 452 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 453 454 /* Creates a bitmask of all ones in less significant bits. 455 idx - index of the most significant bit in the created mask */ 456 #define BIT_VEC64_ONES_MASK(idx) \ 457 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 458 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 459 460 /*******************************************************/ 461 462 /* Number of u64 elements in SGE mask array */ 463 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 464 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 465 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 466 467 union host_hc_status_block { 468 /* pointer to fp status block e1x */ 469 struct host_hc_status_block_e1x *e1x_sb; 470 /* pointer to fp status block e2 */ 471 struct host_hc_status_block_e2 *e2_sb; 472 }; 473 474 struct bnx2x_agg_info { 475 /* 476 * First aggregation buffer is a data buffer, the following - are pages. 477 * We will preallocate the data buffer for each aggregation when 478 * we open the interface and will replace the BD at the consumer 479 * with this one when we receive the TPA_START CQE in order to 480 * keep the Rx BD ring consistent. 481 */ 482 struct sw_rx_bd first_buf; 483 u8 tpa_state; 484 #define BNX2X_TPA_START 1 485 #define BNX2X_TPA_STOP 2 486 #define BNX2X_TPA_ERROR 3 487 u8 placement_offset; 488 u16 parsing_flags; 489 u16 vlan_tag; 490 u16 len_on_bd; 491 u32 rxhash; 492 enum pkt_hash_types rxhash_type; 493 u16 gro_size; 494 u16 full_page; 495 }; 496 497 #define Q_STATS_OFFSET32(stat_name) \ 498 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 499 500 struct bnx2x_fp_txdata { 501 502 struct sw_tx_bd *tx_buf_ring; 503 504 union eth_tx_bd_types *tx_desc_ring; 505 dma_addr_t tx_desc_mapping; 506 507 u32 cid; 508 509 union db_prod tx_db; 510 511 u16 tx_pkt_prod; 512 u16 tx_pkt_cons; 513 u16 tx_bd_prod; 514 u16 tx_bd_cons; 515 516 unsigned long tx_pkt; 517 518 __le16 *tx_cons_sb; 519 520 int txq_index; 521 struct bnx2x_fastpath *parent_fp; 522 int tx_ring_size; 523 }; 524 525 enum bnx2x_tpa_mode_t { 526 TPA_MODE_DISABLED, 527 TPA_MODE_LRO, 528 TPA_MODE_GRO 529 }; 530 531 struct bnx2x_alloc_pool { 532 struct page *page; 533 dma_addr_t dma; 534 unsigned int offset; 535 }; 536 537 struct bnx2x_fastpath { 538 struct bnx2x *bp; /* parent */ 539 540 struct napi_struct napi; 541 542 #ifdef CONFIG_NET_RX_BUSY_POLL 543 unsigned long busy_poll_state; 544 #endif 545 546 union host_hc_status_block status_blk; 547 /* chip independent shortcuts into sb structure */ 548 __le16 *sb_index_values; 549 __le16 *sb_running_index; 550 /* chip independent shortcut into rx_prods_offset memory */ 551 u32 ustorm_rx_prods_offset; 552 553 u32 rx_buf_size; 554 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */ 555 dma_addr_t status_blk_mapping; 556 557 enum bnx2x_tpa_mode_t mode; 558 559 u8 max_cos; /* actual number of active tx coses */ 560 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS]; 561 562 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 563 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 564 565 struct eth_rx_bd *rx_desc_ring; 566 dma_addr_t rx_desc_mapping; 567 568 union eth_rx_cqe *rx_comp_ring; 569 dma_addr_t rx_comp_mapping; 570 571 /* SGE ring */ 572 struct eth_rx_sge *rx_sge_ring; 573 dma_addr_t rx_sge_mapping; 574 575 u64 sge_mask[RX_SGE_MASK_LEN]; 576 577 u32 cid; 578 579 __le16 fp_hc_idx; 580 581 u8 index; /* number in fp array */ 582 u8 rx_queue; /* index for skb_record */ 583 u8 cl_id; /* eth client id */ 584 u8 cl_qzone_id; 585 u8 fw_sb_id; /* status block number in FW */ 586 u8 igu_sb_id; /* status block number in HW */ 587 588 u16 rx_bd_prod; 589 u16 rx_bd_cons; 590 u16 rx_comp_prod; 591 u16 rx_comp_cons; 592 u16 rx_sge_prod; 593 /* The last maximal completed SGE */ 594 u16 last_max_sge; 595 __le16 *rx_cons_sb; 596 unsigned long rx_pkt, 597 rx_calls; 598 599 /* TPA related */ 600 struct bnx2x_agg_info *tpa_info; 601 #ifdef BNX2X_STOP_ON_ERROR 602 u64 tpa_queue_used; 603 #endif 604 /* The size is calculated using the following: 605 sizeof name field from netdev structure + 606 4 ('-Xx-' string) + 607 4 (for the digits and to make it DWORD aligned) */ 608 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 609 char name[FP_NAME_SIZE]; 610 611 struct bnx2x_alloc_pool page_pool; 612 }; 613 614 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) 615 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) 616 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) 617 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) 618 619 #ifdef CONFIG_NET_RX_BUSY_POLL 620 621 enum bnx2x_fp_state { 622 BNX2X_STATE_FP_NAPI = BIT(0), /* NAPI handler owns the queue */ 623 624 BNX2X_STATE_FP_NAPI_REQ_BIT = 1, /* NAPI would like to own the queue */ 625 BNX2X_STATE_FP_NAPI_REQ = BIT(1), 626 627 BNX2X_STATE_FP_POLL_BIT = 2, 628 BNX2X_STATE_FP_POLL = BIT(2), /* busy_poll owns the queue */ 629 630 BNX2X_STATE_FP_DISABLE_BIT = 3, /* queue is dismantled */ 631 }; 632 633 static inline void bnx2x_fp_busy_poll_init(struct bnx2x_fastpath *fp) 634 { 635 WRITE_ONCE(fp->busy_poll_state, 0); 636 } 637 638 /* called from the device poll routine to get ownership of a FP */ 639 static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) 640 { 641 unsigned long prev, old = READ_ONCE(fp->busy_poll_state); 642 643 while (1) { 644 switch (old) { 645 case BNX2X_STATE_FP_POLL: 646 /* make sure bnx2x_fp_lock_poll() wont starve us */ 647 set_bit(BNX2X_STATE_FP_NAPI_REQ_BIT, 648 &fp->busy_poll_state); 649 /* fallthrough */ 650 case BNX2X_STATE_FP_POLL | BNX2X_STATE_FP_NAPI_REQ: 651 return false; 652 default: 653 break; 654 } 655 prev = cmpxchg(&fp->busy_poll_state, old, BNX2X_STATE_FP_NAPI); 656 if (unlikely(prev != old)) { 657 old = prev; 658 continue; 659 } 660 return true; 661 } 662 } 663 664 static inline void bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) 665 { 666 smp_wmb(); 667 fp->busy_poll_state = 0; 668 } 669 670 /* called from bnx2x_low_latency_poll() */ 671 static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) 672 { 673 return cmpxchg(&fp->busy_poll_state, 0, BNX2X_STATE_FP_POLL) == 0; 674 } 675 676 static inline void bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) 677 { 678 smp_mb__before_atomic(); 679 clear_bit(BNX2X_STATE_FP_POLL_BIT, &fp->busy_poll_state); 680 } 681 682 /* true if a socket is polling */ 683 static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) 684 { 685 return READ_ONCE(fp->busy_poll_state) & BNX2X_STATE_FP_POLL; 686 } 687 688 /* false if fp is currently owned */ 689 static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp) 690 { 691 set_bit(BNX2X_STATE_FP_DISABLE_BIT, &fp->busy_poll_state); 692 return !bnx2x_fp_ll_polling(fp); 693 694 } 695 #else 696 static inline void bnx2x_fp_busy_poll_init(struct bnx2x_fastpath *fp) 697 { 698 } 699 700 static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) 701 { 702 return true; 703 } 704 705 static inline void bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) 706 { 707 } 708 709 static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) 710 { 711 return false; 712 } 713 714 static inline void bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) 715 { 716 } 717 718 static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) 719 { 720 return false; 721 } 722 static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp) 723 { 724 return true; 725 } 726 #endif /* CONFIG_NET_RX_BUSY_POLL */ 727 728 /* Use 2500 as a mini-jumbo MTU for FCoE */ 729 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500 730 731 #define FCOE_IDX_OFFSET 0 732 733 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ 734 FCOE_IDX_OFFSET) 735 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) 736 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 737 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) 738 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) 739 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 740 txdata_ptr[FIRST_TX_COS_INDEX] \ 741 ->var) 742 743 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp)) 744 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp)) 745 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp)) 746 747 /* MC hsi */ 748 #define MAX_FETCH_BD 13 /* HW max BDs per packet */ 749 #define RX_COPY_THRESH 92 750 751 #define NUM_TX_RINGS 16 752 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 753 #define NEXT_PAGE_TX_DESC_CNT 1 754 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 755 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 756 #define MAX_TX_BD (NUM_TX_BD - 1) 757 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 758 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 759 (MAX_TX_DESC_CNT - 1)) ? \ 760 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 761 (x) + 1) 762 #define TX_BD(x) ((x) & MAX_TX_BD) 763 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 764 765 /* number of NEXT_PAGE descriptors may be required during placement */ 766 #define NEXT_CNT_PER_TX_PKT(bds) \ 767 (((bds) + MAX_TX_DESC_CNT - 1) / \ 768 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT) 769 /* max BDs per tx packet w/o next_pages: 770 * START_BD - describes packed 771 * START_BD(splitted) - includes unpaged data segment for GSO 772 * PARSING_BD - for TSO and CSUM data 773 * PARSING_BD2 - for encapsulation data 774 * Frag BDs - describes pages for frags 775 */ 776 #define BDS_PER_TX_PKT 4 777 #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) 778 /* max BDs per tx packet including next pages */ 779 #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \ 780 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT)) 781 782 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 783 #define NUM_RX_RINGS 8 784 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 785 #define NEXT_PAGE_RX_DESC_CNT 2 786 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 787 #define RX_DESC_MASK (RX_DESC_CNT - 1) 788 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 789 #define MAX_RX_BD (NUM_RX_BD - 1) 790 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 791 792 /* dropless fc calculations for BDs 793 * 794 * Number of BDs should as number of buffers in BRB: 795 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 796 * "next" elements on each page 797 */ 798 #define NUM_BD_REQ BRB_SIZE(bp) 799 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 800 MAX_RX_DESC_CNT) 801 #define BD_TH_LO(bp) (NUM_BD_REQ + \ 802 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 803 FW_DROP_LEVEL(bp)) 804 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 805 806 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 807 808 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 809 ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 810 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 811 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 812 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 813 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 814 MIN_RX_AVAIL)) 815 816 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 817 (MAX_RX_DESC_CNT - 1)) ? \ 818 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 819 (x) + 1) 820 #define RX_BD(x) ((x) & MAX_RX_BD) 821 822 /* 823 * As long as CQE is X times bigger than BD entry we have to allocate X times 824 * more pages for CQ ring in order to keep it balanced with BD ring 825 */ 826 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 827 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 828 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 829 #define NEXT_PAGE_RCQ_DESC_CNT 1 830 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 831 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 832 #define MAX_RCQ_BD (NUM_RCQ_BD - 1) 833 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 834 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 835 (MAX_RCQ_DESC_CNT - 1)) ? \ 836 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 837 (x) + 1) 838 #define RCQ_BD(x) ((x) & MAX_RCQ_BD) 839 840 /* dropless fc calculations for RCQs 841 * 842 * Number of RCQs should be as number of buffers in BRB: 843 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 844 * "next" elements on each page 845 */ 846 #define NUM_RCQ_REQ BRB_SIZE(bp) 847 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 848 MAX_RCQ_DESC_CNT) 849 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 850 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 851 FW_DROP_LEVEL(bp)) 852 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 853 854 /* This is needed for determining of last_max */ 855 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 856 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 857 858 #define BNX2X_SWCID_SHIFT 17 859 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 860 861 /* used on a CID received from the HW */ 862 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 863 #define CQE_CMD(x) (le32_to_cpu(x) >> \ 864 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 865 866 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 867 le32_to_cpu((bd)->addr_lo)) 868 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 869 870 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 871 #define BNX2X_DB_SHIFT 3 /* 8 bytes*/ 872 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 873 #error "Min DB doorbell stride is 8" 874 #endif 875 #define DOORBELL(bp, cid, val) \ 876 do { \ 877 writel((u32)(val), bp->doorbells + (bp->db_size * (cid))); \ 878 } while (0) 879 880 /* TX CSUM helpers */ 881 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 882 skb->csum_offset) 883 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 884 skb->csum_offset)) 885 886 #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff) 887 888 #define XMIT_PLAIN 0 889 #define XMIT_CSUM_V4 (1 << 0) 890 #define XMIT_CSUM_V6 (1 << 1) 891 #define XMIT_CSUM_TCP (1 << 2) 892 #define XMIT_GSO_V4 (1 << 3) 893 #define XMIT_GSO_V6 (1 << 4) 894 #define XMIT_CSUM_ENC_V4 (1 << 5) 895 #define XMIT_CSUM_ENC_V6 (1 << 6) 896 #define XMIT_GSO_ENC_V4 (1 << 7) 897 #define XMIT_GSO_ENC_V6 (1 << 8) 898 899 #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6) 900 #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6) 901 902 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC) 903 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC) 904 905 /* stuff added to make the code fit 80Col */ 906 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 907 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 908 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 909 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 910 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 911 912 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 913 914 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 915 (((le16_to_cpu(flags) & \ 916 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 917 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 918 == PRS_FLAG_OVERETH_IPV4) 919 #define BNX2X_RX_SUM_FIX(cqe) \ 920 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 921 922 #define FP_USB_FUNC_OFF \ 923 offsetof(struct cstorm_status_block_u, func) 924 #define FP_CSB_FUNC_OFF \ 925 offsetof(struct cstorm_status_block_c, func) 926 927 #define HC_INDEX_ETH_RX_CQ_CONS 1 928 929 #define HC_INDEX_OOO_TX_CQ_CONS 4 930 931 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 932 933 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 934 935 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 936 937 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 938 939 #define BNX2X_RX_SB_INDEX \ 940 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 941 942 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 943 944 #define BNX2X_TX_SB_INDEX_COS0 \ 945 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 946 947 /* end of fast path */ 948 949 /* common */ 950 951 struct bnx2x_common { 952 953 u32 chip_id; 954 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 955 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 956 957 #define CHIP_NUM(bp) (bp->common.chip_id >> 16) 958 #define CHIP_NUM_57710 0x164e 959 #define CHIP_NUM_57711 0x164f 960 #define CHIP_NUM_57711E 0x1650 961 #define CHIP_NUM_57712 0x1662 962 #define CHIP_NUM_57712_MF 0x1663 963 #define CHIP_NUM_57712_VF 0x166f 964 #define CHIP_NUM_57713 0x1651 965 #define CHIP_NUM_57713E 0x1652 966 #define CHIP_NUM_57800 0x168a 967 #define CHIP_NUM_57800_MF 0x16a5 968 #define CHIP_NUM_57800_VF 0x16a9 969 #define CHIP_NUM_57810 0x168e 970 #define CHIP_NUM_57810_MF 0x16ae 971 #define CHIP_NUM_57810_VF 0x16af 972 #define CHIP_NUM_57811 0x163d 973 #define CHIP_NUM_57811_MF 0x163e 974 #define CHIP_NUM_57811_VF 0x163f 975 #define CHIP_NUM_57840_OBSOLETE 0x168d 976 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab 977 #define CHIP_NUM_57840_4_10 0x16a1 978 #define CHIP_NUM_57840_2_20 0x16a2 979 #define CHIP_NUM_57840_MF 0x16a4 980 #define CHIP_NUM_57840_VF 0x16ad 981 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 982 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 983 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 984 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 985 #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF) 986 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 987 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 988 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 989 #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF) 990 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 991 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 992 #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF) 993 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) 994 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) 995 #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF) 996 #define CHIP_IS_57840(bp) \ 997 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \ 998 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \ 999 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) 1000 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \ 1001 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE)) 1002 #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF) 1003 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 1004 CHIP_IS_57711E(bp)) 1005 #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \ 1006 CHIP_IS_57811_MF(bp) || \ 1007 CHIP_IS_57811_VF(bp)) 1008 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 1009 CHIP_IS_57712_MF(bp) || \ 1010 CHIP_IS_57712_VF(bp)) 1011 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 1012 CHIP_IS_57800_MF(bp) || \ 1013 CHIP_IS_57800_VF(bp) || \ 1014 CHIP_IS_57810(bp) || \ 1015 CHIP_IS_57810_MF(bp) || \ 1016 CHIP_IS_57810_VF(bp) || \ 1017 CHIP_IS_57811xx(bp) || \ 1018 CHIP_IS_57840(bp) || \ 1019 CHIP_IS_57840_MF(bp) || \ 1020 CHIP_IS_57840_VF(bp)) 1021 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 1022 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 1023 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 1024 1025 #define CHIP_REV_SHIFT 12 1026 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1027 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 1028 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1029 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1030 /* assume maximum 5 revisions */ 1031 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 1032 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 1033 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 1034 !(CHIP_REV_VAL(bp) & 0x00001000)) 1035 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 1036 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 1037 (CHIP_REV_VAL(bp) & 0x00001000)) 1038 1039 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 1040 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 1041 1042 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 1043 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 1044 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 1045 (CHIP_REV_SHIFT + 1)) \ 1046 << CHIP_REV_SHIFT) 1047 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 1048 CHIP_REV_SIM(bp) :\ 1049 CHIP_REV_VAL(bp)) 1050 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 1051 (CHIP_REV(bp) == CHIP_REV_Bx)) 1052 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 1053 (CHIP_REV(bp) == CHIP_REV_Ax)) 1054 /* This define is used in two main places: 1055 * 1. In the early stages of nic_load, to know if to configure Parser / Searcher 1056 * to nic-only mode or to offload mode. Offload mode is configured if either the 1057 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already 1058 * registered for this port (which means that the user wants storage services). 1059 * 2. During cnic-related load, to know if offload mode is already configured in 1060 * the HW or needs to be configured. 1061 * Since the transition from nic-mode to offload-mode in HW causes traffic 1062 * corruption, nic-mode is configured only in ports on which storage services 1063 * where never requested. 1064 */ 1065 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp)) 1066 1067 int flash_size; 1068 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 1069 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000 1070 #define BNX2X_NVRAM_PAGE_SIZE 256 1071 1072 u32 shmem_base; 1073 u32 shmem2_base; 1074 u32 mf_cfg_base; 1075 u32 mf2_cfg_base; 1076 1077 u32 hw_config; 1078 1079 u32 bc_ver; 1080 1081 u8 int_block; 1082 #define INT_BLOCK_HC 0 1083 #define INT_BLOCK_IGU 1 1084 #define INT_BLOCK_MODE_NORMAL 0 1085 #define INT_BLOCK_MODE_BW_COMP 2 1086 #define CHIP_INT_MODE_IS_NBC(bp) \ 1087 (!CHIP_IS_E1x(bp) && \ 1088 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 1089 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 1090 1091 u8 chip_port_mode; 1092 #define CHIP_4_PORT_MODE 0x0 1093 #define CHIP_2_PORT_MODE 0x1 1094 #define CHIP_PORT_MODE_NONE 0x2 1095 #define CHIP_MODE(bp) (bp->common.chip_port_mode) 1096 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 1097 1098 u32 boot_mode; 1099 }; 1100 1101 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 1102 #define BNX2X_IGU_STAS_MSG_VF_CNT 64 1103 #define BNX2X_IGU_STAS_MSG_PF_CNT 4 1104 1105 #define MAX_IGU_ATTN_ACK_TO 100 1106 /* end of common */ 1107 1108 /* port */ 1109 1110 struct bnx2x_port { 1111 u32 pmf; 1112 1113 u32 link_config[LINK_CONFIG_SIZE]; 1114 1115 u32 supported[LINK_CONFIG_SIZE]; 1116 1117 u32 advertising[LINK_CONFIG_SIZE]; 1118 1119 u32 phy_addr; 1120 1121 /* used to synchronize phy accesses */ 1122 struct mutex phy_mutex; 1123 1124 u32 port_stx; 1125 1126 struct nig_stats old_nig_stats; 1127 }; 1128 1129 /* end of port */ 1130 1131 #define STATS_OFFSET32(stat_name) \ 1132 (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 1133 1134 /* slow path */ 1135 #define BNX2X_MAX_NUM_OF_VFS 64 1136 #define BNX2X_VF_CID_WND 4 /* log num of queues per VF. HW config. */ 1137 #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND) 1138 1139 /* We need to reserve doorbell addresses for all VF and queue combinations */ 1140 #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF) 1141 1142 /* The doorbell is configured to have the same number of CIDs for PFs and for 1143 * VFs. For this reason the PF CID zone is as large as the VF zone. 1144 */ 1145 #define BNX2X_FIRST_VF_CID BNX2X_VF_CIDS 1146 #define BNX2X_MAX_NUM_VF_QUEUES 64 1147 #define BNX2X_VF_ID_INVALID 0xFF 1148 1149 /* the number of VF CIDS multiplied by the amount of bytes reserved for each 1150 * cid must not exceed the size of the VF doorbell 1151 */ 1152 #define BNX2X_VF_BAR_SIZE 512 1153 #if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT)) 1154 #error "VF doorbell bar size is 512" 1155 #endif 1156 1157 /* 1158 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 1159 * control by the number of fast-path status blocks supported by the 1160 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 1161 * status block represents an independent interrupts context that can 1162 * serve a regular L2 networking queue. However special L2 queues such 1163 * as the FCoE queue do not require a FP-SB and other components like 1164 * the CNIC may consume FP-SB reducing the number of possible L2 queues 1165 * 1166 * If the maximum number of FP-SB available is X then: 1167 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 1168 * regular L2 queues is Y=X-1 1169 * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 1170 * c. If the FCoE L2 queue is supported the actual number of L2 queues 1171 * is Y+1 1172 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 1173 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 1174 * FP interrupt context for the CNIC). 1175 * e. The number of HW context (CID count) is always X or X+1 if FCoE 1176 * L2 queue is supported. The cid for the FCoE L2 queue is always X. 1177 */ 1178 1179 /* fast-path interrupt contexts E1x */ 1180 #define FP_SB_MAX_E1x 16 1181 /* fast-path interrupt contexts E2 */ 1182 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 1183 1184 union cdu_context { 1185 struct eth_context eth; 1186 char pad[1024]; 1187 }; 1188 1189 /* CDU host DB constants */ 1190 #define CDU_ILT_PAGE_SZ_HW 2 1191 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 1192 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 1193 1194 #define CNIC_ISCSI_CID_MAX 256 1195 #define CNIC_FCOE_CID_MAX 2048 1196 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 1197 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 1198 1199 #define QM_ILT_PAGE_SZ_HW 0 1200 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 1201 #define QM_CID_ROUND 1024 1202 1203 /* TM (timers) host DB constants */ 1204 #define TM_ILT_PAGE_SZ_HW 0 1205 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 1206 #define TM_CONN_NUM (BNX2X_FIRST_VF_CID + \ 1207 BNX2X_VF_CIDS + \ 1208 CNIC_ISCSI_CID_MAX) 1209 #define TM_ILT_SZ (8 * TM_CONN_NUM) 1210 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 1211 1212 /* SRC (Searcher) host DB constants */ 1213 #define SRC_ILT_PAGE_SZ_HW 0 1214 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1215 #define SRC_HASH_BITS 10 1216 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1217 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1218 #define SRC_T2_SZ SRC_ILT_SZ 1219 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1220 1221 #define MAX_DMAE_C 8 1222 1223 /* DMA memory not used in fastpath */ 1224 struct bnx2x_slowpath { 1225 union { 1226 struct mac_configuration_cmd e1x; 1227 struct eth_classify_rules_ramrod_data e2; 1228 } mac_rdata; 1229 1230 union { 1231 struct tstorm_eth_mac_filter_config e1x; 1232 struct eth_filter_rules_ramrod_data e2; 1233 } rx_mode_rdata; 1234 1235 union { 1236 struct mac_configuration_cmd e1; 1237 struct eth_multicast_rules_ramrod_data e2; 1238 } mcast_rdata; 1239 1240 struct eth_rss_update_ramrod_data rss_rdata; 1241 1242 /* Queue State related ramrods are always sent under rtnl_lock */ 1243 union { 1244 struct client_init_ramrod_data init_data; 1245 struct client_update_ramrod_data update_data; 1246 struct tpa_update_ramrod_data tpa_data; 1247 } q_rdata; 1248 1249 union { 1250 struct function_start_data func_start; 1251 /* pfc configuration for DCBX ramrod */ 1252 struct flow_control_configuration pfc_config; 1253 } func_rdata; 1254 1255 /* afex ramrod can not be a part of func_rdata union because these 1256 * events might arrive in parallel to other events from func_rdata. 1257 * Therefore, if they would have been defined in the same union, 1258 * data can get corrupted. 1259 */ 1260 union { 1261 struct afex_vif_list_ramrod_data viflist_data; 1262 struct function_update_data func_update; 1263 } func_afex_rdata; 1264 1265 /* used by dmae command executer */ 1266 struct dmae_command dmae[MAX_DMAE_C]; 1267 1268 u32 stats_comp; 1269 union mac_stats mac_stats; 1270 struct nig_stats nig_stats; 1271 struct host_port_stats port_stats; 1272 struct host_func_stats func_stats; 1273 1274 u32 wb_comp; 1275 u32 wb_data[4]; 1276 1277 union drv_info_to_mcp drv_info_to_mcp; 1278 }; 1279 1280 #define bnx2x_sp(bp, var) (&bp->slowpath->var) 1281 #define bnx2x_sp_mapping(bp, var) \ 1282 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1283 1284 /* attn group wiring */ 1285 #define MAX_DYNAMIC_ATTN_GRPS 8 1286 1287 struct attn_route { 1288 u32 sig[5]; 1289 }; 1290 1291 struct iro { 1292 u32 base; 1293 u16 m1; 1294 u16 m2; 1295 u16 m3; 1296 u16 size; 1297 }; 1298 1299 struct hw_context { 1300 union cdu_context *vcxt; 1301 dma_addr_t cxt_mapping; 1302 size_t size; 1303 }; 1304 1305 /* forward */ 1306 struct bnx2x_ilt; 1307 1308 struct bnx2x_vfdb; 1309 1310 enum bnx2x_recovery_state { 1311 BNX2X_RECOVERY_DONE, 1312 BNX2X_RECOVERY_INIT, 1313 BNX2X_RECOVERY_WAIT, 1314 BNX2X_RECOVERY_FAILED, 1315 BNX2X_RECOVERY_NIC_LOADING 1316 }; 1317 1318 /* 1319 * Event queue (EQ or event ring) MC hsi 1320 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1321 */ 1322 #define NUM_EQ_PAGES 1 1323 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1324 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1325 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1326 #define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1327 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1328 1329 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1330 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1331 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1332 1333 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1334 #define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1335 1336 #define BNX2X_EQ_INDEX \ 1337 (&bp->def_status_blk->sp_sb.\ 1338 index_values[HC_SP_INDEX_EQ_CONS]) 1339 1340 /* This is a data that will be used to create a link report message. 1341 * We will keep the data used for the last link report in order 1342 * to prevent reporting the same link parameters twice. 1343 */ 1344 struct bnx2x_link_report_data { 1345 u16 line_speed; /* Effective line speed */ 1346 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1347 }; 1348 1349 enum { 1350 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1351 BNX2X_LINK_REPORT_LINK_DOWN, 1352 BNX2X_LINK_REPORT_RX_FC_ON, 1353 BNX2X_LINK_REPORT_TX_FC_ON, 1354 }; 1355 1356 enum { 1357 BNX2X_PORT_QUERY_IDX, 1358 BNX2X_PF_QUERY_IDX, 1359 BNX2X_FCOE_QUERY_IDX, 1360 BNX2X_FIRST_QUEUE_QUERY_IDX, 1361 }; 1362 1363 struct bnx2x_fw_stats_req { 1364 struct stats_query_header hdr; 1365 struct stats_query_entry query[FP_SB_MAX_E1x+ 1366 BNX2X_FIRST_QUEUE_QUERY_IDX]; 1367 }; 1368 1369 struct bnx2x_fw_stats_data { 1370 struct stats_counter storm_counters; 1371 struct per_port_stats port; 1372 struct per_pf_stats pf; 1373 struct fcoe_statistics_params fcoe; 1374 struct per_queue_stats queue_stats[1]; 1375 }; 1376 1377 /* Public slow path states */ 1378 enum sp_rtnl_flag { 1379 BNX2X_SP_RTNL_SETUP_TC, 1380 BNX2X_SP_RTNL_TX_TIMEOUT, 1381 BNX2X_SP_RTNL_FAN_FAILURE, 1382 BNX2X_SP_RTNL_AFEX_F_UPDATE, 1383 BNX2X_SP_RTNL_ENABLE_SRIOV, 1384 BNX2X_SP_RTNL_VFPF_MCAST, 1385 BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 1386 BNX2X_SP_RTNL_RX_MODE, 1387 BNX2X_SP_RTNL_HYPERVISOR_VLAN, 1388 BNX2X_SP_RTNL_TX_STOP, 1389 BNX2X_SP_RTNL_GET_DRV_VERSION, 1390 }; 1391 1392 enum bnx2x_iov_flag { 1393 BNX2X_IOV_HANDLE_VF_MSG, 1394 BNX2X_IOV_HANDLE_FLR, 1395 }; 1396 1397 struct bnx2x_prev_path_list { 1398 struct list_head list; 1399 u8 bus; 1400 u8 slot; 1401 u8 path; 1402 u8 aer; 1403 u8 undi; 1404 }; 1405 1406 struct bnx2x_sp_objs { 1407 /* MACs object */ 1408 struct bnx2x_vlan_mac_obj mac_obj; 1409 1410 /* Queue State object */ 1411 struct bnx2x_queue_sp_obj q_obj; 1412 }; 1413 1414 struct bnx2x_fp_stats { 1415 struct tstorm_per_queue_stats old_tclient; 1416 struct ustorm_per_queue_stats old_uclient; 1417 struct xstorm_per_queue_stats old_xclient; 1418 struct bnx2x_eth_q_stats eth_q_stats; 1419 struct bnx2x_eth_q_stats_old eth_q_stats_old; 1420 }; 1421 1422 enum { 1423 SUB_MF_MODE_UNKNOWN = 0, 1424 SUB_MF_MODE_UFP, 1425 SUB_MF_MODE_NPAR1_DOT_5, 1426 }; 1427 1428 struct bnx2x { 1429 /* Fields used in the tx and intr/napi performance paths 1430 * are grouped together in the beginning of the structure 1431 */ 1432 struct bnx2x_fastpath *fp; 1433 struct bnx2x_sp_objs *sp_objs; 1434 struct bnx2x_fp_stats *fp_stats; 1435 struct bnx2x_fp_txdata *bnx2x_txq; 1436 void __iomem *regview; 1437 void __iomem *doorbells; 1438 u16 db_size; 1439 1440 u8 pf_num; /* absolute PF number */ 1441 u8 pfid; /* per-path PF number */ 1442 int base_fw_ndsb; /**/ 1443 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1444 #define BP_PORT(bp) (bp->pfid & 1) 1445 #define BP_FUNC(bp) (bp->pfid) 1446 #define BP_ABS_FUNC(bp) (bp->pf_num) 1447 #define BP_VN(bp) ((bp)->pfid >> 1) 1448 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 1449 #define BP_L_ID(bp) (BP_VN(bp) << 2) 1450 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 1451 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 1452 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1453 1454 #ifdef CONFIG_BNX2X_SRIOV 1455 /* protects vf2pf mailbox from simultaneous access */ 1456 struct mutex vf2pf_mutex; 1457 /* vf pf channel mailbox contains request and response buffers */ 1458 struct bnx2x_vf_mbx_msg *vf2pf_mbox; 1459 dma_addr_t vf2pf_mbox_mapping; 1460 1461 /* we set aside a copy of the acquire response */ 1462 struct pfvf_acquire_resp_tlv acquire_resp; 1463 1464 /* bulletin board for messages from pf to vf */ 1465 union pf_vf_bulletin *pf2vf_bulletin; 1466 dma_addr_t pf2vf_bulletin_mapping; 1467 1468 union pf_vf_bulletin shadow_bulletin; 1469 struct pf_vf_bulletin_content old_bulletin; 1470 1471 u16 requested_nr_virtfn; 1472 #endif /* CONFIG_BNX2X_SRIOV */ 1473 1474 struct net_device *dev; 1475 struct pci_dev *pdev; 1476 1477 const struct iro *iro_arr; 1478 #define IRO (bp->iro_arr) 1479 1480 enum bnx2x_recovery_state recovery_state; 1481 int is_leader; 1482 struct msix_entry *msix_table; 1483 1484 int tx_ring_size; 1485 1486 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1487 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1488 #define ETH_MIN_PACKET_SIZE 60 1489 #define ETH_MAX_PACKET_SIZE 1500 1490 #define ETH_MAX_JUMBO_PACKET_SIZE 9600 1491 /* TCP with Timestamp Option (32) + IPv6 (40) */ 1492 #define ETH_MAX_TPA_HEADER_SIZE 72 1493 1494 /* Max supported alignment is 256 (8 shift) 1495 * minimal alignment shift 6 is optimal for 57xxx HW performance 1496 */ 1497 #define BNX2X_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT)) 1498 1499 /* FW uses 2 Cache lines Alignment for start packet and size 1500 * 1501 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1502 * at the end of skb->data, to avoid wasting a full cache line. 1503 * This reduces memory use (skb->truesize). 1504 */ 1505 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1506 1507 #define BNX2X_FW_RX_ALIGN_END \ 1508 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \ 1509 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1510 1511 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1512 1513 struct host_sp_status_block *def_status_blk; 1514 #define DEF_SB_IGU_ID 16 1515 #define DEF_SB_ID HC_SP_SB_ID 1516 __le16 def_idx; 1517 __le16 def_att_idx; 1518 u32 attn_state; 1519 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1520 1521 /* slow path ring */ 1522 struct eth_spe *spq; 1523 dma_addr_t spq_mapping; 1524 u16 spq_prod_idx; 1525 struct eth_spe *spq_prod_bd; 1526 struct eth_spe *spq_last_bd; 1527 __le16 *dsb_sp_prod; 1528 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1529 /* used to synchronize spq accesses */ 1530 spinlock_t spq_lock; 1531 1532 /* event queue */ 1533 union event_ring_elem *eq_ring; 1534 dma_addr_t eq_mapping; 1535 u16 eq_prod; 1536 u16 eq_cons; 1537 __le16 *eq_cons_sb; 1538 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1539 1540 /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1541 u16 stats_pending; 1542 /* Counter for completed statistics ramrods */ 1543 u16 stats_comp; 1544 1545 /* End of fields used in the performance code paths */ 1546 1547 int panic; 1548 int msg_enable; 1549 1550 u32 flags; 1551 #define PCIX_FLAG (1 << 0) 1552 #define PCI_32BIT_FLAG (1 << 1) 1553 #define ONE_PORT_FLAG (1 << 2) 1554 #define NO_WOL_FLAG (1 << 3) 1555 #define USING_MSIX_FLAG (1 << 5) 1556 #define USING_MSI_FLAG (1 << 6) 1557 #define DISABLE_MSI_FLAG (1 << 7) 1558 #define NO_MCP_FLAG (1 << 9) 1559 #define MF_FUNC_DIS (1 << 11) 1560 #define OWN_CNIC_IRQ (1 << 12) 1561 #define NO_ISCSI_OOO_FLAG (1 << 13) 1562 #define NO_ISCSI_FLAG (1 << 14) 1563 #define NO_FCOE_FLAG (1 << 15) 1564 #define BC_SUPPORTS_PFC_STATS (1 << 17) 1565 #define TX_SWITCHING (1 << 18) 1566 #define BC_SUPPORTS_FCOE_FEATURES (1 << 19) 1567 #define USING_SINGLE_MSIX_FLAG (1 << 20) 1568 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21) 1569 #define IS_VF_FLAG (1 << 22) 1570 #define BC_SUPPORTS_RMMOD_CMD (1 << 23) 1571 #define HAS_PHYS_PORT_ID (1 << 24) 1572 #define AER_ENABLED (1 << 25) 1573 #define PTP_SUPPORTED (1 << 26) 1574 #define TX_TIMESTAMPING_EN (1 << 27) 1575 1576 #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG) 1577 1578 #ifdef CONFIG_BNX2X_SRIOV 1579 #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG) 1580 #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG)) 1581 #else 1582 #define IS_VF(bp) false 1583 #define IS_PF(bp) true 1584 #endif 1585 1586 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1587 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1588 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1589 1590 u8 cnic_support; 1591 bool cnic_enabled; 1592 bool cnic_loaded; 1593 struct cnic_eth_dev *(*cnic_probe)(struct net_device *); 1594 1595 /* Flag that indicates that we can start looking for FCoE L2 queue 1596 * completions in the default status block. 1597 */ 1598 bool fcoe_init; 1599 1600 int mrrs; 1601 1602 struct delayed_work sp_task; 1603 struct delayed_work iov_task; 1604 1605 atomic_t interrupt_occurred; 1606 struct delayed_work sp_rtnl_task; 1607 1608 struct delayed_work period_task; 1609 struct timer_list timer; 1610 int current_interval; 1611 1612 u16 fw_seq; 1613 u16 fw_drv_pulse_wr_seq; 1614 u32 func_stx; 1615 1616 struct link_params link_params; 1617 struct link_vars link_vars; 1618 u32 link_cnt; 1619 struct bnx2x_link_report_data last_reported_link; 1620 1621 struct mdio_if_info mdio; 1622 1623 struct bnx2x_common common; 1624 struct bnx2x_port port; 1625 1626 struct cmng_init cmng; 1627 1628 u32 mf_config[E1HVN_MAX]; 1629 u32 mf_ext_config; 1630 u32 path_has_ovlan; /* E3 */ 1631 u16 mf_ov; 1632 u8 mf_mode; 1633 #define IS_MF(bp) (bp->mf_mode != 0) 1634 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1635 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1636 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) 1637 u8 mf_sub_mode; 1638 #define IS_MF_UFP(bp) (IS_MF_SD(bp) && \ 1639 bp->mf_sub_mode == SUB_MF_MODE_UFP) 1640 1641 u8 wol; 1642 1643 int rx_ring_size; 1644 1645 u16 tx_quick_cons_trip_int; 1646 u16 tx_quick_cons_trip; 1647 u16 tx_ticks_int; 1648 u16 tx_ticks; 1649 1650 u16 rx_quick_cons_trip_int; 1651 u16 rx_quick_cons_trip; 1652 u16 rx_ticks_int; 1653 u16 rx_ticks; 1654 /* Maximal coalescing timeout in us */ 1655 #define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR) 1656 1657 u32 lin_cnt; 1658 1659 u16 state; 1660 #define BNX2X_STATE_CLOSED 0 1661 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1662 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1663 #define BNX2X_STATE_OPEN 0x3000 1664 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1665 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1666 1667 #define BNX2X_STATE_DIAG 0xe000 1668 #define BNX2X_STATE_ERROR 0xf000 1669 1670 #define BNX2X_MAX_PRIORITY 8 1671 int num_queues; 1672 uint num_ethernet_queues; 1673 uint num_cnic_queues; 1674 int disable_tpa; 1675 1676 u32 rx_mode; 1677 #define BNX2X_RX_MODE_NONE 0 1678 #define BNX2X_RX_MODE_NORMAL 1 1679 #define BNX2X_RX_MODE_ALLMULTI 2 1680 #define BNX2X_RX_MODE_PROMISC 3 1681 #define BNX2X_MAX_MULTICAST 64 1682 1683 u8 igu_dsb_id; 1684 u8 igu_base_sb; 1685 u8 igu_sb_cnt; 1686 u8 min_msix_vec_cnt; 1687 1688 u32 igu_base_addr; 1689 dma_addr_t def_status_blk_mapping; 1690 1691 struct bnx2x_slowpath *slowpath; 1692 dma_addr_t slowpath_mapping; 1693 1694 /* Mechanism protecting the drv_info_to_mcp */ 1695 struct mutex drv_info_mutex; 1696 bool drv_info_mng_owner; 1697 1698 /* Total number of FW statistics requests */ 1699 u8 fw_stats_num; 1700 1701 /* 1702 * This is a memory buffer that will contain both statistics 1703 * ramrod request and data. 1704 */ 1705 void *fw_stats; 1706 dma_addr_t fw_stats_mapping; 1707 1708 /* 1709 * FW statistics request shortcut (points at the 1710 * beginning of fw_stats buffer). 1711 */ 1712 struct bnx2x_fw_stats_req *fw_stats_req; 1713 dma_addr_t fw_stats_req_mapping; 1714 int fw_stats_req_sz; 1715 1716 /* 1717 * FW statistics data shortcut (points at the beginning of 1718 * fw_stats buffer + fw_stats_req_sz). 1719 */ 1720 struct bnx2x_fw_stats_data *fw_stats_data; 1721 dma_addr_t fw_stats_data_mapping; 1722 int fw_stats_data_sz; 1723 1724 /* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB 1725 * context size we need 8 ILT entries. 1726 */ 1727 #define ILT_MAX_L2_LINES 32 1728 struct hw_context context[ILT_MAX_L2_LINES]; 1729 1730 struct bnx2x_ilt *ilt; 1731 #define BP_ILT(bp) ((bp)->ilt) 1732 #define ILT_MAX_LINES 256 1733 /* 1734 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1735 * to CNIC. 1736 */ 1737 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp)) 1738 1739 /* 1740 * Maximum CID count that might be required by the bnx2x: 1741 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI 1742 */ 1743 1744 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \ 1745 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 1746 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \ 1747 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 1748 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1749 ILT_PAGE_CIDS)) 1750 1751 int qm_cid_count; 1752 1753 bool dropless_fc; 1754 1755 void *t2; 1756 dma_addr_t t2_mapping; 1757 struct cnic_ops __rcu *cnic_ops; 1758 void *cnic_data; 1759 u32 cnic_tag; 1760 struct cnic_eth_dev cnic_eth_dev; 1761 union host_hc_status_block cnic_sb; 1762 dma_addr_t cnic_sb_mapping; 1763 struct eth_spe *cnic_kwq; 1764 struct eth_spe *cnic_kwq_prod; 1765 struct eth_spe *cnic_kwq_cons; 1766 struct eth_spe *cnic_kwq_last; 1767 u16 cnic_kwq_pending; 1768 u16 cnic_spq_pending; 1769 u8 fip_mac[ETH_ALEN]; 1770 struct mutex cnic_mutex; 1771 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1772 1773 /* Start index of the "special" (CNIC related) L2 clients */ 1774 u8 cnic_base_cl_id; 1775 1776 int dmae_ready; 1777 /* used to synchronize dmae accesses */ 1778 spinlock_t dmae_lock; 1779 1780 /* used to protect the FW mail box */ 1781 struct mutex fw_mb_mutex; 1782 1783 /* used to synchronize stats collecting */ 1784 int stats_state; 1785 1786 /* used for synchronization of concurrent threads statistics handling */ 1787 struct semaphore stats_lock; 1788 1789 /* used by dmae command loader */ 1790 struct dmae_command stats_dmae; 1791 int executer_idx; 1792 1793 u16 stats_counter; 1794 struct bnx2x_eth_stats eth_stats; 1795 struct host_func_stats func_stats; 1796 struct bnx2x_eth_stats_old eth_stats_old; 1797 struct bnx2x_net_stats_old net_stats_old; 1798 struct bnx2x_fw_port_stats_old fw_stats_old; 1799 bool stats_init; 1800 1801 struct z_stream_s *strm; 1802 void *gunzip_buf; 1803 dma_addr_t gunzip_mapping; 1804 int gunzip_outlen; 1805 #define FW_BUF_SIZE 0x8000 1806 #define GUNZIP_BUF(bp) (bp->gunzip_buf) 1807 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1808 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1809 1810 struct raw_op *init_ops; 1811 /* Init blocks offsets inside init_ops */ 1812 u16 *init_ops_offsets; 1813 /* Data blob - has 32 bit granularity */ 1814 u32 *init_data; 1815 u32 init_mode_flags; 1816 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1817 /* Zipped PRAM blobs - raw data */ 1818 const u8 *tsem_int_table_data; 1819 const u8 *tsem_pram_data; 1820 const u8 *usem_int_table_data; 1821 const u8 *usem_pram_data; 1822 const u8 *xsem_int_table_data; 1823 const u8 *xsem_pram_data; 1824 const u8 *csem_int_table_data; 1825 const u8 *csem_pram_data; 1826 #define INIT_OPS(bp) (bp->init_ops) 1827 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1828 #define INIT_DATA(bp) (bp->init_data) 1829 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1830 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1831 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1832 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1833 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1834 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1835 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1836 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1837 1838 #define PHY_FW_VER_LEN 20 1839 char fw_ver[32]; 1840 const struct firmware *firmware; 1841 1842 struct bnx2x_vfdb *vfdb; 1843 #define IS_SRIOV(bp) ((bp)->vfdb) 1844 1845 /* DCB support on/off */ 1846 u16 dcb_state; 1847 #define BNX2X_DCB_STATE_OFF 0 1848 #define BNX2X_DCB_STATE_ON 1 1849 1850 /* DCBX engine mode */ 1851 int dcbx_enabled; 1852 #define BNX2X_DCBX_ENABLED_OFF 0 1853 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1854 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1855 #define BNX2X_DCBX_ENABLED_INVALID (-1) 1856 1857 bool dcbx_mode_uset; 1858 1859 struct bnx2x_config_dcbx_params dcbx_config_params; 1860 struct bnx2x_dcbx_port_params dcbx_port_params; 1861 int dcb_version; 1862 1863 /* CAM credit pools */ 1864 1865 /* used only in sriov */ 1866 struct bnx2x_credit_pool_obj vlans_pool; 1867 1868 struct bnx2x_credit_pool_obj macs_pool; 1869 1870 /* RX_MODE object */ 1871 struct bnx2x_rx_mode_obj rx_mode_obj; 1872 1873 /* MCAST object */ 1874 struct bnx2x_mcast_obj mcast_obj; 1875 1876 /* RSS configuration object */ 1877 struct bnx2x_rss_config_obj rss_conf_obj; 1878 1879 /* Function State controlling object */ 1880 struct bnx2x_func_sp_obj func_obj; 1881 1882 unsigned long sp_state; 1883 1884 /* operation indication for the sp_rtnl task */ 1885 unsigned long sp_rtnl_state; 1886 1887 /* Indication of the IOV tasks */ 1888 unsigned long iov_task_state; 1889 1890 /* DCBX Negotiation results */ 1891 struct dcbx_features dcbx_local_feat; 1892 u32 dcbx_error; 1893 1894 #ifdef BCM_DCBNL 1895 struct dcbx_features dcbx_remote_feat; 1896 u32 dcbx_remote_flags; 1897 #endif 1898 /* AFEX: store default vlan used */ 1899 int afex_def_vlan_tag; 1900 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1901 u32 pending_max; 1902 1903 /* multiple tx classes of service */ 1904 u8 max_cos; 1905 1906 /* priority to cos mapping */ 1907 u8 prio_to_cos[8]; 1908 1909 int fp_array_size; 1910 u32 dump_preset_idx; 1911 1912 u8 phys_port_id[ETH_ALEN]; 1913 1914 /* PTP related context */ 1915 struct ptp_clock *ptp_clock; 1916 struct ptp_clock_info ptp_clock_info; 1917 struct work_struct ptp_task; 1918 struct cyclecounter cyclecounter; 1919 struct timecounter timecounter; 1920 bool timecounter_init_done; 1921 struct sk_buff *ptp_tx_skb; 1922 unsigned long ptp_tx_start; 1923 bool hwtstamp_ioctl_called; 1924 u16 tx_type; 1925 u16 rx_filter; 1926 1927 struct bnx2x_link_report_data vf_link_vars; 1928 }; 1929 1930 /* Tx queues may be less or equal to Rx queues */ 1931 extern int num_queues; 1932 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 1933 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues) 1934 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ 1935 (bp)->num_cnic_queues) 1936 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1937 1938 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1939 1940 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1941 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1942 1943 #define RSS_IPV4_CAP_MASK \ 1944 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1945 1946 #define RSS_IPV4_TCP_CAP_MASK \ 1947 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1948 1949 #define RSS_IPV6_CAP_MASK \ 1950 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1951 1952 #define RSS_IPV6_TCP_CAP_MASK \ 1953 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1954 1955 /* func init flags */ 1956 #define FUNC_FLG_RSS 0x0001 1957 #define FUNC_FLG_STATS 0x0002 1958 /* removed FUNC_FLG_UNMATCHED 0x0004 */ 1959 #define FUNC_FLG_TPA 0x0008 1960 #define FUNC_FLG_SPQ 0x0010 1961 #define FUNC_FLG_LEADING 0x0020 /* PF only */ 1962 #define FUNC_FLG_LEADING_STATS 0x0040 1963 struct bnx2x_func_init_params { 1964 /* dma */ 1965 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1966 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1967 1968 u16 func_flgs; 1969 u16 func_id; /* abs fid */ 1970 u16 pf_id; 1971 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1972 }; 1973 1974 #define for_each_cnic_queue(bp, var) \ 1975 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1976 (var)++) \ 1977 if (skip_queue(bp, var)) \ 1978 continue; \ 1979 else 1980 1981 #define for_each_eth_queue(bp, var) \ 1982 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1983 1984 #define for_each_nondefault_eth_queue(bp, var) \ 1985 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1986 1987 #define for_each_queue(bp, var) \ 1988 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1989 if (skip_queue(bp, var)) \ 1990 continue; \ 1991 else 1992 1993 /* Skip forwarding FP */ 1994 #define for_each_valid_rx_queue(bp, var) \ 1995 for ((var) = 0; \ 1996 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 1997 BNX2X_NUM_ETH_QUEUES(bp)); \ 1998 (var)++) \ 1999 if (skip_rx_queue(bp, var)) \ 2000 continue; \ 2001 else 2002 2003 #define for_each_rx_queue_cnic(bp, var) \ 2004 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 2005 (var)++) \ 2006 if (skip_rx_queue(bp, var)) \ 2007 continue; \ 2008 else 2009 2010 #define for_each_rx_queue(bp, var) \ 2011 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 2012 if (skip_rx_queue(bp, var)) \ 2013 continue; \ 2014 else 2015 2016 /* Skip OOO FP */ 2017 #define for_each_valid_tx_queue(bp, var) \ 2018 for ((var) = 0; \ 2019 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 2020 BNX2X_NUM_ETH_QUEUES(bp)); \ 2021 (var)++) \ 2022 if (skip_tx_queue(bp, var)) \ 2023 continue; \ 2024 else 2025 2026 #define for_each_tx_queue_cnic(bp, var) \ 2027 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 2028 (var)++) \ 2029 if (skip_tx_queue(bp, var)) \ 2030 continue; \ 2031 else 2032 2033 #define for_each_tx_queue(bp, var) \ 2034 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 2035 if (skip_tx_queue(bp, var)) \ 2036 continue; \ 2037 else 2038 2039 #define for_each_nondefault_queue(bp, var) \ 2040 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 2041 if (skip_queue(bp, var)) \ 2042 continue; \ 2043 else 2044 2045 #define for_each_cos_in_tx_queue(fp, var) \ 2046 for ((var) = 0; (var) < (fp)->max_cos; (var)++) 2047 2048 /* skip rx queue 2049 * if FCOE l2 support is disabled and this is the fcoe L2 queue 2050 */ 2051 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2052 2053 /* skip tx queue 2054 * if FCOE l2 support is disabled and this is the fcoe L2 queue 2055 */ 2056 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2057 2058 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2059 2060 /** 2061 * bnx2x_set_mac_one - configure a single MAC address 2062 * 2063 * @bp: driver handle 2064 * @mac: MAC to configure 2065 * @obj: MAC object handle 2066 * @set: if 'true' add a new MAC, otherwise - delete 2067 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 2068 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 2069 * 2070 * Configures one MAC according to provided parameters or continues the 2071 * execution of previously scheduled commands if RAMROD_CONT is set in 2072 * ramrod_flags. 2073 * 2074 * Returns zero if operation has successfully completed, a positive value if the 2075 * operation has been successfully scheduled and a negative - if a requested 2076 * operations has failed. 2077 */ 2078 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 2079 struct bnx2x_vlan_mac_obj *obj, bool set, 2080 int mac_type, unsigned long *ramrod_flags); 2081 /** 2082 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 2083 * 2084 * @bp: driver handle 2085 * @mac_obj: MAC object handle 2086 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 2087 * @wait_for_comp: if 'true' block until completion 2088 * 2089 * Deletes all MACs of the specific type (e.g. ETH, UC list). 2090 * 2091 * Returns zero if operation has successfully completed, a positive value if the 2092 * operation has been successfully scheduled and a negative - if a requested 2093 * operations has failed. 2094 */ 2095 int bnx2x_del_all_macs(struct bnx2x *bp, 2096 struct bnx2x_vlan_mac_obj *mac_obj, 2097 int mac_type, bool wait_for_comp); 2098 2099 /* Init Function API */ 2100 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 2101 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 2102 u8 vf_valid, int fw_sb_id, int igu_sb_id); 2103 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 2104 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2105 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 2106 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2107 void bnx2x_read_mf_cfg(struct bnx2x *bp); 2108 2109 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); 2110 2111 /* dmae */ 2112 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 2113 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 2114 u32 len32); 2115 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 2116 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 2117 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 2118 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 2119 bool with_comp, u8 comp_type); 2120 2121 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 2122 u8 src_type, u8 dst_type); 2123 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 2124 u32 *comp); 2125 2126 /* FLR related routines */ 2127 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp); 2128 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count); 2129 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt); 2130 u8 bnx2x_is_pcie_pending(struct pci_dev *dev); 2131 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 2132 char *msg, u32 poll_cnt); 2133 2134 void bnx2x_calc_fc_adv(struct bnx2x *bp); 2135 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 2136 u32 data_hi, u32 data_lo, int cmd_type); 2137 void bnx2x_update_coalesce(struct bnx2x *bp); 2138 int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 2139 2140 bool bnx2x_port_after_undi(struct bnx2x *bp); 2141 2142 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 2143 int wait) 2144 { 2145 u32 val; 2146 2147 do { 2148 val = REG_RD(bp, reg); 2149 if (val == expected) 2150 break; 2151 ms -= wait; 2152 msleep(wait); 2153 2154 } while (ms > 0); 2155 2156 return val; 2157 } 2158 2159 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, 2160 bool is_pf); 2161 2162 #define BNX2X_ILT_ZALLOC(x, y, size) \ 2163 x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL) 2164 2165 #define BNX2X_ILT_FREE(x, y, size) \ 2166 do { \ 2167 if (x) { \ 2168 dma_free_coherent(&bp->pdev->dev, size, x, y); \ 2169 x = NULL; \ 2170 y = 0; \ 2171 } \ 2172 } while (0) 2173 2174 #define ILOG2(x) (ilog2((x))) 2175 2176 #define ILT_NUM_PAGE_ENTRIES (3072) 2177 /* In 57710/11 we use whole table since we have 8 func 2178 * In 57712 we have only 4 func, but use same size per func, then only half of 2179 * the table in use 2180 */ 2181 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 2182 2183 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 2184 /* 2185 * the phys address is shifted right 12 bits and has an added 2186 * 1=valid bit added to the 53rd bit 2187 * then since this is a wide register(TM) 2188 * we split it into two 32 bit writes 2189 */ 2190 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 2191 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 2192 2193 /* load/unload mode */ 2194 #define LOAD_NORMAL 0 2195 #define LOAD_OPEN 1 2196 #define LOAD_DIAG 2 2197 #define LOAD_LOOPBACK_EXT 3 2198 #define UNLOAD_NORMAL 0 2199 #define UNLOAD_CLOSE 1 2200 #define UNLOAD_RECOVERY 2 2201 2202 /* DMAE command defines */ 2203 #define DMAE_TIMEOUT -1 2204 #define DMAE_PCI_ERROR -2 /* E2 and onward */ 2205 #define DMAE_NOT_RDY -3 2206 #define DMAE_PCI_ERR_FLAG 0x80000000 2207 2208 #define DMAE_SRC_PCI 0 2209 #define DMAE_SRC_GRC 1 2210 2211 #define DMAE_DST_NONE 0 2212 #define DMAE_DST_PCI 1 2213 #define DMAE_DST_GRC 2 2214 2215 #define DMAE_COMP_PCI 0 2216 #define DMAE_COMP_GRC 1 2217 2218 /* E2 and onward - PCI error handling in the completion */ 2219 2220 #define DMAE_COMP_REGULAR 0 2221 #define DMAE_COM_SET_ERR 1 2222 2223 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 2224 DMAE_COMMAND_SRC_SHIFT) 2225 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 2226 DMAE_COMMAND_SRC_SHIFT) 2227 2228 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 2229 DMAE_COMMAND_DST_SHIFT) 2230 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 2231 DMAE_COMMAND_DST_SHIFT) 2232 2233 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 2234 DMAE_COMMAND_C_DST_SHIFT) 2235 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 2236 DMAE_COMMAND_C_DST_SHIFT) 2237 2238 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 2239 2240 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 2241 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 2242 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 2243 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 2244 2245 #define DMAE_CMD_PORT_0 0 2246 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 2247 2248 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 2249 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 2250 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 2251 2252 #define DMAE_SRC_PF 0 2253 #define DMAE_SRC_VF 1 2254 2255 #define DMAE_DST_PF 0 2256 #define DMAE_DST_VF 1 2257 2258 #define DMAE_C_SRC 0 2259 #define DMAE_C_DST 1 2260 2261 #define DMAE_LEN32_RD_MAX 0x80 2262 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 2263 2264 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 2265 * indicates error 2266 */ 2267 2268 #define MAX_DMAE_C_PER_PORT 8 2269 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2270 BP_VN(bp)) 2271 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2272 E1HVN_MAX) 2273 2274 /* PCIE link and speed */ 2275 #define PCICFG_LINK_WIDTH 0x1f00000 2276 #define PCICFG_LINK_WIDTH_SHIFT 20 2277 #define PCICFG_LINK_SPEED 0xf0000 2278 #define PCICFG_LINK_SPEED_SHIFT 16 2279 2280 #define BNX2X_NUM_TESTS_SF 7 2281 #define BNX2X_NUM_TESTS_MF 3 2282 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ 2283 IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF) 2284 2285 #define BNX2X_PHY_LOOPBACK 0 2286 #define BNX2X_MAC_LOOPBACK 1 2287 #define BNX2X_EXT_LOOPBACK 2 2288 #define BNX2X_PHY_LOOPBACK_FAILED 1 2289 #define BNX2X_MAC_LOOPBACK_FAILED 2 2290 #define BNX2X_EXT_LOOPBACK_FAILED 3 2291 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 2292 BNX2X_PHY_LOOPBACK_FAILED) 2293 2294 #define STROM_ASSERT_ARRAY_SIZE 50 2295 2296 /* must be used on a CID before placing it on a HW ring */ 2297 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 2298 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 2299 (x)) 2300 2301 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 2302 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 2303 2304 #define BNX2X_BTR 4 2305 #define MAX_SPQ_PENDING 8 2306 2307 /* CMNG constants, as derived from system spec calculations */ 2308 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 2309 #define DEF_MIN_RATE 100 2310 /* resolution of the rate shaping timer - 400 usec */ 2311 #define RS_PERIODIC_TIMEOUT_USEC 400 2312 /* number of bytes in single QM arbitration cycle - 2313 * coefficient for calculating the fairness timer */ 2314 #define QM_ARB_BYTES 160000 2315 /* resolution of Min algorithm 1:100 */ 2316 #define MIN_RES 100 2317 /* how many bytes above threshold for the minimal credit of Min algorithm*/ 2318 #define MIN_ABOVE_THRESH 32768 2319 /* Fairness algorithm integration time coefficient - 2320 * for calculating the actual Tfair */ 2321 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 2322 /* Memory of fairness algorithm . 2 cycles */ 2323 #define FAIR_MEM 2 2324 2325 #define ATTN_NIG_FOR_FUNC (1L << 8) 2326 #define ATTN_SW_TIMER_4_FUNC (1L << 9) 2327 #define GPIO_2_FUNC (1L << 10) 2328 #define GPIO_3_FUNC (1L << 11) 2329 #define GPIO_4_FUNC (1L << 12) 2330 #define ATTN_GENERAL_ATTN_1 (1L << 13) 2331 #define ATTN_GENERAL_ATTN_2 (1L << 14) 2332 #define ATTN_GENERAL_ATTN_3 (1L << 15) 2333 #define ATTN_GENERAL_ATTN_4 (1L << 13) 2334 #define ATTN_GENERAL_ATTN_5 (1L << 14) 2335 #define ATTN_GENERAL_ATTN_6 (1L << 15) 2336 2337 #define ATTN_HARD_WIRED_MASK 0xff00 2338 #define ATTENTION_ID 4 2339 2340 #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_PERSONALITY_ONLY(bp) || \ 2341 IS_MF_FCOE_AFEX(bp)) 2342 2343 /* stuff added to make the code fit 80Col */ 2344 2345 #define BNX2X_PMF_LINK_ASSERT \ 2346 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 2347 2348 #define BNX2X_MC_ASSERT_BITS \ 2349 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2350 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2351 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2352 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2353 2354 #define BNX2X_MCP_ASSERT \ 2355 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2356 2357 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2358 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2359 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2360 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2361 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2362 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2363 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2364 2365 #define HW_INTERRUT_ASSERT_SET_0 \ 2366 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 2367 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 2368 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 2369 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \ 2370 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2371 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 2372 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 2373 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 2374 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2375 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2376 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2377 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2378 #define HW_INTERRUT_ASSERT_SET_1 \ 2379 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 2380 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 2381 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 2382 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 2383 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 2384 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 2385 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 2386 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 2387 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 2388 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 2389 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2390 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2391 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 2392 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2393 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 2394 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2395 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 2396 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2397 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2398 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2399 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 2400 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 2401 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2402 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 2403 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 2404 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2405 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2406 #define HW_INTERRUT_ASSERT_SET_2 \ 2407 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 2408 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 2409 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 2410 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2411 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2412 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2413 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2414 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2415 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2416 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2417 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2418 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2419 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2420 2421 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2422 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2423 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 2424 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2425 2426 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2427 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2428 2429 #define MULTI_MASK 0x7f 2430 2431 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2432 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2433 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2434 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2435 2436 #define DEF_USB_IGU_INDEX_OFF \ 2437 offsetof(struct cstorm_def_status_block_u, igu_index) 2438 #define DEF_CSB_IGU_INDEX_OFF \ 2439 offsetof(struct cstorm_def_status_block_c, igu_index) 2440 #define DEF_XSB_IGU_INDEX_OFF \ 2441 offsetof(struct xstorm_def_status_block, igu_index) 2442 #define DEF_TSB_IGU_INDEX_OFF \ 2443 offsetof(struct tstorm_def_status_block, igu_index) 2444 2445 #define DEF_USB_SEGMENT_OFF \ 2446 offsetof(struct cstorm_def_status_block_u, segment) 2447 #define DEF_CSB_SEGMENT_OFF \ 2448 offsetof(struct cstorm_def_status_block_c, segment) 2449 #define DEF_XSB_SEGMENT_OFF \ 2450 offsetof(struct xstorm_def_status_block, segment) 2451 #define DEF_TSB_SEGMENT_OFF \ 2452 offsetof(struct tstorm_def_status_block, segment) 2453 2454 #define BNX2X_SP_DSB_INDEX \ 2455 (&bp->def_status_blk->sp_sb.\ 2456 index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2457 2458 #define CAM_IS_INVALID(x) \ 2459 (GET_FLAG(x.flags, \ 2460 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2461 (T_ETH_MAC_COMMAND_INVALIDATE)) 2462 2463 /* Number of u32 elements in MC hash array */ 2464 #define MC_HASH_SIZE 8 2465 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2466 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2467 2468 #ifndef PXP2_REG_PXP2_INT_STS 2469 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2470 #endif 2471 2472 #ifndef ETH_MAX_RX_CLIENTS_E2 2473 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2474 #endif 2475 2476 #define BNX2X_VPD_LEN 128 2477 #define VENDOR_ID_LEN 4 2478 2479 #define VF_ACQUIRE_THRESH 3 2480 #define VF_ACQUIRE_MAC_FILTERS 1 2481 #define VF_ACQUIRE_MC_FILTERS 10 2482 2483 #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \ 2484 (!((me_reg) & ME_REG_VF_ERR))) 2485 int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err); 2486 2487 /* Congestion management fairness mode */ 2488 #define CMNG_FNS_NONE 0 2489 #define CMNG_FNS_MINMAX 1 2490 2491 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2492 #define HC_SEG_ACCESS_ATTN 4 2493 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2494 2495 static const u32 dmae_reg_go_c[] = { 2496 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2497 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2498 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2499 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2500 }; 2501 2502 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev); 2503 void bnx2x_notify_link_changed(struct bnx2x *bp); 2504 2505 #define BNX2X_MF_SD_PROTOCOL(bp) \ 2506 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2507 2508 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ 2509 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2510 2511 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ 2512 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE) 2513 2514 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) 2515 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) 2516 #define IS_MF_ISCSI_SI(bp) (IS_MF_SI(bp) && BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp)) 2517 2518 #define IS_MF_ISCSI_ONLY(bp) (IS_MF_ISCSI_SD(bp) || IS_MF_ISCSI_SI(bp)) 2519 2520 #define BNX2X_MF_EXT_PROTOCOL_MASK \ 2521 (MACP_FUNC_CFG_FLAGS_ETHERNET | \ 2522 MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD | \ 2523 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2524 2525 #define BNX2X_MF_EXT_PROT(bp) ((bp)->mf_ext_config & \ 2526 BNX2X_MF_EXT_PROTOCOL_MASK) 2527 2528 #define BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp) \ 2529 (BNX2X_MF_EXT_PROT(bp) & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2530 2531 #define BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp) \ 2532 (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2533 2534 #define BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) \ 2535 (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) 2536 2537 #define IS_MF_FCOE_AFEX(bp) \ 2538 (IS_MF_AFEX(bp) && BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp)) 2539 2540 #define IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) \ 2541 (IS_MF_SD(bp) && \ 2542 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \ 2543 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 2544 2545 #define IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp) \ 2546 (IS_MF_SI(bp) && \ 2547 (BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) || \ 2548 BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp))) 2549 2550 #define IS_MF_STORAGE_PERSONALITY_ONLY(bp) \ 2551 (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) || \ 2552 IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp)) 2553 2554 2555 #define SET_FLAG(value, mask, flag) \ 2556 do {\ 2557 (value) &= ~(mask);\ 2558 (value) |= ((flag) << (mask##_SHIFT));\ 2559 } while (0) 2560 2561 #define GET_FLAG(value, mask) \ 2562 (((value) & (mask)) >> (mask##_SHIFT)) 2563 2564 #define GET_FIELD(value, fname) \ 2565 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 2566 2567 enum { 2568 SWITCH_UPDATE, 2569 AFEX_UPDATE, 2570 }; 2571 2572 #define NUM_MACS 8 2573 2574 void bnx2x_set_local_cmng(struct bnx2x *bp); 2575 2576 void bnx2x_update_mng_version(struct bnx2x *bp); 2577 2578 #define MCPR_SCRATCH_BASE(bp) \ 2579 (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 2580 2581 #define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX)) 2582 2583 void bnx2x_init_ptp(struct bnx2x *bp); 2584 int bnx2x_configure_ptp_filters(struct bnx2x *bp); 2585 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb); 2586 2587 #define BNX2X_MAX_PHC_DRIFT 31000000 2588 #define BNX2X_PTP_TX_TIMEOUT 2589 2590 #endif /* bnx2x.h */ 2591