1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/module.h> 118 #include <linux/device.h> 119 #include <linux/pci.h> 120 #include <linux/log2.h> 121 122 #include "xgbe.h" 123 #include "xgbe-common.h" 124 125 static int xgbe_config_msi(struct xgbe_prv_data *pdata) 126 { 127 unsigned int msi_count; 128 unsigned int i, j; 129 int ret; 130 131 msi_count = XGBE_MSIX_BASE_COUNT; 132 msi_count += max(pdata->rx_ring_count, 133 pdata->tx_ring_count); 134 msi_count = roundup_pow_of_two(msi_count); 135 136 ret = pci_enable_msi_exact(pdata->pcidev, msi_count); 137 if (ret < 0) { 138 dev_info(pdata->dev, "MSI request for %u interrupts failed\n", 139 msi_count); 140 141 ret = pci_enable_msi(pdata->pcidev); 142 if (ret < 0) { 143 dev_info(pdata->dev, "MSI enablement failed\n"); 144 return ret; 145 } 146 147 msi_count = 1; 148 } 149 150 pdata->irq_count = msi_count; 151 152 pdata->dev_irq = pdata->pcidev->irq; 153 154 if (msi_count > 1) { 155 pdata->ecc_irq = pdata->pcidev->irq + 1; 156 pdata->i2c_irq = pdata->pcidev->irq + 2; 157 pdata->an_irq = pdata->pcidev->irq + 3; 158 159 for (i = XGBE_MSIX_BASE_COUNT, j = 0; 160 (i < msi_count) && (j < XGBE_MAX_DMA_CHANNELS); 161 i++, j++) 162 pdata->channel_irq[j] = pdata->pcidev->irq + i; 163 pdata->channel_irq_count = j; 164 165 pdata->per_channel_irq = 1; 166 pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL; 167 } else { 168 pdata->ecc_irq = pdata->pcidev->irq; 169 pdata->i2c_irq = pdata->pcidev->irq; 170 pdata->an_irq = pdata->pcidev->irq; 171 } 172 173 if (netif_msg_probe(pdata)) 174 dev_dbg(pdata->dev, "MSI interrupts enabled\n"); 175 176 return 0; 177 } 178 179 static int xgbe_config_msix(struct xgbe_prv_data *pdata) 180 { 181 unsigned int msix_count; 182 unsigned int i, j; 183 int ret; 184 185 msix_count = XGBE_MSIX_BASE_COUNT; 186 msix_count += max(pdata->rx_ring_count, 187 pdata->tx_ring_count); 188 189 pdata->msix_entries = devm_kcalloc(pdata->dev, msix_count, 190 sizeof(struct msix_entry), 191 GFP_KERNEL); 192 if (!pdata->msix_entries) 193 return -ENOMEM; 194 195 for (i = 0; i < msix_count; i++) 196 pdata->msix_entries[i].entry = i; 197 198 ret = pci_enable_msix_range(pdata->pcidev, pdata->msix_entries, 199 XGBE_MSIX_MIN_COUNT, msix_count); 200 if (ret < 0) { 201 dev_info(pdata->dev, "MSI-X enablement failed\n"); 202 devm_kfree(pdata->dev, pdata->msix_entries); 203 pdata->msix_entries = NULL; 204 return ret; 205 } 206 207 pdata->irq_count = ret; 208 209 pdata->dev_irq = pdata->msix_entries[0].vector; 210 pdata->ecc_irq = pdata->msix_entries[1].vector; 211 pdata->i2c_irq = pdata->msix_entries[2].vector; 212 pdata->an_irq = pdata->msix_entries[3].vector; 213 214 for (i = XGBE_MSIX_BASE_COUNT, j = 0; i < ret; i++, j++) 215 pdata->channel_irq[j] = pdata->msix_entries[i].vector; 216 pdata->channel_irq_count = j; 217 218 pdata->per_channel_irq = 1; 219 pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL; 220 221 if (netif_msg_probe(pdata)) 222 dev_dbg(pdata->dev, "MSI-X interrupts enabled\n"); 223 224 return 0; 225 } 226 227 static int xgbe_config_irqs(struct xgbe_prv_data *pdata) 228 { 229 int ret; 230 231 ret = xgbe_config_msix(pdata); 232 if (!ret) 233 goto out; 234 235 ret = xgbe_config_msi(pdata); 236 if (!ret) 237 goto out; 238 239 pdata->irq_count = 1; 240 pdata->irq_shared = 1; 241 242 pdata->dev_irq = pdata->pcidev->irq; 243 pdata->ecc_irq = pdata->pcidev->irq; 244 pdata->i2c_irq = pdata->pcidev->irq; 245 pdata->an_irq = pdata->pcidev->irq; 246 247 out: 248 if (netif_msg_probe(pdata)) { 249 unsigned int i; 250 251 dev_dbg(pdata->dev, " dev irq=%d\n", pdata->dev_irq); 252 dev_dbg(pdata->dev, " ecc irq=%d\n", pdata->ecc_irq); 253 dev_dbg(pdata->dev, " i2c irq=%d\n", pdata->i2c_irq); 254 dev_dbg(pdata->dev, " an irq=%d\n", pdata->an_irq); 255 for (i = 0; i < pdata->channel_irq_count; i++) 256 dev_dbg(pdata->dev, " dma%u irq=%d\n", 257 i, pdata->channel_irq[i]); 258 } 259 260 return 0; 261 } 262 263 static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 264 { 265 struct xgbe_prv_data *pdata; 266 struct device *dev = &pdev->dev; 267 void __iomem * const *iomap_table; 268 struct pci_dev *rdev; 269 unsigned int ma_lo, ma_hi; 270 unsigned int reg; 271 int bar_mask; 272 int ret; 273 274 pdata = xgbe_alloc_pdata(dev); 275 if (IS_ERR(pdata)) { 276 ret = PTR_ERR(pdata); 277 goto err_alloc; 278 } 279 280 pdata->pcidev = pdev; 281 pci_set_drvdata(pdev, pdata); 282 283 /* Get the version data */ 284 pdata->vdata = (struct xgbe_version_data *)id->driver_data; 285 286 ret = pcim_enable_device(pdev); 287 if (ret) { 288 dev_err(dev, "pcim_enable_device failed\n"); 289 goto err_pci_enable; 290 } 291 292 /* Obtain the mmio areas for the device */ 293 bar_mask = pci_select_bars(pdev, IORESOURCE_MEM); 294 ret = pcim_iomap_regions(pdev, bar_mask, XGBE_DRV_NAME); 295 if (ret) { 296 dev_err(dev, "pcim_iomap_regions failed\n"); 297 goto err_pci_enable; 298 } 299 300 iomap_table = pcim_iomap_table(pdev); 301 if (!iomap_table) { 302 dev_err(dev, "pcim_iomap_table failed\n"); 303 ret = -ENOMEM; 304 goto err_pci_enable; 305 } 306 307 pdata->xgmac_regs = iomap_table[XGBE_XGMAC_BAR]; 308 if (!pdata->xgmac_regs) { 309 dev_err(dev, "xgmac ioremap failed\n"); 310 ret = -ENOMEM; 311 goto err_pci_enable; 312 } 313 pdata->xprop_regs = pdata->xgmac_regs + XGBE_MAC_PROP_OFFSET; 314 pdata->xi2c_regs = pdata->xgmac_regs + XGBE_I2C_CTRL_OFFSET; 315 if (netif_msg_probe(pdata)) { 316 dev_dbg(dev, "xgmac_regs = %p\n", pdata->xgmac_regs); 317 dev_dbg(dev, "xprop_regs = %p\n", pdata->xprop_regs); 318 dev_dbg(dev, "xi2c_regs = %p\n", pdata->xi2c_regs); 319 } 320 321 pdata->xpcs_regs = iomap_table[XGBE_XPCS_BAR]; 322 if (!pdata->xpcs_regs) { 323 dev_err(dev, "xpcs ioremap failed\n"); 324 ret = -ENOMEM; 325 goto err_pci_enable; 326 } 327 if (netif_msg_probe(pdata)) 328 dev_dbg(dev, "xpcs_regs = %p\n", pdata->xpcs_regs); 329 330 /* Set the PCS indirect addressing definition registers */ 331 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); 332 if (rdev && 333 (rdev->vendor == PCI_VENDOR_ID_AMD) && (rdev->device == 0x15d0)) { 334 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF; 335 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT; 336 } else { 337 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; 338 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT; 339 } 340 pci_dev_put(rdev); 341 342 /* Configure the PCS indirect addressing support */ 343 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg); 344 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET); 345 pdata->xpcs_window <<= 6; 346 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE); 347 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7); 348 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1; 349 if (netif_msg_probe(pdata)) { 350 dev_dbg(dev, "xpcs window = %#010x\n", 351 pdata->xpcs_window); 352 dev_dbg(dev, "xpcs window size = %#010x\n", 353 pdata->xpcs_window_size); 354 dev_dbg(dev, "xpcs window mask = %#010x\n", 355 pdata->xpcs_window_mask); 356 } 357 358 pci_set_master(pdev); 359 360 /* Enable all interrupts in the hardware */ 361 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff); 362 363 /* Retrieve the MAC address */ 364 ma_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO); 365 ma_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI); 366 pdata->mac_addr[0] = ma_lo & 0xff; 367 pdata->mac_addr[1] = (ma_lo >> 8) & 0xff; 368 pdata->mac_addr[2] = (ma_lo >> 16) & 0xff; 369 pdata->mac_addr[3] = (ma_lo >> 24) & 0xff; 370 pdata->mac_addr[4] = ma_hi & 0xff; 371 pdata->mac_addr[5] = (ma_hi >> 8) & 0xff; 372 if (!XP_GET_BITS(ma_hi, XP_MAC_ADDR_HI, VALID) || 373 !is_valid_ether_addr(pdata->mac_addr)) { 374 dev_err(dev, "invalid mac address\n"); 375 ret = -EINVAL; 376 goto err_pci_enable; 377 } 378 379 /* Clock settings */ 380 pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ; 381 pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ; 382 383 /* Set the DMA coherency values */ 384 pdata->coherent = 1; 385 pdata->axdomain = XGBE_DMA_OS_AXDOMAIN; 386 pdata->arcache = XGBE_DMA_OS_ARCACHE; 387 pdata->awcache = XGBE_DMA_OS_AWCACHE; 388 389 /* Set the maximum channels and queues */ 390 reg = XP_IOREAD(pdata, XP_PROP_1); 391 pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA); 392 pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA); 393 pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES); 394 pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES); 395 if (netif_msg_probe(pdata)) { 396 dev_dbg(dev, "max tx/rx channel count = %u/%u\n", 397 pdata->tx_max_channel_count, 398 pdata->tx_max_channel_count); 399 dev_dbg(dev, "max tx/rx hw queue count = %u/%u\n", 400 pdata->tx_max_q_count, pdata->rx_max_q_count); 401 } 402 403 /* Set the hardware channel and queue counts */ 404 xgbe_set_counts(pdata); 405 406 /* Set the maximum fifo amounts */ 407 reg = XP_IOREAD(pdata, XP_PROP_2); 408 pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE); 409 pdata->tx_max_fifo_size *= 16384; 410 pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size, 411 pdata->vdata->tx_max_fifo_size); 412 pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE); 413 pdata->rx_max_fifo_size *= 16384; 414 pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size, 415 pdata->vdata->rx_max_fifo_size); 416 if (netif_msg_probe(pdata)) 417 dev_dbg(dev, "max tx/rx max fifo size = %u/%u\n", 418 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size); 419 420 /* Configure interrupt support */ 421 ret = xgbe_config_irqs(pdata); 422 if (ret) 423 goto err_pci_enable; 424 425 /* Configure the netdev resource */ 426 ret = xgbe_config_netdev(pdata); 427 if (ret) 428 goto err_pci_enable; 429 430 netdev_notice(pdata->netdev, "net device enabled\n"); 431 432 return 0; 433 434 err_pci_enable: 435 xgbe_free_pdata(pdata); 436 437 err_alloc: 438 dev_notice(dev, "net device not enabled\n"); 439 440 return ret; 441 } 442 443 static void xgbe_pci_remove(struct pci_dev *pdev) 444 { 445 struct xgbe_prv_data *pdata = pci_get_drvdata(pdev); 446 447 xgbe_deconfig_netdev(pdata); 448 449 xgbe_free_pdata(pdata); 450 } 451 452 #ifdef CONFIG_PM 453 static int xgbe_pci_suspend(struct pci_dev *pdev, pm_message_t state) 454 { 455 struct xgbe_prv_data *pdata = pci_get_drvdata(pdev); 456 struct net_device *netdev = pdata->netdev; 457 int ret = 0; 458 459 if (netif_running(netdev)) 460 ret = xgbe_powerdown(netdev, XGMAC_DRIVER_CONTEXT); 461 462 pdata->lpm_ctrl = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); 463 pdata->lpm_ctrl |= MDIO_CTRL1_LPOWER; 464 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl); 465 466 return ret; 467 } 468 469 static int xgbe_pci_resume(struct pci_dev *pdev) 470 { 471 struct xgbe_prv_data *pdata = pci_get_drvdata(pdev); 472 struct net_device *netdev = pdata->netdev; 473 int ret = 0; 474 475 pdata->lpm_ctrl &= ~MDIO_CTRL1_LPOWER; 476 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl); 477 478 if (netif_running(netdev)) { 479 ret = xgbe_powerup(netdev, XGMAC_DRIVER_CONTEXT); 480 481 /* Schedule a restart in case the link or phy state changed 482 * while we were powered down. 483 */ 484 schedule_work(&pdata->restart_work); 485 } 486 487 return ret; 488 } 489 #endif /* CONFIG_PM */ 490 491 static const struct xgbe_version_data xgbe_v2a = { 492 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2, 493 .xpcs_access = XGBE_XPCS_ACCESS_V2, 494 .mmc_64bit = 1, 495 .tx_max_fifo_size = 229376, 496 .rx_max_fifo_size = 229376, 497 .tx_tstamp_workaround = 1, 498 .ecc_support = 1, 499 .i2c_support = 1, 500 }; 501 502 static const struct xgbe_version_data xgbe_v2b = { 503 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2, 504 .xpcs_access = XGBE_XPCS_ACCESS_V2, 505 .mmc_64bit = 1, 506 .tx_max_fifo_size = 65536, 507 .rx_max_fifo_size = 65536, 508 .tx_tstamp_workaround = 1, 509 .ecc_support = 1, 510 .i2c_support = 1, 511 }; 512 513 static const struct pci_device_id xgbe_pci_table[] = { 514 { PCI_VDEVICE(AMD, 0x1458), 515 .driver_data = (kernel_ulong_t)&xgbe_v2a }, 516 { PCI_VDEVICE(AMD, 0x1459), 517 .driver_data = (kernel_ulong_t)&xgbe_v2b }, 518 /* Last entry must be zero */ 519 { 0, } 520 }; 521 MODULE_DEVICE_TABLE(pci, xgbe_pci_table); 522 523 static struct pci_driver xgbe_driver = { 524 .name = XGBE_DRV_NAME, 525 .id_table = xgbe_pci_table, 526 .probe = xgbe_pci_probe, 527 .remove = xgbe_pci_remove, 528 #ifdef CONFIG_PM 529 .suspend = xgbe_pci_suspend, 530 .resume = xgbe_pci_resume, 531 #endif 532 }; 533 534 int xgbe_pci_init(void) 535 { 536 return pci_register_driver(&xgbe_driver); 537 } 538 539 void xgbe_pci_exit(void) 540 { 541 pci_unregister_driver(&xgbe_driver); 542 } 543