18aa9ebccSVladimir Oltean // SPDX-License-Identifier: BSD-3-Clause 28aa9ebccSVladimir Oltean /* Copyright (c) 2016-2018, NXP Semiconductors 38aa9ebccSVladimir Oltean * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com> 48aa9ebccSVladimir Oltean */ 58aa9ebccSVladimir Oltean #include <linux/packing.h> 68aa9ebccSVladimir Oltean #include "sja1105.h" 78aa9ebccSVladimir Oltean 88aa9ebccSVladimir Oltean #define SJA1105_SIZE_CGU_CMD 4 98aa9ebccSVladimir Oltean 10135e3018SVladimir Oltean /* Common structure for CFG_PAD_MIIx_RX and CFG_PAD_MIIx_TX */ 11135e3018SVladimir Oltean struct sja1105_cfg_pad_mii { 128aa9ebccSVladimir Oltean u64 d32_os; 13135e3018SVladimir Oltean u64 d32_ih; 148aa9ebccSVladimir Oltean u64 d32_ipud; 15135e3018SVladimir Oltean u64 d10_ih; 168aa9ebccSVladimir Oltean u64 d10_os; 178aa9ebccSVladimir Oltean u64 d10_ipud; 188aa9ebccSVladimir Oltean u64 ctrl_os; 19135e3018SVladimir Oltean u64 ctrl_ih; 208aa9ebccSVladimir Oltean u64 ctrl_ipud; 218aa9ebccSVladimir Oltean u64 clk_os; 228aa9ebccSVladimir Oltean u64 clk_ih; 238aa9ebccSVladimir Oltean u64 clk_ipud; 248aa9ebccSVladimir Oltean }; 258aa9ebccSVladimir Oltean 26c05ec3d4SVladimir Oltean struct sja1105_cfg_pad_mii_id { 27c05ec3d4SVladimir Oltean u64 rxc_stable_ovr; 28c05ec3d4SVladimir Oltean u64 rxc_delay; 29c05ec3d4SVladimir Oltean u64 rxc_bypass; 30c05ec3d4SVladimir Oltean u64 rxc_pd; 31c05ec3d4SVladimir Oltean u64 txc_stable_ovr; 32c05ec3d4SVladimir Oltean u64 txc_delay; 33c05ec3d4SVladimir Oltean u64 txc_bypass; 34c05ec3d4SVladimir Oltean u64 txc_pd; 35c05ec3d4SVladimir Oltean }; 36c05ec3d4SVladimir Oltean 378aa9ebccSVladimir Oltean /* UM10944 Table 82. 388aa9ebccSVladimir Oltean * IDIV_0_C to IDIV_4_C control registers 398aa9ebccSVladimir Oltean * (addr. 10000Bh to 10000Fh) 408aa9ebccSVladimir Oltean */ 418aa9ebccSVladimir Oltean struct sja1105_cgu_idiv { 428aa9ebccSVladimir Oltean u64 clksrc; 438aa9ebccSVladimir Oltean u64 autoblock; 448aa9ebccSVladimir Oltean u64 idiv; 458aa9ebccSVladimir Oltean u64 pd; 468aa9ebccSVladimir Oltean }; 478aa9ebccSVladimir Oltean 488aa9ebccSVladimir Oltean /* PLL_1_C control register 498aa9ebccSVladimir Oltean * 508aa9ebccSVladimir Oltean * SJA1105 E/T: UM10944 Table 81 (address 10000Ah) 518aa9ebccSVladimir Oltean * SJA1105 P/Q/R/S: UM11040 Table 116 (address 10000Ah) 528aa9ebccSVladimir Oltean */ 538aa9ebccSVladimir Oltean struct sja1105_cgu_pll_ctrl { 548aa9ebccSVladimir Oltean u64 pllclksrc; 558aa9ebccSVladimir Oltean u64 msel; 568aa9ebccSVladimir Oltean u64 autoblock; 578aa9ebccSVladimir Oltean u64 psel; 588aa9ebccSVladimir Oltean u64 direct; 598aa9ebccSVladimir Oltean u64 fbsel; 608aa9ebccSVladimir Oltean u64 bypass; 618aa9ebccSVladimir Oltean u64 pd; 628aa9ebccSVladimir Oltean }; 638aa9ebccSVladimir Oltean 648aa9ebccSVladimir Oltean enum { 658aa9ebccSVladimir Oltean CLKSRC_MII0_TX_CLK = 0x00, 668aa9ebccSVladimir Oltean CLKSRC_MII0_RX_CLK = 0x01, 678aa9ebccSVladimir Oltean CLKSRC_MII1_TX_CLK = 0x02, 688aa9ebccSVladimir Oltean CLKSRC_MII1_RX_CLK = 0x03, 698aa9ebccSVladimir Oltean CLKSRC_MII2_TX_CLK = 0x04, 708aa9ebccSVladimir Oltean CLKSRC_MII2_RX_CLK = 0x05, 718aa9ebccSVladimir Oltean CLKSRC_MII3_TX_CLK = 0x06, 728aa9ebccSVladimir Oltean CLKSRC_MII3_RX_CLK = 0x07, 738aa9ebccSVladimir Oltean CLKSRC_MII4_TX_CLK = 0x08, 748aa9ebccSVladimir Oltean CLKSRC_MII4_RX_CLK = 0x09, 758aa9ebccSVladimir Oltean CLKSRC_PLL0 = 0x0B, 768aa9ebccSVladimir Oltean CLKSRC_PLL1 = 0x0E, 778aa9ebccSVladimir Oltean CLKSRC_IDIV0 = 0x11, 788aa9ebccSVladimir Oltean CLKSRC_IDIV1 = 0x12, 798aa9ebccSVladimir Oltean CLKSRC_IDIV2 = 0x13, 808aa9ebccSVladimir Oltean CLKSRC_IDIV3 = 0x14, 818aa9ebccSVladimir Oltean CLKSRC_IDIV4 = 0x15, 828aa9ebccSVladimir Oltean }; 838aa9ebccSVladimir Oltean 848aa9ebccSVladimir Oltean /* UM10944 Table 83. 858aa9ebccSVladimir Oltean * MIIx clock control registers 1 to 30 868aa9ebccSVladimir Oltean * (addresses 100013h to 100035h) 878aa9ebccSVladimir Oltean */ 888aa9ebccSVladimir Oltean struct sja1105_cgu_mii_ctrl { 898aa9ebccSVladimir Oltean u64 clksrc; 908aa9ebccSVladimir Oltean u64 autoblock; 918aa9ebccSVladimir Oltean u64 pd; 928aa9ebccSVladimir Oltean }; 938aa9ebccSVladimir Oltean 948aa9ebccSVladimir Oltean static void sja1105_cgu_idiv_packing(void *buf, struct sja1105_cgu_idiv *idiv, 958aa9ebccSVladimir Oltean enum packing_op op) 968aa9ebccSVladimir Oltean { 978aa9ebccSVladimir Oltean const int size = 4; 988aa9ebccSVladimir Oltean 998aa9ebccSVladimir Oltean sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op); 1008aa9ebccSVladimir Oltean sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op); 1018aa9ebccSVladimir Oltean sja1105_packing(buf, &idiv->idiv, 5, 2, size, op); 1028aa9ebccSVladimir Oltean sja1105_packing(buf, &idiv->pd, 0, 0, size, op); 1038aa9ebccSVladimir Oltean } 1048aa9ebccSVladimir Oltean 1058aa9ebccSVladimir Oltean static int sja1105_cgu_idiv_config(struct sja1105_private *priv, int port, 1068aa9ebccSVladimir Oltean bool enabled, int factor) 1078aa9ebccSVladimir Oltean { 1088aa9ebccSVladimir Oltean const struct sja1105_regs *regs = priv->info->regs; 1098aa9ebccSVladimir Oltean struct device *dev = priv->ds->dev; 1108aa9ebccSVladimir Oltean struct sja1105_cgu_idiv idiv; 1118aa9ebccSVladimir Oltean u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 1128aa9ebccSVladimir Oltean 113*c5037678SVladimir Oltean if (regs->cgu_idiv[port] == SJA1105_RSV_ADDR) 114*c5037678SVladimir Oltean return 0; 115*c5037678SVladimir Oltean 1168aa9ebccSVladimir Oltean if (enabled && factor != 1 && factor != 10) { 1178aa9ebccSVladimir Oltean dev_err(dev, "idiv factor must be 1 or 10\n"); 1188aa9ebccSVladimir Oltean return -ERANGE; 1198aa9ebccSVladimir Oltean } 1208aa9ebccSVladimir Oltean 1218aa9ebccSVladimir Oltean /* Payload for packed_buf */ 1228aa9ebccSVladimir Oltean idiv.clksrc = 0x0A; /* 25MHz */ 1238aa9ebccSVladimir Oltean idiv.autoblock = 1; /* Block clk automatically */ 1248aa9ebccSVladimir Oltean idiv.idiv = factor - 1; /* Divide by 1 or 10 */ 1258aa9ebccSVladimir Oltean idiv.pd = enabled ? 0 : 1; /* Power down? */ 1268aa9ebccSVladimir Oltean sja1105_cgu_idiv_packing(packed_buf, &idiv, PACK); 1278aa9ebccSVladimir Oltean 1281bd44870SVladimir Oltean return sja1105_xfer_buf(priv, SPI_WRITE, regs->cgu_idiv[port], 1291bd44870SVladimir Oltean packed_buf, SJA1105_SIZE_CGU_CMD); 1308aa9ebccSVladimir Oltean } 1318aa9ebccSVladimir Oltean 1328aa9ebccSVladimir Oltean static void 1338aa9ebccSVladimir Oltean sja1105_cgu_mii_control_packing(void *buf, struct sja1105_cgu_mii_ctrl *cmd, 1348aa9ebccSVladimir Oltean enum packing_op op) 1358aa9ebccSVladimir Oltean { 1368aa9ebccSVladimir Oltean const int size = 4; 1378aa9ebccSVladimir Oltean 1388aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->clksrc, 28, 24, size, op); 1398aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->autoblock, 11, 11, size, op); 1408aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->pd, 0, 0, size, op); 1418aa9ebccSVladimir Oltean } 1428aa9ebccSVladimir Oltean 1438aa9ebccSVladimir Oltean static int sja1105_cgu_mii_tx_clk_config(struct sja1105_private *priv, 1448aa9ebccSVladimir Oltean int port, sja1105_mii_role_t role) 1458aa9ebccSVladimir Oltean { 1468aa9ebccSVladimir Oltean const struct sja1105_regs *regs = priv->info->regs; 1478aa9ebccSVladimir Oltean struct sja1105_cgu_mii_ctrl mii_tx_clk; 1488aa9ebccSVladimir Oltean const int mac_clk_sources[] = { 1498aa9ebccSVladimir Oltean CLKSRC_MII0_TX_CLK, 1508aa9ebccSVladimir Oltean CLKSRC_MII1_TX_CLK, 1518aa9ebccSVladimir Oltean CLKSRC_MII2_TX_CLK, 1528aa9ebccSVladimir Oltean CLKSRC_MII3_TX_CLK, 1538aa9ebccSVladimir Oltean CLKSRC_MII4_TX_CLK, 1548aa9ebccSVladimir Oltean }; 1558aa9ebccSVladimir Oltean const int phy_clk_sources[] = { 1568aa9ebccSVladimir Oltean CLKSRC_IDIV0, 1578aa9ebccSVladimir Oltean CLKSRC_IDIV1, 1588aa9ebccSVladimir Oltean CLKSRC_IDIV2, 1598aa9ebccSVladimir Oltean CLKSRC_IDIV3, 1608aa9ebccSVladimir Oltean CLKSRC_IDIV4, 1618aa9ebccSVladimir Oltean }; 1628aa9ebccSVladimir Oltean u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 1638aa9ebccSVladimir Oltean int clksrc; 1648aa9ebccSVladimir Oltean 165*c5037678SVladimir Oltean if (regs->mii_tx_clk[port] == SJA1105_RSV_ADDR) 166*c5037678SVladimir Oltean return 0; 167*c5037678SVladimir Oltean 1688aa9ebccSVladimir Oltean if (role == XMII_MAC) 1698aa9ebccSVladimir Oltean clksrc = mac_clk_sources[port]; 1708aa9ebccSVladimir Oltean else 1718aa9ebccSVladimir Oltean clksrc = phy_clk_sources[port]; 1728aa9ebccSVladimir Oltean 1738aa9ebccSVladimir Oltean /* Payload for packed_buf */ 1748aa9ebccSVladimir Oltean mii_tx_clk.clksrc = clksrc; 1758aa9ebccSVladimir Oltean mii_tx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */ 1768aa9ebccSVladimir Oltean mii_tx_clk.pd = 0; /* Power Down off => enabled */ 1778aa9ebccSVladimir Oltean sja1105_cgu_mii_control_packing(packed_buf, &mii_tx_clk, PACK); 1788aa9ebccSVladimir Oltean 1791bd44870SVladimir Oltean return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_tx_clk[port], 1801bd44870SVladimir Oltean packed_buf, SJA1105_SIZE_CGU_CMD); 1818aa9ebccSVladimir Oltean } 1828aa9ebccSVladimir Oltean 1838aa9ebccSVladimir Oltean static int 1848aa9ebccSVladimir Oltean sja1105_cgu_mii_rx_clk_config(struct sja1105_private *priv, int port) 1858aa9ebccSVladimir Oltean { 1868aa9ebccSVladimir Oltean const struct sja1105_regs *regs = priv->info->regs; 1878aa9ebccSVladimir Oltean struct sja1105_cgu_mii_ctrl mii_rx_clk; 1888aa9ebccSVladimir Oltean u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 1898aa9ebccSVladimir Oltean const int clk_sources[] = { 1908aa9ebccSVladimir Oltean CLKSRC_MII0_RX_CLK, 1918aa9ebccSVladimir Oltean CLKSRC_MII1_RX_CLK, 1928aa9ebccSVladimir Oltean CLKSRC_MII2_RX_CLK, 1938aa9ebccSVladimir Oltean CLKSRC_MII3_RX_CLK, 1948aa9ebccSVladimir Oltean CLKSRC_MII4_RX_CLK, 1958aa9ebccSVladimir Oltean }; 1968aa9ebccSVladimir Oltean 197*c5037678SVladimir Oltean if (regs->mii_rx_clk[port] == SJA1105_RSV_ADDR) 198*c5037678SVladimir Oltean return 0; 199*c5037678SVladimir Oltean 2008aa9ebccSVladimir Oltean /* Payload for packed_buf */ 2018aa9ebccSVladimir Oltean mii_rx_clk.clksrc = clk_sources[port]; 2028aa9ebccSVladimir Oltean mii_rx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */ 2038aa9ebccSVladimir Oltean mii_rx_clk.pd = 0; /* Power Down off => enabled */ 2048aa9ebccSVladimir Oltean sja1105_cgu_mii_control_packing(packed_buf, &mii_rx_clk, PACK); 2058aa9ebccSVladimir Oltean 2061bd44870SVladimir Oltean return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_rx_clk[port], 2071bd44870SVladimir Oltean packed_buf, SJA1105_SIZE_CGU_CMD); 2088aa9ebccSVladimir Oltean } 2098aa9ebccSVladimir Oltean 2108aa9ebccSVladimir Oltean static int 2118aa9ebccSVladimir Oltean sja1105_cgu_mii_ext_tx_clk_config(struct sja1105_private *priv, int port) 2128aa9ebccSVladimir Oltean { 2138aa9ebccSVladimir Oltean const struct sja1105_regs *regs = priv->info->regs; 2148aa9ebccSVladimir Oltean struct sja1105_cgu_mii_ctrl mii_ext_tx_clk; 2158aa9ebccSVladimir Oltean u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 2168aa9ebccSVladimir Oltean const int clk_sources[] = { 2178aa9ebccSVladimir Oltean CLKSRC_IDIV0, 2188aa9ebccSVladimir Oltean CLKSRC_IDIV1, 2198aa9ebccSVladimir Oltean CLKSRC_IDIV2, 2208aa9ebccSVladimir Oltean CLKSRC_IDIV3, 2218aa9ebccSVladimir Oltean CLKSRC_IDIV4, 2228aa9ebccSVladimir Oltean }; 2238aa9ebccSVladimir Oltean 224*c5037678SVladimir Oltean if (regs->mii_ext_tx_clk[port] == SJA1105_RSV_ADDR) 225*c5037678SVladimir Oltean return 0; 226*c5037678SVladimir Oltean 2278aa9ebccSVladimir Oltean /* Payload for packed_buf */ 2288aa9ebccSVladimir Oltean mii_ext_tx_clk.clksrc = clk_sources[port]; 2298aa9ebccSVladimir Oltean mii_ext_tx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */ 2308aa9ebccSVladimir Oltean mii_ext_tx_clk.pd = 0; /* Power Down off => enabled */ 2318aa9ebccSVladimir Oltean sja1105_cgu_mii_control_packing(packed_buf, &mii_ext_tx_clk, PACK); 2328aa9ebccSVladimir Oltean 2331bd44870SVladimir Oltean return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_tx_clk[port], 2348aa9ebccSVladimir Oltean packed_buf, SJA1105_SIZE_CGU_CMD); 2358aa9ebccSVladimir Oltean } 2368aa9ebccSVladimir Oltean 2378aa9ebccSVladimir Oltean static int 2388aa9ebccSVladimir Oltean sja1105_cgu_mii_ext_rx_clk_config(struct sja1105_private *priv, int port) 2398aa9ebccSVladimir Oltean { 2408aa9ebccSVladimir Oltean const struct sja1105_regs *regs = priv->info->regs; 2418aa9ebccSVladimir Oltean struct sja1105_cgu_mii_ctrl mii_ext_rx_clk; 2428aa9ebccSVladimir Oltean u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 2438aa9ebccSVladimir Oltean const int clk_sources[] = { 2448aa9ebccSVladimir Oltean CLKSRC_IDIV0, 2458aa9ebccSVladimir Oltean CLKSRC_IDIV1, 2468aa9ebccSVladimir Oltean CLKSRC_IDIV2, 2478aa9ebccSVladimir Oltean CLKSRC_IDIV3, 2488aa9ebccSVladimir Oltean CLKSRC_IDIV4, 2498aa9ebccSVladimir Oltean }; 2508aa9ebccSVladimir Oltean 251*c5037678SVladimir Oltean if (regs->mii_ext_rx_clk[port] == SJA1105_RSV_ADDR) 252*c5037678SVladimir Oltean return 0; 253*c5037678SVladimir Oltean 2548aa9ebccSVladimir Oltean /* Payload for packed_buf */ 2558aa9ebccSVladimir Oltean mii_ext_rx_clk.clksrc = clk_sources[port]; 2568aa9ebccSVladimir Oltean mii_ext_rx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */ 2578aa9ebccSVladimir Oltean mii_ext_rx_clk.pd = 0; /* Power Down off => enabled */ 2588aa9ebccSVladimir Oltean sja1105_cgu_mii_control_packing(packed_buf, &mii_ext_rx_clk, PACK); 2598aa9ebccSVladimir Oltean 2601bd44870SVladimir Oltean return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_rx_clk[port], 2618aa9ebccSVladimir Oltean packed_buf, SJA1105_SIZE_CGU_CMD); 2628aa9ebccSVladimir Oltean } 2638aa9ebccSVladimir Oltean 2648aa9ebccSVladimir Oltean static int sja1105_mii_clocking_setup(struct sja1105_private *priv, int port, 2658aa9ebccSVladimir Oltean sja1105_mii_role_t role) 2668aa9ebccSVladimir Oltean { 2678aa9ebccSVladimir Oltean struct device *dev = priv->ds->dev; 2688aa9ebccSVladimir Oltean int rc; 2698aa9ebccSVladimir Oltean 2708aa9ebccSVladimir Oltean dev_dbg(dev, "Configuring MII-%s clocking\n", 2718aa9ebccSVladimir Oltean (role == XMII_MAC) ? "MAC" : "PHY"); 2728aa9ebccSVladimir Oltean /* If role is MAC, disable IDIV 2738aa9ebccSVladimir Oltean * If role is PHY, enable IDIV and configure for 1/1 divider 2748aa9ebccSVladimir Oltean */ 2758aa9ebccSVladimir Oltean rc = sja1105_cgu_idiv_config(priv, port, (role == XMII_PHY), 1); 2768aa9ebccSVladimir Oltean if (rc < 0) 2778aa9ebccSVladimir Oltean return rc; 2788aa9ebccSVladimir Oltean 2798aa9ebccSVladimir Oltean /* Configure CLKSRC of MII_TX_CLK_n 2808aa9ebccSVladimir Oltean * * If role is MAC, select TX_CLK_n 2818aa9ebccSVladimir Oltean * * If role is PHY, select IDIV_n 2828aa9ebccSVladimir Oltean */ 2838aa9ebccSVladimir Oltean rc = sja1105_cgu_mii_tx_clk_config(priv, port, role); 2848aa9ebccSVladimir Oltean if (rc < 0) 2858aa9ebccSVladimir Oltean return rc; 2868aa9ebccSVladimir Oltean 2878aa9ebccSVladimir Oltean /* Configure CLKSRC of MII_RX_CLK_n 2888aa9ebccSVladimir Oltean * Select RX_CLK_n 2898aa9ebccSVladimir Oltean */ 2908aa9ebccSVladimir Oltean rc = sja1105_cgu_mii_rx_clk_config(priv, port); 2918aa9ebccSVladimir Oltean if (rc < 0) 2928aa9ebccSVladimir Oltean return rc; 2938aa9ebccSVladimir Oltean 2948aa9ebccSVladimir Oltean if (role == XMII_PHY) { 2958aa9ebccSVladimir Oltean /* Per MII spec, the PHY (which is us) drives the TX_CLK pin */ 2968aa9ebccSVladimir Oltean 2978aa9ebccSVladimir Oltean /* Configure CLKSRC of EXT_TX_CLK_n 2988aa9ebccSVladimir Oltean * Select IDIV_n 2998aa9ebccSVladimir Oltean */ 3008aa9ebccSVladimir Oltean rc = sja1105_cgu_mii_ext_tx_clk_config(priv, port); 3018aa9ebccSVladimir Oltean if (rc < 0) 3028aa9ebccSVladimir Oltean return rc; 3038aa9ebccSVladimir Oltean 3048aa9ebccSVladimir Oltean /* Configure CLKSRC of EXT_RX_CLK_n 3058aa9ebccSVladimir Oltean * Select IDIV_n 3068aa9ebccSVladimir Oltean */ 3078aa9ebccSVladimir Oltean rc = sja1105_cgu_mii_ext_rx_clk_config(priv, port); 3088aa9ebccSVladimir Oltean if (rc < 0) 3098aa9ebccSVladimir Oltean return rc; 3108aa9ebccSVladimir Oltean } 3118aa9ebccSVladimir Oltean return 0; 3128aa9ebccSVladimir Oltean } 3138aa9ebccSVladimir Oltean 3148aa9ebccSVladimir Oltean static void 3158aa9ebccSVladimir Oltean sja1105_cgu_pll_control_packing(void *buf, struct sja1105_cgu_pll_ctrl *cmd, 3168aa9ebccSVladimir Oltean enum packing_op op) 3178aa9ebccSVladimir Oltean { 3188aa9ebccSVladimir Oltean const int size = 4; 3198aa9ebccSVladimir Oltean 3208aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->pllclksrc, 28, 24, size, op); 3218aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->msel, 23, 16, size, op); 3228aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->autoblock, 11, 11, size, op); 3238aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->psel, 9, 8, size, op); 3248aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->direct, 7, 7, size, op); 3258aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->fbsel, 6, 6, size, op); 3268aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->bypass, 1, 1, size, op); 3278aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->pd, 0, 0, size, op); 3288aa9ebccSVladimir Oltean } 3298aa9ebccSVladimir Oltean 3308aa9ebccSVladimir Oltean static int sja1105_cgu_rgmii_tx_clk_config(struct sja1105_private *priv, 3318aa9ebccSVladimir Oltean int port, sja1105_speed_t speed) 3328aa9ebccSVladimir Oltean { 3338aa9ebccSVladimir Oltean const struct sja1105_regs *regs = priv->info->regs; 3348aa9ebccSVladimir Oltean struct sja1105_cgu_mii_ctrl txc; 3358aa9ebccSVladimir Oltean u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 3368aa9ebccSVladimir Oltean int clksrc; 3378aa9ebccSVladimir Oltean 338*c5037678SVladimir Oltean if (regs->rgmii_tx_clk[port] == SJA1105_RSV_ADDR) 339*c5037678SVladimir Oltean return 0; 340*c5037678SVladimir Oltean 3418aa9ebccSVladimir Oltean if (speed == SJA1105_SPEED_1000MBPS) { 3428aa9ebccSVladimir Oltean clksrc = CLKSRC_PLL0; 3438aa9ebccSVladimir Oltean } else { 3448aa9ebccSVladimir Oltean int clk_sources[] = {CLKSRC_IDIV0, CLKSRC_IDIV1, CLKSRC_IDIV2, 3458aa9ebccSVladimir Oltean CLKSRC_IDIV3, CLKSRC_IDIV4}; 3468aa9ebccSVladimir Oltean clksrc = clk_sources[port]; 3478aa9ebccSVladimir Oltean } 3488aa9ebccSVladimir Oltean 3498aa9ebccSVladimir Oltean /* RGMII: 125MHz for 1000, 25MHz for 100, 2.5MHz for 10 */ 3508aa9ebccSVladimir Oltean txc.clksrc = clksrc; 3518aa9ebccSVladimir Oltean /* Autoblock clk while changing clksrc */ 3528aa9ebccSVladimir Oltean txc.autoblock = 1; 3538aa9ebccSVladimir Oltean /* Power Down off => enabled */ 3548aa9ebccSVladimir Oltean txc.pd = 0; 3558aa9ebccSVladimir Oltean sja1105_cgu_mii_control_packing(packed_buf, &txc, PACK); 3568aa9ebccSVladimir Oltean 3571bd44870SVladimir Oltean return sja1105_xfer_buf(priv, SPI_WRITE, regs->rgmii_tx_clk[port], 3588aa9ebccSVladimir Oltean packed_buf, SJA1105_SIZE_CGU_CMD); 3598aa9ebccSVladimir Oltean } 3608aa9ebccSVladimir Oltean 3618aa9ebccSVladimir Oltean /* AGU */ 3628aa9ebccSVladimir Oltean static void 363135e3018SVladimir Oltean sja1105_cfg_pad_mii_packing(void *buf, struct sja1105_cfg_pad_mii *cmd, 3648aa9ebccSVladimir Oltean enum packing_op op) 3658aa9ebccSVladimir Oltean { 3668aa9ebccSVladimir Oltean const int size = 4; 3678aa9ebccSVladimir Oltean 3688aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->d32_os, 28, 27, size, op); 369135e3018SVladimir Oltean sja1105_packing(buf, &cmd->d32_ih, 26, 26, size, op); 3708aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->d32_ipud, 25, 24, size, op); 3718aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->d10_os, 20, 19, size, op); 372135e3018SVladimir Oltean sja1105_packing(buf, &cmd->d10_ih, 18, 18, size, op); 3738aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->d10_ipud, 17, 16, size, op); 3748aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->ctrl_os, 12, 11, size, op); 375135e3018SVladimir Oltean sja1105_packing(buf, &cmd->ctrl_ih, 10, 10, size, op); 3768aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->ctrl_ipud, 9, 8, size, op); 3778aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->clk_os, 4, 3, size, op); 3788aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->clk_ih, 2, 2, size, op); 3798aa9ebccSVladimir Oltean sja1105_packing(buf, &cmd->clk_ipud, 1, 0, size, op); 3808aa9ebccSVladimir Oltean } 3818aa9ebccSVladimir Oltean 3828aa9ebccSVladimir Oltean static int sja1105_rgmii_cfg_pad_tx_config(struct sja1105_private *priv, 3838aa9ebccSVladimir Oltean int port) 3848aa9ebccSVladimir Oltean { 3858aa9ebccSVladimir Oltean const struct sja1105_regs *regs = priv->info->regs; 386135e3018SVladimir Oltean struct sja1105_cfg_pad_mii pad_mii_tx = {0}; 3878aa9ebccSVladimir Oltean u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 3888aa9ebccSVladimir Oltean 389*c5037678SVladimir Oltean if (regs->pad_mii_tx[port] == SJA1105_RSV_ADDR) 390*c5037678SVladimir Oltean return 0; 391*c5037678SVladimir Oltean 3928aa9ebccSVladimir Oltean /* Payload */ 3938aa9ebccSVladimir Oltean pad_mii_tx.d32_os = 3; /* TXD[3:2] output stage: */ 3948aa9ebccSVladimir Oltean /* high noise/high speed */ 3958aa9ebccSVladimir Oltean pad_mii_tx.d10_os = 3; /* TXD[1:0] output stage: */ 3968aa9ebccSVladimir Oltean /* high noise/high speed */ 3978aa9ebccSVladimir Oltean pad_mii_tx.d32_ipud = 2; /* TXD[3:2] input stage: */ 3988aa9ebccSVladimir Oltean /* plain input (default) */ 3998aa9ebccSVladimir Oltean pad_mii_tx.d10_ipud = 2; /* TXD[1:0] input stage: */ 4008aa9ebccSVladimir Oltean /* plain input (default) */ 4018aa9ebccSVladimir Oltean pad_mii_tx.ctrl_os = 3; /* TX_CTL / TX_ER output stage */ 4028aa9ebccSVladimir Oltean pad_mii_tx.ctrl_ipud = 2; /* TX_CTL / TX_ER input stage (default) */ 4038aa9ebccSVladimir Oltean pad_mii_tx.clk_os = 3; /* TX_CLK output stage */ 4048aa9ebccSVladimir Oltean pad_mii_tx.clk_ih = 0; /* TX_CLK input hysteresis (default) */ 4058aa9ebccSVladimir Oltean pad_mii_tx.clk_ipud = 2; /* TX_CLK input stage (default) */ 406135e3018SVladimir Oltean sja1105_cfg_pad_mii_packing(packed_buf, &pad_mii_tx, PACK); 4078aa9ebccSVladimir Oltean 4081bd44870SVladimir Oltean return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_tx[port], 4098aa9ebccSVladimir Oltean packed_buf, SJA1105_SIZE_CGU_CMD); 4108aa9ebccSVladimir Oltean } 4118aa9ebccSVladimir Oltean 412135e3018SVladimir Oltean static int sja1105_cfg_pad_rx_config(struct sja1105_private *priv, int port) 413135e3018SVladimir Oltean { 414135e3018SVladimir Oltean const struct sja1105_regs *regs = priv->info->regs; 415135e3018SVladimir Oltean struct sja1105_cfg_pad_mii pad_mii_rx = {0}; 416135e3018SVladimir Oltean u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 417135e3018SVladimir Oltean 418*c5037678SVladimir Oltean if (regs->pad_mii_rx[port] == SJA1105_RSV_ADDR) 419*c5037678SVladimir Oltean return 0; 420*c5037678SVladimir Oltean 421135e3018SVladimir Oltean /* Payload */ 422135e3018SVladimir Oltean pad_mii_rx.d32_ih = 0; /* RXD[3:2] input stage hysteresis: */ 423135e3018SVladimir Oltean /* non-Schmitt (default) */ 424135e3018SVladimir Oltean pad_mii_rx.d32_ipud = 2; /* RXD[3:2] input weak pull-up/down */ 425135e3018SVladimir Oltean /* plain input (default) */ 426135e3018SVladimir Oltean pad_mii_rx.d10_ih = 0; /* RXD[1:0] input stage hysteresis: */ 427135e3018SVladimir Oltean /* non-Schmitt (default) */ 428135e3018SVladimir Oltean pad_mii_rx.d10_ipud = 2; /* RXD[1:0] input weak pull-up/down */ 429135e3018SVladimir Oltean /* plain input (default) */ 430135e3018SVladimir Oltean pad_mii_rx.ctrl_ih = 0; /* RX_DV/CRS_DV/RX_CTL and RX_ER */ 431135e3018SVladimir Oltean /* input stage hysteresis: */ 432135e3018SVladimir Oltean /* non-Schmitt (default) */ 433135e3018SVladimir Oltean pad_mii_rx.ctrl_ipud = 3; /* RX_DV/CRS_DV/RX_CTL and RX_ER */ 434135e3018SVladimir Oltean /* input stage weak pull-up/down: */ 435135e3018SVladimir Oltean /* pull-down */ 436135e3018SVladimir Oltean pad_mii_rx.clk_os = 2; /* RX_CLK/RXC output stage: */ 437135e3018SVladimir Oltean /* medium noise/fast speed (default) */ 438135e3018SVladimir Oltean pad_mii_rx.clk_ih = 0; /* RX_CLK/RXC input hysteresis: */ 439135e3018SVladimir Oltean /* non-Schmitt (default) */ 440135e3018SVladimir Oltean pad_mii_rx.clk_ipud = 2; /* RX_CLK/RXC input pull-up/down: */ 441135e3018SVladimir Oltean /* plain input (default) */ 442135e3018SVladimir Oltean sja1105_cfg_pad_mii_packing(packed_buf, &pad_mii_rx, PACK); 443135e3018SVladimir Oltean 444135e3018SVladimir Oltean return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_rx[port], 445135e3018SVladimir Oltean packed_buf, SJA1105_SIZE_CGU_CMD); 446135e3018SVladimir Oltean } 447135e3018SVladimir Oltean 448c05ec3d4SVladimir Oltean static void 449c05ec3d4SVladimir Oltean sja1105_cfg_pad_mii_id_packing(void *buf, struct sja1105_cfg_pad_mii_id *cmd, 450c05ec3d4SVladimir Oltean enum packing_op op) 451c05ec3d4SVladimir Oltean { 452c05ec3d4SVladimir Oltean const int size = SJA1105_SIZE_CGU_CMD; 453c05ec3d4SVladimir Oltean 454c05ec3d4SVladimir Oltean sja1105_packing(buf, &cmd->rxc_stable_ovr, 15, 15, size, op); 455c05ec3d4SVladimir Oltean sja1105_packing(buf, &cmd->rxc_delay, 14, 10, size, op); 456c05ec3d4SVladimir Oltean sja1105_packing(buf, &cmd->rxc_bypass, 9, 9, size, op); 457c05ec3d4SVladimir Oltean sja1105_packing(buf, &cmd->rxc_pd, 8, 8, size, op); 458c05ec3d4SVladimir Oltean sja1105_packing(buf, &cmd->txc_stable_ovr, 7, 7, size, op); 459c05ec3d4SVladimir Oltean sja1105_packing(buf, &cmd->txc_delay, 6, 2, size, op); 460c05ec3d4SVladimir Oltean sja1105_packing(buf, &cmd->txc_bypass, 1, 1, size, op); 461c05ec3d4SVladimir Oltean sja1105_packing(buf, &cmd->txc_pd, 0, 0, size, op); 462c05ec3d4SVladimir Oltean } 463c05ec3d4SVladimir Oltean 464c05ec3d4SVladimir Oltean /* Valid range in degrees is an integer between 73.8 and 101.7 */ 46509c1b412SVladimir Oltean static u64 sja1105_rgmii_delay(u64 phase) 466c05ec3d4SVladimir Oltean { 467c05ec3d4SVladimir Oltean /* UM11040.pdf: The delay in degree phase is 73.8 + delay_tune * 0.9. 468c05ec3d4SVladimir Oltean * To avoid floating point operations we'll multiply by 10 469c05ec3d4SVladimir Oltean * and get 1 decimal point precision. 470c05ec3d4SVladimir Oltean */ 471c05ec3d4SVladimir Oltean phase *= 10; 472c05ec3d4SVladimir Oltean return (phase - 738) / 9; 473c05ec3d4SVladimir Oltean } 474c05ec3d4SVladimir Oltean 475c05ec3d4SVladimir Oltean /* The RGMII delay setup procedure is 2-step and gets called upon each 476c05ec3d4SVladimir Oltean * .phylink_mac_config. Both are strategic. 477c05ec3d4SVladimir Oltean * The reason is that the RX Tunable Delay Line of the SJA1105 MAC has issues 478c05ec3d4SVladimir Oltean * with recovering from a frequency change of the link partner's RGMII clock. 479c05ec3d4SVladimir Oltean * The easiest way to recover from this is to temporarily power down the TDL, 480c05ec3d4SVladimir Oltean * as it will re-lock at the new frequency afterwards. 481c05ec3d4SVladimir Oltean */ 482c05ec3d4SVladimir Oltean int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port) 483c05ec3d4SVladimir Oltean { 484c05ec3d4SVladimir Oltean const struct sja1105_private *priv = ctx; 485c05ec3d4SVladimir Oltean const struct sja1105_regs *regs = priv->info->regs; 486c05ec3d4SVladimir Oltean struct sja1105_cfg_pad_mii_id pad_mii_id = {0}; 487c05ec3d4SVladimir Oltean u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 488c05ec3d4SVladimir Oltean int rc; 489c05ec3d4SVladimir Oltean 490c05ec3d4SVladimir Oltean if (priv->rgmii_rx_delay[port]) 491c05ec3d4SVladimir Oltean pad_mii_id.rxc_delay = sja1105_rgmii_delay(90); 492c05ec3d4SVladimir Oltean if (priv->rgmii_tx_delay[port]) 493c05ec3d4SVladimir Oltean pad_mii_id.txc_delay = sja1105_rgmii_delay(90); 494c05ec3d4SVladimir Oltean 495c05ec3d4SVladimir Oltean /* Stage 1: Turn the RGMII delay lines off. */ 496c05ec3d4SVladimir Oltean pad_mii_id.rxc_bypass = 1; 497c05ec3d4SVladimir Oltean pad_mii_id.rxc_pd = 1; 498c05ec3d4SVladimir Oltean pad_mii_id.txc_bypass = 1; 499c05ec3d4SVladimir Oltean pad_mii_id.txc_pd = 1; 500c05ec3d4SVladimir Oltean sja1105_cfg_pad_mii_id_packing(packed_buf, &pad_mii_id, PACK); 501c05ec3d4SVladimir Oltean 5021bd44870SVladimir Oltean rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port], 503c05ec3d4SVladimir Oltean packed_buf, SJA1105_SIZE_CGU_CMD); 504c05ec3d4SVladimir Oltean if (rc < 0) 505c05ec3d4SVladimir Oltean return rc; 506c05ec3d4SVladimir Oltean 507c05ec3d4SVladimir Oltean /* Stage 2: Turn the RGMII delay lines on. */ 508c05ec3d4SVladimir Oltean if (priv->rgmii_rx_delay[port]) { 509c05ec3d4SVladimir Oltean pad_mii_id.rxc_bypass = 0; 510c05ec3d4SVladimir Oltean pad_mii_id.rxc_pd = 0; 511c05ec3d4SVladimir Oltean } 512c05ec3d4SVladimir Oltean if (priv->rgmii_tx_delay[port]) { 513c05ec3d4SVladimir Oltean pad_mii_id.txc_bypass = 0; 514c05ec3d4SVladimir Oltean pad_mii_id.txc_pd = 0; 515c05ec3d4SVladimir Oltean } 516c05ec3d4SVladimir Oltean sja1105_cfg_pad_mii_id_packing(packed_buf, &pad_mii_id, PACK); 517c05ec3d4SVladimir Oltean 5181bd44870SVladimir Oltean return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port], 519c05ec3d4SVladimir Oltean packed_buf, SJA1105_SIZE_CGU_CMD); 520c05ec3d4SVladimir Oltean } 521c05ec3d4SVladimir Oltean 522c05ec3d4SVladimir Oltean static int sja1105_rgmii_clocking_setup(struct sja1105_private *priv, int port, 523c05ec3d4SVladimir Oltean sja1105_mii_role_t role) 5248aa9ebccSVladimir Oltean { 5258aa9ebccSVladimir Oltean struct device *dev = priv->ds->dev; 5268aa9ebccSVladimir Oltean struct sja1105_mac_config_entry *mac; 5278aa9ebccSVladimir Oltean sja1105_speed_t speed; 5288aa9ebccSVladimir Oltean int rc; 5298aa9ebccSVladimir Oltean 5308aa9ebccSVladimir Oltean mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; 5318aa9ebccSVladimir Oltean speed = mac[port].speed; 5328aa9ebccSVladimir Oltean 5338aa9ebccSVladimir Oltean dev_dbg(dev, "Configuring port %d RGMII at speed %dMbps\n", 5348aa9ebccSVladimir Oltean port, speed); 5358aa9ebccSVladimir Oltean 5368aa9ebccSVladimir Oltean switch (speed) { 5378aa9ebccSVladimir Oltean case SJA1105_SPEED_1000MBPS: 5388aa9ebccSVladimir Oltean /* 1000Mbps, IDIV disabled (125 MHz) */ 5398aa9ebccSVladimir Oltean rc = sja1105_cgu_idiv_config(priv, port, false, 1); 5408aa9ebccSVladimir Oltean break; 5418aa9ebccSVladimir Oltean case SJA1105_SPEED_100MBPS: 5428aa9ebccSVladimir Oltean /* 100Mbps, IDIV enabled, divide by 1 (25 MHz) */ 5438aa9ebccSVladimir Oltean rc = sja1105_cgu_idiv_config(priv, port, true, 1); 5448aa9ebccSVladimir Oltean break; 5458aa9ebccSVladimir Oltean case SJA1105_SPEED_10MBPS: 5468aa9ebccSVladimir Oltean /* 10Mbps, IDIV enabled, divide by 10 (2.5 MHz) */ 5478aa9ebccSVladimir Oltean rc = sja1105_cgu_idiv_config(priv, port, true, 10); 5488aa9ebccSVladimir Oltean break; 5498aa9ebccSVladimir Oltean case SJA1105_SPEED_AUTO: 5508aa9ebccSVladimir Oltean /* Skip CGU configuration if there is no speed available 5518aa9ebccSVladimir Oltean * (e.g. link is not established yet) 5528aa9ebccSVladimir Oltean */ 5538aa9ebccSVladimir Oltean dev_dbg(dev, "Speed not available, skipping CGU config\n"); 5548aa9ebccSVladimir Oltean return 0; 5558aa9ebccSVladimir Oltean default: 5568aa9ebccSVladimir Oltean rc = -EINVAL; 5578aa9ebccSVladimir Oltean } 5588aa9ebccSVladimir Oltean 5598aa9ebccSVladimir Oltean if (rc < 0) { 5608aa9ebccSVladimir Oltean dev_err(dev, "Failed to configure idiv\n"); 5618aa9ebccSVladimir Oltean return rc; 5628aa9ebccSVladimir Oltean } 5638aa9ebccSVladimir Oltean rc = sja1105_cgu_rgmii_tx_clk_config(priv, port, speed); 5648aa9ebccSVladimir Oltean if (rc < 0) { 5658aa9ebccSVladimir Oltean dev_err(dev, "Failed to configure RGMII Tx clock\n"); 5668aa9ebccSVladimir Oltean return rc; 5678aa9ebccSVladimir Oltean } 5688aa9ebccSVladimir Oltean rc = sja1105_rgmii_cfg_pad_tx_config(priv, port); 5698aa9ebccSVladimir Oltean if (rc < 0) { 5708aa9ebccSVladimir Oltean dev_err(dev, "Failed to configure Tx pad registers\n"); 5718aa9ebccSVladimir Oltean return rc; 5728aa9ebccSVladimir Oltean } 573f5b8631cSVladimir Oltean if (!priv->info->setup_rgmii_delay) 5748aa9ebccSVladimir Oltean return 0; 575c05ec3d4SVladimir Oltean /* The role has no hardware effect for RGMII. However we use it as 576c05ec3d4SVladimir Oltean * a proxy for this interface being a MAC-to-MAC connection, with 577c05ec3d4SVladimir Oltean * the RGMII internal delays needing to be applied by us. 578c05ec3d4SVladimir Oltean */ 579c05ec3d4SVladimir Oltean if (role == XMII_MAC) 580c05ec3d4SVladimir Oltean return 0; 581f5b8631cSVladimir Oltean 582f5b8631cSVladimir Oltean return priv->info->setup_rgmii_delay(priv, port); 5838aa9ebccSVladimir Oltean } 5848aa9ebccSVladimir Oltean 5858aa9ebccSVladimir Oltean static int sja1105_cgu_rmii_ref_clk_config(struct sja1105_private *priv, 5868aa9ebccSVladimir Oltean int port) 5878aa9ebccSVladimir Oltean { 5888aa9ebccSVladimir Oltean const struct sja1105_regs *regs = priv->info->regs; 5898aa9ebccSVladimir Oltean struct sja1105_cgu_mii_ctrl ref_clk; 5908aa9ebccSVladimir Oltean u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 5918aa9ebccSVladimir Oltean const int clk_sources[] = { 5928aa9ebccSVladimir Oltean CLKSRC_MII0_TX_CLK, 5938aa9ebccSVladimir Oltean CLKSRC_MII1_TX_CLK, 5948aa9ebccSVladimir Oltean CLKSRC_MII2_TX_CLK, 5958aa9ebccSVladimir Oltean CLKSRC_MII3_TX_CLK, 5968aa9ebccSVladimir Oltean CLKSRC_MII4_TX_CLK, 5978aa9ebccSVladimir Oltean }; 5988aa9ebccSVladimir Oltean 599*c5037678SVladimir Oltean if (regs->rmii_ref_clk[port] == SJA1105_RSV_ADDR) 600*c5037678SVladimir Oltean return 0; 601*c5037678SVladimir Oltean 6028aa9ebccSVladimir Oltean /* Payload for packed_buf */ 6038aa9ebccSVladimir Oltean ref_clk.clksrc = clk_sources[port]; 6048aa9ebccSVladimir Oltean ref_clk.autoblock = 1; /* Autoblock clk while changing clksrc */ 6058aa9ebccSVladimir Oltean ref_clk.pd = 0; /* Power Down off => enabled */ 6068aa9ebccSVladimir Oltean sja1105_cgu_mii_control_packing(packed_buf, &ref_clk, PACK); 6078aa9ebccSVladimir Oltean 6081bd44870SVladimir Oltean return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ref_clk[port], 6098aa9ebccSVladimir Oltean packed_buf, SJA1105_SIZE_CGU_CMD); 6108aa9ebccSVladimir Oltean } 6118aa9ebccSVladimir Oltean 6128aa9ebccSVladimir Oltean static int 6138aa9ebccSVladimir Oltean sja1105_cgu_rmii_ext_tx_clk_config(struct sja1105_private *priv, int port) 6148aa9ebccSVladimir Oltean { 6158aa9ebccSVladimir Oltean const struct sja1105_regs *regs = priv->info->regs; 6168aa9ebccSVladimir Oltean struct sja1105_cgu_mii_ctrl ext_tx_clk; 6178aa9ebccSVladimir Oltean u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 6188aa9ebccSVladimir Oltean 619*c5037678SVladimir Oltean if (regs->rmii_ext_tx_clk[port] == SJA1105_RSV_ADDR) 620*c5037678SVladimir Oltean return 0; 621*c5037678SVladimir Oltean 6228aa9ebccSVladimir Oltean /* Payload for packed_buf */ 6238aa9ebccSVladimir Oltean ext_tx_clk.clksrc = CLKSRC_PLL1; 6248aa9ebccSVladimir Oltean ext_tx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */ 6258aa9ebccSVladimir Oltean ext_tx_clk.pd = 0; /* Power Down off => enabled */ 6268aa9ebccSVladimir Oltean sja1105_cgu_mii_control_packing(packed_buf, &ext_tx_clk, PACK); 6278aa9ebccSVladimir Oltean 6281bd44870SVladimir Oltean return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ext_tx_clk[port], 6298aa9ebccSVladimir Oltean packed_buf, SJA1105_SIZE_CGU_CMD); 6308aa9ebccSVladimir Oltean } 6318aa9ebccSVladimir Oltean 6328aa9ebccSVladimir Oltean static int sja1105_cgu_rmii_pll_config(struct sja1105_private *priv) 6338aa9ebccSVladimir Oltean { 6348aa9ebccSVladimir Oltean const struct sja1105_regs *regs = priv->info->regs; 6358aa9ebccSVladimir Oltean u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 6368aa9ebccSVladimir Oltean struct sja1105_cgu_pll_ctrl pll = {0}; 6378aa9ebccSVladimir Oltean struct device *dev = priv->ds->dev; 6388aa9ebccSVladimir Oltean int rc; 6398aa9ebccSVladimir Oltean 640*c5037678SVladimir Oltean if (regs->rmii_pll1 == SJA1105_RSV_ADDR) 641*c5037678SVladimir Oltean return 0; 642*c5037678SVladimir Oltean 6438aa9ebccSVladimir Oltean /* PLL1 must be enabled and output 50 Mhz. 6448aa9ebccSVladimir Oltean * This is done by writing first 0x0A010941 to 6458aa9ebccSVladimir Oltean * the PLL_1_C register and then deasserting 6468aa9ebccSVladimir Oltean * power down (PD) 0x0A010940. 6478aa9ebccSVladimir Oltean */ 6488aa9ebccSVladimir Oltean 6498aa9ebccSVladimir Oltean /* Step 1: PLL1 setup for 50Mhz */ 6508aa9ebccSVladimir Oltean pll.pllclksrc = 0xA; 6518aa9ebccSVladimir Oltean pll.msel = 0x1; 6528aa9ebccSVladimir Oltean pll.autoblock = 0x1; 6538aa9ebccSVladimir Oltean pll.psel = 0x1; 6548aa9ebccSVladimir Oltean pll.direct = 0x0; 6558aa9ebccSVladimir Oltean pll.fbsel = 0x1; 6568aa9ebccSVladimir Oltean pll.bypass = 0x0; 6578aa9ebccSVladimir Oltean pll.pd = 0x1; 6588aa9ebccSVladimir Oltean 6598aa9ebccSVladimir Oltean sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK); 6601bd44870SVladimir Oltean rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf, 6611bd44870SVladimir Oltean SJA1105_SIZE_CGU_CMD); 6628aa9ebccSVladimir Oltean if (rc < 0) { 6638aa9ebccSVladimir Oltean dev_err(dev, "failed to configure PLL1 for 50MHz\n"); 6648aa9ebccSVladimir Oltean return rc; 6658aa9ebccSVladimir Oltean } 6668aa9ebccSVladimir Oltean 6678aa9ebccSVladimir Oltean /* Step 2: Enable PLL1 */ 6688aa9ebccSVladimir Oltean pll.pd = 0x0; 6698aa9ebccSVladimir Oltean 6708aa9ebccSVladimir Oltean sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK); 6711bd44870SVladimir Oltean rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf, 6721bd44870SVladimir Oltean SJA1105_SIZE_CGU_CMD); 6738aa9ebccSVladimir Oltean if (rc < 0) { 6748aa9ebccSVladimir Oltean dev_err(dev, "failed to enable PLL1\n"); 6758aa9ebccSVladimir Oltean return rc; 6768aa9ebccSVladimir Oltean } 6778aa9ebccSVladimir Oltean return rc; 6788aa9ebccSVladimir Oltean } 6798aa9ebccSVladimir Oltean 6808aa9ebccSVladimir Oltean static int sja1105_rmii_clocking_setup(struct sja1105_private *priv, int port, 6818aa9ebccSVladimir Oltean sja1105_mii_role_t role) 6828aa9ebccSVladimir Oltean { 6838aa9ebccSVladimir Oltean struct device *dev = priv->ds->dev; 6848aa9ebccSVladimir Oltean int rc; 6858aa9ebccSVladimir Oltean 6868aa9ebccSVladimir Oltean dev_dbg(dev, "Configuring RMII-%s clocking\n", 6878aa9ebccSVladimir Oltean (role == XMII_MAC) ? "MAC" : "PHY"); 6888aa9ebccSVladimir Oltean /* AH1601.pdf chapter 2.5.1. Sources */ 6898aa9ebccSVladimir Oltean if (role == XMII_MAC) { 6908aa9ebccSVladimir Oltean /* Configure and enable PLL1 for 50Mhz output */ 6918aa9ebccSVladimir Oltean rc = sja1105_cgu_rmii_pll_config(priv); 6928aa9ebccSVladimir Oltean if (rc < 0) 6938aa9ebccSVladimir Oltean return rc; 6948aa9ebccSVladimir Oltean } 6958aa9ebccSVladimir Oltean /* Disable IDIV for this port */ 6968aa9ebccSVladimir Oltean rc = sja1105_cgu_idiv_config(priv, port, false, 1); 6978aa9ebccSVladimir Oltean if (rc < 0) 6988aa9ebccSVladimir Oltean return rc; 6998aa9ebccSVladimir Oltean /* Source to sink mappings */ 7008aa9ebccSVladimir Oltean rc = sja1105_cgu_rmii_ref_clk_config(priv, port); 7018aa9ebccSVladimir Oltean if (rc < 0) 7028aa9ebccSVladimir Oltean return rc; 7038aa9ebccSVladimir Oltean if (role == XMII_MAC) { 7048aa9ebccSVladimir Oltean rc = sja1105_cgu_rmii_ext_tx_clk_config(priv, port); 7058aa9ebccSVladimir Oltean if (rc < 0) 7068aa9ebccSVladimir Oltean return rc; 7078aa9ebccSVladimir Oltean } 7088aa9ebccSVladimir Oltean return 0; 7098aa9ebccSVladimir Oltean } 7108aa9ebccSVladimir Oltean 7118aa9ebccSVladimir Oltean int sja1105_clocking_setup_port(struct sja1105_private *priv, int port) 7128aa9ebccSVladimir Oltean { 7138aa9ebccSVladimir Oltean struct sja1105_xmii_params_entry *mii; 7148aa9ebccSVladimir Oltean struct device *dev = priv->ds->dev; 7158aa9ebccSVladimir Oltean sja1105_phy_interface_t phy_mode; 7168aa9ebccSVladimir Oltean sja1105_mii_role_t role; 7178aa9ebccSVladimir Oltean int rc; 7188aa9ebccSVladimir Oltean 7198aa9ebccSVladimir Oltean mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries; 7208aa9ebccSVladimir Oltean 7218aa9ebccSVladimir Oltean /* RGMII etc */ 7228aa9ebccSVladimir Oltean phy_mode = mii->xmii_mode[port]; 7238aa9ebccSVladimir Oltean /* MAC or PHY, for applicable types (not RGMII) */ 7248aa9ebccSVladimir Oltean role = mii->phy_mac[port]; 7258aa9ebccSVladimir Oltean 7268aa9ebccSVladimir Oltean switch (phy_mode) { 7278aa9ebccSVladimir Oltean case XMII_MODE_MII: 7288aa9ebccSVladimir Oltean rc = sja1105_mii_clocking_setup(priv, port, role); 7298aa9ebccSVladimir Oltean break; 7308aa9ebccSVladimir Oltean case XMII_MODE_RMII: 7318aa9ebccSVladimir Oltean rc = sja1105_rmii_clocking_setup(priv, port, role); 7328aa9ebccSVladimir Oltean break; 7338aa9ebccSVladimir Oltean case XMII_MODE_RGMII: 734c05ec3d4SVladimir Oltean rc = sja1105_rgmii_clocking_setup(priv, port, role); 7358aa9ebccSVladimir Oltean break; 736ffe10e67SVladimir Oltean case XMII_MODE_SGMII: 737ffe10e67SVladimir Oltean /* Nothing to do in the CGU for SGMII */ 738ffe10e67SVladimir Oltean rc = 0; 739ffe10e67SVladimir Oltean break; 7408aa9ebccSVladimir Oltean default: 7418aa9ebccSVladimir Oltean dev_err(dev, "Invalid interface mode specified: %d\n", 7428aa9ebccSVladimir Oltean phy_mode); 7438aa9ebccSVladimir Oltean return -EINVAL; 7448aa9ebccSVladimir Oltean } 745135e3018SVladimir Oltean if (rc) { 7468aa9ebccSVladimir Oltean dev_err(dev, "Clocking setup for port %d failed: %d\n", 7478aa9ebccSVladimir Oltean port, rc); 7488aa9ebccSVladimir Oltean return rc; 7498aa9ebccSVladimir Oltean } 7508aa9ebccSVladimir Oltean 751135e3018SVladimir Oltean /* Internally pull down the RX_DV/CRS_DV/RX_CTL and RX_ER inputs */ 752135e3018SVladimir Oltean return sja1105_cfg_pad_rx_config(priv, port); 753135e3018SVladimir Oltean } 754135e3018SVladimir Oltean 7558aa9ebccSVladimir Oltean int sja1105_clocking_setup(struct sja1105_private *priv) 7568aa9ebccSVladimir Oltean { 757542043e9SVladimir Oltean struct dsa_switch *ds = priv->ds; 7588aa9ebccSVladimir Oltean int port, rc; 7598aa9ebccSVladimir Oltean 760542043e9SVladimir Oltean for (port = 0; port < ds->num_ports; port++) { 7618aa9ebccSVladimir Oltean rc = sja1105_clocking_setup_port(priv, port); 7628aa9ebccSVladimir Oltean if (rc < 0) 7638aa9ebccSVladimir Oltean return rc; 7648aa9ebccSVladimir Oltean } 7658aa9ebccSVladimir Oltean return 0; 7668aa9ebccSVladimir Oltean } 767